Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a circuit element on the first substrate, a lower interconnect structure coupled with the circuit element, and a lower bonding structure coupled with the lower interconnect structure. The second semiconductor structure includes an upper bonding structure bonded to the lower bonding structure, a conductive layer, a stack structure including an interlayer insulating layer and a gate electrode, a plurality of separation regions at least partially penetrating the stack structure, a channel structure including a channel layer and at least partially penetrating the stack structure, a semiconductor device includes a stack structure, a plurality of channel structures, a plurality of address posts spaced apart from each other by a first separation distance, a plurality of channel posts under the channel structures, and an upper interconnect structure under the stack structure, coupled to the plurality of channel posts, and spaced apart from the plurality of address posts.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to a semiconductor device and a data storage system including the semiconductor device. Background Technology

[0002] Data storage systems that may require data storage can utilize semiconductor devices capable of storing relatively large amounts of data. Therefore, methods for potentially increasing the data storage capacity of semiconductor devices have been investigated. For example, a possible method for potentially increasing the data storage capacity of semiconductor devices may include arranging the memory cells of the semiconductor device in three dimensions, rather than in two dimensions. Summary of the Invention

[0003] One or more exemplary embodiments of this disclosure provide a semiconductor device that, when compared with related semiconductor devices, has relatively high reliability and is capable of performing quality checks.

[0004] Therefore, highly reliable semiconductor devices and data storage systems including such semiconductor devices can be provided through error checking with improved reliability.

[0005] Furthermore, one or more exemplary embodiments of this disclosure provide a data storage system that includes semiconductor devices having relatively high reliability and capable of performing error checking operations.

[0006] According to one aspect of this disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure. The second semiconductor structure includes: an upper bonding structure bonded to the lower bonding structure; a conductive layer; a stacked structure below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction; a plurality of partition regions, at least partially penetrating the stacked structure, extending in a second direction and spaced apart from each other in a third direction; a channel structure including a channel layer and at least partially penetrating the stacked structure in the first direction; a plurality of address pillars spaced apart from each other in the second direction by a first partition distance below at least one of the partition regions; a plurality of channel pillars below the channel structure; and an upper interconnect structure below the stacked structure, connected to the plurality of channel pillars and spaced apart from the plurality of address pillars. The first direction is perpendicular to the upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to both the first and second directions.

[0007] According to one aspect of this disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure. The second semiconductor structure includes: an upper bonding structure bonded to the lower bonding structure; a conductive layer; a stacked structure below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction; a channel structure including a channel layer and at least partially penetrating the stacked structure in the first direction; a plurality of partition regions, at least partially penetrating the stacked structure, extending in a second direction and spaced apart from each other in a third direction; a plurality of address pillars spaced apart from each other in the second direction by a multiple of a unit partition distance and disposed below the first and second address partition regions; and a plurality of channel pillars disposed below the channel structure. The first direction is perpendicular to the upper surface of the conductive layer. The second direction is perpendicular to the first direction. The third direction is perpendicular to both the first and second directions. The plurality of partition regions include an address partition group, the address partition group including a first address partition region and a second address partition region adjacent to the first address partition region in a third direction.

[0008] According to one aspect of this disclosure, a data storage system includes a semiconductor device and a controller, the controller being coupled to the semiconductor device via input / output pads and configured to control the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and input / output pads. The first semiconductor structure includes a substrate and circuit elements on the substrate. The second semiconductor structure includes a stacked structure and a channel structure. The stacked structure includes an interlayer insulating layer and a gate electrode stacked in a first direction. The channel structure at least partially penetrates the stacked structure. The input / output pads are coupled to the circuit elements. The first semiconductor structure further includes a lower interconnect structure coupled to the circuit elements and a lower bonding structure coupled to the lower interconnect structure. The second semiconductor structure further includes an upper interconnect structure disposed below the stacked structure, an upper bonding structure coupled to the upper interconnect structure and bonded to the lower bonding structure, a plurality of partition regions at least partially penetrating the stacked structure and extending in a second direction and spaced apart from each other in a third direction, a plurality of address pillars disposed below at least one of the partition regions and spaced apart from each other in the second direction by a first partition distance, and a plurality of channel pillars below the channel structure. The upper interconnect structure is coupled to the plurality of channel pillars and spaced apart from the plurality of address pillars. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first and second directions.

[0009] The advantages and effects of this application are not limited to the foregoing, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure.

[0010] Other aspects may be set forth in part in the description below, and in part may be apparent from the description, and / or may be learned by practice of the embodiments given. Attached Figure Description

[0011] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a schematic plan view of a semiconductor device according to an example embodiment;

[0013] Figure 2 This is a partial enlarged view of a semiconductor device according to an example embodiment;

[0014] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 4A and Figure 4B It is based on the example implementation method. Figure 3 Enlarged cross-sectional view of a portion of the area;

[0016] Figures 5 to 7 This is an enlarged view of a semiconductor device according to an example embodiment;

[0017] Figure 8 This is a plan view of a semiconductor device according to an example embodiment;

[0018] Figure 9 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0019] Figures 10 to 13 This is a schematic partial enlarged view of a semiconductor device according to an example embodiment;

[0020] Figures 14A to 14G This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment;

[0021] Figure 15 This is a schematic diagram of a data storage system including semiconductor devices according to an example embodiment; and

[0022] Figure 16 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment. Detailed Implementation

[0023] The following description, provided with reference to the accompanying drawings, is intended to aid in a comprehensive understanding of embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to aid understanding, but these details are considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Furthermore, descriptions of well-known functions and structures have been omitted for clarity and brevity.

[0024] Regarding the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that, unless the relevant context explicitly states otherwise, the singular form of the noun corresponding to an item may include one or more things. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B or C” may include any one or all possible combinations of the items listed together in the corresponding phrase. As used herein, terms such as “first” and “second” or “first” and “second” may be used simply to distinguish corresponding parts from another part and do not limit the parts in other respects (e.g., importance or order). It should be understood that if an element (e.g., the first element) is referred to as "connected to another element (e.g., the second element)," "attached to another element (e.g., the second element)," "connected to another element (e.g., the second element)," or "connected to another element (e.g., the second element)" with or without the terms "operably" or "communically," it means that the element can be connected to the other element directly (e.g., wired), wirelessly, or via a third element.

[0025] It should be understood that when a component or layer is referred to as being "above," "over," "on," "below," "under," "connected to," or "attached to" another component or layer, it can be directly above, above, above, below, under, connected to, or attached to the other component or layer, or there may be intermediate components or layers. In contrast, when a component is referred to as being "directly above," "directly above," "directly on," "directly below," "directly under," "directly connected to," or "directly attached to," there are no intermediate components or layers.

[0026] The terms “upper,” “middle,” “lower,” etc., can be replaced by terms such as “first,” “second,” “third,” etc., to describe the relative positions of elements. The terms “first,” “second,” “third,” etc., can be used to describe various elements, but the elements are not limited by these terms, and a “first element” can be referred to as a “second element.” Alternatively or additionally, the terms “first,” “second,” “third,” etc., can be used to distinguish parts from each other and do not limit this disclosure. For example, the terms “first,” “second,” “third,” etc., do not necessarily imply any form of order or numerical meaning.

[0027] As used herein, when an element or layer is referred to as “covering,” “overlapping,” or “surrounding” another element or layer, the element or layer may cover at least a portion of the other element or layer, wherein the at least portion may include a part of the other element or layer or may include the entirety of the other element or layer. Similarly, when an element or layer is referred to as “penetrating” another element or layer, the element or layer may penetrate at least a portion of the other element or layer, wherein the at least portion may include a part of the other element or layer or may include the entire dimensions (e.g., length, width, depth) of the other element or layer.

[0028] References throughout this disclosure to “one embodiment,” “implementation,” “exemplary embodiment,” or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases “in one embodiment,” “in an embodiment,” “in an exemplary embodiment,” and similar language throughout this disclosure may, but do not necessarily, refer to the same embodiment. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms.

[0029] As shown in the accompanying drawings, embodiments described and illustrated herein can be represented by blocks that perform one or more of the functions described. These blocks (which may be referred to herein as cells or modules, or by names such as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc.) can be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0030] In this disclosure, the articles “a” and “one” are intended to include one or more items and can be used interchangeably with “one or more.” The term “one” or similar language is used where the intent is to include only one item. For example, the term “processor” can refer to a single processor or multiple processors. When a processor is described as performing operations and the processor is referred to as performing additional operations, multiple operations can be performed by a single processor or any one or a combination of multiple processors.

[0031] As used herein, each of the terms “SiC”, “SiCN”, “SiGe”, “Si3N4”, “SiO2”, “SiOC”, “SiOCN”, “SiON”, “TaN”, “TaSiN”, “TiN”, “TiSiN”, “WN”, “WSiN”, etc., may refer to a material made from the element included in each of the terms, and is not a chemical formula representing a stoichiometric relationship.

[0032] In the following text, see references Figures 1 to 4B Describe a semiconductor device according to an example implementation. Figure 1 This is a schematic plan view of a semiconductor device according to an example embodiment. Figure 2 It is based on the example implementation method. Figure 1 A magnified plan view of region A.

[0033] The semiconductor device 10 may include a first semiconductor structure S1 and a second semiconductor structure S2, and the first semiconductor structure S1 may be stacked in the Z direction, which is perpendicular to the second semiconductor structure S2. For example, the first semiconductor structure S1 may be disposed below the second semiconductor structure S2 in the Z direction. As another example, the second semiconductor structure S2 may be disposed below the first semiconductor structure S1.

[0034] In an example implementation, the semiconductor device 10 may include a peripheral circuit structure (e.g., Figure 3 The peripheral circuit structure (PERI) and memory cell structure (e.g., Figure 3 The memory cell structure (CELL) can be a first semiconductor structure S1 in which the peripheral circuit region is formed on the first substrate 101, and the memory cell structure can be a second semiconductor structure S2 including a common source line CSL.

[0035] The first semiconductor structure S1 can form peripheral circuitry by forming transistors and / or metal patterns for wiring the transistors on the first substrate 101. The second semiconductor structure S2 of the semiconductor device 10 may include a memory block BLK, which may be and / or may include a collection of multiple channel structures CH.

[0036] The semiconductor device 10 may include a first region R1 and a second region R2 on both sides of the first region R1 in the X direction.

[0037] The first region R1 may correspond to a memory cell region in which memory cells are disposed, and may be a region in which a channel structure CH is disposed. The second region R2 may correspond to a region for electrically connecting the memory cells to the peripheral circuit structure PERI, and thus, the second region R2 may be and / or may include a region in which the gate electrode layer can extend to different lengths. However, this disclosure is not limited thereto.

[0038] refer to Figure 1 Edge regions EA can be provided on each side. Edge regions EA can be provided outside the second region R2, above and below the first region R1, and can be regions in which the mold structure is retained. Edge regions EA can refer to regions in which pad areas connected from the outside are provided, external contact paths connected to the pad areas are provided, or various through paths connected to the first semiconductor structure S1 are provided. Although the semiconductor device 10 is shown as having a frame shape by providing edge regions EA on each side, this disclosure is not limited thereto.

[0039] The semiconductor device 10 may have partition regions MS extending in the X direction within a first region R1 and a second region R2. The partition regions MS may be spaced apart from each other in the Y direction, and the first region R1 between adjacent partition regions MS may be referred to as a memory block BLK. The memory block BLK may be used as an operating unit and signal application unit for a channel structure CH. However, this disclosure is not limited thereto.

[0040] Multiple memory blocks BLK can be disposed within a first region R1 of the semiconductor device 10. For example, dozens to hundreds of memory blocks BLK can be disposed within the first region R1. However, this disclosure is not limited in this respect. Address studs 275 can be configured by at least some of the partition regions MS corresponding to the partitions separating the memory blocks BLK.

[0041] The partition region MS containing address pins 275 can be referred to as an address partition region MSc. A partition region MS that has one partition region every n partition regions in the Y direction (e.g., the nth partition region, the 2nth partition region, the 3nth partition region, etc., where n is a positive integer greater than zero (0)) can be referred to as an address partition region MSc. The remaining partition regions MS that are not address partition regions MSc can be referred to as general partition regions MSg, and can be partition regions MS in which address pins 275 are not set in the lower part.

[0042] Address-separated regions (MSc) can be set in pairs and / or groups. That is, adjacent separated regions (MS) located above and below a memory block (BLK) can be address-separated regions (MSc). In other words, n can be a predetermined number, such as, but not limited to, 50, 100, etc. For example, when n is 50, the 50th and 51st address-separated regions (MSc) can form a pair, and the 100th and 101st address-separated regions (MSc) can form another pair.

[0043] Address columns 275 set on a pair of address-separated regions MSc can be set regularly according to the array rules. Address columns 275 can be arranged in two (2) rows on a pair of address-separated regions MSc. One row of address columns 275 can be arranged on each address-separated region MSc that forms a pair of address-separated regions MSc.

[0044] In a pair of address separation regions MSc, the number of address pillars 275 in each row can vary. For example, if the number of address pillars 275 in the first row is at least 'a', then the number of address pillars 275 in the second row can be 'b' - (a-1). In such an example, 'b' can be the number of pillar positions (e.g., first pillar position n1, second pillar position n2, third pillar position n3, fourth pillar position n4, and fifth pillar position n5) within the array group AG, which can be a set of address pillars 275 to which array rules are applied. Pillar positions n1 to n5 can refer to positions that can be spaced apart from each other by the same first separation distance I1. For example, the first separation distance I1 can be determined based on the sum of the pitches of a predetermined number (k) bit lines BL (multiples of the pitch). Pillar positions n1 to n5 can refer to the positions where address pillars 275 can be set within the array group AG, and can be the same pillar positions n1 to n5 aligned in the Y direction for each row. Therefore, address columns 275 can be spaced apart from each other on the address separation region MSc by an integer r (where r is a positive integer greater than zero (0)).

[0045] In some implementations, k can be 50, 100, etc. For example, when the number b of column positions n1 to n5 in array group AG is five (5), the number a of address columns 275 in the first row can be two (2), and the number of address columns 275 in the second row can be four (4).

[0046] Array groups AG can be repeatedly set in the extension direction (X direction) of a pair of address-separated regions MSc. The array rules of each array group AG can be substantially similar and / or identical to each other, and the same array of address columns 275 following the same array rules can be repeatedly set in a pair of address-separated regions MSc. In addition, the same array rules can be applied to other pairs of address-separated regions MSc.

[0047] like Figure 1 and Figure 2 As shown, when five column positions n1 to n5 are set in a row within an array group AG, address column 275 can be set in the first column position n1 and the second column position n2 in the first row, and address column 275 can be set in the first column position n1, the third column position n3, the fourth column position n4, and the fifth column position n5 in the second row. That is, address column 275 can be set only in the first row at the second column position n2, such that the starting address column 275 and the next address column 275 in the second row can be separated from each other by a second separation distance I2. The second separation distance I2 can be twice the first separation distance I1 (e.g., I2 = 2 × I1).

[0048] In other words, the position of address column 275 in the two rows can be called the first column position n1, and the address column 275 in the first column position n1 in the two rows can be called the starting address column 275. The position of address column 275 only in the first row can be called the second column position n2, the position of address column 275 adjacent to the second column position n2 in the second row can be called the third column position n3, the position of address column 275 to the left of the starting address column 275 of the adjacent array group AG in the second row can be called the fifth position n5, and the position of address column 275 between the third column position n3 and the fifth column position n5 in the second row can be called the fourth column position n4. Additionally or alternatively, since the address separation region MSc can be regularly set within the entire separation region MS, the positions of the address separation region MSc can be counted.

[0049] Therefore, during error checking, by confirming the arrangement of address posts 275 and the position of the address separation region MSc in which address posts 275 are set, the location where the error occurred can be confirmed. That is, it can be confirmed which memory block BLK is located in the Y direction and which bit line BL is located in the X direction within the location of the error.

[0050] In the following text, see references Figures 2 to 4B Example implementations of this disclosure are described.

[0051] Figure 2 This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 3 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 4A and Figure 4B This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 2 yes Figure 1 A magnified view of region A, and Figure 3 It shows along Figure 2The cross section of the cutting line I-I'. Figure 4A and Figure 4B They are Figure 3 Enlarged views of regions B and C.

[0052] refer to Figures 2 to 4B The semiconductor device 10 may include a first semiconductor structure S1, referred to as a peripheral circuit structure PERI, and a second semiconductor structure S2, referred to as a memory cell structure CELL, on the first semiconductor structure S1. The first semiconductor structure S1 and the second semiconductor structure S2 may be joined together by bonding structures (e.g., a lower bonding structure 180 and an upper bonding structure 280).

[0053] The first semiconductor structure S1 may include a first substrate 101, circuit elements 120 on the first substrate 101, a lower interconnect structure 130, a lower bonding structure 180, and a lower capping layer 190.

[0054] The first substrate 101 may include a semiconductor material, such as, but not limited to, group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. The first substrate 101 may be provided as a bulk wafer or an epitaxial layer. An active region may be defined by a device isolation layer 110 in the first substrate 101. A source / drain region 105 including impurities may be disposed in a portion of the active region.

[0055] Circuit element 120 may include a transistor. Each of circuit elements 120 may include a gate dielectric layer 122, a gate electrode 124, a spacer layer 126, and a source / drain region 105. The source / drain region 105, including impurities, may be disposed in a first substrate 101 on both sides of the gate electrode 124. The spacer layer 126 may be disposed on both sides of the gate electrode 124. The gate dielectric layer 122 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or a high-k material. The gate electrode 124 may include, but is not limited to, at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), etc. For example, the gate electrode 124 may include a doped polysilicon layer. According to the example implementation, the circuit gate electrode 124 may be formed of two (2) or more layers.

[0056] The lower interconnect structure 130 can be electrically connected to the circuit gate electrode 124 and the source / drain region 105 of the circuit element 120. The lower interconnect structure 130 can include lower contact plugs 135 and lower interconnect lines 137, at least one region of the lower interconnect line 137 may have a line shape. Some of the lower contact plugs 135 can be connected to the source / drain region 105, and other lower contact plugs 135 can be connected to the circuit gate electrode 124. The lower contact plugs 135 can electrically connect the lower interconnect lines 137 disposed at different levels from the upper surface of the first substrate 101 to each other. The lower interconnect structure 130 can include a conductive material, such as, but not limited to, tungsten (W), copper (Cu), and aluminum (Al). Each component may further include a diffusion barrier, comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). According to the example implementation, the number of layers and their arrangement shape of the lower contact plug 135 and lower interconnect line 137 included in the lower interconnect structure 130 can be changed differently.

[0057] The lower bonding structure 180 can be connected to the lower interconnect structure 130. The lower bonding structure 180 may include a lower bonding path 182, a lower bonding pad 184, and a lower bonding insulating layer 186. The lower bonding path 182 can be connected to the lower interconnect structure 130. The lower bonding pad 184 can be connected to the lower bonding path 182. The lower bonding path 182 and the lower bonding pad 184 may include conductive materials, such as, but not limited to, tungsten (W), copper (Cu), aluminum (Al), etc. Each of the components may further include a diffusion barrier. The lower bonding insulating layer 186 may also serve as a diffusion barrier for the lower bonding pad 184 and may include, but is not limited to, at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), and silicon carbide (SiOC).

[0058] The lower bonding insulating layer 186 may have a thickness thinner (smaller) than the lower bonding pad 184. However, this disclosure is not limited thereto. The lower bonding structure 180 may be directly bonded and / or connected to the upper bonding structure 280 by hybrid bonding. For example, the lower bonding pad 184 may contact the upper bonding pad 284 and may be bonded to the upper bonding pad 284 by copper-to-copper (Cu-Cu) bonding, and the lower bonding insulating layer 186 may contact the upper bonding insulating layer 286 and may be bonded to the upper bonding insulating layer 286 by dielectric-to-dielectric bonding. The lower bonding structure 180 may, together with the upper bonding structure 280, provide an electrical connection path between the peripheral circuit structure PERI S1 and the memory cell structure CELL S2.

[0059] The lower capping layer 190 may be disposed on the first substrate 101 to cover the circuit element 120 and the lower interconnect structure 130. The lower capping layer 190 may include multiple insulating layers. The lower capping layer 190 may include insulating materials and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or silicon oxide carbide (SiOC).

[0060] The second semiconductor structure S2, which may be and / or may include a memory cell structure, may include a first conductive layer 201 in a first region R1 (e.g., a memory cell region), a second conductive layer 202 on the upper surface of the first conductive layer 201, a gate electrode 230 stacked on the lower surface of the first conductive layer 201 and disposed in the first region R1 and the second region R2, an interlayer insulating layer 220 alternately stacked with the gate electrode 230, a channel structure CH configured to penetrate the gate electrode 230, a separating region MS extending in one direction through penetrating the gate electrode 230, and an insulating region SS penetrating a portion of the gate electrode 230. The second semiconductor structure S2 may include an edge region EA surrounding the first region R1 and the second region R2. The second semiconductor structure S2 may further include a capping layer 290 covering the gate electrode 230. The gate electrodes 230 may be perpendicularly spaced from each other and stacked on the lower surface of the first conductive layer 201, thus forming a stacked structure (e.g., a first stacked structure GS1 and a second stacked structure GS2) together with the interlayer insulating layer 220.

[0061] The second semiconductor structure S2 may include channel pillars 272 for electrical connection to the first semiconductor structure S1, upper interconnect structures (e.g., first upper interconnect 271, connection path 273, and second upper interconnect 274) below the first stacked structure GS1 and the second stacked structure GS2, and upper bonding structures 280 connected to the upper interconnect structures 271, 273, and 274. The second semiconductor structure S2 may include address pillars 275, which are disposed at a level substantially similar to and / or the same as the channel pillars 272 and on an address separation region MSc within the separation region MS.

[0062] The second semiconductor structure S2 may further include a contact plug in the second region R2 and an external contact path in the edge region EA.

[0063] like Figures 1 to 3 As shown, the first region R1 can be a region in which gate electrodes 230 are stacked and spaced apart from each other in the vertical direction (e.g., the Z direction), and a channel structure CH is provided therein. The second region R2 can be disposed on both sides of the first region R1 in the X direction, as shown... Figure 1As shown, it may include regions where contact plugs are respectively connected to the gate electrode 230 and electrically connected to the memory cell in the first semiconductor structure S1.

[0064] The first stacking structure GS1 and the second stacking structure GS2 may include multiple stacking structures GS1 and GS2 that can be stacked vertically. Figure 3 The diagram shows a lower stack structure GS1 and an upper stack structure GS2. However, this disclosure is not limited thereto and may include d-level stack structures GS1 to GSd, where d is a positive integer greater than one (1), for example, d is three (3) to five (5). However, according to the example embodiment, the stack structures GS1 to GSd may be formed as a single stack structure.

[0065] The gate electrode 230 may include: at least one lower gate electrode 230L included in the gate of a ground select transistor, a memory gate electrode 230M included in a plurality of memory cells, and an upper gate electrode 230U included in the gate of a string select transistor. As used herein, the lower gate electrode 230L and the upper gate electrode 230U may be referred to as “lower” and “upper” based on the orientation during the manufacturing process. The number of memory gate electrodes 230M included in the memory cells may be determined according to the capacity of the semiconductor device 10. According to an example embodiment, there may be one, two, or more upper gate electrodes 230U and lower gate electrodes 230L, and they may have a structure substantially similar to and / or the same as or different from the structure of the memory gate electrode 230M. In an example embodiment, an erase gate electrode may be further disposed below the upper gate electrode 230U. Additionally, some of the gate electrodes 230 (e.g., memory gate electrodes 230M adjacent to the upper gate electrode 230U or the lower gate electrode 230L) may be dummy gate electrodes. However, this disclosure is not limited thereto.

[0066] The gate electrode 230 can be configured to be separated from each other in the Y direction by a separating region MS that extends continuously within a first region R1 and a second region R2. The gate electrode 230 between a pair of separating regions MS can be included in a memory block BLK. Some of the gate electrodes 230 (e.g., memory gate electrode 230M) can each form a layer within a memory block BLK.

[0067] Gate electrodes 230 may be vertically stacked and spaced apart from each other in a first region R1 and a second region R2, and may extend from the first region R1 to the second region R2 by different lengths to form a portion of the second region R2 (e.g., a stepped structure in the second region R2). Due to the stepped structure, the gate electrodes 230 may have regions where the lower gate electrode 230 extends longer than the upper gate electrode 230, the upper surfaces of which are exposed upward from the interlayer insulating layer 220 and other gate electrodes 230, and these regions may be referred to as gate pad regions. In each gate electrode 230, the gate pad region may be a region including the end of the gate electrode 230 in the X direction. The gate electrodes 230 may be connected to contact plugs in the gate pad regions respectively.

[0068] The gate electrode 230 may include a metallic material, such as tungsten (W). According to an example embodiment, the gate electrode 230 may include polysilicon, a metal silicide material, etc. According to an example embodiment, the gate electrode 230 may further include a diffusion barrier 231, for example, the diffusion barrier 231 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0069] Interlayer insulating layers 220 may be disposed between gate electrodes 230 and may be included in the first stack structure GS1 and the second stack structure GS2. Interlayer insulating layers 220 may also be spaced apart from each other in a direction perpendicular to the lower surface of the first conductive layer 201 and may extend in the X direction similar to the gate electrodes 230. Interlayer insulating layers 220 may be disposed in the sacrificial insulating layer 218 (see reference) by extending to the edge region EA. Figure 14B The interlayer insulating layer 220 may be between, and may be included in the mold structure. The interlayer insulating layer 220 may include insulating materials such as, but not limited to, silicon oxide (SiO2) or silicon nitride (Si3N4).

[0070] In the example embodiment, the thickness of the interlayer insulating layers 220 may not all be the same. For example, the uppermost interlayer insulating layer 223, the lowermost interlayer insulating layer 222, and the intermediate interlayer insulating layer 225 may have a greater thickness than the other interlayer insulating layers 220. However, this disclosure is not limited thereto. The intermediate interlayer insulating layer 225 may be referred to as the interlayer insulating layer between the first stack structure GS1 and the second stack structure GS2.

[0071] As described above, the partition region MS can be configured to extend in the X direction by penetrating the gate electrode 230. The partition regions MS can be configured to be parallel to each other and spaced apart from each other in the Y direction. The partition regions MS can completely penetrate the stacked gate electrode 230 and can be connected to the top cover layer 290. The partition regions MS can be an extension in the X direction, but can extend intermittently in some regions or can be set only in some regions.

[0072] A separating insulating layer 264 may be disposed in the separating region MS. Due to its high aspect ratio, the separating insulating layer 264 may have a shape in which its width increases toward the first substrate 101. However, this disclosure is not limited thereto. The lower surface Sa of the separating insulating layer 264 may contact the upper capping layer 290, and its upper surface may contact the lower surface of the first conductive layer 201. The separating insulating layer 264 may not extend into the edge region EA.

[0073] like Figure 2 As shown, the partition region MS can be formed with a flat side surface, but it can also have a structure in which curved surfaces with outward convex curvature are continuously formed. The curved surfaces on the side surfaces can be obtained by forming a plurality of partition holes that are separate from each other while forming the channel holes (e.g., at substantially similar and / or the same time), and then extending the plurality of partition holes to connect them to each other and form the partition region MS by a cleaning process.

[0074] The insulating region SS can extend in the X direction between adjacent separating regions MS. The insulating region SS can be disposed in a portion of the second region R2 and the first region R1. The insulating region SS can penetrate the uppermost gate electrode 230U within the gate electrode 230. Figure 2 As shown, the insulating region SS can divide the upper gate electrode 230U in the Y direction. However, in the example embodiment, the number of upper gate electrodes 230U separated by the insulating region SS can be varied.

[0075] An insulating region SS may be disposed across a portion of the channel structure CH. The insulating region SS has a predetermined width in the Y direction and may extend in the X direction across the space between multiple channel structures CH arranged in a Z-shape. Therefore, when multiple channel structures CH are arranged with the same spacing, the insulating region SS may extend across a row of channel structures CH simultaneously. The insulating region SS may be recessed into the upper portion (e.g., an upper gate electrode 230U) of the channel structure CH facing the gate electrode 230, thus a portion of the channel structure CH may be removed. In this case, the channel structure CH may be recessed by a length less than the radius of the channel structure CH, i.e., the distance from the channel central axis to the inner wall of the channel hole. Therefore, the insulating region SS may not cross the channel central axis of the channel structure CH and may be configured such that at least half of the channel structure CH remains on its upper surface. However, this disclosure is not limited thereto. The channel structure CH into which the insulating region SS is recessed may be an effective channel structure actually used as a memory cell, rather than a dummy channel structure. Each of the insulating regions SS may include an upper separating insulating layer 266. The upper separating insulating layer 266 may include, but is not limited to, insulating materials, such as silicon oxide (SiO2), silicon nitride (Si3N4), or silicon nitride oxide (SiON).

[0076] The channel structures CH can be spaced apart from each other by forming rows and / or columns on the lower surface of the first conductive layer 201 in the first region R1. The channel structures CH can be arranged in a zigzag shape in one direction of the XY plane. The channel structures CH can penetrate the gate electrode 230 and can extend in a vertical direction perpendicular to the lower surface of the first conductive layer 201 (e.g., in the Z direction), can have a columnar shape and can have inclined side surfaces, such that the width of the channel structures CH becomes narrower according to the aspect ratio as the channel structures CH approach the first conductive layer 201.

[0077] Each of the channel structures CH can have a first channel structure CH1 and a second channel structure CH2 in which the lower stacked structure GS1 and the upper stacked structure GS2, which respectively penetrate the gate electrode 230, are connected to each other, and can have a curved portion due to differences or variations in the width of the connection region.

[0078] like Figure 4A As shown in the enlarged view, each of the channel structures CH may include a first portion within the first stack structure GS1 and the second stack structure GS2, and a second portion protruding above the first stack structure GS1 and the second stack structure GS2.

[0079] The channel layer 240 may be entirely disposed within the first and second portions of the channel structure CH, and may extend to the upper end of the second portion. The channel layer 240 may include a protruding portion 240a disposed within the second portion of the channel structure CH and protruding and exposed above the first stack structure GS1 and the second stack structure GS2, and a non-protruding portion 240b disposed within the first portion of the channel structure CH. The lengths of the second portions of the channel structure CH (i.e., the protruding lengths of the protruding portions 240a of the channel layer 240) may be different from each other. However, this disclosure is not limited thereto. According to an example embodiment, the channel layer 240 may be formed in an annular shape, wherein the side surfaces of the channel layer 240 surround an internal channel-buried insulating layer 247; however, the channel layer 240 may also have a columnar shape, such as a cylindrical or prismatic shape, without the channel-buried insulating layer 247. The protruding portion 240a of the channel layer 240 may be covered by the first conductive layer 201 and may be in direct contact with the first conductive layer 201. The protruding portion 240a can be formed with a gentle slope compared to the non-protruding portion 240b, thereby maintaining the annular shape, such as... Figure 4A As shown. The channel layer 240 may include a semiconductor material, such as, but not limited to, polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type or N-type impurities.

[0080] In the channel structure CH, channel pads 249 may be disposed in the lower portion of the channel layer 240. Channel pads 249 may be configured to cover the lower surface of the channel buried insulating layer 247 and may be electrically connected to the channel layer 240. Channel pads 249 may comprise, for example, doped polysilicon.

[0081] Information storage structure 245 may be disposed between gate electrode 230 and channel layer 240. Information storage structure 245 may include a tunneling layer 241, a charge storage layer 242, and a barrier layer 243 sequentially stacked from channel layer 240. Tunneling layer 241 can tunnel charge into charge storage layer 242 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or combinations thereof. Charge storage layer 242 may be a charge trapping layer or a floating gate conductive layer. Barrier layer 243 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), high-k dielectric material, or combinations thereof. According to an example embodiment, at least a portion of information storage structure 245 may be included in a channel dielectric layer extending horizontally along gate electrode 230.

[0082] The information storage structure 245 can be removed from the upper portion of the first stacked structure GS1 and the second stacked structure GS2, so that the protruding portion 240a of the channel layer 240 can be exposed to the outside in the second portion. Therefore, the upper end of the information storage structure 245 can contact the first conductive layer 201, and the side surface of the information storage structure 245 in the first portion can be configured to surround the non-protruding portion 240b of the channel layer 240.

[0083] The trench layer 240, the information storage structure 245, and the trench burial insulation layer 247 can be connected to each other between the second trench structure CH2 and the first trench structure CH1. As described above, a relatively thick intermediate interlayer insulation layer 225 can be disposed between the second trench structure CH2 and the first trench structure CH1.

[0084] In the edge region EA, external contact paths can be connected to transmit external signals to the first semiconductor structure S1 through the exposed pad regions and the upper interconnect structures 271, 273 and 274 of the second semiconductor structure S2.

[0085] In the first region R1, the semiconductor device 10 may include a first conductive layer 201 between the lower surface of the second conductive layer 202 and the first stacked structure GS1 and the second stacked structure GS2. The first conductive layer 201 may include a semiconductor material. For example, the first conductive layer 201 may include semiconductor materials such as, but not limited to, group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The first conductive layer 201 may serve as the common source line CSL of the semiconductor device 10. The first conductive layer 201 may include a silicon layer, for example, a silicon layer having an N-type conductivity type. For example, the first conductive layer 201 may be provided as a crystalline semiconductor layer or an epitaxial layer, such as, but not limited to, a single-crystal silicon layer or a polycrystalline silicon layer doped with impurities. Figure 4A As shown in the enlarged view, the first conductive layer 201 can cover the second part of the channel structure CH and can be in direct contact with the protruding part 240a of the channel layer 240.

[0086] The first conductive layer 201 may be and / or may include a plate layer that completely covers the protrusion 240a of the channel layer 240, and may be configured to have a flat upper surface. The first conductive layer 201 may have a thickness greater than the length of the protrusion 240a of the channel layer 240, and may be conformally formed according to the shape of the channel structure CH.

[0087] The second conductive layer 202 may be disposed along the first conductive layer 201. The second conductive layer 202 may have a thickness thinner than the first conductive layer 201, and may be a conductive layer in contact with the first conductive layer 201. The second conductive layer 202 may include, but is not limited to, at least one of metal semiconductor compounds, metal nitrides, and metals (e.g., tungsten (W), copper (Cu), and aluminum (Al)). The second conductive layer 202 may be perpendicularly aligned with the first conductive layer 201.

[0088] The first conductive layer 201 and the second conductive layer 202 can be used as source layers and can be included together in the source structure. The source structure can be used as the common source line CSL of the semiconductor device 10.

[0089] In some embodiments, a buffer layer may be further formed on the second conductive layer 202. The buffer layer may be an oxide that conformally covers the second conductive layer 202, and may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), etc.

[0090] Upper interconnect structures 271, 273, and 274 can electrically connect the gate electrode 230 and the channel structure CH to the circuit element 120 within the lower capping layer 190. Upper interconnect structures 271, 273, and 274 can be connected to channel posts 272 connected to the channel structure CH. The channel posts 272, located below the channel structure CH, can be connected to the channel pads 249 of the channel structure CH. In the first region R1, the channel posts 272 connected to the channel structure CH can be electrically connected to the channel layer 240 via the channel pads 249 of the channel structure CH. In the second region R2, the posts can be connected to contact plugs connected to the gate electrode 230. The channel pillar 272 may include a conductive material, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al), and the channel pillar 272 may further include a diffusion barrier 272b, which includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). However, this disclosure is not limited in this respect.

[0091] The first upper interconnect 271 may be electrically connected to the channel post 272 and may include multiple bit lines BL extending in the Y direction and spaced apart from each other in the X direction at a predetermined pitch. The second upper interconnect 274 may be disposed below the first upper interconnect 271, and a connection passage 273 may be disposed between the second upper interconnect 274 and the first upper interconnect 271, and between the channel post 272 and the first upper interconnect 271. The upper interconnect structures 271, 273, and 274 may also include conductive materials, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each component may further include a diffusion barrier comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). However, this disclosure is not limited in this respect. According to exemplary embodiments, the number of layers and their arrangement pattern of the first upper interconnect 271 and the second upper interconnect 274 included in the upper interconnect structures 271, 273, and 274 may vary.

[0092] Address column 275 can be set by the address separation region MSc corresponding to the separation region MS, and can be set below the lower surface Sa of the address separation region MSc.

[0093] Each of the address posts 275 may include an upper surface Sb and a lower surface, and a side surface between the upper surface Sb and the lower surface. Each of the address posts 275 may have a width of the upper surface Sb smaller than the width W2 of the lower surface, and may have a width that increases toward the lower surface. The side surface may have an inclination due to the difference in width between the upper surface Sb and the lower surface. However, this disclosure is not limited thereto. The size and shape of each of the address posts 275 may be substantially similar to and / or identical to the size and shape of the channel posts 272. The channel posts 272 may also include an upper surface, a lower surface, and a side surface between the upper and lower surfaces. Each of the channel posts 272 may have a width of the upper surface smaller than the width W3 of the lower surface, and may have a width that increases toward the lower surface. The side surface may have an inclination due to the difference in width between the upper and lower surfaces. However, this disclosure is not limited thereto. That is, when the width W2 of the lower surface of each of the address posts 275 is at its maximum (e.g., widest), the width W3 of the lower surface of the channel post 272 can also be at its maximum, and the widths W2 and W3 of the lower surfaces of the address posts 275 and the channel posts 272 can be substantially similar and / or the same. The length h1 of each of the address posts 275 (e.g., length h1 in the Z direction) can be substantially similar and / or the same as the length of the channel post 272, and can be greater than the length of the connecting path 273 in the Z direction. The lower surfaces of the address posts 275 and the lower surfaces of the channel posts 272 can be set at substantially similar and / or the same levels. The distance between the address post 275 and the nearest channel post 272 can satisfy a minimum distance d1 or greater. The minimum distance d1 can be greater than the distance between the channel posts 272.

[0094] The cover layer 290 may include multiple cover insulating layers, and may include a first cover insulating layer 291, a second cover insulating layer 295, and a third cover insulating layer 296. However, this disclosure is not limited thereto.

[0095] The structure of the first cover insulating layer 291 to the third cover insulating layer 296 can represent that the first cover insulating layer 291 to the third cover insulating layer 296 are stacked in different orders during the process, and the first cover insulating layer 291 to the third cover insulating layer 296 can include substantially similar and / or identical materials. For example, the first cover insulating layer 291 to the third cover insulating layer 296 can include, but is not limited to, at least one of silicon carbon nitride (SiCN), silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbon oxide (SiOC), silicon nitride (SiON), and silicon oxycarbon nitride (SiOCN).

[0096] The separator region MS may have a lower surface Sa with a width W1 that is greater than the width of the upper surface of the separator region MS, and the lower surface Sa of the separator region MS may have a first width W1 in the Y direction. The lower surface Sa of the address separator region MSc and the lower surface of the channel structure CH may be substantially coplanar with the lower surface of the uppermost interlayer insulating layer 223.

[0097] The first cover insulating layer 291 may cover the lower surface Sa of the address separation region MSc and the lower surface of the channel structure CH. Address posts 275 and channel posts 272 may be configured to penetrate the first cover insulating layer 291. The upper surface Sb of address post 275 may contact the lower surface Sa of the address separation region MSc. However, this disclosure is not limited thereto, and address posts 275 may be disposed within the first cover insulating layer 291.

[0098] The center line of the width W1 of the lower surface Sa of the address separation region MSc in the Y direction is called the reference line. When the center line of the width of the upper surface Sb of address column 275 below the address separation region MSc is called the first line, Then the reference line and the front line They can be arranged coaxially. Therefore, address post 275 can be configured to be aligned in the Z direction so as to be centered on the lower surface Sa of the address separation region MSc.

[0099] The second cover insulating layer 295 can be disposed below the first cover insulating layer 291. The first upper passage 273a in the connection passage 273 can be configured to penetrate the second cover insulating layer 295. The first upper passage 273a can be connected to the channel post 272 instead of the address post 275.

[0100] The first upper pass 273a can be connected to the first upper interconnect 271. The first upper pass 273a can be connected to the first upper interconnect 271, for example, a bit line BL, to apply an electrical signal to the channel structure CH. Address posts 275 can be spaced apart from the first upper interconnect 271, including the bit line BL, in the Z direction. A second cover insulating layer 295 can be disposed between the address posts 275 and the first upper interconnect 271, including the bit line BL.

[0101] The third cover insulating layer 296 can be disposed on the second cover insulating layer 295, and the second upper passage 273b and the second upper interconnect 274 can be disposed within the third cover insulating layer 296 and can be connected to the first upper interconnect 271.

[0102] Upper bonding structure 280 may be connected to upper interconnect structures 271, 273, and 274. For example, channel post 272 may be electrically connected to upper bonding structure 280. Upper bonding structure 280 may include upper bonding passage 282, upper bonding pad 284, and upper bonding insulating layer 286. Upper bonding passage 282 may be connected to upper interconnect structures 271, 273, and 274. Upper bonding pad 284 may be connected to upper bonding passage 282. Upper bonding passage 282 and upper bonding pad 284 may include conductive materials and may include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each of the components may further include a diffusion barrier. Upper bonding insulating layer 286 may also serve as a diffusion barrier for upper bonding pad 284 and may include at least one of silicon carbon nitride (SiCN), silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbon oxide (SiOC), silicon nitride (SiON), and silicon oxycarbon nitride (SiOCN). The upper bonding insulating layer 286 may have a thickness thinner than that of the upper bonding pad 284. However, this disclosure is not limited thereto.

[0103] In the following text, see references Figures 5 to 13 Example implementations of this disclosure are described. Figures 5 to 7 This is an enlarged view of a semiconductor device according to an example embodiment, and corresponds to... Figure 4B A magnified view of the area.

[0104] refer to Figure 5 Semiconductor device 10a may include the above reference Figures 1 to 4B The semiconductor device 10 described herein may be similar in many respects to the one referenced above. Figures 1 to 4B The semiconductor device 10 is described, and may include additional features not mentioned above. For example, the semiconductor device 10a may further include a substrate layer 298. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 4B The semiconductor device 10 is described repeatedly.

[0105] That is, the semiconductor device 10a may further include a base layer 298 on the lower surface of the channel structure CH and the lower surface Sa of the partition region MS. The base layer 298 may include an insulating material different from the capping layer 290; for example, when the capping layer 290 includes silicon oxide (SiO2), the base layer 298 may include a material such as, but not limited to, silicon nitride (Si3N4). The base layer 298 is an etch stop layer and may be used to prevent the formation of vias from the lower surface Sa of the address partition region MSc into its interior during the formation of the address pillars 275. Depending on the size of the partition region MS, some metal material may remain in the partition region MS after the replacement process of the gate electrode 230. When forming vias for forming the address pillars 275, if the address pillars 275 are etched into the interior of the partition region MS, the address pillars 275 may be formed to extend into the interior of the partition region MS, thereby forming parasitic capacitance and potentially causing a short circuit between the gate electrodes 230 of adjacent memory blocks BLK.

[0106] Therefore, in order to prevent vias from being formed inside the separation region MS when forming vias, an etch-selective top cover layer 290 and a base layer 298 can be further formed. Thus, when forming vias for address pillars 275, the vias can be formed only to the lower surface of the base layer 298, thereby protecting the address separation region MSc in the upper part.

[0107] Therefore, the first cover insulating layer 291 can be disposed on the lower surface of the base layer 298, and posts (e.g., address posts 275 and channel posts 272) can be provided penetrating the first cover insulating layer 291. In an embodiment, a third upper passage 297 (see reference) can be further provided. Figure 11 This is used for the electrical connection between the channel structure CH and the channel post 272. The third upper passage 297 may include a conductive material and may include the same material as the first upper passage 273a and the second upper passage 273b, and may have a smaller area and length than the channel post 272. The third upper passage 297 may have a length equal to the thickness of the base layer 298.

[0108] In this way, the base layer 298 can be disposed between the upper surface Sb of the address pillar 275 and the lower surface Sa of the address separation region MSc, and the address separation region MSc and the address pillar 275 can be physically separated from each other by a second distance d2.

[0109] refer to Figure 6 Semiconductor device 10b may include the above reference Figures 1 to 4B The semiconductor device 10 described herein may be similar in many respects to the one referenced above. Figures 1 to 4BThe semiconductor device 10 is described, and may include additional features not mentioned above. For example, the size of the address pillar 275 may be different. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 4B The semiconductor device 10 is described repeatedly.

[0110] Each of the address posts 275 may include an upper surface Sb and a lower surface, and a side surface between the upper surface Sb and the lower surface. Each of the address posts 275 may have a width of the upper surface Sb smaller than the width W4 of the lower surface, and may have a width that increases toward the lower surface. The side surface may have an inclination due to the difference in width between the upper surface Sb and the lower surface. However, this disclosure is not limited thereto. The size and shape of each of the address posts 275 may differ from the size and shape of the channel posts 272. The channel posts 272 may also include an upper surface and a lower surface, and a side surface between the upper surface and the lower surface. Each of the channel posts 272 may have a width of the upper surface smaller than the width of the lower surface, and may have a width that increases toward the lower surface. The side surface may have an inclination due to the difference in width between the upper surface and the lower surface. However, this disclosure is not limited thereto. In other words, when the width W4 of the lower surface of each address post 275 is at its maximum (e.g., widest), the width W3 of the lower surface of the channel post 272 can also be at its maximum, and the width W4 of the lower surface of the address post 275 can be less than the width W3 of the lower surface of the channel post 272. The width of the upper surface Sb of the address post 275 can be less than the width of the upper surface of the channel post 272, and the length h2 of the address post 275 (e.g., the length h2 in the Z direction) can be less than the length h1 of the channel post 272, but can be greater than the length of the connecting path 273.

[0111] Therefore, address post 275 can be disposed in the first cover insulating layer 291, and the lower surface of address post 275 can be coplanar with the lower surface of channel post 272 and with the lower surface of the first cover insulating layer 291. However, the upper surface Sb of address post 275 can be physically separated from the lower surface Sa of address separation region MSc by a third distance d3 in the Z direction, and a portion of the first cover insulating layer 291 can be disposed in the separation space.

[0112] refer to Figure 7 Semiconductor device 10c may include the above reference Figures 1 to 4B The semiconductor device 10 described herein may be similar in many respects to the one referenced above. Figures 1 to 4B The semiconductor device 10 is described, and may include additional features not mentioned above. For example, the alignment of address pillars 275 may be different. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 4B The semiconductor device 10 is described repeatedly.

[0113] The first cover insulating layer 291 can be configured to cover the lower surface Sa of the address separation region MS and the lower surface of the channel structure CH. Address posts 275 and channel posts 272 can be configured by penetrating the first cover insulating layer 291. The upper surface Sb of the address post 275 can contact the lower surface Sa of the address separation region MSc. However, this disclosure is not limited thereto, and the address post 275 can be disposed within the first cover insulating layer 291.

[0114] The center line of the width W1 of the lower surface Sa of the address separator region MSc is called the reference line. When the center line of the width of the upper surface Sb of address column 275 below the address separation region MSc is called the first line, Then address column 275 can be set to make the first line From the reference line The address post 275 is offset by a fourth distance d4. Therefore, the address post 275 can be configured to be offset from its center and close to one side of the lower surface Sa of the address separation region MSc. At least a portion of the upper surface Sb of the address post 275 can contact the uppermost interlayer insulating layer 223. However, this disclosure is not limited thereto.

[0115] Figure 8 The semiconductor device 10d may include the above reference Figures 1 to 4B The semiconductor device 10 described herein may be similar in many respects to the one referenced above. Figures 1 to 4B The semiconductor device 10 is described, and may include additional features not mentioned above. For example, the array rule of the address pillars 275 may be different. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 4B The semiconductor device 10 is described repeatedly.

[0116] refer to Figure 8 The partition region MS with address pillar 275 can be referred to as address partition region MSc. One address partition region MSc can be set every n partition regions MS in the Y direction. Address partition regions MSc can be arranged in pairs. That is, adjacent partition regions MS located above and below the memory block BLK can be a pair of address partition regions MSc. For example, when n is 50 (e.g., n=50), the nth (e.g., the 50th) and (n+1)th (e.g., the 51st) partition regions MS can form a pair of address partition regions MSc, the (2n)th (e.g., the 100th) and (2n+1)th (e.g., the 101st) partition regions MS can form another pair of address partition regions MSc, and the (3n)th (e.g., the 150th) and (3n+1)th (e.g., the 151st) partition regions MS can form yet another pair of address partition regions MSc. In other words, array rules can be applied differently to multiple pairs of address partition regions MSc.

[0117] In a pair of address-separated regions MSc, address columns 275 can be arranged in a row in the X direction on each address-separated region MSc and spaced apart from each other. The two rows of address columns 275 on a pair of address-separated regions MSc can form an array group AG configured according to array rules, and as... Figure 1 and Figure 2 As shown, the array rules can determine that address columns 275 are selectively located in the X direction for column positions n1 to n5.

[0118] For example, when there are five (5) column positions (e.g., first column position n1 to fifth column position n5) in each row of an array group AG, the address columns 275 forming the first pair of address separation regions MSc (e.g., MSn and MSn+1) can be configured with an array rule where the starting address column 275i is located at the first column position n1 of the first and second rows, and the address column 275 at the second column position n2 is located in the first row. Therefore, a first separation distance I1 can be satisfied between the starting address column 275i and the adjacent address column 275 in the first row.

[0119] The address columns 275 forming the second pair of address separation regions MSc (e.g., MS2n and MS2n+1) can be configured with an array rule where the starting address column 275i is located at the first column position n1 of the first and second rows, and the address column 275 at the third column position n3 is located in the first row. Therefore, a second separation distance I2 (e.g., twice the first separation distance I1, I2 = 2 × I1) can be satisfied between the starting address column 275i and the adjacent address column 275 in the first row.

[0120] The address columns 275 forming the third pair of address separation regions MSc (e.g., MS3n and MS3n+1) can be configured with an array rule where the starting address column 275i is located at the first column position n1 in the first and second rows, and the address column 275 at the fourth column position n4 is located in the first row. Therefore, a third separation distance I3 (e.g., three times the first separation distance I1, I3 = 3 × I1) can be satisfied between the starting address column 275i and the adjacent address column 275 in the first row.

[0121] In this way, by setting the array rules of the array group AG differently according to the position of the address separation region MSc, the arrangement of the address column 275 can be confirmed during error checking. Therefore, the position in the Y direction and the position in the X direction (e.g., the position of the memory block BLK) can be quickly confirmed.

[0122] refer to Figure 9 and Figure 13 It describes various semiconductor devices.

[0123] Figure 9 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 10 It is based on the example implementation method. Figure 9 Enlarged cross-sectional view of region D.

[0124] refer to Figure 9 and Figure 10 Semiconductor device 10e may include the above reference Figures 1 to 4B The semiconductor device 10 described herein may be similar in many respects to the one referenced above. Figures 1 to 4B The semiconductor device 10 is described and may include additional features not mentioned above. For example, an upper channel structure CH3 may be disposed on a first channel structure CH1 and a second channel structure CH2, and included in a single channel structure CH. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 4B The semiconductor device 10 is described repeatedly.

[0125] The upper channel structure CH3 may extend through the upper gate electrode 293 in the Z direction and may be connected to the first channel structure CH1 and the second channel structure CH2. The upper channel structure CH3 may be disposed on the first channel structure CH1 and the second channel structure CH2, and may be configured to be offset from the first channel structure CH1 and the second channel structure CH2 in the horizontal direction. However, this disclosure is not limited thereto.

[0126] like Figure 9 and Figure 10 As shown, each of the upper channel structures CH3 may include an upper channel layer 240c, an upper gate dielectric layer 245a, an upper channel buried insulating layer 247a, and an upper channel pad 249a disposed within an upper channel via. The upper channel layer 240c may be formed in an annular shape surrounding the upper channel buried insulating layer 247a therein. The upper channel layer 240c may be connected to a connection pad 299 at its upper portion, and may be electrically connected to the channel layers 240 of the first channel structure CH1 and the second channel structure CH2 at its upper portion via the connection pad 299.

[0127] The descriptions of the channel layer 240, information storage structure 245, channel buried insulating layer 247, and channel pad 249 described above can also be applied to the descriptions of the materials of the upper channel layer 240c, upper gate dielectric layer 245a, upper channel buried insulating layer 247a, and upper channel pad 249a.

[0128] A horizontal insulating layer 292 can be disposed between the first channel structure CH1, the second channel structure CH2, and the upper channel structure CH3, and can extend horizontally. The horizontal insulating layer 292 can be disposed between the upper gate electrode 293 and the uppermost interlayer insulating layer 223. The horizontal insulating layer 292 can be used as an etch stop layer when forming the upper channel structure CH3, and can also be used when forming the connection pads 299.

[0129] The horizontal insulating layer 292 may include an insulating material and may include a material different from the uppermost interlayer insulating layer 223. The horizontal insulating layer 292 may be a hydrogen barrier layer and may include a material that blocks or reduces the diffusion of hydrogen (H). The horizontal insulating layer 292 may include nitrides and may include at least one of, for example, silicon nitride (Si3N4), silicon oxide nitride (SiON), silicon carbon nitride (SiCN), and silicon oxycarbon nitride (SiOCN).

[0130] The connection pad 299 can penetrate the horizontal insulating layer 292 between the first channel structure CH1, the second channel structure CH2, and the upper channel structure CH3, and can electrically connect the channel layer 240 and the upper channel layer 240c. The connection pad 299 can be formed by removing a portion of the horizontal insulating layer 292, thus having an upper surface coplanar with the upper surface of the horizontal insulating layer 292. The connection pad 299 can partially overlap with the channel pad 249 in the Z direction. However, in the example embodiment, the specific arrangement of the connection pad 299 can be varied. The connection pad 299 can include a conductive material and can include, for example, polysilicon. However, this disclosure is not limited in this respect.

[0131] The upper gate electrode 293 may be disposed on the XY plane and may comprise a conductive material. The upper gate electrode 293 may comprise a material substantially similar to and / or the same as that of the gate electrode 230, but may comprise doped polysilicon.

[0132] The insulating region SS can extend in the X direction between adjacent separating regions MS. The insulating region SS can penetrate the upper gate electrode 293 disposed in the uppermost portion of the gate electrode 230. The insulating region SS can divide the upper gate electrode 293 in the Y direction. Some of the insulating regions SS can be disposed on the separating regions MS. Therefore, the insulating region SS can be configured to separate only the upper gate electrode 293, rather than as... Figure 3 The channel structure CH is formed by creating some depressions in it.

[0133] Each of the insulating regions SS may include an upper separating insulating layer 266. The upper separating insulating layer 266 may include an insulating material and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon nitride oxide (SiON). However, this disclosure is not limited in this respect.

[0134] The second horizontal insulating layer 294 can be configured to cover the upper gate electrode 293. The second horizontal insulating layer 294 can be disposed on the horizontal insulating layer 292 and can cover the lower surface and side surface of the upper gate electrode 293. The first cover insulating layer 291 can be disposed below the second horizontal insulating layer 294, and the first cover insulating layer 291 and the second horizontal insulating layer 294 can be formed of insulating material and can be formed of multiple insulating layers.

[0135] Channel posts 272 and address posts 275 can be disposed through the first cover insulating layer 291. Address post 275 can be disposed below the address separation region MSc, and channel post 272 can be disposed below the upper channel pad 249a of the upper channel structure CH3. The shape and arrangement of channel posts 272 can be consistent with... Figure 4B The shape and arrangement of the channel posts 272 are basically similar and / or the same, except that the channel pads 249 can be changed to upper channel pads 249a.

[0136] The shape of address post 275 can be similar to Figure 4B The shapes of the address columns 275 are substantially similar and / or identical. The center line of the width of the address separator region MSc in the Y direction is called the reference line. At that time, the center line of the width of address column 275 can be referred to as the first line. Furthermore, the center line of the width of the insulation region SS in the Y direction can be referred to as the second line. .

[0137] like Figure 10 As shown, reference line Second line It can be coaxial and aligned in the Z direction, and in this case, the first line From the reference line Offset. At least a portion of the upper surface Sb of the address post 275 may not be disposed on the lower surface Sc of the insulating region SS, but rather on the second horizontal insulating layer 294.

[0138] In one embodiment, a second horizontal insulating layer 294 may be disposed between the upper gate electrode 293 and the address post 275, and the insulating region SS is offset from the address post 275. Therefore, when a via is formed for the address post 275, a short circuit with the upper gate electrode 293 can be prevented due to the via penetrating into the insulating region SS.

[0139] Figure 11 The semiconductor device 10f may include the above reference Figure 10 The semiconductor device 10e described herein may be similar in many respects to the one referenced above. Figure 10 The semiconductor device 10e is described, and may include additional features not mentioned above. For example, the semiconductor device 10f may include a substrate layer 298. Therefore, for the sake of brevity, the references above can be omitted. Figure 10 The semiconductor device 10e is described repeatedly.

[0140] That is, the semiconductor device 10f may further include a base layer 298 on the lower surface of the upper channel structure CH3 and the lower surface Sc of the insulating region SS. The base layer 298 may include an insulating material different from the capping layer 290; for example, when the capping layer 290 includes silicon oxide (SiO2), the base layer 298 may include a material such as silicon nitride (Si3N4). The base layer 298 is an etch stop layer, and when the address pillars 275 are formed, the base layer 298 prevents the address pillars 275 from protruding from the lower surface Sc of the insulating region SS into the interior of the insulating region SS.

[0141] To prevent vias from being formed inside the insulating region SS during via formation, an etch-selective capping layer 290 and a base layer 298 can be further formed. Therefore, when forming vias for address posts 275, the vias can be formed only to the lower surface of the base layer 298, thereby protecting the insulating region SS above the base layer 298.

[0142] Therefore, the first cover insulating layer 291 can be disposed on the lower surface of the base layer 298, and address posts 275 penetrating the first cover insulating layer 291 can be provided. In an embodiment, a third upper passage 297 can be further provided for electrical connection between the upper channel structure CH3 and the channel posts 272. The third upper passage 297 may include a conductive material, may include a material substantially similar to and / or the same as the first upper passage 273a and the second upper passage 273b, and may have a smaller area and length than the channel posts 272 and 275. The third upper passage 297 may have a length equal to the thickness of the base layer 298.

[0143] Reference line With the front line Second line It can be coaxial, and the address post 275 and the insulating region SS can be aligned in the Z direction, but the base layer 298 can be disposed between the address post 275 and the insulating region SS, and the insulating region SS and the address post 275 can be physically separated from each other.

[0144] refer to Figure 12The semiconductor device 10g may include the above reference. Figure 10 The semiconductor device 10e described herein may be similar in many respects to the one referenced above. Figure 10 The semiconductor device 10e is described, and may include additional features not mentioned above. For example, the size of the address column 275 may be different. Therefore, for the sake of brevity, the reference above can be omitted. Figure 10 The semiconductor device 10e is described repeatedly.

[0145] Each address post 275 may include an upper surface Sb, a lower surface, and a side surface between the upper and lower surfaces. Each address post 275 may have a width of the upper surface Sb that is smaller than the width of the lower surface, and may have a width that increases toward the lower surface. The side surface may have a slope due to the difference in width between the upper surface Sb and the lower surface. However, this disclosure is not limited thereto. The size and shape of each address post 275 may differ from the size and shape of the channel post 272. The channel post 272 may also include an upper surface, a lower surface, and a side surface between the upper and lower surfaces. The width of the upper surface of each channel post 272 may be smaller than (e.g., narrower than) the width of the lower surface, and may have a width that increases toward the lower surface. The side surface may have a slope due to the difference in width between the upper and lower surfaces. However, this disclosure is not limited thereto. In other words, when the width of the lower surface of each address post 275 is at its maximum (e.g., widest), the width of the lower surface of the channel post 272 can also be at its maximum, and the width of the lower surface of the address post 275 can be less than the width of the lower surface of the channel post 272. The width of the upper surface Sb of the address post 275 can be less than the width of the upper surface of the channel post 272, and the length h2 of the address post 275 (e.g., the length h2 in the Z direction) can be less than the length h1 of the channel post 272, but can be greater than the length of the connecting path 273.

[0146] Therefore, address post 275 can be disposed within the first cover insulating layer 291, and the lower surface of address post 275 can be coplanar with the lower surface of channel post 272 and with the lower surface of the first cover insulating layer 291. However, the upper surface Sb of address post 275 can be physically spaced apart from the lower surface Sc of insulating region SS in the Z direction, and a portion of the first cover insulating layer 291 can be disposed in the separation space. By miniaturizing address post 275, the reference line... With the front line Second line They can be coaxial, and the insulating region SS and the address post 275 can be physically separated.

[0147] refer to Figure 13 Semiconductor device 10h may include the above reference. Figure 10The semiconductor device 10e described herein may be similar in many respects to the one referenced above. Figure 10 The semiconductor device 10e is described, and may include additional features not mentioned above. For example, the arrangement of the address pillars 275 and the insulating region SS may differ. Therefore, for the sake of brevity, the references above can be omitted. Figure 10 The semiconductor device 10e is described repeatedly.

[0148] First line of address column 275 Reference lines for the address-separated region MSc Coaxial, and the second wire of the insulation area SS Reference lines for separating regions MS can be used in the horizontal direction (e.g., the Y direction). Offset.

[0149] In other words, the insulating region SS can be configured to be offset to one side from the lower portion of the address separation region MSc so that they do not overlap in the Z direction. Therefore, even if the via of the address post 275 penetrates the second horizontal insulating layer 294, and this via can contact the upper gate electrode 293, it can be physically and electrically separated from the adjacent upper gate electrode 293 through the insulating region SS. Thus, short circuits between the upper gate electrodes 293 caused by over-etching of the address post 275 can be prevented.

[0150] Figures 14A to 14G This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 14A to 14G It shows the corresponding Figure 3 The area.

[0151] refer to Figure 14A It can form a first semiconductor structure S1 as a peripheral circuit structure PERI. The first semiconductor structure S1 includes a first substrate 101, circuit elements 120 on the first substrate 101, a lower interconnect structure 130, a lower bonding structure 180 and a lower capping layer 190.

[0152] In one embodiment, a device isolation layer 110 may be formed in a first substrate 101, and a circuit gate dielectric layer 122 and a circuit gate electrode 124 may be sequentially formed on the first substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 122 may be formed on the first substrate 101, and the circuit gate electrode 124 may be formed on the circuit gate dielectric layer 122. The circuit gate dielectric layer 122 and the circuit gate electrode 124 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 122 may be formed of silicon oxide (SiO2), and the circuit gate electrode 124 may be formed of at least one of polysilicon and metal silicide layers. However, this disclosure is not limited thereto. Subsequently, spacer layers 126 can be formed on the sidewalls of the circuit gate dielectric layer 122 and the circuit gate electrode 124, and impurities can be injected into the active region of the first substrate 101 on both sides of the circuit gate electrode 124 to form source / drain regions 105.

[0153] The lower contact plug 135 in the lower interconnect structure 130 can be formed by forming a portion of the lower capping layer 190, etching and removing a portion of the lower capping layer 190, and filling the removed portion with a conductive material. The lower interconnect line 137 can be formed, for example, by depositing and patterning a conductive material.

[0154] The lower bonding via 182 in the lower bonding structure 180 can be formed by forming a portion of the lower capping layer 190, etching and removing a portion of the lower capping layer 190, and filling the removed portion with a conductive material. The lower bonding pad 184 can be formed, for example, by depositing and patterning a conductive material. The lower bonding structure 180 can be formed, for example, by a deposition process or a plating process. The lower bonding insulating layer 186 can be formed by covering a portion of the upper surface and side surfaces of the lower bonding pad 184 and performing a planarization process until the upper surface of the lower bonding pad 184 is exposed.

[0155] The lower capping layer 190 may be formed of multiple insulating layers. The lower capping layer 190 may be and / or may include as part of the corresponding operations forming the lower interconnect structure 130 and the lower bonding structure 180. Thus, a first semiconductor structure S1 as a peripheral circuit structure PERI can be formed.

[0156] refer to Figure 14BThe fabrication process for the second semiconductor structure S2 can then begin. The sacrificial insulating layer 218 and the interlayer insulating layer 220 can be alternately stacked on the substrate 300 (SUB) to form a mold structure, and sacrificial vertical structures (e.g., a first vertical sacrificial layer 216a, a second vertical sacrificial layer 216b, a first separating sacrificial layer 217a, and a second separating sacrificial layer 217b) can be formed respectively on each vertical structure (i.e., Figure 3 The location of the channel structure (CH) and the separating region (MS).

[0157] The lower mold structure MS1 can be formed on the substrate 300 at the height where the first channel structure CH1 is set. The substrate 300 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0158] The sacrificial insulating layer 218 may be a layer in which at least a portion is replaced by a portion of the gate electrode 230 through a subsequent process. The sacrificial insulating layer 218 may be formed of a different material than the interlayer insulating layer 220. For example, the interlayer insulating layer 220, as well as the uppermost interlayer insulating layer 223, the middle interlayer insulating layer 225, and the lowermost interlayer insulating layer 222, may be formed of at least one of silicon oxide (SiO2) and silicon nitride (Si3N4), while the sacrificial insulating layer 218 may be formed of a different material selected from silicon (Si), silicon oxide (SiO2), silicon carbide (SiC), and silicon nitride (Si3N4) than the interlayer insulating layer 220. In the example embodiment, the thickness of the interlayer insulating layer 220 may not all be the same. Furthermore, the thicknesses of the interlayer insulating layer 220 and the sacrificial insulating layer 218, as well as the number of films included therein, may vary from those shown.

[0159] The interlayer insulating layer 220 and the sacrificial insulating layer 218 included in the lower mold structure MS1 can be alternately stacked on the substrate 300.

[0160] When the gate pad region is formed in the second region R2, the photolithography and etching processes for the sacrificial insulating layer 218 and the interlayer insulating layer 220 can be repeated. However, in the example embodiment, the specific shape of the gate pad region can be varied.

[0161] The first vertical sacrificial layer 216a can be formed in the lower portion of the first channel structure CH1 corresponding to the first region R1. The first vertical sacrificial layer 216a can be formed by forming holes to penetrate the lower mold structure MS1, depositing sacrificial layer material in the holes, and performing a planarization process. When forming the holes for forming the first vertical sacrificial layer 216a, a plurality of spaced-apart holes can be formed in the region corresponding to the partition region MS, and a first partition sacrificial layer 217a filling the plurality of spaced-apart holes can be formed together with the first vertical sacrificial layer 216a. The first vertical sacrificial layer 216a and the first partition sacrificial layer 217a can include at least one of, for example, titanium nitride (TiN) and polysilicon.

[0162] The sacrificial insulating layer 218 and interlayer insulating layer 220 included in the upper mold structure MS2 can be alternately stacked on the lower mold structure MS1, and can form a second vertical sacrificial layer 216b and a second separating sacrificial layer 217b.

[0163] Each component of the upper mold structure MS2 can be formed in the same manner as the lower mold structure MS1. The second vertical sacrificial layer 216b can be formed to be connected to the first vertical sacrificial layer 216a. The second separating sacrificial layer 217b can be formed to be connected to the first separating sacrificial layer 217a. The second vertical sacrificial layer 216b and the second separating sacrificial layer 217b can be formed by depositing a material substantially similar to and / or the same as the first vertical sacrificial layer 216a (e.g., polysilicon). However, this disclosure is not limited in this respect.

[0164] Therefore, corresponding to Figure 3 Multiple sacrificial vertical structures 216a to 217b of all vertical structures (i.e., channel structure CH and partition region MS) can be formed simultaneously (e.g., at substantially similar and / or the same time).

[0165] like Figure 14C As shown, a channel structure CH can be formed on the substrate 300, which penetrates the structure of the sacrificial insulating layer 218 and the interlayer insulating layer 220.

[0166] The channel structure CH can be formed by forming an upper via on vertical sacrificial layers 216a and 216b, then removing the vertical sacrificial layers 216a and 216b to form a via-shaped channel, and filling the via with multiple layers. The multiple layers may include an information storage structure 245, a channel layer 240, a channel buried insulating layer 247, and a channel pad 249. The upper channel via can be formed by anisotropically etching the upper stacked structure of the sacrificial insulating layer 218 and the interlayer insulating layer 220 using a separate mask layer. The lower channel via can be formed by removing the vertical sacrificial layers exposed through the upper channel via.

[0167] Due to the height of the channel structure CH, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the substrate 300. The channel structure CH may be formed such that a portion of the substrate 300 is recessed according to the depth of the channel hole.

[0168] The information storage structure 245 can be formed to have a uniform thickness. The information storage structure 245 can be formed wholly or partially in this operation, and can be formed in this operation to extend vertically along the channel structure CH to the substrate 300. A channel layer 240 can be formed on the information storage structure 245 within the channel structure CH. A channel buried insulating layer 247 can be formed to fill the channel structure CH and can be formed of an insulating material. Channel pads 249 can be formed of a conductive material and can be formed, for example, polysilicon. After forming the channel structure CH, contact plugs can be formed in the second region R2.

[0169] refer to Figure 14D A gate electrode 230 can be formed. The first separator sacrificial layers 217a and 217b, which fill the separator holes formed in the separator region MS, can be removed, and the separator holes can be expanded and connected to each other through cleaning, etc., thereby forming openings connected to each other in the X direction, such as... Figure 2 As shown. Since multiple separator holes extend in the circumferential direction and connect to each other, the side surface forming the separator region MS can have a shape in which a curved surface with an outward convex curvature is continuously formed. However, this disclosure is not limited thereto. In this way, the sacrificial insulating layer 218 can be selectively removed relative to the interlayer insulating layer 220 by wet etching within the extended opening, and the gate electrode 230 can be formed.

[0170] The gate electrode 230 can be formed by depositing a conductive material in the region from which the sacrificial insulating layer 218 has been removed. The conductive material can include, but is not limited to, metals, polysilicon, or metal silicides. In some example embodiments, a portion of the gate dielectric layer can be formed prior to the formation of the gate electrode 230.

[0171] After the gate electrode 230 is formed, a separating insulating layer 264 can be formed in the opening corresponding to the separating region MS. In an embodiment, an insulating region SS penetrating the upper gate electrode 230U can also be formed.

[0172] refer to Figure 14E This can form channel posts 272 and address posts 275.

[0173] The first cover insulating layer 291 can be formed on the uppermost interlayer insulating layer 223 to cover both the upper surface of the separating region MS and the upper surface of the channel structure CH.

[0174] In the first cover insulating layer 291, channel post holes exposing the channel pads 249 of each channel structure CH and address post holes exposing the upper surface of the address separation region MSc in the separation region MS can be formed simultaneously (e.g., at substantially similar and / or the same time).

[0175] Piston holes can be formed by etching away the corresponding area of ​​the first cover insulating layer 291, and the dimensions and depths of the channel pinholes and address pinholes can be substantially similar and / or identical to each other.

[0176] Diffusion barriers (e.g., first diffusion barrier 272b and second diffusion barrier 275b) can be stacked along the side surfaces of the channel post holes and address post holes, and the channel post holes and address post holes can be buried within the first diffusion barrier 272b and second diffusion barrier 275b, and conductive material can be stacked to form channel posts 272 and address posts 275. Depending on the shape of the channel post holes and address post holes, the width of the upper portion of the channel post holes and address post holes can be greater than the width of the lower end of the channel post holes and address post holes, and they can have sloping side surfaces. Therefore, address post holes can be formed on address separation regions MSc, which are portions of separation regions MS.

[0177] refer to Figure 14F Interconnect structures 271, 273 and 274 can be formed on channel post 272 and address post 275.

[0178] A second cover insulating layer 295 may be formed to cover the channel post 272 and the address post 275, and a portion of the second cover insulating layer 295 may be removed to form a first upper pass-through hole exposing the upper surface of the channel post 272. The first upper pass-through hole may be formed to have a smaller size than the channel post hole and may not be formed on the address post 275.

[0179] A diffusion barrier and conductive material can be formed in the first upper passage hole to form a first upper passage 273a connected to the channel post 272.

[0180] Subsequently, a third cover insulating layer 296 can be formed covering the first upper passage 273a, and a first upper interconnect 271, a second upper passage 273b, and a second upper interconnect 274 connected to the first upper passage 273a can be formed. The third cover insulating layer 296 can be implemented as a multilayer, and the first upper interconnect 271, the second upper passage 273b, and the second upper interconnect 274 can be formed by stacking diffusion barriers and conductive materials in the same manner as the first upper passage 273a.

[0181] The upper bonding structure 280 can be formed on the upper interconnect structures 271, 273 and 274.

[0182] The upper bonding structure 280 can be formed in a similar manner to the formation of the lower bonding structure 180. Therefore, a second semiconductor structure S2 can be formed, which may be a memory cell structure (CELL). However, during the manufacturing process of the semiconductor device 10, the second semiconductor structure S2 may further include a substrate 300.

[0183] refer to Figure 14G The first semiconductor structure S1, which can be a peripheral circuit structure PERI, and the second semiconductor structure S2, which can be a memory cell structure CELL, can be connected to each other.

[0184] The first semiconductor structure S1 and the second semiconductor structure S2 can be connected by applying pressure to join the lower bonding pad 184 and the upper bonding pad 284. The lower bonding insulating layer 186 and the upper bonding insulating layer 286 can be joined and connected by applying pressure. The second semiconductor structure S2 can be bonded to the first semiconductor structure S1 such that the upper bonding pad 284 faces downward. The first semiconductor structure S1 and the second semiconductor structure S2 can be directly bonded without the intervention of an adhesive (such as, for example, a separate adhesive layer).

[0185] With the first semiconductor structure S1 and the second semiconductor structure S2 bonded together, the substrate 300 exposed to the upper portion of the second semiconductor structure S2 can be removed, and the lower portion of the channel structure CH can be exposed. In this embodiment, the information storage structure 245 on the exposed second portion of the channel structure CH can be removed. The information storage structure 245 can be removed by photolithography and etching processes (such as, but not limited to, wet etching and / or dry etching). Therefore, in the second portion of the channel structure CH protruding onto the first stacked structure GS1 and the second stacked structure GS2, a protruding portion 240a can be formed by exposing the channel layer 240. Therefore, the channel layer 240 of the second portion can be in direct contact with the first conductive layer 201.

[0186] like Figure 3 As shown, the first conductive layer 201 can be formed to cover the entire first region R1. The first conductive layer 201 can be formed by depositing a semiconductor layer (such as, but not limited to, a crystalline silicon layer (e.g., a polycrystalline silicon layer)). The first conductive layer 201 can be formed to have variations along the protruding channel structure CH, but can be formed to a predetermined thickness such that its upper surface is substantially flat. The second conductive layer 202 can be formed on the first conductive layer 201. That is, the second conductive layer 202 can be formed as a multilayer. A buffer layer can be conformally formed to completely cover the second conductive layer 202, and an oxide film (e.g., a silicon oxide (SiO2) film) can be formed as the buffer layer.

[0187] In structures that combine two or more semiconductor structures, when performing operational error checks, the combined structures can be recut to capture their images, thereby identifying the location of error points. In this case, it may be difficult to identify the location of error points in a cell structure captured from a cut surface because repeating circuit patterns (such as pillars in bit lines and channel structures) are captured. Therefore, by arranging address pillars for identifying the location of error points according to predetermined rules, the location of the error points can be calculated based on the arrangement of the corresponding address pillars.

[0188] Address columns can be placed on the separator area, allowing them to be positioned clearly distinct from the columns on the channel structure, and can be used as indicators of error location through various arrangements. Furthermore, block addresses can be identified by regularly changing the arrangement of address columns according to the location of the separator area.

[0189] Therefore, highly reliable semiconductor devices and data storage systems including such semiconductor devices can be provided through error checking with improved reliability.

[0190] Figure 15 This is a schematic diagram of a data storage system including semiconductor devices according to an example embodiment.

[0191] refer to Figure 15 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be and / or may include a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device containing one or more semiconductor devices 1100.

[0192] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, the one described in the reference above. Figures 1 to 13The NAND flash memory device described herein. Semiconductor device 1100 may include a first semiconductor structure 1100F and a second semiconductor structure 1100S on the first semiconductor structure 1100F. According to an example embodiment, the first semiconductor structure 1100F may be disposed adjacent to the second semiconductor structure 1100S. The first semiconductor structure 1100F may be and / or may include peripheral circuitry including a decoder circuitry 1110, a page buffer 1120, and logic circuitry 1130. The second semiconductor structure 1100S may be and / or may include a memory cell structure including a bit line BL, a common source line CSL, a word line WL, upper gate lines (e.g., a first upper gate line UL1 and a second upper gate line UL2), lower gate lines (e.g., a first lower gate line LL1 and a second lower gate line LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0193] In the second semiconductor structure 1100S, each memory cell string CSTR may include a lower transistor (e.g., a first lower transistor LT1 and a second lower transistor LT2) adjacent to the common source line CSL, an upper transistor (e.g., a first upper transistor UT1 and a second upper transistor UT2) adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the first lower transistor LT1 and the second lower transistor LT2 and the first upper transistor UT1 and the second upper transistor UT2. According to the example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 can be varied.

[0194] According to an example embodiment, the first upper transistor UT1 and the second upper transistor UT2 may include a string select transistor, and the first lower transistor LT1 and the second lower transistor LT2 may include a ground select transistor. The first lower gate line LL1 and the second lower gate line LL2 may be the gate electrodes of the first lower transistor LT1 and the second lower transistor LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the first upper gate line UL1 and the second upper gate line UL2 may be the gate electrodes of the first upper transistor UT1 and the second upper transistor UT2, respectively.

[0195] According to an example implementation, the first lower transistor LT1 and the second lower transistor LT2 may include ground select transistors connected in series with each other. The first upper transistor UT1 and the second upper transistor UT2 may include string select transistors connected in series with each other.

[0196] The common source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0197] In the first semiconductor structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0198] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and the controller 1200 may control the plurality of semiconductor devices 1100.

[0199] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, data to be read from memory cell transistors (MCTs) of semiconductor device 1100, etc., can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0200] Figure 16 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment.

[0201] refer to Figure 16A data storage system 2000 according to an exemplary embodiment of the present disclosure may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0202] The motherboard 2001 may include a connector 2006, which includes a plurality of pins for connection to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. According to an example embodiment, the data storage system 2000 may communicate with the external host via any of an interface such as, but not limited to, USB, PCI-Express, Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Memory (UFS), etc. According to an example embodiment, the data storage system 2000 may be operated by power supplied from the external host through the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0203] The controller 2002 can write data to and / or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0204] DRAM 2004 may be and / or may include a buffer memory for mitigating speed differences between the semiconductor package 2003 (which may be data storage space) and an external host. DRAM 2004 included in the data storage system 2000 may also serve as a cache memory and may provide space for temporary data storage during control operations on the semiconductor package 2003. When DRAM 2004 is included in the data storage system 2000, controller 2002 may further include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003.

[0205] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0206] The package substrate 2100 may be a printed circuit board (PCB) including a package top pad 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 15 The input / output pads 1101. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include the above-referenced... Figures 1 to 13 The semiconductor device described.

[0207] According to an example embodiment, the connection structure 2400 may be a bonding wire for electrically connecting the input / output pads 2210 and the package top pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the package top pads 2130 of the package substrate 2100. According to an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a bonding wire-like connection structure 2400.

[0208] According to an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. According to an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via interconnects formed on the interposer substrate.

[0209] This disclosure is not limited to the embodiments and drawings described above, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, changes, and combinations to the exemplary embodiments without departing from the scope of this disclosure as defined by the appended claims, and such substitutions, modifications, or changes should be interpreted as being included within the scope of this disclosure.

[0210] This application claims priority to Korean Patent Application No. 10-2024-0157340, filed on November 7, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The first semiconductor structure includes: First substrate; Circuit elements are on the first substrate; The lower interconnect structure is connected to the circuit element; and The lower bonding structure is connected to the lower interconnect structure; and The second semiconductor structure includes: The upper joining structure is joined to the lower joining structure; Conductive layer; A stacked structure, below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the upper surface of the conductive layer; Multiple partitioned regions, at least partially penetrating the stacked structure, extend in a second direction and are spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, and the third direction being perpendicular to both the first and second directions; A channel structure, including a channel layer and at least partially penetrating the stacked structure in the first direction; Multiple address columns, spaced apart from each other by a first separation distance below at least one of the multiple separation regions in the second direction; Multiple channel pillars are located below the channel structure; and An upper interconnect structure is located below the stacked structure, connected to the plurality of channel posts, and spaced apart from the plurality of address posts.

2. The semiconductor device of claim 1, wherein each of the plurality of address pillars includes a first upper surface, a first lower surface, and a first side surface between the first upper surface and the first lower surface. Each of the plurality of channel posts includes a second upper surface, a second lower surface, and a second side surface between the second upper surface and the second lower surface. The first lower surface of the plurality of address posts is positioned at the same level as the second lower surface of the plurality of channel posts.

3. The semiconductor device of claim 2, wherein the first upper surface of the plurality of address pillars is disposed below the third lower surface of the at least one separating region. In each of the plurality of address columns, the width of the first upper surface is smaller than the width of the first lower surface, and The width of the third lower surface of at least one of the dividing regions is greater than the width of the first lower surface of each of the plurality of address posts.

4. The semiconductor device of claim 3, wherein the third lower surface of the at least one partition region is spaced apart from the first upper surface of each of the plurality of address pillars in the first direction.

5. The semiconductor device according to claim 3, further comprising: A base layer is located between the third lower surface of the at least one partitioned region and the first upper surface of each of the plurality of address posts.

6. The semiconductor device of claim 2, wherein a first reference line passing through the center of the first upper surface of each of the plurality of address pillars in the first direction is offset relative to a second reference line passing through the center of the width of the at least one dividing region in the third direction.

7. The semiconductor device according to claim 2, further comprising: An upper insulating layer is formed between the first lower surface of each of the plurality of address pillars and the upper interconnect structure. The plurality of address posts are isolated from the upper interconnect structure by the upper insulating layer.

8. The semiconductor device of claim 1, wherein the first length of each of the plurality of address pillars in the first direction is equal to the second length of each of the plurality of channel pillars in the first direction.

9. The semiconductor device of claim 1, wherein the first length of each of the plurality of address pillars in the first direction is less than the second length of each of the plurality of channel pillars in the first direction.

10. The semiconductor device of claim 1, wherein the upper interconnect structure includes bit lines connected to the plurality of channel pillars, extending upward in the third direction and spaced apart from each other in the second direction, and The first separation distance is a multiple of the pitch of the bit line.

11. The semiconductor device of claim 1, further comprising: An upper gate electrode is located between the channel structure and the plurality of channel posts; The upper channel structure at least partially penetrates the upper gate electrode and is connected to each channel structure in the channel structure; as well as An insulating region, at least partially penetrating the upper gate electrode and disposed below the plurality of partition regions, The plurality of address posts are located below the insulating region.

12. The semiconductor device of claim 11, wherein a first reference line passing through the center of the upper surface of each of the plurality of address posts in the first direction is coaxial with a second reference line passing through the center of the width of the at least one separating region in the third direction, and is offset from a third reference line passing through the center of the width of the insulating region in the third direction.

13. The semiconductor device of claim 11, wherein the width of the upper surface of each of the plurality of address pillars is less than the width of the lower surface of each of the plurality of partition regions.

14. A semiconductor device, comprising: The first semiconductor structure includes: First substrate; Circuit elements are on the first substrate; The lower interconnect structure is connected to the circuit element; and The lower bonding structure is connected to the lower interconnect structure; and The second semiconductor structure includes: The upper joining structure is joined to the lower joining structure; Conductive layer; A stacked structure, below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the upper surface of the conductive layer; A channel structure, including a channel layer and at least partially penetrating the stacked structure in the first direction; Multiple partition regions, at least partially penetrating the stacked structure, extend in a second direction and are spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, the third direction being perpendicular to both the first and second directions, the multiple partition regions including an address partition group, the address partition group including a first address partition region and a second address partition region adjacent to the first address partition region in the third direction; Multiple address columns, spaced apart from each other by a multiple of a unit separation distance in the second direction, and positioned below the first address separation region and the second address separation region; and Multiple channel columns are installed below the channel structure.

15. The semiconductor device of claim 14, wherein the first address separation region is provided every n separation regions in the third direction, where n is a positive integer greater than zero (0), and The second address separation region includes the remaining separation regions among the plurality of separation regions other than the first address separation region.

16. The semiconductor device of claim 14, wherein the plurality of address pillars includes at least one address pillar disposed at a location determined based on the same array rule for setting each address separation group in the address separation group.

17. The semiconductor device of claim 14, wherein the plurality of address pillars are arranged in different locations based on different array rules for setting the address separation group.

18. The semiconductor device of claim 14, further comprising: The upper interconnect structure is connected to the plurality of channel posts and spaced apart from the plurality of address posts. The upper interconnect structure includes bit lines connected to the plurality of channel posts, extending upward in the third direction, and spaced apart from each other in the second direction. The unit separation distance is a multiple of the bit line pitch.

19. A data storage system, comprising: Semiconductor devices, including: A first semiconductor structure includes a substrate and circuit elements on the substrate; A second semiconductor structure includes a stacked structure and a channel structure, the stacked structure including an interlayer insulating layer and a gate electrode stacked in a first direction, and the channel structure at least partially penetrating the stacked structure; and Input / output pads are connected to the circuit elements; and The controller is connected to the semiconductor device via the input / output pads and configured to control the semiconductor device. The first semiconductor structure further includes: The lower interconnect structure is connected to the circuit element; and The lower bonding structure is connected to the lower interconnect structure. The second semiconductor structure further includes: The upper interconnect structure is disposed below the stacked structure; An upper joining structure is connected to the upper interconnecting structure and joined to the lower joining structure; Multiple partitioned regions, at least partially penetrating the stacked structure and extending in a second direction, and spaced apart from each other in a third direction, the second direction being perpendicular to the first direction, and the third direction being perpendicular to both the first and second directions; Multiple address posts are disposed below at least one of the multiple partition regions and spaced apart from each other by a first partition distance in the second direction; and Multiple channel pillars, below the channel structure, and The upper interconnect structure is connected to the plurality of channel posts and spaced apart from the plurality of address posts.

20. The data storage system of claim 19, wherein the plurality of address columns are disposed only below a first address separation region among the plurality of separation regions in the second direction, and The first address separation region is set once every n separation regions in the third direction, where n is a positive integer greater than zero (0).

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