Multi-suspension shield grid MOSFET and preparation method thereof

Abstract

The invention provides a multi-suspension shield grid MOSFET and a preparation method thereof, a shield grid is divided into a left part, a middle part and a right part, the left part and the right part are symmetrically distributed along the middle part, the upper part width of the middle part is larger than the lower part width, and the top of the middle part is higher than the tops of the left part and the right part. The middle part of the shield gate is connected with a source electrode, the left and right parts are floating, in a blocking state, the left and right floating shield gates can improve electric field distribution in the middle of a drift region, the thicker field oxide layer at the bottom can bear a higher electric field, and device breakdown at the bottom of the shield gate electrode is avoided. The output capacitance Coss contributed by the shield gate electrode is reduced while the reliability is improved, the switching loss is reduced, and the on-resistance is lower when the withstand voltage is the same.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a multi-floating shielded gate MOSFET and its fabrication method. Background Technology

[0002] Shielded gate MOSFETs (SGT MOSFETs) improve power figure of merit while reducing gate-drain capacitance and lowering switching losses by introducing electrodes separate from the gate. With the increasing market demand for power MOSFETs in recent years, achieving a device with high breakdown voltage and low on-resistance is crucial. However, there is a certain trade-off between on-resistance (RDSON) and breakdown voltage (BVDSS). On-resistance is mainly determined by R... CH + R D + R SUB Composition, and as the breakdown voltage increases, R D This will increase significantly. Therefore, while increasing the breakdown voltage of the shielded gate MOSFET, it is necessary to further reduce the on-resistance of the device to improve its performance and competitiveness. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a multi-floating shielded gate MOSFET and its fabrication method, so as to solve the problem that the breakdown voltage of the shielded gate MOSFET increases while the on-resistance increases significantly.

[0004] To achieve the above and other related objectives, this application provides a multi-floating shielded gate MOSFET and its fabrication method. The technical solution is as follows: In a first aspect, embodiments of this application provide a multi-floating shielded gate MOSFET, comprising: a substrate, a buffer layer, and an epitaxial layer stacked from bottom to top; a shielded gate formed in the epitaxial layer, the shielded gate being divided into three parts: left, middle, and right, the left and right parts being symmetrically distributed along the middle part, the upper width of the middle part being greater than the lower width, and the top of the middle part being higher than the top of the left and right parts; and a gate formed in the epitaxial layer above the shielded gate, wherein the middle part of the shielded gate is connected to the source electrode, and the left and right parts are floating.

[0005] Secondly, embodiments of this application provide a method for fabricating a multi-floating shielded gate MOSFET, comprising: Step 1: Provide a substrate, and sequentially form a buffer layer and an epitaxial layer on the substrate. Form a trench in the epitaxial layer, and sequentially form a first oxide layer and a sacrificial material layer in the trench. Step two: Etch the sacrificial material layer and the first oxide layer sequentially; Step 3: After removing the sacrificial material layer, a second oxide layer and a first gate material layer are sequentially formed in the trench; Step 4: Grind the first gate material layer until the second oxide layer is exposed; Step 5: Etch the first gate material layer to make its upper part reach the preset thickness; Step six: Form a third oxide layer within the trench; Step 7: Etch the third oxide layer until the top of the first gate material layer is exposed; Step 8: Remove the exposed first gate material layer to form the left and right portions of the shielding gate; Step nine: Form a fourth oxide layer within the trench; Step 10: Form a second gate material layer in the trench, which constitutes the middle part of the shielding gate; Step 11: Form a fifth oxide layer in the trench, covering the top of the second gate material layer; Step 12: Sequentially form a gate dielectric layer and a third gate material layer within the trench.

[0006] Preferably, the material of the sacrificial material layer includes an anti-reflective coating.

[0007] Preferably, after step two is completed, the top of the sacrificial material layer is higher than the top of the first oxide layer.

[0008] Preferably, the step of forming the second oxide layer includes: forming the second oxide layer in the trench by a deposition process to cover the first oxide layer; and performing an annealing process to make the formed oxide layer dense.

[0009] Preferably, after the third oxide layer is formed, the width of the trench opening is greater than the top width of the lower part of the first gate material layer.

[0010] Preferably, the third oxide layer consists of an oxide layer formed by a thermal oxidation process and an oxide layer formed by a deposition process.

[0011] Preferably, after step seven, the top corner of the third oxide layer is rounded.

[0012] Preferably, the removal is carried out in step eight by a sidewall blocking etching process.

[0013] Preferably, after the fourth oxide layer is formed, the width of the upper gap in the trench is greater than the width of the lower gap, and the left and right parts of the shielding grid constitute a suspended shielding grid.

[0014] Preferably, the fourth oxide layer consists of an oxide layer formed by a thermal oxidation process and an oxide layer formed by a deposition process.

[0015] Preferably, the step of forming a fifth oxide layer in the trench includes: forming a fifth oxide layer by a high aspect ratio deposition process, covering the fourth oxide layer while filling the trench; removing the oxide layer located outside the trench by a polishing process; and etching the oxide layer located inside the trench to expose part of the sidewall of the trench but not the top of the second gate material layer.

[0016] Preferably, after forming a third gate material layer in the trench, the method further includes: performing well region implantation; forming an interlayer dielectric layer; forming a contact hole and performing contact hole implantation; filling the contact hole with a metal contact plug; forming a source electrode and a gate electrode, and connecting them through the metal contact plug.

[0017] As described above, the multi-floating shielded gate MOSFET and its fabrication method provided in this application have the following beneficial effects: In the blocking state, the left and right floating shielded gates can improve the electric field distribution in the middle of the drift region, and the thicker field oxide layer at the bottom can withstand a higher electric field, avoiding device breakdown at the bottom of the shielded gate electrode, improving reliability while reducing the output capacitance Coss contributed by the shielded gate electrode, reducing switching losses, and having a lower on-resistance when the withstand voltage is the same. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 The diagram shown is a cross-sectional view of the multi-floating shielded gate MOSFET provided in an embodiment of this application. Figure 2 The flowchart shown is a method for fabricating a multi-floating shielded gate MOSFET provided in an embodiment of this application; Figure 3 The diagram shown is a cross-sectional view of the device structure formed after step one in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 4 The diagram shown is a cross-sectional view of the device structure formed after step two in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 5 The diagram shown is a cross-sectional view of the device structure formed after step three in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 6The diagram shown is a cross-sectional view of the device structure formed after step four in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 7 The diagram shown is a cross-sectional view of the device structure formed after step five in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 8 The diagram shown is a cross-sectional view of the device structure formed after step six in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 9 The diagram shown is a cross-sectional view of the device structure formed after step seven in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 10 The diagram shown is a cross-sectional view of the device structure formed after step eight in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 11 The diagram shown is a cross-sectional view of the device structure formed after step nine in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 12 The diagram shown is a cross-sectional view of the device structure formed after step ten in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 13 The diagram shown is a cross-sectional view of the device structure formed after step eleven in the fabrication method of the multi-floating shielded gate MOSFET provided in the embodiments of this application. Figure 14 The diagram shown is a cross-sectional view of the device formed after step twelfth in the fabrication method of the multi-floating shielded gate MOSFET provided in this application embodiment. Detailed Implementation

[0020] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0021] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0025] Please see Figure 1 The diagram shows a cross-sectional view of the multi-floating shielded gate MOSFET provided in an embodiment of this application.

[0026] like Figure 1 As shown, the multi-floating shielded gate MOSFET includes: a substrate 100, a buffer layer 101, and an epitaxial layer 102 stacked from bottom to top; a shielded gate 103 formed in the epitaxial layer 102, which is divided into three parts: left, middle, and right. The left and right parts are symmetrically distributed along the middle part, the upper width of the middle part is greater than the lower width, and the top of the middle part is higher than the top of the left and right parts; and a gate 105 formed in the epitaxial layer 102 above the shielded gate 103. The oxide surrounding the shielded gate 103 and the gate dielectric layer of the gate 105 are made of the same material and are not distinguished by marking.

[0027] The middle part of the shielding gate 103 is connected to the source electrode, while the left and right parts are floating. In the blocking state, the floating shielding gates on the left and right can improve the electric field distribution in the middle of the drift region. The thicker field oxide layer at the bottom can withstand a higher electric field, preventing device breakdown from occurring at the bottom of the shielding gate electrode. This improves reliability while reducing the output capacitance Coss contributed by the shielding gate electrode, thus reducing switching losses. The upper width of the middle part of the shielding gate 103 is greater than the lower width, resulting in a lower on-resistance.

[0028] Please see Figure 2 The diagram illustrates a flowchart of a method for fabricating a multi-floating shielded gate MOSFET according to an embodiment of this application. like Figure 2 As shown, the fabrication method of this multi-floating shielded gate MOSFET includes the following steps: Step 1: Provide a substrate, and sequentially form a buffer layer and an epitaxial layer on the substrate. Form a trench in the epitaxial layer, and sequentially form a first oxide layer and a sacrificial material layer in the trench. Step two: Etch the sacrificial material layer and the first oxide layer sequentially; Step 3: After removing the sacrificial material layer, a second oxide layer and a first gate material layer are sequentially formed in the trench; Step 4: Grind the first gate material layer until the second oxide layer is exposed; Step 5: Etch the first gate material layer to make its upper part reach the preset thickness; Step six: Form a third oxide layer within the trench; Step 7: Etch the third oxide layer until the top of the first gate material layer is exposed; Step 8: Remove the exposed first gate material layer to form the left and right portions of the shielding gate; Step nine: Form a fourth oxide layer within the trench; Step 10: Form a second gate material layer in the trench, which constitutes the middle part of the shielding gate; Step 11: Form a fifth oxide layer in the trench, covering the top of the second gate material layer; Step 12: Sequentially form a gate dielectric layer and a third gate material layer within the trench.

[0029] In step one, as Figure 3 As shown, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 300 may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the constituent material of the substrate 300 according to the type of device structure formed on the substrate 300, therefore the type of substrate 300 should not limit the scope of protection of this invention.

[0030] As an example, a buffer layer 301 is formed on a substrate 300 using a deposition process. Exemplarily, the buffer layer 301 is N- doped, and the dopants include ions such as P, As, and Sb.

[0031] As an example, an epitaxial layer 302 is formed on the buffer layer 301 using an epitaxial growth process. Exemplarily, the epitaxial layer 302 is an N-type epitaxial layer, wherein the dopants include P, As, Sb ions, etc.

[0032] As an example, the step of forming a trench in the epitaxial layer 302 includes: forming a hard mask layer on the surface of the epitaxial layer 302, the material of which may be silicon oxide or silicon nitride; coating photoresist on the surface of the hard mask layer and defining the trench formation area using a photolithography process; etching the hard mask layer using the photoresist as a mask, the etching process removing the hard mask layer located in the formation area and retaining the hard mask layer outside the formation area; removing the photoresist and etching the epitaxial layer 302 using the hard mask layer as a mask to form a trench; removing the hard mask layer, and then forming a sacrificial oxide layer on the bottom surface and side surfaces of the trench and on the surface of the epitaxial layer 302 outside the trench and removing it by wet etching to repair the damage caused during the dry etching process of forming the trench.

[0033] Next, a first oxide layer is formed on the epitaxial layer 302 to cover the inner surface of the trench, and then a sacrificial material layer 303 is formed on the epitaxial layer 302 to fill the trench.

[0034] For example, a first oxide layer and a sacrificial material layer 303 are formed by a deposition process. The material of the first oxide layer includes silicon oxide, and the material of the sacrificial material layer 303 includes an anti-reflective coating, such as TARC or BARC.

[0035] In step two, the sacrificial material layer 303 is etched first, followed by the first oxide layer, as follows: Figure 4 As shown, the top of the sacrificial material layer 303 is higher than the top of the first oxide layer. Exemplarily, the etching in step two is all dry etching.

[0036] In step three, as Figure 5 As shown, after the sacrificial material layer 303 is removed by etching, a second oxide layer and a first gate material layer 305 are sequentially formed in the trench. The second oxide layer and the first oxide layer are made of the same material and are not distinguished in the illustration.

[0037] As an example, the steps for forming the second oxide layer include: forming the second oxide layer in the trench by a deposition process, covering the previously formed first oxide layer; and performing an annealing process to make the formed oxide layers (the second oxide layer and the first oxide layer) dense.

[0038] As an example, a first gate material layer 305 is formed by a deposition process to fill the trench. Exemplarily, the material of the first gate material layer 305 includes polysilicon.

[0039] In step four, as Figure 6 As shown, the first gate material layer 305 is ground until the second oxide layer is exposed. Exemplarily, this grinding is chemical mechanical polishing.

[0040] In step five, the first gate material layer 305 is etched so that the thickness of its upper part reaches a preset value, such as... Figure 7As shown, the width of the upper part of the first gate material layer 305 is greater than the width of the lower part. In this case, the thickness of the upper part of the first gate material layer 305 is the thickness of the left and right parts of the subsequently formed shielding gate. For example, this etching is a dry etching process.

[0041] In step six, as Figure 8 As shown, a third oxide layer is formed within the trench. The width of the trench opening is greater than the top width of the lower portion of the first gate material layer 305, ensuring smooth filling of the gate material layer when the middle portion of the shielding gate is subsequently formed. The third oxide layer and the second oxide layer are made of the same material and are not distinguished in the illustration.

[0042] For example, an oxide layer is first formed on top of the first gate material layer 305 by a thermal oxidation process, and then another oxide layer covering the second oxide layer and the oxide layer is formed by a deposition process. That is, the third oxide layer is composed of the oxide layer formed by the thermal oxidation process and the oxide layer formed by the deposition process.

[0043] In step seven, as Figure 9 As shown, the third oxide layer is etched until the top of the first gate material layer 305 is exposed. Exemplarily, this etching is a dry etching process. After this etching, the top corner of the third oxide layer is rounded.

[0044] In step eight, as Figure 10 As shown, the exposed first gate material layer 305 is removed to form the left and right portions of the shielding gate. Exemplarily, this removal is performed using a sidewall blocking etching process, which is highly selective for the first gate material layer 305 and the third and second oxide layers. This etching is equivalent to sidewall blocking etching, with the oxide layers composed of the third and second oxide layers serving as sidewalls on the upper and lower sides of the remaining first gate material layer 305 after etching.

[0045] In step nine, as Figure 11 As shown, a fourth oxide layer is formed within the trench. At this point, the width of the upper gap within the trench is greater than the width of the lower gap. The fourth oxide layer and the third oxide layer are made of the same material and are not distinguished in the illustration. Compared to existing technologies, a thicker field oxide layer is formed at the bottom of the trench.

[0046] For example, an oxide layer is first formed on the surface of the exposed first gate material layer 305 by a thermal oxidation process, and then another oxide layer covering the third oxide layer and the oxide layer is formed by a deposition process. That is, the fourth oxide layer is composed of the oxide layer formed by the thermal oxidation process and the oxide layer formed by the deposition process.

[0047] After step nine is completed, the first gate material layer 305 (i.e. the left and right parts of the shielding gate) constitutes the floating shielding gate.

[0048] In step ten, as Figure 12 As shown, a second gate material layer 306 is formed in the trench, constituting the middle part of the shielding gate.

[0049] For example, a second gate material layer 306 is first formed to fill the trench, i.e. Figure 11 The upper and lower gaps are formed in the middle trench; then, through an etching process, the top of the second gate material layer 306 is made higher than the top of the first gate material layer 305 and lower than the top of the epitaxial layer 302.

[0050] In step eleven, as Figure 13 As shown, a fifth oxide layer is formed within the trench, covering the top of the second gate material layer 306. The fifth oxide layer and the fourth oxide layer are made of the same material and are not distinguished in the illustration.

[0051] For example, the step of forming a fifth oxide layer in the trench includes: forming a fifth oxide layer by a high aspect ratio deposition process, covering the fourth oxide layer while filling the trench; removing the oxide layer (including the fifth oxide layer, the fourth oxide layer, the third oxide layer and the second oxide layer) located outside the trench by a polishing process; and etching the oxide layer located in the trench to expose part of the sidewall of the trench but not the top of the second gate material layer 306.

[0052] In step twelf, as Figure 14 As shown, a gate dielectric layer and a third gate material layer 307 are sequentially formed within the trench. The gate dielectric layer and the fifth oxide layer are made of the same material and are not distinguished in the illustration.

[0053] Next, well region implantation is performed; an interlayer dielectric layer is formed; contact holes are formed, and contact hole implantation is performed; metal contact plugs are filled into the contact holes; source electrodes and gate electrodes are formed and connected through the metal contact plugs.

[0054] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] In summary, the multi-floating shielded gate MOSFET and its fabrication method provided in this application, under the blocking state, improve the electric field distribution in the middle of the drift region through the left and right floating shielded gates. The thicker field oxide layer at the bottom can withstand a higher electric field, preventing device breakdown from occurring at the bottom of the shielded gate electrode. This improves reliability while reducing the output capacitance Coss contributed by the shielded gate electrode, thus reducing switching losses. Furthermore, it exhibits lower on-resistance while maintaining the same withstand voltage. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0056] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A multi-floating shielded gate MOSFET, characterized in that, The multi-floating shielded gate MOSFET includes: a substrate, a buffer layer, and an epitaxial layer stacked from bottom to top; a shielded gate formed in the epitaxial layer, the shielded gate being divided into three parts: left, middle, and right, the left and right parts being symmetrically distributed along the middle part, the upper width of the middle part being greater than the lower width, and the top of the middle part being higher than the top of the left and right parts; and a gate formed in the epitaxial layer above the shielded gate, wherein the middle part of the shielded gate is connected to the source electrode, and the left and right parts are floating.

2. A method for fabricating a multi-floating shielded gate MOSFET, characterized in that, The method includes: Step 1: Provide a substrate, and sequentially form a buffer layer and an epitaxial layer on the substrate, form a trench in the epitaxial layer, and sequentially form a first oxide layer and a sacrificial material layer in the trench; Step two: Etch the sacrificial material layer and the first oxide layer sequentially; Step 3: After removing the sacrificial material layer, a second oxide layer and a first gate material layer are sequentially formed in the trench; Step 4: Grind the first gate material layer until the second oxide layer is exposed; Step 5: Etch the first gate material layer to make its upper part reach a preset thickness; Step six: Form a third oxide layer in the trench; Step 7: Etch the third oxide layer until the top of the first gate material layer is exposed; Step 8: Remove the exposed first gate material layer to form the left and right portions of the shielding gate; Step nine, forming a fourth oxide layer within the trench; Step 10: A second gate material layer is formed in the trench, constituting the middle part of the shielding gate; Step 11: A fifth oxide layer is formed in the trench, covering the top of the second gate material layer; Step 12: A gate dielectric layer and a third gate material layer are sequentially formed in the trench.

3. The method according to claim 2, characterized in that, The material of the sacrificial material layer includes an anti-reflective coating.

4. The method according to claim 2, characterized in that, After step two is completed, the top of the sacrificial material layer is higher than the top of the first oxide layer.

5. The method according to claim 2, characterized in that, The step of forming the second oxide layer includes: forming the second oxide layer in the trench by a deposition process to cover the first oxide layer; and performing an annealing process to make the formed oxide layer dense.

6. The method according to claim 2, characterized in that, After the third oxide layer is formed, the width of the trench opening is greater than the top width of the lower part of the first gate material layer.

7. The method according to claim 2 or 6, characterized in that, The third oxide layer consists of an oxide layer formed by a thermal oxidation process and an oxide layer formed by a deposition process.

8. The method according to claim 2, characterized in that, After step seven is completed, the top corner of the third oxide layer is rounded.

9. The method according to claim 2, characterized in that, In step eight, the removal is carried out using a sidewall blocking etching process.

10. The method according to claim 2, characterized in that, After the fourth oxide layer is formed, the width of the upper gap in the trench is greater than the width of the lower gap, and the left and right parts of the shielding grid constitute a suspended shielding grid.

11. The method according to claim 2 or 10, characterized in that, The fourth oxide layer consists of an oxide layer formed by a thermal oxidation process and an oxide layer formed by a deposition process.

12. The method according to claim 2, characterized in that, The step of forming the fifth oxide layer in the trench includes: forming the fifth oxide layer by a high aspect ratio deposition process, covering the fourth oxide layer while filling the trench; removing the oxide layer located outside the trench by a polishing process; and etching the oxide layer located inside the trench to expose part of the sidewall of the trench but not the top of the second gate material layer.

13. The method according to claim 2, characterized in that, After forming a third gate material layer in the trench, the method further includes: performing well region implantation; forming an interlayer dielectric layer; forming a contact hole and performing contact hole implantation; filling the contact hole with a metal contact plug; forming a source electrode and a gate electrode, and connecting them through the metal contact plug.

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