Ultra-high voltage mosfet termination structure

Abstract

The utility model provides a kind of ultrahigh pressure MOSFET terminal structure, above-mentioned terminal structure includes: substrate, it is in and set up main knot and VLD knot, the depth of the VLD knot gradually becomes smaller along the direction away from the main knot;Oxide layer is located on the substrate;Polysilicon field plate is located on the oxide layer;Dielectric layer is located on the polysilicon field plate;And metal field plate is located on the dielectric layer.The utility model embodiment is changed by setting VLD knot and its depth, and is matched with polysilicon field plate and metal field plate, while guaranteeing high pressure resistance, so that terminal structure is shorter, cost is less, and reliability is higher.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor device technology, and in particular to an ultra-high voltage MOSFET termination structure. Background Technology

[0002] Ultra-high voltage MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are characterized by low control power and fast switching speed, and are widely used in industrial power supplies, photovoltaic energy storage, instrumentation, medical and aerospace applications, rail transportation, and State Grid power supply. The technical challenge lies in the design of the termination structure. The main function of the termination structure is to optimize the surface electric field distribution, preventing premature breakdown at the device edges due to electric field concentration, thereby increasing the breakdown voltage. To meet the ultra-high voltage withstand requirements of the termination, the design size of the termination in ultra-high voltage applications is inevitably much larger than that in medium-high voltage applications, resulting in an increase in the overall chip size. Therefore, how to achieve a shorter termination length and higher reliability while ensuring voltage withstand capability has become a key issue in device design. Utility Model Content

[0003] In order to improve at least some of the shortcomings or deficiencies in the prior art, embodiments of the present invention provide an ultra-high voltage MOSFET termination structure that, while ensuring high withstand voltage, makes the termination structure shorter, less expensive, and more reliable.

[0004] This invention provides an ultra-high voltage MOSFET termination structure, comprising: a substrate having a main junction and a VLD junction disposed therein, the depth of the VLD junction gradually decreasing in the direction away from the main junction; an oxide layer located on the substrate; a polysilicon field plate located on the oxide layer; a dielectric layer located on the polysilicon field plate; and a metal field plate located on the dielectric layer.

[0005] In some embodiments, the VLD junction includes a plurality of field limiting loops, the depth of which gradually decreases along a direction away from the main junction.

[0006] In some embodiments, the resistivity of the substrate is 150 Ω•cm to 170 Ω•cm, the thickness of the substrate is 300 μm to 380 Ω•cm, and the length of the substrate is 650 μm.

[0007] In some embodiments, a cutoff ring is further disposed on the substrate, and the VLD junction is located between the main junction and the cutoff ring.

[0008] In some embodiments, a stop field plate is formed on the oxide layer, with one end of the stop field plate located on the oxide layer and the other end overlapping the stop ring.

[0009] In some embodiments, the length of the cutoff field plate is 18.5 μm.

[0010] In some embodiments, the number of polycrystalline silicon field plates is 19.

[0011] In some embodiments, the length of the polycrystalline silicon field plate is 20 μm.

[0012] In some embodiments, the spacing between each pair of adjacent polycrystalline silicon field plates is 4 μm.

[0013] In some embodiments, a passivation layer is further included on the metal field plate.

[0014] As can be seen from the above, the above-mentioned technical features of this utility model can have one or more of the following beneficial effects: The ultra-high voltage MOSFET termination structure provided by the embodiment of this utility model, through the gradient VLD junction design, its depth gradually decreases along the direction away from the main junction, optimizes the electric field distribution, reduces the risk of electric field concentration, improves the breakdown voltage of the termination structure, has high withstand voltage capability, and meets the ultra-high voltage application scenarios; and the combined application of VLD junction with polysilicon field plate and metal field plate enables the termination structure to achieve ultra-high withstand voltage within a short length, effectively reducing chip area and manufacturing cost. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of an ultra-high voltage MOSFET termination structure provided in an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of a photolithographic windowing structure in an ultra-high voltage MOSFET terminal structure provided for an embodiment of this utility model.

[0018] Figure 3 This is a schematic diagram of a doping impurity implantation structure in an ultra-high voltage MOSFET terminal structure provided in an embodiment of this utility model.

[0019] Figure 4 This is a schematic diagram of a polysilicon field plate formed in an ultra-high voltage MOSFET terminal structure provided in an embodiment of the present invention.

[0020] Figure label:

[0021] 10. Substrate; 20. Oxide layer; 210. Terminal injection window; 220. Main junction injection window; 30. Main junction; 40. VLD junction; 50. Polysilicon field plate; 60. Metal field plate; 70. Cut-off field plate; 80. Cut-off ring. Detailed Implementation

[0022] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0023] See Figure 1 This invention provides an ultra-high voltage MOSFET termination structure formed according to the above method, including a substrate 10, an oxide layer 20, a polysilicon field plate 50, a dielectric layer, and a metal field plate 60. A main junction 30 and a VLD junction 40 are disposed within the substrate 10. The depth of the VLD junction 40 gradually decreases away from the main junction 30. This gradual doping concentration distribution effectively expands the depletion region, reduces the electric field peak, and thus optimizes the electric field distribution at the device edge, avoiding local electric field concentration. The oxide layer 20 is located on the substrate 10, the polysilicon field plate 50 is located on the oxide layer 20, the dielectric layer is located on the polysilicon field plate 50, and the metal field plate 60 is located on the dielectric layer. The polysilicon field plate 50 and the metal field plate 60 work synergistically to further improve the electric field distribution, reduce electric field concentration, and improve the device's withstand voltage capability. This termination structure can reduce the size of the termination structure, increase chip integration, and reduce manufacturing costs by optimizing the doping and electric field distribution while ensuring withstand voltage capability.

[0024] Please see again Figure 1 The VLD junction 40 includes multiple field-limiting rings 410, the depth of which gradually decreases away from the main junction 30. The PN junctions formed by the field-limiting rings 410 are connected together, allowing the VLD terminal junctions to form a large, continuous PN junction, with the junction depth gradually decreasing away from the main junction 30. The field-limiting rings 410 are doped with impurities such as P-type ions, ensuring that the concentration of impurities in the VLD junction 40 varies linearly in the lateral direction of the junction push-in, thereby eliminating peak electric fields, making the surface electric field uniform, and thus improving the breakdown voltage.

[0025] In some embodiments, the resistivity of substrate 10 is 150 Ω•cm to 170 Ω•cm to suppress lateral leakage current; the thickness of substrate 10 is 300 μm to 380 μm to extend the longitudinal breakdown path; and the length of substrate 10 is 650 μm. This combination allows the device to meet voltage withstand requirements while avoiding excessive chip size due to excessive thickness.

[0026] See Figure 1 and Figure 4 In some embodiments, a cutoff ring 80 is also provided on the substrate 10. The cutoff ring 80 is located at the edge of the termination structure, and the VLD junction 40 is located between the main junction 30 and the cutoff ring 80. The depth of the VLD junction 40 gradually decreases from the main junction 30 to the cutoff ring 80, reducing the accumulation of strong electric field at the end of the termination structure. This allows the PN junction depletion region to quickly cut off after extending to the cutoff ring 80, reducing the possibility of leakage current in the termination structure.

[0027] See Figure 1 In some embodiments, a cutoff field plate 70 is formed on the oxide layer 20, with one end of the cutoff field plate 70 located on the oxide layer 20 and the other end overlapping the cutoff ring 80. The cutoff field plate 70 can transfer a portion of the bulk electric field of the substrate 10 onto the oxide layer 20, further reducing the leakage current of the device, improving the regional field strength, reducing regional field strength concentration, and thus improving the withstand voltage of the termination structure.

[0028] Furthermore, the length of the cutoff field plate 70 is, for example, 18.5 μm.

[0029] In some embodiments, the number of polysilicon field plates 50 is, for example, 19.

[0030] In some embodiments, the length of the polysilicon field plate 50 is, for example, 20 μm.

[0031] See Figure 1 and Figure 4 In some embodiments, the spacing between any two adjacent polysilicon field plates 50 is 4 μm. The polysilicon field plates 50 effectively smooth the longitudinal electric field distribution through the electric field superposition effect. The cutoff field plate 70 is slightly shorter than the other polysilicon field plates 50, forming a gradual electric field attenuation at the terminal end, avoiding premature breakdown caused by concentrated electric field at the edges.

[0032] In some embodiments, a passivation layer (not shown) is also included on the metal field plate 60. The passivation layer isolates the device from ambient moisture, ionic contaminants, and particles, preventing device failure due to corrosion or leakage. High-dose back-side implantation forms a highly doped region on the back side of the substrate 10, creating a low-resistance contact and stopping the depletion region from expanding at the substrate edge, thus preventing edge breakdown and improving reliability.

[0033] Specifically, the above-mentioned ultra-high voltage MOSFET termination structure can be prepared by the following method, wherein the preparation method of the ultra-high voltage MOSFET termination structure includes:

[0034] Step S10: Provide substrate 10.

[0035] Step S20: An oxide layer 20 is formed on the substrate 10.

[0036] Step S30: A main junction 30 and a VLD junction 40 are formed in the substrate 10.

[0037] Step S40: A polycrystalline silicon field plate 50 is deposited on the oxide layer 20;

[0038] Step S50: Deposit a metal field plate 60 on the polycrystalline silicon field plate 50.

[0039] In step S10, substrate 10 is a silicon substrate. Since the substrate material of ultra-high voltage devices needs to use a relatively thick low-doped layer, generally greater than 300 μm, and silicon-based wafers cannot achieve such a thick epitaxial process, a low-doped single crystal material is selected as the substrate material.

[0040] In step S20, the substrate 10 undergoes field oxidation to form an oxide layer 20 with a thickness of, for example, 4000 angstroms, for subsequent deposition of the polysilicon field plate 50; then, it undergoes a second oxidation to form an oxide layer 20 with a thickness of, for example, 20000 angstroms, for subsequent deposition of the polysilicon field plate 50. The thick oxide layer, through its high dielectric strength, suppresses surface electric field concentration, especially the lateral electric field peak in the terminal region. As an insulating layer between the polysilicon field plate 50 and the underlying substrate 10, the oxide layer 20 prevents the polysilicon field plate 50 from directly contacting the semiconductor surface, avoiding leakage current or short circuit risks, and providing a flat and stable surface for the deposition and etching of the polysilicon field plate 50, ensuring the precise forming of the field plate structure.

[0041] See Figure 3 In step S30, the depth of the VLD junction 40 gradually decreases along the direction away from the main junction 30, forming a laterally gradient doping concentration distribution in the VLD junction 40. This effectively expands the depletion region, reduces the electric field peak, and thus improves the device's breakdown voltage capability. The VLD junction 40 includes multiple field limiting rings 410, and the PN junctions formed by each field limiting ring 410 are connected together, allowing the VLD terminal junctions to form a large, continuous PN junction, with the junction depth gradually decreasing along the direction away from the main junction 30.

[0042] See Figure 1 and Figure 4 In steps S40 and S50, the metal field plate 60 can be made of copper, aluminum, or tungsten. In this embodiment, the metal field plate 60 is made of aluminum. The polycrystalline silicon field plate 50 and the metal field plate 60 are used to improve the electric field distribution of the semiconductor device. By changing the electric field distribution, the electric field concentration phenomenon is reduced, thereby improving the device's withstand voltage and reliability.

[0043] This embodiment uses lateral variable doping technology to form a terminal PN junction, and uses a terminal structure made of polysilicon field plate 50 and metal field plate 60. The terminal withstand voltage can reach more than 3100V. While ensuring the withstand voltage, the manufactured terminal structure is shorter and smaller. Through the synergistic effect of polysilicon field plate and metal field plate, the electric field concentration phenomenon is reduced and the reliability is improved.

[0044] Specifically, see Figure 2 and Figure 3 Step S30 specifically includes:

[0045] Step S31: Multiple terminal injection windows 210 are horizontally opened on the oxide layer 20.

[0046] Step S32: Doped impurities are injected into the substrate 10 through multiple terminal injection windows 210.

[0047] Step S33: Open a main junction injection window 220 on the oxide layer 20.

[0048] Step S34: Doped impurities are injected into the substrate 10 through the main junction injection window 220.

[0049] Step S35: High-temperature junction pushing is performed to form a continuous VLD junction 40 by the doped impurities injected through the terminal injection window 210, and to form a main junction by the doped impurities injected through the main junction injection window 220.

[0050] In step S31, the terminal injection window 210 is photolithographically formed using photoresist, and the oxide layer 20 of the terminal injection window 210 is removed by etching, thus removing the photoresist and exposing the terminal injection window 210. The width difference between any two adjacent terminal injection windows 210 can be, for example, 0 μm - 0.2 μm, the width range of the terminal injection window 210 is, for example, 1 μm - 7 μm, and the distance between any two adjacent terminal injection windows 210 ranges, for example, 3 μm - 10.5 μm; and the width of the multiple terminal injection windows 210 gradually decreases, while the distance between any two adjacent terminal injection windows 210 gradually increases. The width of the multiple terminal injection windows 210 can be designed to gradually decrease along the direction away from the main junction 30; specifically, the width difference between any two adjacent terminal injection windows 210 can be, for example, 0 μm, 0.10 μm, 0.15 μm, or 0.20 μm.

[0051] In step S32, doped impurities are injected into the substrate 10 through the terminal injection window 210. The substrate 10 is of a first conductivity type, and the doped impurities are of a second conductivity type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. Specifically, the doped impurities are boron ions.

[0052] In step S33, the oxide layer 20 is subjected to main junction photolithography to etch the main junction implantation window 220. The width of the main junction implantation window 220 is, for example, greater than 35 μm.

[0053] In step S34, boron ions, a dopant, are injected through the main junction implantation window 220. After the main junction implantation is completed, the photoresist is removed.

[0054] In step S35, for example, the device is advanced at 1150°C for more than 300 minutes, causing the dopant injected through the main junction implantation window 220 to form the main junction 30; and causing the dopant injected through the terminal implantation window 210 to form a continuous VLD junction 40, that is, the dopant of each terminal implantation window 210 diffuses and forms a PN junction (i.e., field-limiting ring), and these field-limiting rings constitute a VLD junction 40 with a linearly varying concentration of implanted dopant. Specifically, the high-temperature process causes the boron ion impurities in the terminal implantation window 210 to diffuse laterally and vertically. Lateral diffusion connects the PN junctions of each terminal implantation window 210 together to form a long series PN junction (i.e., VLD junction 40); vertical diffusion causes the main junction 30 and the PN junction to reach a specified depth.

[0055] In this design, the widths of multiple terminal injection windows 210 decrease sequentially away from the main junction 30, while the distance between any two adjacent terminal injection windows 210 increases sequentially away from the main junction 30. Because the widths of the terminal injection windows 210 differ, the impurity concentration in each terminal injection window 210 will be different after boron ion implantation. Narrower terminal injection windows 210 have lower impurity concentrations, resulting in a shallower PN junction (i.e., field-limiting ring) formed after push-junction. Therefore, the PN junction is deeper near the main junction 30 and shallower away from it, ensuring a linear lateral variation in the concentration of implanted doped impurities. This eliminates spike electric fields, makes the surface electric field uniform, and thus improves the breakdown voltage.

[0056] In some embodiments, the energy of the dopant injected through the terminal injection window 210 is less than the energy of the dopant injected through the main junction injection window 220. This ensures a higher PN junction concentration and a deeper PN junction in the main junction 30, which is beneficial for optimizing the electric field of the terminal structure.

[0057] Specifically, the energy range of the dopant injected through the terminal injection window 210 is 60 KeV-100 KeV. The dopant in this terminal region has a shallow penetration depth in the substrate 10, forming shallow doping. Combined with subsequent high-temperature junction push-in, this results in significant lateral diffusion of the dopant, creating multiple PN junctions in series to form a gradient and disperse the surface electric field. The energy range of the dopant injected through the main junction injection window 220 is 80 KeV-120 KeV, allowing for deeper penetration. Combined with a high dose, this forms a deep and high-concentration PN junction. After high-temperature junction push-in, the junction depth of the main junction region is deeper than that of the terminal region. The high-concentration doping reduces the on-resistance of the main junction 30, improves current carrying capacity, and optimizes the longitudinal electric field distribution through the deep junction structure, preventing premature breakdown in the main junction region and contributing to electric field optimization. Furthermore, the dose of the dopant injected through the terminal injection window 210 is less than the dose of the dopant injected through the main junction injection window 220.

[0058] See Figure 3 In some embodiments, before depositing the polysilicon field plate 50 on the oxide layer 20 in step S40, the process further includes active region photolithography, defining the boundary between the active region and the terminal region using a photoresist mask; selectively etching the oxide layer 20 (i.e., the secondary field oxide layer) on the surface of the active region to expose the substrate 10, providing a clean substrate 10 for subsequent processes such as gate oxidation, source implantation, and metal contact, and maintaining the thick oxide layer in the terminal region to ensure that its withstand voltage performance is not affected; removing the photoresist residue after photolithography to ensure surface cleanliness and avoid introducing impurities or defects from photolithography residue, which could affect device reliability.

[0059] Furthermore, after step S40, the process also includes: P-well implantation; P+ lithography / implantation / resin removal; P-well push-in; N+ lithography / implantation / resin removal.

[0060] See Figure 1 and Figure 4 In some embodiments, step S50, which involves depositing a metal field plate 60 on the polysilicon field plate 50, includes forming a dielectric layer on the polysilicon field plate 50 by photolithography and etching.

[0061] Hole lithography and etching are performed on the dielectric layer;

[0062] Metal field plate 60 is formed by metal deposition on the dielectric layer.

[0063] The dielectric layer can be made of materials such as phosphosilicate glass (PSG), undoped silicon glass (USG), borosilicate glass (BPSG), or a two-layer composite material of USG and PSG or BPSG.

[0064] Following step S50, the process further includes: depositing silicon dioxide and silicon oxide, depositing a passivation layer; and performing high-dose backside implantation on substrate 10. The passivation layer isolates the device from environmental moisture, ionic contaminants, and particles, preventing device failure due to corrosion or leakage. High-dose backside implantation creates a highly doped region on the backside of substrate 10, forming a low-resistance contact and stopping the depletion region from expanding at the substrate edge, thus preventing edge breakdown and improving reliability.

[0065] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0066] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of this utility model. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of this utility model is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A high-voltage MOSFET termination structure, characterized in that, include: The substrate (10) has a main junction (30) and a VLD junction (40) disposed therein, wherein the depth of the VLD junction (40) gradually decreases in the direction away from the main junction (30); An oxide layer (20) is located on the substrate (10); A polycrystalline silicon field plate (50) is located on the oxide layer (20); A dielectric layer is located on the polycrystalline silicon field plate (50); and A metal field plate (60) is located on the dielectric layer.

2. The ultra-high voltage MOSFET termination structure as described in claim 1, characterized in that, The VLD junction (40) includes a plurality of field limiting rings (410), the depth of which gradually decreases along the direction away from the main junction (30).

3. The ultra-high voltage MOSFET termination structure as described in claim 1, characterized in that, The resistivity of the substrate (10) is 150Ω•cm to 170Ω•cm, the thickness of the substrate (10) is 300μm to 380μm, and the length of the substrate (10) is 650μm.

4. The ultra-high voltage MOSFET termination structure as described in claim 1, characterized in that, A cutoff ring (80) is also provided on the substrate (10), and the VLD junction (40) is located between the main junction (30) and the cutoff ring (80).

5. The ultra-high voltage MOSFET termination structure as described in claim 4, characterized in that, A stop field plate (70) is formed on the oxide layer (20), with one end of the stop field plate (70) located on the oxide layer (20) and the other end overlapping the stop ring (80).

6. The ultra-high voltage MOSFET termination structure as described in claim 5, characterized in that, The length of the cutoff field plate (70) is 18.5 μm.

7. The ultra-high voltage MOSFET termination structure as described in claim 1, characterized in that, The number of polycrystalline silicon field plates (50) is 19.

8. The ultra-high voltage MOSFET termination structure as described in claim 7, characterized in that, The length of the polycrystalline silicon field plate (50) is 20 μm.

9. The ultra-high voltage MOSFET termination structure as described in claim 7, characterized in that, The spacing between each two adjacent polycrystalline silicon field plates (50) is 4 μm.

10. The ultra-high voltage MOSFET termination structure as described in claim 1, characterized in that, Also includes: A passivation layer is located on the metal field plate (60).

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