Monolithic integrated structure of transverse and longitudinal devices, manufacturing method and equivalent circuit
By growing multilayer semiconductor materials on a substrate and etching to form mesa isolation regions and vertical device regions, ion implantation to form N-implantation regions, deposition of passivation layers and etching of gates and electrodes, the problems of complex processes and low efficiency in monolithic integration of horizontal and vertical devices are solved, achieving efficient horizontal and vertical device integration, which is suitable for scenarios such as new energy vehicles and 5G base stations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2025-12-26
- Publication Date
- 2026-05-08
AI Technical Summary
In existing monolithic integration solutions for horizontal and vertical devices, the chip area utilization rate of horizontal transistors is low under high voltage applications, and there is no efficient integration of discrete solutions for vertical transistors with horizontal HEMT drive circuits, resulting in complex processes and low efficiency.
By growing multiple layers of semiconductor materials on a substrate, etching to form mesa isolation regions and vertical device regions, ion implantation to form N-implantation regions, depositing passivation layers and etching gates and electrodes, monolithic integration of lateral and vertical devices is achieved.
A high-performance drive circuit for lateral GaN low-voltage transistors and an efficient power switch for vertical GaN high-voltage transistors are realized on a single chip, eliminating parasitic parameters of traditional packaging and achieving power conversion with ultra-high frequency, extremely small size and extreme efficiency.
Smart Images
Figure CN122002883A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a monolithic integrated structure and fabrication method of a horizontal and vertical device, and its equivalent circuit. Background Technology
[0002] Gallium nitride (GaN), as a third-generation semiconductor, has shown great potential in the field of power electronics.
[0003] Lateral GaN HEMT (High Electron Mobility Transistor) utilizes the two-dimensional electron gas generated by the AlGaN / GaN heterojunction as a conductive channel. Its advantages include high electron mobility, fast switching speed, and relatively mature manufacturing process, making it very suitable for fabricating low-voltage, high-frequency logic and control circuits. However, its withstand voltage capability usually depends on the increase of the gate-drain pitch, resulting in low chip area utilization in high-voltage applications.
[0004] In vertical GaN devices, the current flows vertically inside the chip. This has the advantages of easily achieving high breakdown voltage and high current density, as well as high chip area utilization, making them ideal high-voltage power transistors.
[0005] In existing monolithic integration schemes for lateral and vertical transistors, complex processes such as secondary epitaxy on a pre-patterned substrate are typically employed to form lateral and vertical transistors separately. Lateral transistors are easy to integrate with driver circuits, but in high-voltage applications, their withstand voltage and on-resistance are determined by the gate-drain spacing, resulting in extremely low chip area utilization. Vertical transistors, as power switches, possess superior area efficiency and high-voltage performance, but currently only discrete vertical device schemes exist. A monolithic integration scheme that allows direct and efficient control of vertical power transistors by lateral HEMT driver circuits has not yet been found. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a monolithic integrated structure and fabrication method for horizontal and vertical devices, as well as an equivalent circuit. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide a method for monolithic integration fabrication of horizontal and vertical devices, the fabrication method comprising: Obtain a substrate, and sequentially grow an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and a pGaN cap layer on the substrate. The pGaN cap layer at both ends of the device is etched down to the upper surface of the n+GaN heavily doped layer to form a mesa isolation region on one side of the device and a vertical device fabrication region on the other side; wherein, the area between the mesa isolation region and the vertical device fabrication region serves as the lateral device fabrication region and the equivalent resistance fabrication region. Continue etching the n+GaN heavily doped layers at both ends of the device until the n-GaN drift layer is formed, so as to finally form a mesa isolation region on both sides of the device. The n+GaN heavily doped layer is etched in the vertical device fabrication area until it reaches the n-GaN drift layer, forming the gate trench of the vertical device. In the lateral device fabrication area, a portion of the pGaN cap layer is etched away at intervals until the upper surface of the AlGaN barrier layer is reached. The remaining pGaN cap layer is used for the fabrication of lateral GaN low-voltage transistors. In the equivalent resistance fabrication area, all pGaN cap layers are etched away until the upper surface of the AlGaN barrier layer is reached. Ion implantation is performed between adjacent pGaN cap layers in the lateral device fabrication region, between the lateral device fabrication region and the equivalent resistance fabrication region, and between the equivalent resistance fabrication region and the vertical device fabrication region to form N implantation regions. A passivation layer is deposited across the entire device surface; The passivation layer of the gate region in the lateral device fabrication area is etched to expose the pGaN cap layer. A gate is formed on each exposed pGaN cap layer and a gate is formed in the gate trench in the vertical device fabrication area. Etch the passivation layer of the source and drain regions in the equivalent resistance fabrication area and the lateral device fabrication area down to the upper surface of the AlGaN barrier layer. Form the source and drain on the exposed AlGaN barrier layer to form the equivalent resistance device and several lateral GaN low-voltage transistors. Etch the passivation layer of the source region in the vertical device fabrication area down to the upper surface of the n+ GaN heavily doped layer. Form two sources on the exposed n+ GaN heavily doped layer and form a drain on the lower surface of the substrate to form the vertical GaN high-voltage transistor. Electrodes are led out above the source, drain, and gate to form a monolithic integrated structure of vertical GaN high-voltage transistors and lateral GaN low-voltage transistors.
[0007] In one embodiment of the present invention, the ion implantation depth of the N-implantation region extends into the n+GaN heavily doped layer.
[0008] In one embodiment of the present invention, in the lateral device fabrication region, a plurality of lateral GaN low-voltage transistors are formed by a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, a plurality of pGaN cap layers, and gate, source and drain corresponding to the lateral device fabrication region, stacked sequentially from bottom to top.
[0009] In one embodiment of the present invention, in the equivalent resistance fabrication region, an equivalent resistance device is constituted by a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and the source and drain corresponding to the equivalent resistance fabrication region, which are stacked sequentially from bottom to top.
[0010] In one embodiment of the present invention, in the vertical device fabrication region, a vertical GaN high-voltage transistor is formed by a drain, a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, and a gate and two sources corresponding to the vertical device fabrication region, which are stacked sequentially from bottom to top.
[0011] After etching the pGaN cap layer at intervals in the lateral device fabrication area, three pGaN cap layers are retained for the fabrication of lateral GaN low-voltage transistors. This allows the N-implanted region to divide the lateral device fabrication area into a first lateral device sub-region, a second lateral device sub-region, and a third lateral device sub-region. Each of the first, second, and third lateral device sub-regions includes a corresponding gate, source, and drain, respectively, to form the first, second, and third lateral GaN low-voltage transistors.
[0012] In one embodiment of the present invention, electrodes are led out above the source, drain, and gate, including: The gates of the first and second lateral GaN low-voltage transistors are connected and used as input terminals. The sources of the first and second lateral GaN low-voltage transistors and the two sources of the vertical GaN high-voltage transistor are all grounded. The drains of the second and third lateral GaN low-voltage transistors and the gate of the vertical GaN high-voltage transistor are connected and used as output terminals. The drains of the third lateral GaN low-voltage transistor and the drain of the equivalent resistance device are both connected to the power supply VDD. The drain of the vertical GaN high-voltage transistor is connected to an external circuit. The drain of the first lateral GaN low-voltage transistor is connected to the gate of the third lateral GaN low-voltage transistor and the source of the equivalent resistance device.
[0013] Secondly, embodiments of the present invention provide a monolithic integrated structure for horizontal and vertical devices, wherein the monolithic integrated structure is fabricated according to any of the monolithic integrated fabrication methods for horizontal and vertical devices described in the first aspect.
[0014] Thirdly, embodiments of the present invention provide an equivalent circuit for monolithic integration of horizontal and vertical devices, the equivalent circuit being derived from the monolithic integrated structure of the horizontal and vertical devices described in the second aspect.
[0015] In one embodiment of the present invention, the equivalent circuit includes transistor M1, transistor M2, transistor M3, transistor M4, and resistor R1; wherein transistor M1, transistor M2, and transistor M3 are lateral GaN low-voltage transistors, transistor M4 is a vertical GaN high-voltage transistor, and resistor R1 is an equivalent resistor device.
[0016] The beneficial effects of this invention are: The monolithic integration method for horizontal and vertical devices proposed in this invention is a process-compatible monolithic integration process that avoids complex processes such as secondary epitaxy in existing monolithic integration processes. It minimizes process conflicts in the fabrication steps of horizontal GaN low-voltage transistors and vertical GaN high-voltage transistors, realizing a high-performance drive circuit composed of horizontal GaN low-voltage transistors and an efficient power switch of vertical GaN high-voltage transistors on a single chip. Through the monolithic integration of horizontal and vertical devices, the performance potential of GaN is fully utilized, fundamentally eliminating parasitic parameters of traditional packaging, and achieving ultra-high frequency, extremely small size and extreme efficiency power conversion. This makes it better suited for applications such as DC-DC converters for new energy vehicles, main drive inverters, photovoltaic inverters, ultra-high speed chargers, and 5G base station power amplifiers.
[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0018] Figure 1 This is a schematic flowchart of a monolithic integrated fabrication method for horizontal and vertical devices provided in an embodiment of the present invention; Figures 2(a) to 2(j) This is a schematic diagram of the process corresponding to the monolithic integration fabrication method of horizontal and vertical devices provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of a monolithic integrated structure of a horizontal and vertical device provided in an embodiment of the present invention; Figure 4 This is an equivalent circuit diagram of a monolithic integrated structure of horizontal and vertical devices provided in an embodiment of the present invention. Detailed Implementation
[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0020] Firstly, please see Figure 1 This invention provides a method for monolithic integration fabrication of horizontal and vertical devices, the method comprising: S10. Obtain a substrate and sequentially grow an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and a pGaN cap layer on the substrate.
[0021] This invention first obtains a substrate, which can be a GaN, Si, sapphire, AlN, SOI, or a composite material. Then, an n-GaN drift layer with a thickness of 1000 nm to 20000 nm is grown on the substrate using MOCVD (Metal-organic Chemical Vapor Deposition). A p-GaN current-blocking layer with a thickness of 50 nm to 2000 nm is grown on the n-GaN drift layer using MOCVD. An n+GaN heavily doped layer with a thickness of 10 nm to 1000 nm is grown on the p-GaN current-blocking layer using MOCVD. Finally, an n+GaN heavily doped layer is grown on the n+GaN heavily doped layer using MOCVD. A GaN channel layer with a thickness of 10 nm to 3000 nm is formed. An AlGaN barrier layer with a thickness of 3 nm to 100 nm is grown on the GaN channel layer using MOCVD, wherein the Al composition is 0.1 to 0.7. Alternatively, an InGaN barrier layer with a thickness of 3 nm to 100 nm and an In composition of 0.1 to 0.7 can be grown on the AlGaN barrier layer using MOCVD. A Mg doping impurity with a doping concentration of 1 × 10⁻¹⁸ cm⁻¹ is then grown on the AlGaN barrier layer. -3 ~1×10e21cm -3 The pGaN cap layer was then applied. The final device structure is shown in Figure 2(a).
[0022] S20. Etch the pGaN cap layer at both ends of the device down to the upper surface of the n+GaN heavily doped layer to form a mesa isolation region on one side of the device and a vertical device fabrication region on the other side; wherein, the area between the mesa isolation region and the vertical device fabrication region serves as the lateral device fabrication region and the equivalent resistance fabrication region.
[0023] In this embodiment of the invention, an ICP (Inductively Coupled Plasma) etching process is used to etch the pGaN cap layers at both ends of the device down to the upper surface of the heavily doped n+GaN layer, forming a mesa isolation region on one side of the device and a vertical device fabrication region on the other side, as shown in Figure 2(b). The area between the mesa isolation region and the vertical device fabrication region serves as the lateral device fabrication region and the equivalent resistance fabrication region, with the lateral device fabrication region closer to the mesa isolation region and the equivalent resistance fabrication region closer to the vertical device fabrication region.
[0024] S30. Continue etching the n+GaN heavily doped layers at both ends of the device until the n-GaN drift layer is formed, so as to form the final mesa isolation region on both sides of the device.
[0025] In this embodiment of the invention, an ICP etching process is used to continue etching the heavily doped n+GaN layers at both ends of the device until the n-GaN drift layer is reached, so as to form a mesa isolation region on both sides of the device, as shown in Figure 2(c). The mesa isolation region on one side of the device is located on the side of the lateral device fabrication area, and the mesa isolation region on the other side of the device is located on the side of the vertical device fabrication area.
[0026] S40. Etch the n+GaN heavily doped layer in the vertical device fabrication area until it reaches the n-GaN drift layer to form the gate trench of the vertical device.
[0027] In this embodiment of the invention, the ICP etching process is used to etch the n+GaN heavily doped layer in the vertical device fabrication area in the middle position until the n-GaN drift layer is reached, forming the gate trench of the vertical device, as shown in Figure 2(d).
[0028] S50. Part of the pGaN cap layer is etched away at intervals in the lateral device fabrication area until the upper surface of the AlGaN barrier layer is reached. The remaining pGaN cap layers are used for the fabrication of lateral GaN low-voltage transistors. All pGaN cap layers are etched away in the equivalent resistance fabrication area until the upper surface of the AlGaN barrier layer is reached.
[0029] This embodiment of the invention employs an ICP etching process to etch away portions of the pGaN cap layer at intervals in the lateral device fabrication region, up to the upper surface of the AlGaN barrier layer. Several pGaN cap layers are retained for the fabrication of lateral GaN low-voltage transistors. An example is illustrated by etching pGaN cap layers at intervals in the lateral device fabrication region, leaving three pGaN cap layers for the fabrication of lateral GaN low-voltage transistors. Simultaneously, all pGaN cap layers are etched away in the equivalent resistance fabrication region, up to the upper surface of the AlGaN barrier layer. The resulting device structure is shown in Figure 2(e).
[0030] S60. Ion implantation is performed between adjacent pGaN cap layers in the lateral device fabrication region, between the lateral device fabrication region and the equivalent resistance fabrication region, and between the equivalent resistance fabrication region and the vertical device fabrication region to form N implantation regions.
[0031] This invention employs an ion implantation process to form N-implantation regions, such as nitrogen or fluorine ions, between adjacent pGaN cap layers in the lateral device fabrication region, between the lateral device fabrication region and the equivalent resistance fabrication region, and between the equivalent resistance fabrication region and the vertical device fabrication region, as shown in Figure 2(f). The ion implantation depth of the N-implantation regions extends into the heavily doped n+GaN layer. The N-implantation regions divide the lateral device fabrication region into a first lateral device sub-region, a second lateral device sub-region, and a third lateral device sub-region. Device isolation is formed between each lateral device sub-region, between the third lateral device sub-region and the equivalent resistance fabrication region, and between the equivalent resistance fabrication region and the vertical device fabrication region.
[0032] S70, deposit a passivation layer on the entire device surface.
[0033] In this embodiment of the invention, a passivation layer with a thickness of 5 nm to 10000 nm is deposited on the entire device surface in S60 using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process. Specifically, the passivation layer is deposited on the n-GaN drift layer in the mesa isolation region at both ends of the device, the AlGaN barrier layer and pGaN cap layer in the lateral device fabrication region, the AlGaN barrier layer in the equivalent resistance fabrication region, the GaN channel layer in the vertical device fabrication region, the gate trench, and all N-implantation regions, as shown in Figure 2(g). The material of the passivation layer can be at least one of Si3N4, Al2O3, SiO2, AlTiO, and HfO2.
[0034] S80. Etch the passivation layer of the gate region in the lateral device fabrication area to expose the pGaN cap layer, form a gate on each exposed pGaN cap layer, and form a gate in the gate trench in the vertical device fabrication area.
[0035] In this embodiment of the invention, an ICP etching process is used to etch the passivation layer of the gate region in the lateral device fabrication area to expose the pGaN cap layer. On each exposed pGaN cap layer, an electron beam evaporation process is used to deposit gate metal to form a gate. Gate metal is also deposited in the gate trench in the vertical device fabrication area to form a gate, as shown in Figure 2(h). The gate metal can be a Ni / Au based metal combination or a Ti / Al based metal combination.
[0036] S90. Etch the passivation layer of the source and drain regions in the equivalent resistance fabrication area and the lateral device fabrication area until the upper surface of the AlGaN barrier layer. Form the source and drain on the exposed AlGaN barrier layer to form the equivalent resistance device and several lateral GaN low-voltage transistors. Etch the passivation layer of the source region in the vertical device fabrication area until the upper surface of the n+ GaN heavily doped layer. Form two sources on the exposed n+ GaN heavily doped layer and form a drain on the lower surface of the substrate to form the vertical GaN high-voltage transistor.
[0037] In this embodiment of the invention, an ICP etching process is used to etch the passivation layers of the source and drain regions in the equivalent resistance fabrication area and the lateral device fabrication area, down to the upper surface of the AlGaN barrier layer. On the exposed AlGaN barrier layer, source and drain metals are deposited using electron beam evaporation to form the source and drain, thus forming an equivalent resistance device and several lateral GaN low-voltage transistors. The ICP etching process is also used to etch the passivation layer of the source region in the vertical device fabrication area, down to the upper surface of the n+ GaN heavily doped layer. On the exposed n+ GaN heavily doped layer, source metals are deposited using electron beam evaporation to form two sources. On the lower surface of the substrate, drain metals are deposited using electron beam evaporation to form the drain, thus forming a vertical GaN high-voltage transistor. The source and drain metals can be Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or other metal combinations based on Ti / Al. Annealing at 850°C for 30 seconds forms high-temperature ohmic contacts. The final device structure is shown in Figure 2(i). More specifically: In this embodiment of the invention, the lateral device fabrication region comprises, from bottom to top, a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, several pGaN cap layers, and corresponding gate, source, and drain electrodes to form several lateral GaN low-voltage transistors, which can also be referred to as several lateral HEMTs. Figure 2(i) shows a first lateral device sub-region, a second lateral device sub-region, and a third lateral device fabrication sub-region as examples. The first lateral device sub-region, the second lateral device sub-region, and the third lateral device fabrication sub-region each include corresponding gate, source, and drain electrodes to form the first lateral GaN low-voltage transistor, the second lateral GaN low-voltage transistor, and the third lateral GaN low-voltage transistor.
[0038] In this embodiment of the invention, the equivalent resistance device is composed of a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and the source and drain corresponding to the equivalent resistance fabrication region, stacked sequentially from bottom to top.
[0039] In this embodiment of the invention, a vertical GaN high-voltage transistor is constructed in the vertical device fabrication area by a drain, a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, and a gate and two sources corresponding to the vertical device fabrication area, which can also be called a vertical GaN trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
[0040] S100: Electrodes are led out above the source, drain, and gate to form a monolithic integrated structure of a vertical GaN high-voltage transistor and a lateral GaN low-voltage transistor.
[0041] As shown in Figure 2(j), the embodiments of the present invention have electrodes led out above the source, drain, and gate, including: connecting the gate of the first lateral GaN low-voltage transistor and the gate of the second lateral GaN low-voltage transistor and using them as input terminals; grounding the source of the first lateral GaN low-voltage transistor, the source of the second lateral GaN low-voltage transistor, and the two sources of the vertical GaN high-voltage transistor; connecting the drain of the second lateral GaN low-voltage transistor, the source of the third lateral GaN low-voltage transistor, and the gate of the vertical GaN high-voltage transistor as output terminals; connecting the drain of the third lateral GaN low-voltage transistor and the drain of the equivalent resistance device to the power supply VDD; connecting the drain of the vertical GaN high-voltage transistor to an external circuit; and connecting the drain of the first lateral GaN low-voltage transistor to the gate of the third lateral GaN low-voltage transistor and the source of the equivalent resistance device.
[0042] Through the steps S10~S100 above, the designed process flow for fabricating monolithic integrated horizontal and vertical devices enables the fabricated monolithic integrated structure to use a driving circuit composed of multiple horizontal GaN low-voltage transistors to drive the vertical GaN high-voltage transistor as a power transistor. The specific working principle is as follows: the driving circuit composed of multiple horizontal GaN low-voltage transistors receives control signals from external circuits, such as low-voltage PWM (Pulse-Width Modulation) signals from an external controller, and rapidly charges and discharges the gate capacitance of the vertical GaN high-voltage transistor using its high-speed switching capability. Due to the extremely short interconnection distance and minimal parasitic inductance, the following are achieved: a near-ideal switching waveform, significantly reducing switching losses and voltage overshoot; allowing for higher switching frequencies, thus enabling smaller passive component inductors and capacitors; and the driving and power transistors are located in the same heat sink, resulting in good thermal balance and high system reliability.
[0043] In summary, the monolithic integration fabrication method for horizontal and vertical devices proposed in this invention is a process-compatible monolithic integration process that avoids complex processes such as secondary epitaxy in existing monolithic integration processes. It minimizes process conflicts in the fabrication steps of horizontal GaN low-voltage transistors and vertical GaN high-voltage transistors, realizing a high-performance drive circuit composed of horizontal GaN low-voltage transistors and an efficient power switch of vertical GaN high-voltage transistors on a single chip. Through monolithic integration of horizontal and vertical devices, the performance potential of GaN is fully utilized, fundamentally eliminating parasitic parameters of traditional packaging. This achieves ultra-high frequency, extremely small size, and extreme efficiency power conversion, making it better suited for applications such as DC-DC converters in new energy vehicles, main drive inverters, photovoltaic inverters, ultra-high-speed chargers, and 5G base station power amplifiers.
[0044] Secondly, embodiments of the present invention provide a monolithic integrated structure for horizontal and vertical devices, which is fabricated according to any of the monolithic integrated fabrication methods for horizontal and vertical devices described in the first aspect, such as... Figure 3 As shown.
[0045] Thirdly, embodiments of the present invention provide an equivalent circuit for monolithic integration of horizontal and vertical devices, which is derived from the monolithic integrated structure of the horizontal and vertical devices described in the second aspect.
[0046] The embodiments of the present invention are based on Figure 3 The corresponding equivalent circuit is as follows Figure 4 As shown, the circuit includes transistors M1, M2, M3, and M4, and resistor R1. Transistors M1, M2, and M3 are lateral GaN low-voltage transistors, specifically the first, second, and third lateral GaN low-voltage transistors, respectively. Transistor M4 is a vertical GaN high-voltage transistor, and resistor R1 is an equivalent resistance device. In the equivalent circuit, the gates of transistors M1 and M2 are connected and serve as the input terminal V. in The sources of silicon transistor M1, M2, and M4 are all grounded. The drain of transistor M2, the source of transistor M3, and the gate of transistor M4 are connected and serve as the output terminal V. out The drain of transistor M3 and one end of resistor R1 are both connected to power supply VDD. The drain of transistor M4 is connected to external circuit. The drain of transistor M1 is connected to the gate of transistor M3 and the other end of resistor R1.
[0047] The second and third embodiments are basically similar to the first embodiment, so the description is relatively simple. For relevant details, please refer to the description of the first embodiment.
[0048] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0049] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.
[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A method for monolithic integration fabrication of horizontal and vertical components, characterized in that, The manufacturing method includes: Obtain a substrate, and sequentially grow an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and a pGaN cap layer on the substrate. The pGaN cap layer at both ends of the device is etched down to the upper surface of the n+GaN heavily doped layer to form a mesa isolation region on one side of the device and a vertical device fabrication region on the other side; wherein, the area between the mesa isolation region and the vertical device fabrication region serves as the lateral device fabrication region and the equivalent resistance fabrication region. Continue etching the n+GaN heavily doped layers at both ends of the device until the n-GaN drift layer is formed, so as to finally form a mesa isolation region on both sides of the device. The n+GaN heavily doped layer is etched in the vertical device fabrication area until it reaches the n-GaN drift layer, forming the gate trench of the vertical device. In the lateral device fabrication area, a portion of the pGaN cap layer is etched away at intervals until the upper surface of the AlGaN barrier layer is reached. The remaining pGaN cap layer is used for the fabrication of lateral GaN low-voltage transistors. In the equivalent resistance fabrication area, all pGaN cap layers are etched away until the upper surface of the AlGaN barrier layer is reached. Ion implantation is performed between adjacent pGaN cap layers in the lateral device fabrication region, between the lateral device fabrication region and the equivalent resistance fabrication region, and between the equivalent resistance fabrication region and the vertical device fabrication region to form N implantation regions. A passivation layer is deposited across the entire device surface; The passivation layer of the gate region in the lateral device fabrication area is etched to expose the pGaN cap layer. A gate is formed on each exposed pGaN cap layer and a gate is formed in the gate trench in the vertical device fabrication area. Etch the passivation layer of the source and drain regions in the equivalent resistance fabrication area and the lateral device fabrication area down to the upper surface of the AlGaN barrier layer. Form the source and drain on the exposed AlGaN barrier layer to form the equivalent resistance device and several lateral GaN low-voltage transistors. Etch the passivation layer of the source region in the vertical device fabrication area down to the upper surface of the n+ GaN heavily doped layer. Form two sources on the exposed n+ GaN heavily doped layer and form a drain on the lower surface of the substrate to form the vertical GaN high-voltage transistor. Electrodes are led out above the source, drain, and gate to form a monolithic integrated structure of vertical GaN high-voltage transistors and lateral GaN low-voltage transistors.
2. The monolithic integrated fabrication method for horizontal and vertical devices according to claim 1, characterized in that, The ion implantation depth of the N-implantation region extends into the heavily doped n+GaN layer.
3. The monolithic integrated fabrication method for horizontal and vertical devices according to claim 1, characterized in that, In the lateral device fabrication area, a number of lateral GaN low-voltage transistors are formed by a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, several pGaN cap layers, and the corresponding gate, source, and drain of the lateral device fabrication area, which are stacked sequentially from bottom to top.
4. The monolithic integrated fabrication method for horizontal and vertical devices according to claim 1, characterized in that, In the equivalent resistance fabrication region, the equivalent resistance device is composed of a substrate, an n-GaN drift layer, a p-GaN current blocking layer, an n+GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and the source and drain corresponding to the equivalent resistance fabrication region, stacked sequentially from bottom to top.
5. The monolithic integrated fabrication method for horizontal and vertical devices according to claim 1, characterized in that, In the vertical device fabrication region, a vertical GaN high-voltage transistor is formed by stacking the drain, substrate, n-GaN drift layer, p-GaN current blocking layer, n+GaN heavily doped layer, GaN channel layer, gate and two sources corresponding to the vertical device fabrication region from bottom to top.
6. The monolithic integrated fabrication method for horizontal and vertical devices according to claim 1, characterized in that, After etching the pGaN cap layer at intervals in the lateral device fabrication area, three pGaN cap layers are retained for the fabrication of lateral GaN low-voltage transistors. This allows the N-implanted region to divide the lateral device fabrication area into a first lateral device sub-region, a second lateral device sub-region, and a third lateral device sub-region. Each of the first, second, and third lateral device sub-regions includes a corresponding gate, source, and drain, respectively, to form the first, second, and third lateral GaN low-voltage transistors.
7. The monolithic integrated fabrication method for horizontal and vertical devices according to claim 6, characterized in that, Electrodes are led out above the source, drain, and gate, including: The gates of the first and second lateral GaN low-voltage transistors are connected and used as input terminals. The sources of the first and second lateral GaN low-voltage transistors and the two sources of the vertical GaN high-voltage transistor are all grounded. The drains of the second and third lateral GaN low-voltage transistors and the gate of the vertical GaN high-voltage transistor are connected and used as output terminals. The drains of the third lateral GaN low-voltage transistor and the drain of the equivalent resistance device are both connected to the power supply VDD. The drain of the vertical GaN high-voltage transistor is connected to an external circuit. The drain of the first lateral GaN low-voltage transistor is connected to the gate of the third lateral GaN low-voltage transistor and the source of the equivalent resistance device.
8. A monolithic integrated structure for a horizontal and vertical device, characterized in that, The monolithic integrated structure is fabricated using the monolithic integrated fabrication method for horizontal and vertical devices according to any one of claims 1 to 7.
9. An equivalent circuit for monolithic integration of horizontal and vertical devices, characterized in that, The equivalent circuit is derived from the monolithic integrated structure of the horizontal and vertical devices according to claim 8.
10. The equivalent circuit of the monolithically integrated horizontal and vertical devices according to claim 9, characterized in that, The equivalent circuit includes transistors M1, M2, M3, and M4, and resistor R1; wherein transistors M1, M2, and M3 are lateral GaN low-voltage transistors, transistor M4 is a vertical GaN high-voltage transistor, and resistor R1 is an equivalent resistor device.