Monolithic integrated GaN HEMT and Si MOS double-gate bidirectional switch cascode and preparation method thereof
By integrating GaN HEMT and Si MOS dual-gate bidirectional switch cascode structure on a single chip, the optimization problem of SiC and GaN bidirectional switches in the prior art is solved, achieving zero static power consumption and flexible switching control, which is suitable for low power consumption scenarios, simplifies circuit design and reduces costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2025-12-17
- Publication Date
- 2026-05-08
AI Technical Summary
In the existing technology, the structure and performance of SiC and GaN bidirectional switches need further optimization. Discrete device cascading schemes lead to increased system size, increased on-resistance and increased cost. Depletion-mode GaN devices have high static power consumption and poor process stability. p-GaN etching process has high precision requirements and is difficult to manufacture. SiC bidirectional switches cannot achieve both low on-resistance and fast switching characteristics.
A monolithic GaN HEMT and Si MOS dual-gate bidirectional switch cascode structure is adopted. By integrating the low-voltage Si MOS with the high-voltage dual-gate GaN HEMT to form a cascode connection, the enhancement-mode characteristics are achieved by utilizing the switching control of Si MOS. The GaN HEMT is fabricated using a standard depletion-mode process, simplifying the p-GaN etching process.
It achieves zero static power consumption, reduces system size and cost, improves circuit stability and reliability, provides flexible switching control and precise current regulation, is suitable for low-power scenarios, simplifies circuit design and reduces switching losses.
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Figure CN122002893A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically relating to a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode and its fabrication method. Background Technology
[0002] Bidirectional switches play a crucial role in power applications such as electric vehicles, renewable energy generation, vehicle-to-vehicle communication, and energy storage systems. They efficiently control bidirectional energy flow, ensuring reliable and safe system operation. Based on monolithic integration technology, bidirectional switches achieve high power conversion efficiency and are gradually becoming an industry standard in power electronics, widely used in charging piles, battery energy management systems, and uninterruptible power supplies (UPS). Currently, mainstream technologies include SiC and GaN bidirectional switches, but their structure and performance still require further optimization.
[0003] Currently, there are three main technical approaches to achieving bidirectional switching: First, cascading multiple discrete devices (such as MOSFETs) to form a bidirectional switch. However, this approach increases system size, on-resistance, and cost. Second, using depletion-mode GaN devices. However, depletion-mode devices suffer from high static power consumption and poor process stability, making them unsuitable for low-power applications. Third, enhancement-mode GaN bidirectional switch structures based on p-GaN gates achieve bidirectional conduction and blocking through a dual-gate design and a common drain region. While enhancement-mode GaN devices can achieve bidirectional control, the p-GaN etching process requires high precision, is difficult to manufacture, and has limited on-current density. Furthermore, SiC bidirectional switches are mostly vertically configured, presenting challenges in bidirectional voltage blocking and making it difficult to balance low on-resistance with fast switching characteristics. Summary of the Invention
[0004] To address the aforementioned problems in the prior art, this invention provides a monolithic integrated GaN HEMT and SiMOS dual-gate bidirectional switch cascode and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, comprising: a substrate and a dual-gate GaN HEMT, a first Si MOS, and a second Si MOS integrated on the substrate; wherein, A passivation layer is disposed between the first Si MOS, the dual-gate GaN HEMT and the second Si MOS and on their upper surfaces; The dual-gate GaN HEMT forms a cascode connection with the first Si MOS and the second Si MOS.
[0005] In one embodiment of the present invention, the dual-gate GaN HEMT is located between the first Si MOS and the second Si MOS; The source of the first Si MOS is interconnected with the first gate of the dual-gate GaN HEMT by a metal, and the drain of the first Si MOS is interconnected with the source of the dual-gate GaN HEMT by a metal. The source of the second Si MOS is interconnected with the second gate of the dual-gate GaN HEMT by a metal, and the drain of the second Si MOS is interconnected with the drain of the dual-gate GaN HEMT by a metal.
[0006] In one embodiment of the present invention, the substrate includes a Si substrate, a GaN substrate, a sapphire substrate, or a SiC substrate.
[0007] In one embodiment of the present invention, both the first Si MOS and the second Si MOS include a P-type silicon semiconductor epitaxial region located on the substrate. A first N+ source region and a second N+ source region are disposed at intervals in the P-type silicon semiconductor epitaxial region. A source of the Si MOS is disposed on the first N+ source region, and a drain of the Si MOS is disposed on the second N+ source region. A gate of the Si MOS is disposed on the P-type silicon semiconductor epitaxial region between the drain of the Si MOS and the source of the Si MOS.
[0008] In one embodiment of the present invention, the dual-gate GaN HEMT includes a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially from bottom to top on the substrate. The barrier layer is provided with a source, a first gate, a second gate and a drain of the dual-gate GaN HEMT, wherein the first gate of the dual-gate GaN HEMT is located between its source and drain, and the second gate of the dual-gate GaN HEMT is located between its first gate and drain.
[0009] In one embodiment of the present invention, the material of the nucleation layer includes AlN or AlGaN, and the thickness is 30-500 μm.
[0010] In one embodiment of the present invention, the material of the buffer layer includes GaN, AlN or AlGaN, and the thickness is 0.5-5 μm.
[0011] In one embodiment of the present invention, the material of the channel layer includes GaN, AlN or AlGaN, and the thickness is 50-500 nm.
[0012] In one embodiment of the present invention, the barrier layer is made of AlGaN and has a thickness of 10-50 nm.
[0013] This invention provides a method for fabricating a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, applicable to the monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode described in any of the above embodiments. The fabrication method includes: Step 1: Obtain an epitaxial wafer, which includes a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially from bottom to top; Step 2: Etch the barrier layer, channel layer, buffer layer and nucleation layer on both sides of the epitaxial wafer to form Si MOS regions on both sides of the GaN HEMT region; Step 3: Epitaxially form a P-type silicon semiconductor epitaxial region on the substrate of the Si MOS region; Step 4: Form the first N+ source region and the second N+ source region in the P-type silicon semiconductor epitaxial region by ion implantation; Step 5: Fabricate ohmic contact metal electrodes on the first N+ source region, the second N+ source region, and the barrier layer to form the source and drain of Si MOS and the source and drain of dual-gate GaN HEMT; Step 6: Prepare Schottky contact metal electrodes on the P-type silicon semiconductor epitaxial region and on the barrier layer between the source and drain of the dual-gate GaN HEMT to form the gate of the Si MOS and the first and second gates of the dual-gate GaN HEMT. Step 7: A passivation layer is deposited on the surface of the device using plasma chemical vapor deposition. The passivation layer on the source and drain of the SiMOS and the source, drain, first gate, and second gate of the dual-gate GaN HEMT is etched to form electrode contact holes. The two SiMOS and the dual-gate GaN HEMT are cascode connected through the electrode contact holes using metal interconnects.
[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention relates to a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, which monolithically integrates a high-voltage dual-gate GaNHEMT with a low-voltage Si MOS to form a cascode structure. The GaN HEMT in the cascode structure can be fabricated using standard depletion-mode processes, eliminating the need for complex enhancement-mode processes such as p-GaN etching. Through the switching control of the Si MOS, the entire cascode combination exhibits enhancement-mode characteristics from the perspective of the Si MOS gate, achieving zero static power consumption and making it suitable for low-power scenarios such as battery-powered applications.
[0015] 2. The monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode of this invention reduces the connection and packaging links between multiple discrete components in traditional solutions. This not only reduces the overall circuit size and the impact of parasitic parameters (such as parasitic inductance and parasitic capacitance), improving circuit stability and reliability, but also reduces assembly costs and board space, which is beneficial for achieving system miniaturization and weight reduction.
[0016] 3. The monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode of this invention utilizes the dual-gate structure to provide more degrees of control freedom, allowing independent adjustment of the voltage of different gates, thereby achieving more flexible switching control and more precise current regulation. The bidirectional switching characteristic allows current to flow in both directions, which is crucial for applications requiring bidirectional energy transfer (such as battery charge / discharge management systems, renewable energy storage systems, etc.), simplifying circuit design, improving system adaptability and versatility. Combined with two independent Si MOS cascode controls, the on / off state of two current directions can be precisely and independently controlled, improving the flexibility and efficiency of switching control and reducing switching losses.
[0017] 4. The monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode of this invention reduces the complexity of peripheral circuits and the number of required devices through monolithic integration, thereby lowering the overall cost at the system level. Furthermore, with the continuous maturation and mass production of GaN manufacturing processes, the cost of GaN devices is gradually decreasing, making this integrated structure more cost-effective. It is simpler and easier to implement than p-GaN technology. This integrated structure combines the advantages of both GaN and Si materials, enabling better compatibility with existing silicon-based circuits and systems, and facilitating upgrades and expansions based on existing technologies.
[0018] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention; Figure 2 This is a circuit schematic diagram of the bidirectional conduction of a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a method for fabricating a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the fabrication process of a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention.
[0020] Icons: 100 - Dual-gate GaN HEMT; 200 - First Si MOS; 300 - Second Si MOS; 400 - Passivation layer; 101 - Substrate; 102 - Nucleation layer; 103 - Buffer layer; 104 - Channel layer; 105 - Barrier layer; 106 - Source of dual-gate GaN HEMT; 107 - Drain of dual-gate GaN HEMT; 108 - First gate; 109 - Second gate; 10 - P-type silicon epitaxial region; 20 - First N+ source region; 30 - Second N+ source region; 40 - Source of Si MOS; 50 - Drain of Si MOS; 60 - Gate of Si MOS. Detailed Implementation
[0021] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode and its fabrication method based on the present invention.
[0022] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0023] In a first aspect, embodiments of the present invention provide a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode. This structure integrates a low-voltage silicon-based MOSFET and a high-voltage dual-gate GaN HEMT on a single chip and forms a cascode connection. It utilizes Si MOS as a low-voltage, high-reliability, and wide-safety-range gate-controlled switch to drive the main current path of the high-voltage GaNHEMT, thereby achieving a high-performance bidirectional switching function.
[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention, as shown below. Figure 1As shown, this embodiment of the monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode includes a dual-gate GaN HEMT 100, a first Si MOS 200, and a second Si MOS 300, all integrated on a substrate 101. A passivation layer 400 covers the dual-gate GaN HEMT 100, the first Si MOS 200, and the second Si MOS 300, providing dielectric isolation between them. The material of the passivation layer 400 can be SiNx or SiO2.
[0025] Optionally, the substrate 101 may be a Si substrate, a GaN substrate, a sapphire substrate, or a SiC substrate.
[0026] In this embodiment, the dual-gate GaN HEMT 100 is located between the first Si MOS and the second Si MOS.
[0027] Specifically, the dual-gate GaN HEMT 100 includes a nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105 stacked sequentially from bottom to top on a substrate 101. The source 106 and drain 107 of the dual-gate GaN HEMT are formed on the barrier layer 105 using an ohmic contact process. Between the source 106 and drain 107 of the dual-gate GaN HEMT, a first gate 108 and a second gate 109 are sequentially formed using a Schottky contact process.
[0028] In this dual-gate GaN HEMT, the first gate 108 is located between its source 106 and drain 107, and the second gate 109 is located between its first gate 108 and drain 107. That is, the first gate 108 of the dual-gate GaN HEMT is closer to its source 106, and the second gate 109 is closer to its drain 107.
[0029] In an optional embodiment, the nucleation layer 102 is made of AlN or AlGaN and has a thickness of 30-500 μm. The buffer layer 103 is made of GaN, AlN, or AlGaN and has a thickness of 0.5-5 μm. The channel layer 104 is made of GaN, AlN, or AlGaN and has a thickness of 50-500 nm. The barrier layer 105 is made of AlGaN and has a thickness of 10-50 nm.
[0030] Specifically, the first Si MOS 200 includes a P-type silicon semiconductor epitaxial region 10 located on a substrate 101. In the P-type silicon semiconductor epitaxial region 10, a first N+ source region 20 and a second N+ source region 30 are formed by ion implantation. A source 40 of the Si MOS is disposed on the first N+ source region 20, and a drain 50 of the Si MOS is disposed on the second N+ source region 30. A gate 60 of the Si MOS is disposed on the P-type silicon semiconductor epitaxial region 10 between the drain 40 and the source 50 of the Si MOS.
[0031] In this embodiment, the structure of the second Si MOS 300 is symmetrical to that of the first Si MOS 200, including a P-type silicon semiconductor epitaxial region 10, a first N+ source region 20, a second N+ source region 30, a source of the Si MOS 40, a drain of the Si MOS 50, and a gate of the Si MOS 60.
[0032] In this embodiment, the interconnection relationships between the dual-gate GaN HEMT 100, the first Si MOS 200, and the second Si MOS 300 are as follows: the source 40 of the first Si MOS 200 is interconnected with the first gate 108 of the dual-gate GaN HEMT 100 via a metal interconnection, and the drain 50 of the first Si MOS 200 is interconnected with the source 106 of the dual-gate GaN HEMT 100 via a metal interconnection. The source 40 of the second Si MOS 300 is interconnected with the second gate 109 of the dual-gate GaN HEMT 100 via a metal interconnection, and the drain 50 of the second Si MOS 300 is interconnected with the drain 107 of the dual-gate GaN HEMT 100 via a metal interconnection.
[0033] This embodiment integrates a monolithic GaN HEMT and a Si MOS dual-gate bidirectional switch cascode, which is equivalent to two independent cascode units sharing a high-voltage GaN HEMT channel, with direction control achieved through its internal dual gates. Further combining... Figure 2 The working principle of the monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode in embodiments of the present invention will be explained. Figure 2 This is a circuit schematic diagram of a monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention, wherein (a) is the forward conduction mode and (b) is the reverse conduction mode. In the diagram, G1 represents the gate of the first Si MOS, G3 represents the first gate of the dual-gate GaN HEMT, G4 represents the second gate of the dual-gate GaN HEMT, and G2 represents the gate of the second Si MOS.
[0034] When the drain and source of a device are subjected to a positive voltage, the applied voltage is divided across different parasitic capacitances inside the device.
[0035] Forward conduction mode: A positive voltage higher than its threshold voltage Vth1 is applied to the gate of the first Si MOS, turning it on. Its drain-source parasitic capacitance begins to discharge. Since the gate-source parasitic capacitance of the depletion-mode GaN HEMT is in parallel with the drain-source parasitic capacitance of the first Si MOS, the gate-source parasitic capacitance of the GaN HEMT also begins to discharge. The gate-source voltage Vgs(G3) of the depletion-mode GaN HEMT rises, and the conductive channel opens. Simultaneously, a 0V or negative voltage is applied to the gate of the second Si MOS to turn it off, thereby isolating the second gate of the dual-gate GaN HEMT. The entire device is forward-biased. At this time, the current direction is as follows: Figure 2 As shown in Figure (a).
[0036] Reverse conduction mode: When a positive voltage higher than its threshold voltage Vth2 is applied to the gate of the second Si MOS, the second Si MOS turns on, and its drain-source parasitic capacitance begins to discharge. Since the gate-source parasitic capacitance of the depletion-mode GaN HEMT is in parallel with the drain-source parasitic capacitance of the second Si MOS, the gate-source parasitic capacitance of the GaN HEMT also begins to discharge, and the gate-source voltage Vgs(G4) of the depletion-mode GaN HEMT rises, opening the conductive channel. Simultaneously, a 0V or negative voltage is applied to the gate of the first Si MOS to turn it off, thereby isolating the first gate of the dual-gate GaN HEMT. The entire device is forward-biased, and the current direction is as follows: Figure 2 As shown in Figure (b).
[0037] Bidirectional shutdown mode: When both the gates of the first Si MOS and the second Si MOS are turned off by applying 0V or negative voltage, neither Si MOS is turned on. Both gates of the dual-gate GaN HEMT are in a floating or high-resistance state, and the channels below them are pinched off, thereby achieving bidirectional voltage blocking between the source and drain.
[0038] This invention relates to a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode. The high-voltage dual-gate GaN HEMT is monolithically integrated with a low-voltage Si MOS to form a cascode structure. The GaN HEMT in the cascode structure can be fabricated using standard depletion-mode processes, eliminating the need for complex enhancement-mode processes such as p-GaN etching. Through the switching control of the Si MOS, the entire cascode combination exhibits enhancement-mode characteristics from the perspective of the Si MOS gate, achieving zero static power consumption and making it suitable for low-power scenarios such as battery-powered applications.
[0039] Secondly, embodiments of the present invention provide a method for fabricating a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, applicable to the monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in the first aspect above.
[0040] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating a method for fabricating a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to an embodiment of the present invention. Figure 3 As shown, the preparation method includes: Step 1: Obtain an epitaxial wafer, which consists of a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially from bottom to top.
[0041] The substrate material can be Si, GaN, sapphire, or SiC; the nucleation layer material can be AlN or AlGaN with a thickness of 30-500 μm; the buffer layer material can be GaN, AlN, or AlGaN with a thickness of 0.5-5 μm; the channel layer material can be GaN, AlN, or AlGaN with a thickness of 50-500 nm; and the barrier layer material is AlGaN with a thickness of approximately 10-50 nm.
[0042] Understandably, the epitaxial wafer needs to be cleaned after acquisition to remove impurities, dust, oxides, organic matter, etc. The epitaxial wafer can be first ultrasonically cleaned in acetone for 2 minutes, then heated in a 60°C stripping solution water bath for about 10 minutes, then cleaned in acetone for 3 minutes, followed by cleaning in ethanol and ultrapure water for 2 minutes each, and finally dried with nitrogen (N2).
[0043] Step 2: Etch the barrier layer, channel layer, buffer layer and nucleation layer on both sides of the epitaxial wafer to form Si MOS regions on both sides of the GaN HEMT region.
[0044] Alternatively, ICP or RIE techniques can be used to etch the epitaxial wafer, retaining the central GaN HEMT region while etching away the barrier layer, channel layer, buffer layer, and nucleation layer of the SiMOS regions on both sides.
[0045] Step 3: Epitaxially form a P-type silicon semiconductor epitaxial region on the substrate of the Si MOS region.
[0046] Alternatively, a P-type silicon semiconductor epitaxial region can be formed on the substrate using an MOCVD process.
[0047] Step 4: Ion implantation is used to form the first N+ source region and the second N+ source region in the epitaxial region of the P-type silicon semiconductor.
[0048] Step 5: Fabricate ohmic contact metal electrodes on the first N+ source region, the second N+ source region, and the barrier layer to form the source and drain of Si MOS and the source and drain of dual-gate GaN HEMT.
[0049] Specifically, metals are deposited on the first N+ source region, the second N+ source region, and the barrier layer using an electron beam evaporation process, and then subjected to high-temperature annealing in a rapid annealing furnace to form good ohmic contacts, thereby producing the source and drain of a dual-gate GaN HEMT and the source and drain of a Si MOS.
[0050] Optionally, the source and drain materials of the dual-gate GaN HEMT and the source and drain materials of the Si MOS can be one of the metal layer combinations of Ti / Al, Ti / Au, and Ti / Al / Ni / Au.
[0051] Step 6: Fabricate Schottky contact metal electrodes on the P-type silicon semiconductor epitaxial region and on the barrier layer between the source and drain of the dual-gate GaN HEMT to form the gate of the Si MOS and the first and second gates of the dual-gate GaN HEMT.
[0052] Optionally, the gate materials of the dual-gate GaN HEMT and the Si MOS can be one of the combinations of Ni / Au / Ni, Ni / Au, and W / Au metal layers.
[0053] Step 7: A passivation layer is deposited on the surface of the device using plasma chemical vapor deposition. The passivation layer on the source and drain of the SiMOS and the source, drain, first gate, and second gate of the dual-gate GaN HEMT is etched to form electrode contact holes. The two SiMOS and the dual-gate GaN HEMT are cascode connected through the electrode contact holes using metal interconnects.
[0054] Specifically, firstly, a SiNx or SiO2 passivation layer is deposited on the device surface using plasma chemical vapor deposition (PECVD). The nitrogen source can be provided by ammonia, and the silicon source can be provided by silane, thereby effectively suppressing current collapse.
[0055] After the passivation layer is fabricated, photolithography and etching are performed on the passivation layer above the drain of the left Si MOS, the source of the right Si MOS, and the source and drain of the dual-gate GaNHEMT to form contact holes and lead-out electrodes, thus completing the metal interconnection between the source of the dual-gate GaNHEMT and the drain of the left Si MOS, and the metal interconnection between the drain of the dual-gate GaN HEMT and the source of the right Si MOS.
[0056] Then, the epitaxial wafer that has undergone the above steps is placed in the PECVD reaction chamber for a second passivation layer deposition.
[0057] Finally, photolithography and etching are performed on the passivation layers above the source of the left Si MOS, the drain of the right Si MOS, and the gate of the dual-gate GaN HEMT to form contact holes and lead-out electrodes, thus completing the metal interconnection between the gate of the dual-gate GaN HEMT and the source of the left Si MOS, and the metal interconnection between the gate of the dual-gate GaN HEMT and the drain of the right Si MOS.
[0058] For example, the fabrication process of a monolithic integrated GaN HEMT and a Si MOS dual-gate bidirectional switch cascode on a Si substrate is as follows: Figure 4 As shown, Figure 4 This is a flowchart illustrating the fabrication process of a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in an embodiment of the present invention.
[0059] The method for fabricating a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode in this invention combines mature GaN HEMT epitaxy and etching processes with standard processes such as epitaxy, ion implantation, and thermal oxidation of silicon-based MOSFETs, which is beneficial for achieving high-yield and low-cost manufacturing.
[0060] For details regarding the fabrication method of the monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, as well as its corresponding beneficial effects, please refer to the relevant content on the monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode provided in the first aspect; it will not be repeated here.
[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.
[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, characterized in that, include: The substrate and the dual-gate GaN HEMT, the first Si MOS, and the second Si MOS integrated on the substrate; wherein, A passivation layer is disposed between the first Si MOS, the dual-gate GaN HEMT and the second Si MOS and on their upper surfaces; The dual-gate GaN HEMT forms a cascode connection with the first Si MOS and the second Si MOS.
2. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 1, characterized in that, The dual-gate GaN HEMT is located between the first Si MOS and the second Si MOS; The source of the first Si MOS is interconnected with the first gate of the dual-gate GaN HEMT by a metal, and the drain of the first Si MOS is interconnected with the source of the dual-gate GaN HEMT by a metal. The source of the second Si MOS is interconnected with the second gate of the dual-gate GaN HEMT by a metal, and the drain of the second Si MOS is interconnected with the drain of the dual-gate GaN HEMT by a metal.
3. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 1, characterized in that, The substrate includes a Si substrate, a GaN substrate, a sapphire substrate, or a SiC substrate.
4. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 1, characterized in that, Both the first Si MOS and the second Si MOS include a P-type silicon semiconductor epitaxial region located on the substrate. A first N+ source region and a second N+ source region are disposed at intervals in the P-type silicon semiconductor epitaxial region. The source of the Si MOS is disposed on the first N+ source region, and the drain of the Si MOS is disposed on the second N+ source region. The gate of the Si MOS is disposed on the P-type silicon semiconductor epitaxial region between the drain of the Si MOS and the source of the Si MOS.
5. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 1, characterized in that, The dual-gate GaN HEMT includes a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially from bottom to top on the substrate. The barrier layer has a source, a first gate, a second gate, and a drain of the dual-gate GaN HEMT. The first gate of the dual-gate GaN HEMT is located between its source and drain, and the second gate of the dual-gate GaN HEMT is located between its first gate and drain.
6. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 5, characterized in that, The nucleation layer is made of AlN or AlGaN and has a thickness of 30-500 μm.
7. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 5, characterized in that, The buffer layer is made of GaN, AlN, or AlGaN and has a thickness of 0.5-5 μm.
8. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 5, characterized in that, The channel layer is made of GaN, AlN, or AlGaN and has a thickness of 50-500 nm.
9. The monolithically integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to claim 5, characterized in that, The barrier layer is made of AlGaN and has a thickness of 10-50 nm.
10. A method for fabricating a monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode, characterized in that, The method for fabricating the monolithic integrated GaN HEMT and Si MOS dual-gate bidirectional switch cascode according to any one of claims 1-9 includes: Step 1: Obtain an epitaxial wafer, which includes a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked sequentially from bottom to top; Step 2: Etch the barrier layer, channel layer, buffer layer and nucleation layer on both sides of the epitaxial wafer to form Si MOS regions on both sides of the GaN HEMT region; Step 3: Epitaxially form a P-type silicon semiconductor epitaxial region on the substrate of the Si MOS region; Step 4: Form the first N+ source region and the second N+ source region in the P-type silicon semiconductor epitaxial region by ion implantation; Step 5: Fabricate ohmic contact metal electrodes on the first N+ source region, the second N+ source region, and the barrier layer to form the source and drain of Si MOS and the source and drain of dual-gate GaN HEMT; Step 6: Prepare Schottky contact metal electrodes on the P-type silicon semiconductor epitaxial region and on the barrier layer between the source and drain of the dual-gate GaN HEMT to form the gate of the Si MOS and the first and second gates of the dual-gate GaN HEMT. Step 7: A passivation layer is deposited on the surface of the device using plasma chemical vapor deposition. The passivation layer on the source and drain of the Si MOS and the source, drain, first gate, and second gate of the dual-gate GaN HEMT is etched to form electrode contact holes. The two Si MOS and the dual-gate GaN HEMT are cascode connected through the electrode contact holes using metal interconnects.