Manufacturing method for improving etching window of aluminum oxide passivation layer of gallium arsenide device

Abstract

The invention relates to the technical field of gallium arsenide semiconductor device manufacturing, in particular to a manufacturing method for improving an aluminum oxide passivation layer etching window of a gallium arsenide device, and the method comprises the steps: reserving silicon nitride in a cutting channel region when a first passivation layer is opened through optimizing a technological process; after a second metal electrode and an Al2O3 passivation layer are deposited, a two-step etching strategy is adopted, firstly, a PAD and an Al2O3 thin film in a cutting channel area are removed through SF6 + O mixed gas, then residual silicon nitride in the cutting channel area is removed through SF6 + Ar mixed gas, and a Ti layer in the PAD area is thoroughly removed; and meanwhile, the problem of routing failure caused by Ti residues in a PAD area and the problem of structural damage caused by cutting channel semiconductor layer etching through are solved, the process window is widened, and the production efficiency and the product comprehensive yield are improved.

Description

Technical Field

[0001] This invention relates to the field of gallium arsenide semiconductor device manufacturing technology, and more specifically to a method for improving the manufacturing method of the etching window of the alumina passivation layer in gallium arsenide devices. Background Technology

[0002] Gallium arsenide (GaAs) devices are widely used in radio frequency (RF) communications and microwave power applications due to their superior characteristics such as high frequency, high speed, and low power consumption. During the manufacturing process of GaAs devices, the etching window process of the passivation layer directly affects the bonding reliability and mechanical stability of the device.

[0003] See Figure 1-11 In the prior art, the manufacturing process of the passivation layer etching window of gallium arsenide devices is as follows: First, an epitaxial layer, an ohmic contact metal, and a first metal electrode are sequentially formed on a gallium arsenide substrate, and silicon nitride is deposited as the first passivation layer; the PAD and dicing area of ​​the first passivation layer are opened by photolithography and etching processes; then, a second metal electrode is formed, which includes a bottom Ti / Pt / Au layer and a top Ti layer; an Al2O3 thin film is deposited as the second passivation layer using atomic layer deposition (ALD) process; the PAD and dicing area of ​​the second passivation layer are opened again by photolithography and etching processes. The etching process uses an SF6+O2 mixed gas plasma process, which needs to simultaneously remove Al2O3 from the PAD area and the top Ti layer, and remove Al2O3 from the dicing area.

[0004] However, existing technologies have the following significant drawbacks: The process window is extremely narrow: Al2O3 dry etching needs to meet two contradictory requirements at the same time - completely remove Al2O3 and Ti on the PAD, and cannot etch through the GaAs / InGaP epitaxial layer of the cut channel. It is difficult to achieve this stably in the same etching step. Poor etching stability: The Al2O3 film is thin and the etching time is short. Small fluctuations in the equipment status (gas flow rate, plasma uniformity) can easily lead to insufficient or excessive etching. In addition, the ALD deposition rate is slow, and it is impossible to frequently insert control wafers to monitor the etching rate during mass production. Process drift is difficult to correct. PAD wire bonding has a high risk of failure: During conservative etching, the Ti layer (inert and easily oxidized) remaining on the PAD surface will prevent the gold wire bonding from forming a good intermetallic compound (IMC), resulting in weak bonding strength, desoldering or non-adhesion; Risk of damage to the dicing channel: When over-etched, SF6+O2 plasma will quickly erode through the epitaxial layer in the dicing channel area. The ammonia solution etched after subsequent dicing will invade and corrode the substrate, resulting in abnormal appearance of the dicing channel, reduced mechanical strength, or even chip edge breakage. Yield and reliability are difficult to achieve simultaneously: the process must make trade-offs between "ensuring wire bonding" and "ensuring dicing", which leads to potential variations in yield and reliability between different batches or different areas of the same wafer.

[0005] Therefore, there is an urgent need for a manufacturing method that can broaden the process window, eliminate the risk of Ti residue and kerf damage, and improve production efficiency and product reliability. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned defects of the prior art and provide a manufacturing method for improving the etching window of the alumina passivation layer of gallium arsenide devices. By optimizing the process steps and etching strategy, the invention simultaneously solves the wire bonding failure problem caused by Ti residue in the PAD region and the structural damage problem caused by the etch-through of the semiconductor layer in the dicing channel, thereby widening the process window and improving production efficiency and overall product yield.

[0007] The technical solution of the present invention is as follows: A method for improving the fabrication of the etching window of the aluminum oxide passivation layer in gallium arsenide devices includes the following steps: Step 1: An ohmic contact metal and a first metal electrode are sequentially formed on the epitaxial layer of a gallium arsenide substrate, and a silicon nitride thin film is deposited as the first passivation layer; Step 2: Coat the first layer of photoresist and open the first passivation layer. Remove the silicon nitride in the PAD area, retain the silicon nitride in the dicing area, and remove the residual photoresist after the opening process. Step 3: Coat the second layer of photoresist, deposit the second metal electrode, and remove excess metal and photoresist after deposition; Step 4: Deposit an Al2O3 thin film as a second passivation layer on the entire wafer surface; Step 5: Apply the third layer of photoresist, align it with the PAD area and the cut area, expose and develop to form a patterned window; Step 6: Use a mixture of SF6 and O2 to perform plasma etching to remove the Al2O3 film on the surface of the PAD area and the cut track area; Step 7: Use a mixed gas of SF6 and Ar to perform plasma etching to remove the residual silicon nitride in the cut area and completely remove the Ti on the top layer of the second metal electrode in the PAD area; Step 8: Remove the third layer of photoresist, and then proceed with wafer thinning, back via fabrication, back gold deposition, back gold etching of the dicing channels, and wafer dicing to finally complete the device manufacturing process.

[0008] Further, step 2 specifically involves: applying positive photoresist, exposing and developing the PAD area using a mask, removing the silicon nitride in the PAD area using a reactive ion etching machine, retaining the silicon nitride in the dicing area, and then removing the residual photoresist.

[0009] Furthermore, in step 2, the coating speed of the positive photoresist is 3000-5000 rpm, and the photoresist thickness is controlled to be 1.82 µm; after exposure, development is performed using 2.38% TMAH developer; silicon nitride etching is performed using SF6 gas, and after etching, residual photoresist is removed by N-methylpyrrolidone (NMP) solution.

[0010] Further, step 3 specifically involves: coating a thick film of positive photoresist, exposing and developing it to form the M2 pattern, sequentially depositing multiple layers of Ti / Pt / Au / Ti metal, removing excess metal and photoresist through a lift-off process, and retaining the patterned second metal electrode.

[0011] Furthermore, in step 3, the coating speed of the thick-film positive photoresist is 1500-5000 rpm, and the photoresist thickness reaches 6 µm; the thicknesses of the multilayer metal deposition are: Ti thickness is 30 Å, Pt thickness is 100 Å, Au thickness is 16000 Å, and Ti thickness is 100 Å; the lift-off process uses NMP solution immersion and is supplemented by ultrasonic or megasonic wave treatment.

[0012] Furthermore, step 4 specifically involves: depositing an Al2O3 thin film as a second passivation layer on the entire wafer surface using an atomic layer deposition process; The parameters for the atomic layer deposition are as follows: trimethylaluminum (TMA) is used as the metal source precursor, and deionized water (H2O) is used as the oxygen source precursor; the deposition temperature is 80°C-250°C. The TMA vapor pulse duration is 0.05-0.1 s; the first nitrogen purging time is 5-15 s. The water vapor pulse duration is 0.05-0.1 s; the second nitrogen purging duration is 5-15 s; The Al2O3 film thickness is 25 nm.

[0013] Furthermore, in step 6: the ratio of SF6 to O2 in the mixed gas is 10:1; the flow rate of SF6 is 20-50 sccm, the flow rate of O2 is 1-5 sccm; and the etching time is 30-50 seconds.

[0014] Furthermore, in step 7, the flow rate of SF6 is 30-100 sccm, the flow rate of Ar is 10-50 sccm, and the etching time is 60-90 seconds.

[0015] Furthermore, in step 8, the wafer is thinned to 100µm; after wafer dicing, it is etched using a solution of ammonia:hydrogen peroxide:water = 1:1:50.

[0016] Compared with the prior art, the present invention has the following beneficial effects: Significantly widening the process window: The contradictory etching requirements of the original "one-step method" are decomposed into two independent "wide window" steps. The first step only needs to achieve "etching Al2O3 without etching through the semiconductor", and the second step only needs to achieve "etching SiN and removing residual Ti". Each step has simpler requirements and is easier to achieve stably, completely solving the problem of the narrow process window of the original method.

[0017] Completely eliminate Ti residue and improve bonding reliability: The first etching step removes some Ti, and the second etching step uses SF6+Ar gas to etch Ti, completely removing the remaining Ti and exposing the clean Au surface underneath. This provides an excellent metal contact interface for gold wire bonding, significantly improving bonding strength and consistency and avoiding wire bonding failure.

[0018] Perfect protection of the dicing structure: The first step of etching sets a clear stop point for "non-etching through the semiconductor". In the second step, the SF6+Ar gas has an extremely low etching rate on the GaAs / InGaP epitaxial layer, which will not attack the semiconductor material in the dicing area, thus fundamentally eliminating the risk of abnormal dicing appearance, reduced mechanical strength and chip edge breakage.

[0019] Improved production efficiency and reduced costs: The elimination of the need for a dedicated control chip to monitor the Al2O3 etching rate reduces process steps and the utilization pressure on ALD equipment, thereby improving mass production efficiency and reducing manufacturing costs.

[0020] Optimize overall product performance: Simultaneously solve two key defects, namely poor wire bonding and dicing damage, improving the overall yield of front-end manufacturing and back-end packaging of the device; reliable bonding quality and robust chip structure significantly improve the long-term reliability and service life of the product at the customer's site. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of silicon nitride deposition in its initial state. Figure 2 This is a schematic diagram of the exposure and development process in the prior art; Figure 3 This is a schematic diagram of silicon nitride after etching in the prior art; Figure 4 This is a schematic diagram of the photoresist removal process in the prior art; Figure 5 This is a schematic diagram of the process of coating photoresist before depositing the second metal electrode and then exposing and developing it in the prior art. Figure 6 This is a schematic diagram of metal deposition in the prior art; Figure 7 This is a schematic diagram of the lifting process in the prior art; Figure 8 This is a schematic diagram of Al2O3 deposition in ALD in the prior art; Figure 9 This is a schematic diagram of the existing technology after coating with a third layer of photoresist. Figure 10 This is a schematic diagram of Al2O3 after etching in the prior art; Figure 11 This is a schematic diagram of the process after removing the third layer of photoresist in the prior art; Figure 12 This is a schematic diagram after the first passivation layer has been patterned in this invention; Figure 13 This is a schematic diagram of the present invention after removing the photoresist; Figure 14 This is a schematic diagram of the metal electrode after deposition according to the present invention; Figure 15 This is a schematic diagram of Al2O3 deposition by ALD according to the present invention; Figure 16 This is a schematic diagram of the third layer of photoresist after the present invention has been coated; Figure 17 This is a schematic diagram of Al2O3 after etching according to the present invention; Figure 18 This is a schematic diagram of silicon nitride after etching according to the present invention; In the figure: 1-Gallium arsenide, 2-Ohmic contact metal, 3-First metal electrode, 4-First passivation layer, 5-First photoresist, 6-Second photoresist, 7-Second metal electrode, 8-Second passivation layer, 9-Third photoresist. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0023] A method for improving the fabrication of the etching window of the aluminum oxide passivation layer in gallium arsenide devices includes the following steps: Preparation of the first passivation layer 4: Ohmic contact metal 2 and first metal electrode 3 are sequentially formed on the epitaxial layer of gallium arsenide substrate 1, and then silicon nitride thin film is deposited as the first passivation layer 4. The first passivation layer 4 opening: the first photoresist 5 is coated, the first photoresist 5 uses positive photoresist (rotation speed 3000-5000rpm, thickness 1.82µm), and is exposed only to the PAD area through the mask. After development with 2.38% TMAH developer, the wafer is placed in a reactive ion etching machine, and SF6 gas is used to etch and remove the silicon nitride in the PAD area, while keeping the silicon nitride in the dicing area sealed. Finally, NMP solution is used to remove residual photoresist and by-products.

[0024] Depositing the second metal electrode 7: Spin-coating the second layer of photoresist 6, which is a thick-film positive photoresist (1500-5000 rpm, 6µm thickness). The PAD and metal interconnect pattern are exposed and developed by TMAH through the second mask to form the M2 pattern. Ti (30Å) / Pt (100Å) / Au (16000Å) / Ti (100Å) multilayer metals are deposited sequentially using electron beam evaporation or sputtering equipment. The photoresist and excess metal covering it are removed by immersion in NMP solution and ultrasonic or megasonic wave lifting process, leaving the patterned second metal electrode 7.

[0025] Second passivation layer 8 (Al2O3) deposition: An Al2O3 film with a thickness of 25 nm was deposited on the entire wafer surface using an atomic layer deposition (ALD) device; the deposition parameters were as follows: the metal source precursor was trimethylaluminum (TMA), the oxygen source precursor was deionized water (H2O), the deposition temperature was 80°C-250°C, and the single-cycle timing was as follows: TMA vapor pulse time was 0.05-0.1s, the first nitrogen purging time was 5-15s, the water vapor pulse time was 0.05-0.1s, and the second nitrogen purging time was 5-15s.

[0026] The third layer of photoresist 9 is coated and patterned: the third layer of positive photoresist is coated, and the PAD area and the dicing area are exposed and developed to form a patterned window. The process conditions are the same as the photolithography process for the opening of the first passivation layer 4.

[0027] Etching of Al2O3 film: Plasma etching is performed using a mixture of SF6 and O2 gas, with SF6 flow rate of 20-50 sccm and O2 flow rate of 1-5 sccm (ratio 10:1), and etching time of 30-50 seconds to remove the Al2O3 film from the surface of the PAD area and the cut track area. Etching (SiN removal and Ti removal): Plasma etching is performed using a mixture of SF6 and Ar gases, with an SF6 flow rate of 30-100 sccm and an Ar flow rate of 0-50 sccm. The etching time is 60-90 seconds to remove residual silicon nitride in the cut area and thoroughly remove Ti from the top layer of the second metal electrode 7 in the PAD area.

[0028] Subsequent processes: Similar to existing technologies, NMP solution is used to remove the third photoresist layer 9; the wafer is thinned to 100µm, back vias are fabricated, back gold is deposited, the back gold on the dicing track is etched, and the wafer is diced; finally, a solution of ammonia:hydrogen peroxide:water = 1:1:50 is used for post-dicing etching to remove the redeposited material and epitaxial layer material on the sidewalls of the dicing track. Example 1:

[0029] A method for improving the fabrication of the etching window of the aluminum oxide passivation layer in gallium arsenide (GaAs) devices, comprising the following specific steps: Preparation and opening of the first passivation layer 4: as follows Figure 1 As shown, an epitaxial layer, an ohmic contact metal 2, and a first metal electrode 3 are sequentially formed on a GaAs substrate, and a 1500 Å thick silicon nitride layer 4 is deposited as the first passivation layer using a PECVD device. A first layer of photoresist 5 was coated onto the silicon nitride surface using a spin coater at 4000 rpm. The first layer of photoresist 5 was a positive photoresist, and its thickness was controlled to be 1.82 µm. Exposure was then performed only on the PAD area using a mask, followed by development with 2.38% TMAH developer to remove the photoresist from the exposed area. (See [link to documentation]). Figure 12 Compared with existing technologies, it can be found that ( Figure 12 and Figure 2 (In comparison), the difference between this invention and the prior art in this step is that the cutting channel area has no opening; the location of the cutting channel area is shown in [reference needed]. Figure 2 .

[0030] The wafer is placed in a reactive ion etching machine, and SF6 gas is introduced to etch away the silicon nitride in the PAD area. After etching, the wafer is immersed in NMP solution to remove residual first layer photoresist 5 and byproducts. The silicon nitride in the dicing area remains intact. See [link to relevant documentation]. Figure 13 Compared with existing technologies, it can be found that ( Figure 13 and Figure 4 (In comparison), the difference between the present invention and the prior art in this step is that there is no opening in the cutting area after removing the photoresist.

[0031] Formation of the second metal electrode 7: A thick-film positive photoresist (second photoresist layer) is applied by rotary coating at 3000 rpm, achieving a photoresist thickness of 6 µm; the PAD and metal interconnect patterns are exposed and developed using a second mask, forming the M2 pattern; a multilayer metal layer of Ti (30 Å) / Pt (100 Å) / Au (16000 Å) / Ti (100 Å) is sequentially deposited using an electron beam evaporation device; the wafer is immersed in an NMP solution and subjected to ultrasonic treatment to perform a lift-off process, removing the photoresist and excess metal, retaining the patterned second metal electrode 7. See the final image. Figure 14 Compared with existing technologies (see Figure 7 A comparison reveals that the difference between the present invention and the prior art in this step is that there is no opening in the cutting channel area.

[0032] Al2O3 passivation layer deposition: An atomic layer deposition (ALD) system was used to deposit an Al2O3 film at a deposition temperature of 165°C. The metal source precursor was TMA, and the oxygen source precursor was deionized water. The single-cycle timing was as follows: TMA vapor pulse time 0.075 s, first nitrogen purging time 10 s, water vapor pulse time 0.075 s, and second nitrogen purging time 10 s. After deposition, the Al2O3 film thickness was 25 nm. See the final image for details. Figure 15 Compared with existing technologies ( Figure 8 A comparison reveals that the difference between the present invention and the prior art in this step lies in the presence of silicon nitride and AlOx2 layers in the cutting area.

[0033] Third layer photoresist coating and patterning: The third layer of positive photoresist is coated at 4000 rpm. Exposure is performed on the PAD area and the dicing area using a mask, followed by TMAH development to form a patterned window. See image below. Figure 16 Compared with existing technologies ( Figure 9 A comparison reveals that the difference between the present invention and the prior art in this step lies in the presence of silicon nitride and AlOx2 layers in the cutting area.

[0034] Two-step etching process: Step 1 Etching (Al2O3 Removal): The wafer is placed in a reactive ion etching machine, and a mixture of SF6 and O2 gases is introduced, with an SF6 flow rate of 35 sccm and an O2 flow rate of 3 sccm (ratio 10:1). The etching time is set to 40 seconds to completely remove the Al2O3 film from the surface of the PAD area and the dicing area. See image. Figure 17 ; The second step, etching (SiN removal and Ti removal): The etching gas was adjusted to a mixture of SF6 and Ar, with an SF6 flow rate of 65 sccm and an Ar flow rate of 25 sccm. The etching time was set to 75 seconds. This removed the silicon nitride in the dicing area and thoroughly removed the Ti on the top layer of the second metal electrode 7 in the PAD area, exposing the underlying Au surface. See the image. Figure 18 .

[0035] Subsequent processes: The wafer is immersed in NMP solution to remove the third photoresist layer 9; the wafer is thinned to 100µm using a grinding machine; back vias are fabricated using photolithography and etching processes, and back gold is deposited; the back gold on the dicing track is etched, and the wafer is diced using a dicing machine; finally, the diced chip is immersed in a solution of ammonia:hydrogen peroxide:water = 1:1:50 for dicing and etching to remove redeposited material and epitaxial layer material from the sidewalls of the dicing track, thus completing device manufacturing. Example 2:

[0036] The difference between this embodiment and Embodiment 1 is that: The ALD deposition temperature was 250°C, and the single-cycle timing was as follows: TMA was 0.05 s, the first nitrogen purging was 5 s, the water vapor pulse time was 0.05 s, and the second nitrogen purging time was 5 s. Etching Al2O3: SF6 flow rate is 50 sccm, O2 flow rate is 5 sccm, and etching time is 30 seconds; In the etching of SiN, the SF6 flow rate is 100 sccm, the Ar flow rate is 50 sccm, and the etching time is 60 seconds.

[0037] The remaining steps are the same as in Example 1, and can achieve the same technical effect as the present invention. Example 3:

[0038] The difference between this embodiment and Embodiment 1 is that: In step 3, the ALD deposition temperature is 80°C, and the single cycle time is 0.1s for TMA, 15s for the first nitrogen purging, 0.1s for H2O, and 15s for the second nitrogen purging. In the etching of Al2O3, the SF6 flow rate was 20 sccm, the O2 flow rate was 1 sccm, and the etching time was 50 seconds. In the etching of SiN, the SF6 flow rate is 30 sccm, the Ar flow rate is 10 sccm, and the etching time is 90 seconds.

[0039] The remaining steps are the same as in Example 1, which can effectively remove Ti residue and protect the dicing structure, thereby improving device performance.

[0040] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for improving the etching window of the alumina passivation layer in gallium arsenide devices, characterized in that, Includes the following steps: Step 1: An ohmic contact metal and a first metal electrode are sequentially formed on the epitaxial layer of a gallium arsenide substrate, and a silicon nitride thin film is deposited as the first passivation layer; Step 2: Coat the first layer of photoresist and open the first passivation layer to remove the silicon nitride in the PAD area, retain the silicon nitride in the dicing area, and remove the residual photoresist after the opening process. Step 3: Coat the second layer of photoresist, deposit the second metal electrode, and remove excess metal and photoresist after deposition; Step 4: Deposit an Al2O3 thin film as a second passivation layer on the entire wafer surface; Step 5: Apply the third layer of photoresist, align it with the PAD area and the cut area, expose and develop to form a patterned window; Step 6: Use a mixed gas of SF6 and O2 for plasma etching to remove the Al2O3 film on the surface of the PAD area and the cut track area; Step 7: Use a mixture of SF6 and Ar gas for plasma etching to remove residual silicon nitride in the cut area and thoroughly remove Ti from the top layer of the second metal electrode in the PAD area. Step 8: Remove the third layer of photoresist, and then proceed with wafer thinning, back via fabrication, back gold deposition, back gold etching of the dicing channels, and wafer dicing processes to finally complete device manufacturing.

2. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 1, characterized in that, Step 2 specifically involves: applying positive photoresist, exposing and developing the PAD area using a photomask, removing the silicon nitride in the PAD area using a reactive ion etching machine, retaining the silicon nitride in the dicing area, and then removing the residual photoresist.

3. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 2, characterized in that, In step 2, the coating speed of the positive photoresist is 3000-5000 rpm, and the photoresist thickness is controlled to be 1.82µm; After exposure, development was performed using 2.38% TMAH developer; silicon nitride etching was performed using SF6 gas, and residual photoresist was removed after etching using N-methylpyrrolidone (NMP) solution.

4. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 1, characterized in that, Step 3 specifically involves: coating a thick film of positive photoresist, exposing and developing it to form the M2 pattern, sequentially depositing multiple layers of Ti / Pt / Au / Ti metal, removing excess metal and photoresist through a lift-off process, and retaining the patterned second metal electrode.

5. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 4, characterized in that, In step 3, the coating speed of the thick film positive photoresist is 1500-5000 rpm, and the photoresist thickness reaches 6µm; the thicknesses of the multilayer metal deposition are: Ti thickness is 30Å, Pt thickness is 100Å, Au thickness is 16000Å, and Ti thickness is 100Å; the lift-off process uses NMP solution immersion and is supplemented by ultrasonic or megasonic wave treatment.

6. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 1, characterized in that, Step 4 specifically involves depositing an Al2O3 thin film as a second passivation layer on the entire wafer surface using atomic layer deposition (ALD). The parameters for atomic layer deposition are as follows: trimethylaluminum (TMA) is used as the metal source precursor, and deionized water (H2O) is used as the oxygen source precursor; the deposition temperature is 80°C-250°C; the TMA vapor pulse time is 0.05-0.1s; the first nitrogen purging time is 5-15s; the water vapor pulse time is 0.05-0.1s; and the second nitrogen purging time is 5-15s. The Al2O3 film thickness is 25 nm.

7. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 1, characterized in that, In step 6: the ratio of SF6 to O2 in the mixed gas is 10:1; the flow rate of SF6 is 20-50 sccm, the flow rate of O2 is 1-5 sccm; and the etching time is 30-50 seconds.

8. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 1, characterized in that, In step 7, the flow rate of SF6 is 30-100 sccm, the flow rate of Ar is 10-50 sccm, and the etching time is 60-90 seconds.

9. The method for manufacturing an improved aluminum oxide passivation layer etching window for gallium arsenide devices according to claim 1, characterized in that, In step 8, the wafer is thinned to 100µm; After wafer dicing, an etching process is performed using a solution of ammonia, hydrogen peroxide, and water in a ratio of 1:1:50.

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