Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductor manufacturing methods, and the method comprises the following steps: firstly, preparing a shallow trench structure on a substrate; then, an isolation layer is formed on the surface of the nitride layer through deposition, and a sunken part is formed in the position, corresponding to the shallow trench structure, of the isolation layer. And depositing and forming a hard mask layer on the surface of the isolation layer. Grinding for the first time to remove the hard mask layer around the concave part; and taking the hard mask layer as a mask pattern to etch and remove the isolation layer around the sunken part. And finally, the hard mask layer and the isolation layer are removed through secondary grinding. Compared with the prior art, the method has the advantages that no new photomask pattern is introduced, the physical structure naturally generated by the process is ingeniously utilized, the residual oxide can be removed without an AR photomask, meanwhile, the process steps are simplified, multiple steps such as photoetching, gluing, developing and photoresist removing are reduced, and the cost and time are greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing methods, and more specifically, to a method for preparing a semiconductor structure and a semiconductor structure. Background Technology

[0002] Existing BCD process platforms can integrate multiple devices onto the same silicon wafer. During the process, if the initial thickness of the oxide layer deposited on the entire silicon wafer surface is too large before Chemical Mechanical Polishing (CMP), or if the density or area of ​​the active area (AA) is too large in the design, it is necessary to remove large oxide residues on the active area (AA) to prevent oxide residues on SiN after shallow trench isolation chemical mechanical polishing (STI CMP), which would lead to uneven SiN removal in subsequent steps and seriously affect device performance.

[0003] To address this, traditional processes typically involve defining the pattern using photolithography and then etching away the unwanted large oxide layers on the AA area. This requires the use of an AR photomask, and the process is complex, involving multiple steps such as photolithography, resist coating, development, and resist removal, which increases costs and time consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing a semiconductor structure and a semiconductor structure that can remove residual oxides without an AR photomask, while simplifying the process steps and significantly reducing costs and time.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor structure, comprising: A substrate is provided, wherein a shallow trench structure is formed therein, and a nitride layer is deposited on the surface of the substrate, the shallow trench structure penetrating the nitride layer; An isolation layer is deposited on the surface of the nitride layer, the isolation layer fills the shallow trench structure, and a recess is formed at a position corresponding to the shallow trench structure; A hard mask layer is deposited on the surface of the isolation layer, and the hard mask layer also covers the inner surface of the recess; The first grinding removes the hard mask layer around the recess, while retaining the hard mask layer on the inner surface of the recess; The isolation layer surrounding the recess is removed by etching using the hard mask layer as a mask pattern; The second grinding process removes the remaining hard mask layer and the isolation layer located on the shallow trench structure, so that the isolation layer within the shallow trench structure is flush with the nitride layer.

[0006] In an optional embodiment, prior to the step of depositing an isolation layer on the surface of the nitride layer, the method further includes: A liner layer is formed on the inner wall of the shallow trench structure.

[0007] In an optional embodiment, the step of a second grinding to remove the remaining hard mask layer and the isolation layer located on the shallow trench structure includes: The residual hard mask layer is removed using a timed grinding process; An endpoint testing grinding process is used to planarize the isolation layer located on the shallow trench structure so that the isolation layer in the shallow trench structure is flush with the nitride layer.

[0008] In an optional implementation, the step of planarizing the isolation layer located on the shallow trench structure using an endpoint detection grinding process includes: Using the nitride layer as the grinding stop layer, an endpoint detection grinding process is employed to grind and remove the isolation layer located on the shallow trench structure.

[0009] In an optional implementation, the step of providing the substrate includes: A buffer layer is formed on the substrate; A nitride layer is formed on the buffer layer; A shallow trench structure is formed by slotting on the surface of the nitride layer, wherein the shallow trench structure penetrates the nitride layer and the buffer layer.

[0010] In an optional embodiment, after the step of a second grinding to remove the residual hard mask layer and the isolation layer, the method further includes: Remove the nitride layer.

[0011] In an optional embodiment, the step of depositing an isolation layer on the surface of the nitride layer includes: High-density plasma oxides are grown in the nitride layer and the shallow trench structure using a high-density plasma chemical vapor deposition process to form the isolation layer.

[0012] In an optional embodiment, both the nitride layer and the hard mask layer are made of silicon nitride.

[0013] In a second aspect, the present invention provides a semiconductor structure prepared by the semiconductor structure preparation method described in the foregoing embodiments, the semiconductor structure comprising: A substrate in which a shallow trench structure is formed; A nitride layer is deposited on the surface of the substrate, and the shallow trench structure extends through the nitride layer; An isolation layer is filled into the shallow trench structure and flush with the nitride layer.

[0014] In an optional embodiment, the width of the shallow trench structure is less than 1 μm.

[0015] The beneficial effects of the embodiments of the present invention include: The semiconductor structure fabrication method and semiconductor structure provided in this invention first form a shallow trench structure in a substrate, wherein a nitride layer is deposited on the surface of the substrate, and the shallow trench structure penetrates the nitride layer and is formed on the surface of the substrate. Then, an isolation layer is deposited on the surface of the nitride layer, wherein the isolation layer fills the shallow trench structure and forms a recess at a position corresponding to the shallow trench structure. Next, a hard mask layer is deposited on the surface of the isolation layer, wherein the hard mask layer also covers the inner surface of the recess. Then, a first grinding process removes the hard mask layer around the recess, retaining the hard mask layer on the inner surface of the recess. Next, the isolation layer around the recess is etched away using the hard mask layer as a mask pattern. Finally, a second grinding process removes the remaining hard mask layer and the isolation layer located on the shallow trench structure, so that the isolation layer within the shallow trench structure is flush with the nitride layer.

[0016] Compared to existing technologies, the semiconductor structure fabrication method and semiconductor structure provided in this invention do not introduce any new photomask patterns. Instead, they cleverly utilize the physical structures naturally generated by the process itself to form a mask pattern through their own structural form. This not only saves an AR photomask, eliminating the need to remove residual oxides, but also simplifies the process steps, reducing multiple steps such as photolithography, resist coating, development, and resist removal, significantly reducing costs and time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the relevant process flow in the existing technology; Figure 2 A flowchart illustrating the steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure corresponding to step S1 in the semiconductor structure fabrication method provided in the embodiment of the present invention. Figure 4 This is a schematic diagram of the structure corresponding to step S2 in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S3 in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the structure corresponding to step S4 in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to step S5 in the semiconductor structure fabrication method provided in the embodiment of the present invention. Figure 8 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention.

[0019] Icons: 100 - Semiconductor structure; 110 - Substrate; 120 - Nitride layer; 130 - Shallow trench structure; 140 - Buffer layer; 150 - Pad layer; 160 - Isolation layer; 161 - Recess; 170 - Hard mask layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0024] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0025] As disclosed in the background section, the existing methods for removing large oxide residues on the active region typically involve defining a pattern using photolithography and then etching away the unwanted large oxide layer on the AA region.

[0026] Specifically, see Figure 1 In the existing technology, the oxide isolation material is first prepared on the SiN layer, then an AR photomask is added on top of the STI to block the STI area, then a photolithography process is performed to define the pattern, and the oxide layer outside the AR photomask area is removed, that is, the large oxide layer that is not needed on the AA area is etched away. Finally, STI CMP is performed to make the oxide layer flush with the SiN layer, thus achieving planarization.

[0027] The use of AR photomasks increases the overall cost and complexity of the process, which involves multiple steps such as photolithography, resist coating, development, and resist removal, thus increasing both cost and time consumption.

[0028] To address the aforementioned problems, embodiments of the present invention provide a novel method for preparing a semiconductor structure and a semiconductor structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0029] See Figures 2 to 8 This invention provides a method for fabricating a semiconductor structure 100, which can remove residual oxides without an AR photomask, while simplifying the process steps and significantly reducing costs and time.

[0030] See also Figure 2 The method for preparing the semiconductor structure 100 provided in this embodiment of the invention is used to prepare the semiconductor structure 100, which is a transitional structure in the device fabrication process. Its pre-process and subsequent processes can refer to the existing BCD process.

[0031] The method for fabricating the semiconductor structure 100 provided in this embodiment of the invention may include the following steps: S1: Provide substrate.

[0032] See also Figure 3 A shallow trench structure 130 is formed in the substrate 110, and a nitride layer 120 is deposited on the surface of the substrate 110. The shallow trench structure 130 penetrates the nitride layer 120 and is formed on the surface of the substrate 110.

[0033] Specifically, a substrate 110, preferably a silicon substrate 110, can be provided first. Then, a buffer layer 140 is deposited on the substrate 110. The buffer layer 140 can be an oxide material. Then, a nitride layer 120 is formed on the buffer layer 140. The nitride layer 120 can be silicon nitride (SiN) and can be used as a mask layer for subsequent etching to form STI trenches and as a termination layer for subsequent planarization processes.

[0034] The buffer layer 140 serves to buffer the stress caused by lattice misalignment between the nitride layer 120 and the substrate 110. Then, a shallow trench structure 130 is formed on the surface of the nitride layer 120 using a shallow trench isolation (STI) process, where the shallow trench structure 130 penetrates both the nitride layer 120 and the buffer layer 140, completing the fabrication of the shallow trench structure 130 on the substrate 110. Here, the nitride layer 120 can be defined as being located in the active region (AA), i.e., the area surrounding the shallow trench structure 130.

[0035] It should be noted that after forming the shallow trench structure 130, a liner layer 150 can be formed on the inner wall of the shallow trench structure 130. The liner layer 150 can be an oxide material formed by high-density plasma deposition (STI LinerOxide). For example, an extremely thin and dense silicon dioxide layer can be grown on the silicon sidewalls and bottom of the trench by thermal oxidation, which can repair etching damage, eliminate defects, and improve interface quality.

[0036] S2: An isolation layer 160 is deposited on the surface of the nitride layer 120.

[0037] See also Figure 4 The isolation layer 160 fills the shallow trench structure 130, and a recess 161 is formed at the position corresponding to the shallow trench structure 130.

[0038] Specifically, a high-density plasma oxide layer can be grown in the nitride layer 120 and the shallow trench structure 130 using a high-density plasma chemical vapor deposition (HDP) process to form an isolation layer 160. In actual fabrication, an HDP OX layer can be grown above the shallow trench structure 130 and the active region. Due to the characteristics of the HDP process, the oxide deposited above the raised active region will be higher than the oxide deposited within the recessed shallow trench structure 130, naturally creating a height difference (the oxide height above the active region is greater than the oxide height above the shallow trench structure 130), thus forming the recess 161.

[0039] S3: A hard mask layer 170 is deposited on the surface of the isolation layer 160.

[0040] See also Figure 5 The hard mask layer 170 also covers the inner surface of the recess 161.

[0041] Specifically, a hard mask material, such as a SiN layer, can be grown above the isolation layer 160. By utilizing the structural features of the recess 161, the surface of this SiN layer can also replicate the same height difference (the height of the SiN above the active region is greater than the height of the SiN above the shallow trench structure 130), which prepares for the subsequent fabrication of the "SiN hard mask template".

[0042] S4: The first grinding removes the hard mask layer 170 around the recess 161, while retaining the hard mask layer 170 on the inner surface of the recess 161.

[0043] See also Figure 6 Specifically, a first CMP process can be used to remove SiN. SiN CMP polishing removes the SiN above the active region, specifically the SiN around the recess 161, while retaining the SiN above the shallow trench structure 130, i.e., retaining the SiN within the recess 161, thus forming a "SiN hard mask". In actual fabrication, CMP polishes higher areas faster. During SIN CMP, the polishing is done just enough to remove the SIN above the active region (at this point, the isolation layer 160 can be used as a polishing stop layer). When the SIN above the active region is completely removed, exposing the underlying isolation layer 160, the SIN above the shallow trench structure 130, because only a portion has been polished away, still remains. Finally, a "pattern" is naturally formed, where the area of ​​the shallow trench structure 130 is protected by the remaining SiN, while the isolation layer 160 of the active region is completely exposed. This "pattern" is entirely determined by the initial AA / STI layout and does not require any photomask definition.

[0044] S5: Using the hard mask layer 170 as a mask pattern, etch away the isolation layer 160 around the recess 161.

[0045] See also Figure 7 Specifically, dry etching can be used with a process that has a high selectivity for oxides, primarily etching the oxide isolation layer 160 while barely etching the SiN hard mask layer 170. This removes the isolation layer 160 above the exposed active region, while the isolation layer 160 above the shallow trench structure 130 remains intact due to the protection of the hard mask layer 170. This achieves the same purpose as traditional AR etching steps, removing large amounts of oxide above the active region.

[0046] S6: The second grinding removes the remaining hard mask layer 170 and the isolation layer 160 located on the shallow trench structure 130, so that the isolation layer 160 in the shallow trench structure 130 is flush with the nitride layer 120.

[0047] See also Figure 8 Specifically, STI CMP can be completed using a second CMP process, which can be divided into timed grinding and end-point testing grinding. First, timed grinding is used to remove the residual hard mask layer 170. Then, end-point testing grinding is used to planarize the isolation layer 160 on the shallow trench structure 130, making the isolation layer 160 flush with the nitride layer 120 within the shallow trench structure 130. During the planarization of the isolation layer 160, the nitride layer 120 is used as the grinding stop layer, and the end-point testing grinding process is used to grind the isolation layer 160.

[0048] In actual fabrication, a CMP process can be performed first. The main purpose of this stage is to grind away the hard mask layer 170 that protects the shallow trench structure 130. Because the grinding rates of SiN and oxide may differ, the time needs to be precisely controlled to ensure complete removal of the hard mask layer 170. After the SiN hard mask is removed, only the oxide isolation layer 160, which needs to be planarized, remains on the entire wafer surface. At this point, the nitride layer 120 can be used as the grinding stop layer. The CMP machine uses an endpoint detection system (e.g., monitoring changes in motor current) to accurately determine when to grind the nitride layer 120 (SiN) above the active region and then automatically stops. The result is a flat surface with the nitride layer 120 (SiN) above the active region clearly exposed, the shallow trench structure 130 filled with the isolation layer 160 (oxide material), and no oxide residue on the nitride layer 120.

[0049] After obtaining a flat surface, subsequent processes can continue, and the nitride layer 120 can be removed or retained. It should be noted that in this embodiment, both the nitride layer 120 and the hard mask layer 170 are made of silicon nitride. Of course, in other preferred embodiments of the present invention, other materials such as aluminum nitride can also be used, and no specific limitation is made here.

[0050] Please continue reading Figure 8 This invention also provides a semiconductor structure 100, which is prepared by the semiconductor structure 100 preparation method described in the foregoing embodiments.

[0051] Specifically, the semiconductor structure 100 may include a substrate 110, a nitride layer 120, and an isolation layer 160. A shallow trench structure 130 is formed on the substrate 110. The nitride layer 120 is deposited on the surface of the substrate 110, wherein the shallow trench structure 130 penetrates the nitride layer 120 and is formed on the surface of the substrate 110. The isolation layer 160 fills the shallow trench structure 130 and is flush with the nitride layer 120.

[0052] The semiconductor structure 100 is a transitional structure in the device manufacturing process, and its pre-processing and subsequent processes can refer to the existing BCD process.

[0053] Furthermore, a buffer layer 140 is formed on the substrate 110. The buffer layer 140 can buffer the stress caused by lattice misalignment between the nitride layer 120 and the substrate 110. At the same time, a liner layer 150 is formed on the inner wall of the shallow trench structure 130. The liner layer 150 can be an oxide material formed by high-density plasma deposition (STI Liner Oxide). For example, it can be an extremely thin and dense silicon dioxide layer grown on the silicon sidewalls and bottom of the trench by thermal oxidation. This layer can repair etching damage, eliminate defects, and improve interface quality.

[0054] In some embodiments, the width of the shallow trench structure 130 is less than 1 μm. It should be noted that the process method mentioned in this embodiment is mainly applicable to cases where the width of the shallow trench structure 130 is small, and is generally applicable to submicron level scenarios, such as scenarios less than 0.5 μm - 1 μm, so that the height difference of the naturally formed isolation layer 160 is large enough to perfectly replace the AR cover.

[0055] In summary, the semiconductor structure 100 fabrication method and the semiconductor structure 100 provided in this embodiment of the invention firstly fabricate a shallow trench structure 130 on a substrate 110, wherein a nitride layer 120 is deposited on the surface of the substrate 110, and the shallow trench structure 130 penetrates the nitride layer 120 and is formed on the surface of the substrate 110. Then, an isolation layer 160 is deposited on the surface of the nitride layer 120, wherein the isolation layer 160 fills the shallow trench structure 130, and a recess 161 is formed at a position corresponding to the shallow trench structure 130. Next, a hard mask layer 170 is deposited on the surface of the isolation layer 160, wherein the hard mask layer 170 fills the recess 161. Then, the hard mask layer 170 around the recess 161 is removed by a first grinding process, while retaining the hard mask layer 170 within the recess 161. Finally, the isolation layer 160 around the recess 161 is etched away using the hard mask layer 170 as a mask pattern. Finally, a second grinding process removes the hard mask layer 170 and the isolation layer 160, making the isolation layer 160 flush with the nitride layer 120. Compared to existing technologies, the semiconductor structure 100 fabrication method and semiconductor structure 100 provided in this embodiment of the invention do not introduce any new photomask patterns. Instead, they cleverly utilize the physical structure naturally generated by the process itself to form a mask pattern through the structure's own form. This not only saves an AR photomask, eliminating the need for an AR photomask to remove residual oxides, but also simplifies the process steps, reducing multiple steps such as photolithography, resist coating, development, and resist removal, significantly reducing costs and time.

[0056] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a shallow trench structure is formed therein, and a nitride layer is deposited on the surface of the substrate, the shallow trench structure penetrating the nitride layer; An isolation layer is deposited on the surface of the nitride layer, the isolation layer fills the shallow trench structure, and a recess is formed at a position corresponding to the shallow trench structure; A hard mask layer is deposited on the surface of the isolation layer, and the hard mask layer also covers the inner surface of the recess; The first grinding removes the hard mask layer around the recess, while retaining the hard mask layer on the inner surface of the recess; The isolation layer surrounding the recess is removed by etching using the hard mask layer as a mask pattern; The second grinding process removes the remaining hard mask layer and the isolation layer located on the shallow trench structure, so that the isolation layer within the shallow trench structure is flush with the nitride layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Prior to the step of depositing an isolation layer on the surface of the nitride layer, the method further includes: A liner layer is formed on the inner wall of the shallow trench structure.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second grinding step to remove the remaining hard mask layer and the isolation layer located on the shallow trench structure includes: The residual hard mask layer is removed using a timed grinding process; An endpoint testing grinding process is used to planarize the isolation layer located on the shallow trench structure so that the isolation layer in the shallow trench structure is flush with the nitride layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The step of planarizing the isolation layer located on the shallow trench structure using an endpoint testing grinding process includes: Using the nitride layer as the grinding stop layer, an endpoint detection grinding process is employed to grind and remove the isolation layer located on the shallow trench structure.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps of providing a substrate include: A buffer layer is formed on the substrate; A nitride layer is formed on the buffer layer; A shallow trench structure is formed by slotting on the surface of the nitride layer, wherein the shallow trench structure penetrates the nitride layer and the buffer layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the second grinding step to remove the remaining hard mask layer and the isolation layer, the method further includes: Remove the nitride layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of depositing an isolation layer on the surface of the nitride layer includes: High-density plasma oxides are grown in the nitride layer and the shallow trench structure using a high-density plasma chemical vapor deposition process to form the isolation layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, Both the nitride layer and the hard mask layer are made of silicon nitride.

9. A semiconductor structure, fabricated using the method for fabricating a semiconductor structure as described in claim 1, characterized in that, The semiconductor structure includes: A substrate in which a shallow trench structure is formed; A nitride layer is deposited on the surface of the substrate, and the shallow trench structure extends through the nitride layer; An isolation layer is filled into the shallow trench structure and flush with the nitride layer.

10. The semiconductor structure according to claim 9, characterized in that, The width of the shallow trench structure is less than 1 μm.

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