A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The preparation method comprises the following steps: providing a metal interconnection semi-finished product, which comprises a first dielectric layer, a metal layer arranged in the first dielectric layer and on the surface of the first dielectric layer, and a barrier layer for isolating the metal layer from the first dielectric layer; performing first planarization treatment on the metal layer with the barrier layer as a stop layer; forming a photosensitive dielectric layer on the surface of the barrier layer and the metal layer; performing second planarization treatment on the photosensitive dielectric layer under first light conditions with the barrier layer as the stop layer; performing third planarization treatment on the barrier layer under light-shielding conditions to remove the barrier layer on the surface of the first dielectric layer; performing fourth planarization treatment on the remaining photosensitive dielectric layer under second light conditions until the photosensitive dielectric layer is completely removed; and performing fifth planarization treatment on the remaining metal layer. The preparation method can reduce the notch depression of the junction area between the metal layer and the barrier layer, and is beneficial to the stability of subsequent electrical properties.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing processes, planarization is a crucial step in fabricating multilayer interconnect structures. The planarization process for metal interconnect layers is the core of this process, and its accuracy directly determines the electrical performance and long-term reliability of the semiconductor interconnect structure. During actual process implementation, due to differences in material properties between the metal interconnect layer and adjacent structures such as the substrate or barrier layer, and the influence of the physicochemical properties of the functional dielectric used in the process at the interface, localized depressions can easily form at the boundary between the metal interconnect layer and adjacent structures. These defects not only easily lead to paste residue but may also cause poor filling of subsequent dielectric layers, affecting the integrity of the interconnect structure.

[0003] Research has found that the metal materials used in the metal layers forming the metal interconnect structure (such as copper) typically possess high ductility, low hardness, and good chemical reactivity. During the grinding process, on the one hand, the metal material is easily subjected to plastic deformation due to mechanical grinding force; on the other hand, it undergoes a relatively severe chemical corrosion reaction with the functional media used in the grinding process, resulting in a relatively fast removal rate of the metal material on the surface of the metal interconnect structure. Meanwhile, the barrier layer material, as an isolation layer that blocks the diffusion of metal atoms, is usually made of materials with high hardness and strong chemical stability. Its ductility is much lower than that of the metal material, and its chemical reactivity with the functional media is weaker. Therefore, under the same grinding process parameters, the removal rate of the barrier layer material is significantly lower than that of the metal material on the surface of the metal interconnect structure. This unevenness in the grinding removal rate leads to the rapid removal of excess metal material from the surface of the metal interconnect structure while the removal of material from the barrier layer surface is slow, resulting in a stepped drop at the interface between the two. As the grinding process continues, this drop gradually evolves into a localized notch or depression (such as...). Figure 1 and Figure 2 (The structure within the red circle is shown). Invention patent CN108682650A discloses a surface planarization method and a semiconductor multilayer interconnect structure, which uses a polishing-deposition-polishing process to repair dish-shaped depressions generated during copper processing. However, this technical solution can only achieve post-processing repair of defects and fails to fundamentally solve the problem of gap depressions in the interface area caused by the difference in polishing rates between the metal layer and the barrier layer. Summary of the Invention

[0004] This invention provides a method for fabricating a semiconductor structure and a semiconductor structure to reduce the gaps and depressions at the interface between the metal layer and the barrier layer during the formation of the metal interconnect structure.

[0005] The present invention provides a method for fabricating a semiconductor structure, comprising:

[0006] A metal interconnect semi-finished device is provided, the metal interconnect semi-finished device including a first dielectric layer, a metal layer disposed in the first dielectric layer and on the surface therein, and a barrier layer that isolates the metal layer from the first dielectric layer; Using the barrier layer as a stop layer, the metal layer undergoes a first planarization process; A photosensitive dielectric layer is formed on the surfaces of the barrier layer and the metal layer; Under the first illumination condition, the photosensitive medium layer is subjected to a second planarization process using the blocking layer as a stop layer; Under light-protected conditions, the barrier layer is subjected to a third planarization process to remove the barrier layer from the surface of the first dielectric layer; Under the second illumination condition, the remaining photosensitive medium layer is subjected to a fourth planarization process until the photosensitive medium layer is completely removed. The remaining metal layer is then subjected to a fifth planarization process.

[0007] In one embodiment of the present invention, a photosensitive dielectric layer is formed on the surface of the barrier layer and the metal layer, comprising the following steps: A second dielectric layer with distributed pores is formed on the surfaces of the barrier layer and the metal layer; Photosensitive material is grafted into the hole.

[0008] In one embodiment of the present invention, a plasma-enhanced chemical vapor deposition process is used to form a second dielectric layer on the surface of the barrier layer and the metal layer. The precursor for forming the second dielectric layer is an organosilicon precursor, and the deposition temperature of the plasma-enhanced chemical vapor deposition process is 200~250°C.

[0009] In one embodiment of the present invention, the photosensitive material comprises a ferrocene-anthraquinone complex.

[0010] In one embodiment of the present invention, after the second dielectric layer is formed and before the photosensitive material is grafted into the pores, the preparation method further includes a pretreatment process for the pores.

[0011] In one embodiment of the present invention, after forming the second dielectric layer and before grafting the photosensitive material into the pores, the preparation method further includes a process of modifying the photosensitive material.

[0012] In one embodiment of the present invention, the first illumination condition and the second illumination condition are ultraviolet light irradiation.

[0013] In one embodiment of the present invention, the first planarization process, the second planarization process, the third planarization process, the fourth planarization process, and the fifth planarization process are all performed using chemical mechanical polishing.

[0014] In one embodiment of the present invention, after the first planarization process, the second planarization process, the third planarization process, the fourth planarization process, and the fifth planarization process, the metal interconnect semi-finished device is cleaned.

[0015] The present invention also provides a semiconductor structure, which is fabricated by any of the preparation methods described above.

[0016] The beneficial effects of this invention are as follows: This invention proposes a method for fabricating a semiconductor structure. First, a barrier layer is used as a stop layer to planarize a metal layer. Then, a photosensitive dielectric layer is formed on the surface of the barrier layer and the metal layer. The photosensitive dielectric layer is planarized under a first illumination condition, and the barrier layer is planarized under a light-shielded condition. Under a second illumination condition, the remaining photosensitive dielectric layer on the surface of the metal layer is removed. Finally, the remaining metal layer is planarized. An unexpected effect of this application is that: forming a photosensitive dielectric layer on the surface of the metal layer before planarizing the barrier layer; forming a passivation layer on the surface of the metal layer under a light-shielded condition; protecting the metal layer during the planarization of the barrier layer; and performing planarization on the metal layer after removing the barrier layer from the surface of the first dielectric layer, respectively, can reduce the gaps and depressions at the interface between the metal layer and the barrier layer, which is beneficial to the stability of subsequent electrical properties. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] In the attached diagram: Figure 1 Microscopic morphology diagram of a metal interconnect structure provided for the prior art; Figure 2 Microscopic morphology diagram of another metal interconnect structure provided for the prior art; Figure 3 This is a flowchart illustrating the fabrication process of a semiconductor structure provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of the formation of a first dielectric layer provided in one embodiment of the present invention; Figure 5This is a schematic diagram of the formation of a trench according to one embodiment of the present invention; Figure 6 This is a schematic diagram of forming a barrier layer according to one embodiment of the present invention; Figure 7 This is a schematic diagram of the formation of a metal layer provided in one embodiment of the present invention; Figure 8 This is a schematic diagram of a first planarization process for a metal layer provided in one embodiment of the present invention; Figure 9 This is a schematic diagram of the formation of a photosensitive dielectric layer provided in one embodiment of the present invention; Figure 10 This is a schematic diagram of the second planarization process of the photosensitive dielectric layer provided in one embodiment of the present invention; Figure 11 This is a schematic diagram of a third planarization process for a barrier layer provided in one embodiment of the present invention; Figure 12 This is a schematic diagram illustrating the fourth planarization process of the photosensitive dielectric layer and the fifth planarization process of the metal layer provided in one embodiment of the present invention.

[0019] The attached figures are labeled as follows: 10. Metal interconnect semi-finished device; 100. Substrate; 200. First dielectric layer; 210. Trench; 300. Barrier layer; 400. Metal layer; 500. Photosensitive dielectric layer. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0021] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0023] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0024] This application provides a method for fabricating a semiconductor structure and a semiconductor structure to reduce gaps and depressions at the interface between the metal layer and the barrier layer, thereby improving the integrity of the metal interconnect structure.

[0025] Please see Figures 3 to 12 As shown, the method for preparing the semiconductor structure provided by the present invention includes the following steps: S1, such as Figure 7 As shown, a metal interconnect semi-finished device 10 is provided. The metal interconnect semi-finished device 10 includes a first dielectric layer 200, a metal layer 400 disposed in the first dielectric layer 200 and on its surface, and a barrier layer 300 that isolates the metal layer 400 from the first dielectric layer 200. S2, such as Figure 8 As shown, the metal layer 400 is subjected to a first planarization process with the barrier layer 300 as the stop layer; S3, such as Figure 9 As shown, a photosensitive dielectric layer 500 is formed on the surface of the barrier layer 300 and the metal layer 400; S4, such as Figure 10 As shown, under the first illumination condition, the photosensitive medium layer 500 is subjected to a second planarization process with the blocking layer 300 as the stop layer; S5, such as Figure 11 As shown, under light-shielding conditions, the barrier layer 300 is subjected to a third planarization process to remove the barrier layer 300 on the surface of the first dielectric layer 200. S6, such as Figure 12 As shown, under the second illumination condition, the remaining photosensitive medium layer 500 is subjected to a fourth planarization process until the photosensitive medium layer 500 is completely removed. S7, such as Figure 12 As shown, the remaining metal layer 400 undergoes a fifth planarization process.

[0026] Please see Figure 7As shown, in one embodiment of the present invention, the metal interconnect semi-finished device 10 further includes a substrate 100, and a first dielectric layer 200 is formed on the surface of the substrate 100. In other embodiments, the metal interconnect semi-finished device 10 may not include the substrate 100.

[0027] Please see Figures 4 to 7 As shown, the fabrication process of the metal interconnect semi-finished device 10 is as follows: Please see Figure 4 In one embodiment of the present invention, a substrate 100 is first provided. The substrate 100 includes, for example, a substrate and a pre-structure formed on the substrate (not shown in the figure). The substrate can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. The present invention does not limit the specific material and thickness of the substrate, and the substrate can be a p-doped semiconductor substrate or an n-doped semiconductor substrate. The doping type of the impurities can be flexibly set according to the semiconductor structure to be formed.

[0028] Please see Figure 4 As shown, in one embodiment of the present invention, a first dielectric layer 200 is formed on the surface of a substrate 100. The material of the first dielectric layer 200 is, for example, an ultra-low-K dielectric material. Ultra-low-K dielectric materials are, for example, porous dielectric materials, including one or a combination of Si-based porous dielectric materials, C-based porous dielectric materials, and organic polymer porous dielectric materials. Si-based porous dielectric materials include, for example, silica aerogel, nanoporous silica, and microporous silica. C-based porous dielectric materials include, for example, porous diamond materials. Organic polymer porous dielectric materials include, for example, polyimide porous materials, polyethylene porous materials, and polysilazane porous materials. Ultra-low-K dielectric materials can also be one or a combination of SiCO, porous SiCOH, carbon, carbon aerogel, and oxide aerogel. In this embodiment, for example, the dielectric constant K of the ultra-low-K dielectric material is less than or equal to 2.2.

[0029] Please see Figure 5As shown, in one embodiment of the present invention, after forming the first dielectric layer 200, photoresist is coated on the surface of the first dielectric layer 200 to form a photoresist layer. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are used to pattern the coated photoresist layer, exposing the area corresponding to the trench 210 on the surface of the first dielectric layer 200. The patterned photoresist layer is used as a mask layer to etch the first dielectric layer 200 to form the trench 210. The shape of the trench 210 is not limited here and can be adjusted according to actual needs. For example, the cross-section of the trench 210 can be rectangular, U-shaped, or V-shaped. In this embodiment, the cross-section of the trench 210 is, for example, rectangular. When etching the first dielectric layer 200 to form the trench 210, the first dielectric layer 200 can be etched, for example, by dry etching. Dry etching includes physical etching, chemical etching, and physicochemical etching. Physical etching utilizes the sputtering effect generated by ion collisions with the surface of the etched structure to achieve etching; chemical etching achieves etching by the chemical reaction between activated etching gas and the etched structure to generate volatile compounds; physicochemical etching achieves etching through the physical and chemical interactions between ions or active groups in plasma and the etched structure. In this embodiment, the dry etching process is a plasma dry etching process, and the etching gas includes, for example, one or a mixture of several of the following: carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), or octafluorocyclobutane (C4F8). After etching, the photoresist layer is removed by wet cleaning or ashing treatment.

[0030] Please see Figure 6 As shown, in one embodiment of the present invention, a barrier layer 300 is formed after the trench 210 is formed. The barrier layer 300 covers the surface of the substrate 100 exposed by the first dielectric layer 200, the sidewalls of the trench 210, and the surface of the first dielectric layer 200. The barrier layer 300 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma-enhanced chemical vapor deposition. The thickness of the barrier layer 300 is not limited here and can be adjusted according to actual needs. The barrier layer 300 is used to reduce the probability of metal material diffusing into the first dielectric layer 200 when the filling metal layer 400 is subsequently added to the trench 210, thereby reducing the impact on the performance of the back-end circuit. The material of the barrier layer 300 is, for example, one or more of tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium nitride (TiN), zirconium nitride (ZrN), and zirconium titanium nitride (ZrTiN).

[0031] Please see Figure 7As shown, in one embodiment of the present invention, a metal layer 400 is formed after the barrier layer 300 is formed. The metal layer 400 covers the surface of the barrier layer 300 and fills the trench 210. The method for forming the metal layer 400 is, for example, an electrochemical plating (ECP) process. In this embodiment, the material of the metal layer 400 is, for example, copper.

[0032] Please see Figure 8 As shown, in one embodiment of the present invention, after the metal layer 400 is formed, a first planarization process is performed on the metal layer 400 using a barrier layer 300 as a stop layer. This first planarization process may employ chemical mechanical polishing (CMP). In semiconductor manufacturing, the main working principle of CMP is to create relative motion between the surface to be polished and the polishing pad under certain pressure and in the presence of polishing slurry. This is achieved by combining the mechanical polishing action of nano-abrasives with the chemical interaction between various chemical reagents, resulting in a highly planarized surface with low surface roughness and low defects. In this embodiment, when polishing the metal layer 400, the metal interconnect semi-finished device 10 is clamped on a polishing head, and a certain pressure is applied to the metal interconnect semi-finished device 10 through the polishing head, causing the substrate 100 to rotate on the polishing pad under the drive of the polishing head. The polishing pad can be placed above or below the metal layer 400. In this embodiment, the invention is described with the polishing pad placed below the metal layer 400. Specifically, the polishing pad is adsorbed by a pressure plate and placed below the surface of the metal layer 400 to be polished. The polishing head adsorbs and fixes the semi-finished metal interconnect device 10 above the polishing pad for polishing, with the metal layer 400 facing the polishing pad. After the metal layer 400 is subjected to a first planarization treatment, the semi-finished metal interconnect device 10 is cleaned to remove impurities and residual polishing slurry generated during the polishing process, preventing it from affecting subsequent production.

[0033] Please see Figure 9As shown, in one embodiment of the present invention, after the metal layer 400 undergoes a first planarization treatment, a photosensitive dielectric layer 500 is formed on the surfaces of the barrier layer 300 and the metal layer 400. During the formation of the photosensitive dielectric layer 500, a second dielectric layer (not shown in the figure) with distributed pores is first formed on the surfaces of the barrier layer 300 and the metal layer 400. The formation process of the second dielectric layer is not limited here, as long as the formed second dielectric layer has distributed pores. In this embodiment, for example, a plasma-enhanced chemical vapor deposition process is used to deposit the second dielectric layer on the surfaces of the barrier layer 300 and the metal layer 400. The precursor of the second dielectric layer can be an organosilicon precursor or an inorganic precursor, which can be determined according to the material of the second dielectric layer. For example, the material of the second dielectric layer is silicon-oxygen-carbon-hydrogen (SiOCH), and the precursor of the second dielectric layer is an organosilicon precursor, such as methyltriethoxysilane (MTES), tetramethylsilane (TMS), or trimethoxysilane (TMOS). For example, the deposition temperature of the plasma-enhanced chemical vapor deposition process is 200~250°C, such as any value within the range of 200°C, 220°C, 240°C, or 250°C. During the deposition of the organosilicon precursor, the active groups after precursor pyrolysis require sufficient thermal energy to migrate and rearrange on the surface, thereby forming a dense film. At a temperature of 200~250°C, the surface migration rate of the active groups after precursor pyrolysis is significantly reduced, and the groups rapidly nucleate and accumulate on the surfaces of the barrier layer 300 and the metal layer 400, forming a porous film. Furthermore, at this temperature, the plasma energy is insufficient to completely pyrolyze the organic groups, and some organic groups remain in the porous film, reducing the porosity. In some embodiments, to increase the porosity of the second dielectric layer, an annealing process is performed after the deposition of the second dielectric layer to remove unreacted organosilicon precursor from the second dielectric layer. The annealing temperature can be adjusted according to the decomposition temperature of the organosilicon precursor, ensuring that the organosilicon precursor is decomposed without affecting the porous film. Annealing, for example, can be performed in a vacuum environment, which accelerates the removal of organic group decomposition products and improves porosity. The chamber pressure during plasma-enhanced chemical vapor deposition is, for example, 0.1~2 Torr, such as any value within the range of 0.1~2 Torr (e.g., 0.1 Torr, 0.5 Torr, 1 Torr, 1.5 Torr, or 2 Torr). Lower pressure increases the mean free path of active groups and avoids collisional densification, while excessive pressure can lead to pinhole defects in the film. The pore size is not limited here and can be adjusted according to actual needs.

[0034] After forming a porous second dielectric layer, a photosensitive material is grafted into the pores of the second dielectric layer. The photosensitive material includes, for example, a ferrocene-anthraquinone complex, such as ferrocene-2,6-dihydroxyanthraquinone hexafluorophosphate, ferrocene-2,6-diaminoanthraquinone hexafluorophosphate, or 1-(ferrocenemethylamino)anthraquinone. Exemplarily, a vaporized ferrocene-anthraquinone complex is introduced into the reaction chamber under an inert atmosphere, allowing it to diffuse into the pores of the second dielectric layer and adsorb onto the inner walls of the pores. This process can be performed in the same chamber as the step of depositing the second dielectric layer, or in a different chamber. The chamber temperature is, for example, 150–180°C, such as any value within the range of 150–180°C. In other embodiments, the porous second dielectric layer can also be prepared by mixing a pore-forming agent into the precursor during the deposition of the second dielectric layer. After the deposition is completed, the pore-forming agent is decomposed and released by annealing, thereby leaving pores on the second dielectric layer.

[0035] During the formation of the second dielectric layer, due to incomplete pyrolysis of the organosilicon precursor, Si-H bonds in the form of surface suspensions are formed on the inner walls of the pores in the second dielectric layer. Based on this, in some embodiments, to improve the adhesion stability of the ferrocene-anthraquinone complex within the pores of the second dielectric layer and achieve its long-term loading, active groups capable of covalently bonding with Si-H bonds can be introduced onto the ferrocene-anthraquinone complex. The adhesion stability of the complex is enhanced through the reaction of the active groups with the Si-H bonds on the surface of the second dielectric layer. Exemplarily, alkynyl or alkenyl groups are introduced onto the ferrocene-anthraquinone complex for modification. In this embodiment, terminal alkynyl groups (-C≡CH) or terminal alkenyl groups (-CH=CH2) are selected. The terminal structure has no steric hindrance, which can significantly improve the reaction efficiency with Si-H bonds. Under relatively mild conditions, Si-H bonds can undergo regioselective addition reactions with unsaturated functional groups such as carbon-carbon double bonds (C=C) and carbon-carbon triple bonds (C≡C) to generate stable Si-C covalent bonds. Moreover, this reaction does not interact with the aromatic ring or ferrocene ring of the ferrocene-anthraquinone complex itself, and will not have an adverse effect on subsequent processes.

[0036] Due to limitations in the fabrication process itself, the second dielectric layer prepared using plasma-enhanced chemical vapor deposition (PECVD) often retains impurities within its pores. Furthermore, the original active sites on the pore walls tend to have low content and uneven distribution, and are prone to forming hydroxyl clusters or being covered by inert groups. These issues hinder polymer diffusion during photosensitive material grafting, resulting in low grafting density and uneven distribution, ultimately affecting the adhesion stability of the photosensitive material. To ensure stable covalent grafting between the pores of the second dielectric layer and the photosensitive material, pretreatment of the pores in the second dielectric layer is necessary before grafting the photosensitive material. For example, the pretreatment process is as follows: After the second dielectric layer is formed, the metal interconnect semi-finished device 10 is placed in a plasma chamber, and a mixed plasma of O2 and Ar is introduced. This causes the organic residues within the pores to undergo an oxidation reaction, generating CO2 and H2O. These products can be purged out using inert gas. This pretreatment process does not etch the Si-O-Si framework of the second dielectric layer or damage its porous structure, effectively preserving the original performance of the second dielectric layer.

[0037] Please see Figure 10 As shown, in one embodiment of the present invention, after the photosensitive dielectric layer 500 is formed, a second planarization process is performed on the photosensitive dielectric layer 500 under a first illumination, with the blocking layer 300 as a stop layer. The second planarization process, for example, employs chemical mechanical polishing (CMP). Exemplarily, the first illumination condition is ultraviolet light irradiation, and the ultraviolet light intensity under the first illumination condition is, for example, 80 mW / cm². 2 In this embodiment, the photosensitive material includes, for example, a ferrocene-anthraquinone complex. Under ultraviolet light irradiation, the ferrocene-anthraquinone complex is fully excited, and the Fe in the ferrocene... 2+ Converted to Fe 3+ Fe 3+ Catalytic oxidation of anthraquinone to anthraquinone generates a large number of highly reactive superoxide radicals. These superoxide radicals disrupt the three-dimensional network structure of the second dielectric layer, eventually breaking it down into soluble small molecules. These soluble small molecules are gradually removed during chemical mechanical polishing until the photosensitive dielectric layer 500 is planarized to be flush with the barrier layer 300, exposing the barrier layer 300 on the surface of the first dielectric layer 200. After the photosensitive dielectric layer 500 undergoes a second planarization process, the metal interconnect semi-finished device 10 is cleaned to remove impurities and residual polishing slurry generated during the polishing process, preventing any impact on subsequent production.

[0038] Please see Figure 11As shown, in one embodiment of the present invention, after planarizing the photosensitive dielectric layer 500, a third planarization process is performed on the barrier layer 300 under light-shielded conditions to remove the barrier layer 300 from the surface of the first dielectric layer 200. This third planarization process, for example, employs chemical mechanical polishing (CMP). Under light-shielded conditions, the remaining photosensitive dielectric layer 500 forms a protective layer on the surface of the metal layer 400, preventing damage to the metal layer 400 during the planarization process of the barrier layer 300. Under light-shielded conditions, anthraquinone reacts with Fe... 3+ The reaction produces anthraquinone and Fe. 2+ This process does not damage the second dielectric layer. During the third planarization treatment of the barrier layer 300, under the action of chemical mechanical polishing, the molecules on the surface of the photosensitive dielectric layer 500 are slowly consumed along with the barrier layer 300. When the surface of the photosensitive dielectric layer 500 is partially worn through, exposing the underlying metal layer 400, a small amount of metal molecules will be exposed in the polishing slurry. At this time, copper metal acts as the anode and the barrier layer 300 acts as the cathode, forming a microcouple between the metal and the barrier layer 300, resulting in a tendency to corrode. Under light-protected conditions, the instantaneous corrosion tendency, combined with the exposed copper surface, can trigger a response of the ferrocene-anthraquinone complex. This ferrocene-anthraquinone complex uses a reverse electron transfer mechanism to rapidly re-coordinate and deposit on the exposed copper points, forming new passivation film molecules to repair the consumed parts. Therefore, the protective layer is in a dynamic and sustainable consumption-regeneration equilibrium state, which can reduce the wear of the metal layer 400 during the removal of the barrier layer 300. When removing the barrier layer 300 from the surface of the first dielectric layer 200, the present invention does not limit planarization to a specific location. Depending on the semiconductor device design requirements, it can be set at any location. For example, after removing the barrier layer 300, the first dielectric layer 200 can continue to undergo chemical mechanical polishing (CMP) until the top surface of the first dielectric layer 200 is lower than the contact surface between the photosensitive dielectric layer 500 and the metal layer 400. After CMP, the metal interconnect semi-finished device 10 is cleaned to remove impurities and residual polishing slurry generated during the polishing process, preventing any impact on subsequent production.

[0039] Please see Figure 12 As shown, in one embodiment of the present invention, after grinding the top surface of the first dielectric layer 200 below the contact surface between the photosensitive dielectric layer 500 and the metal layer 400, a fourth planarization process is performed on the remaining photosensitive dielectric layer 500 under a second illumination condition until the photosensitive dielectric layer 500 is completely removed. The second illumination condition is ultraviolet light irradiation, and the ultraviolet light intensity under the second illumination condition is, for example, 30 mW / cm². 2This invention does not limit the planarization of the remaining photosensitive dielectric layer 500 to a specific location. For example, it is sufficient to completely remove the photosensitive dielectric layer 500 from the surface of the metal layer 400 to avoid affecting the fifth planarization process on the remaining metal layer 400. After removing the photosensitive dielectric layer 500 from the surface of the metal layer 400, the remaining metal layer 400 is subjected to a fifth planarization process. This invention does not limit the planarization of the metal layer 400 to a specific location. For example, the metal layer 400 can be planarized to be flush with the first dielectric layer 200. There are no special requirements for the illumination conditions during the fifth planarization process on the remaining metal layer 400. The fourth and fifth planarization processes can be performed, for example, using chemical mechanical polishing (CMP). After the fourth and fifth planarization processes, cleaning is performed to remove impurities and residual polishing slurry generated during the polishing process to prevent affecting subsequent production.

[0040] The present invention also provides a semiconductor structure prepared using the above-described method. In the semiconductor structure of the present invention, the notch depression at the interface between the metal layer and the barrier layer is improved, which is beneficial to the stability of subsequent electrical properties.

[0041] In summary, the semiconductor structure fabrication method proposed in this invention first uses a barrier layer as a stop layer to planarize a metal layer. Then, a photosensitive dielectric layer is formed on the surfaces of the barrier layer and the metal layer. The photosensitive dielectric layer is planarized under a first illumination condition, and the barrier layer is planarized under a light-shielded condition. Under a second illumination condition, the remaining photosensitive dielectric layer on the surface of the metal layer is removed. Finally, the remaining metal layer is planarized. An unexpected effect of this application is that forming a photosensitive dielectric layer on the surface of the metal layer before planarizing the barrier layer, forming a passivation layer on the surface of the metal layer under light-shielded conditions, protecting the metal layer during the planarization of the barrier layer, and performing planarization on the metal layer after removing the barrier layer from the surface of the first dielectric layer, and performing planarization on both the barrier layer and the metal layer separately, can reduce the gaps and depressions at the interface between the metal layer and the barrier layer, which is beneficial for subsequent electrical stability.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A metal interconnect semi-finished device is provided, the metal interconnect semi-finished device including a first dielectric layer, a metal layer disposed in the first dielectric layer and on the surface therein, and a barrier layer that isolates the metal layer from the first dielectric layer; Using the barrier layer as a stop layer, the metal layer undergoes a first planarization process; A photosensitive dielectric layer is formed on the surfaces of the barrier layer and the metal layer; Under the first illumination condition, the photosensitive medium layer is subjected to a second planarization process using the blocking layer as a stop layer; Under light-protected conditions, the barrier layer is subjected to a third planarization process to remove the barrier layer from the surface of the first dielectric layer; Under the second illumination condition, the remaining photosensitive medium layer is subjected to a fourth planarization process until the photosensitive medium layer is completely removed. The remaining metal layer is then subjected to a fifth planarization process; The formation of a photosensitive dielectric layer on the surfaces of the barrier layer and the metal layer includes the following steps: A second dielectric layer with distributed pores is formed on the surfaces of the barrier layer and the metal layer; A photosensitive material, comprising a ferrocene-anthraquinone complex, is grafted into the cavity.

2. The preparation method according to claim 1, characterized in that, Plasma-enhanced chemical vapor deposition (PECVD) is used to form the second dielectric layer on the surfaces of the barrier layer and the metal layer. The precursor for forming the second dielectric layer is an organosilicon precursor, and the deposition temperature of the PCVD process is 200~250℃.

3. The preparation method according to claim 2, characterized in that, After the second dielectric layer is formed, before grafting photosensitive material into the pores, the preparation method further includes a pretreatment process for the pores. The pretreatment process is as follows: after the second dielectric layer is formed, the metal interconnect semi-finished device is placed in a plasma chamber, and a mixed plasma of O2 and Ar is introduced to cause the organic residues in the pores to undergo an oxidation reaction, and the products are purged out by an inert gas.

4. The preparation method according to claim 1, characterized in that, After the second dielectric layer is formed and before the photosensitive material is grafted into the pores, the preparation method further includes a process of introducing alkynyl or alkenyl groups onto the ferrocene-anthraquinone complex for modification.

5. The preparation method according to claim 1, characterized in that, The first and second lighting conditions use ultraviolet light irradiation.

6. The preparation method according to claim 1, characterized in that, The first planarization process, the second planarization process, the third planarization process, the fourth planarization process, and the fifth planarization process all employ chemical mechanical polishing.

7. The preparation method according to claim 1, characterized in that, After the first planarization process, the second planarization process, the third planarization process, the fourth planarization process, and the fifth planarization process, the metal interconnect semi-finished device is cleaned.

8. A semiconductor structure, characterized in that, Prepared by the preparation method according to any one of claims 1 to 7.

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