Power metering device and method based on synchronization of FPGA (Field Programmable Gate Array) and GPS (Global Positioning System)

Abstract

The invention discloses a power metering device and method based on FPGA and GPS synchronization, and relates to the field of power metering. The device comprises a main processor, a coprocessor, an analog-to-digital converter and a GPS module, the analog-to-digital converter synchronously and parallelly acquires electric energy parameters of the power grid; a data acquisition and cache module in the coprocessor converts the electric energy parameters into parallel data; the GPS module provides absolute time for outputting second pulse signals for the asynchronous clock source synchronization module; an asynchronous clock source synchronization module in the coprocessor adopts a counter to dynamically calibrate clock skew based on absolute time, and generates a timestamp for each frame of data collected by the analog-to-digital converter; an FFT (Fast Fourier Transform) processing module in the coprocessor performs serial processing on parallel data with timestamps in a time division multiplexing mode by adopting hardware arbitration logic; and an electric energy quality analysis module in the main processor calculates the power of the power grid according to the FFT processing result. According to the invention, power metering can be realized with high precision and low cost.

Description

Technical Field

[0001] This application relates to the field of power metering, and in particular to a power metering device and method based on FPGA and GPS synchronization. Background Technology

[0002] With the increasing prevalence of nonlinear loads, high-precision, wide-bandwidth measurements of power quality (such as power) have become crucial. Furthermore, in smart grids, high-precision time synchronization of distributed measurement units (such as PMUs (Phasor Measurement Units)) is required to enable wide-area condition monitoring and fault analysis of the power grid.

[0003] High-precision measurement solutions typically face the following challenges: First, the synchronization problem. High-speed ADCs (Analog-to-Digital Converters) usually use independent crystal oscillators as sampling clocks, while the external GPS (Global Positioning System) PPS (Pulses Per Second) signal is usually used as the system's absolute time reference. Accurately synchronizing these two independent clock sources with frequency deviations and assigning a nanosecond-level precision timestamp to each sampling point is a technical challenge. Second, the computational bottleneck. Multi-channel data processing at high sampling rates (such as FFT (Fast Fourier Transform)) requires enormous computational resources. Traditional MCUs (Microcontroller Units) struggle to perform this in real-time, while FPGA (Field Programmable Gate Array) solutions using parallel multi-channel FFT processing consume significant hardware logic resources and are costly.

[0004] In summary, how to achieve power metering with high accuracy and low cost has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this application is to provide a power metering device and method based on FPGA and GPS synchronization, which can realize power metering with high accuracy and low cost.

[0006] To achieve the above objectives, this application provides the following solution.

[0007] In a first aspect, this application provides a power metering device based on FPGA and GPS synchronization, comprising: a main processor, a coprocessor, an analog-to-digital converter, and a GPS module; wherein the coprocessor is an FPGA.

[0008] The analog-to-digital converter is used to synchronously and in parallel acquire the power parameters of the power grid; the power parameters include voltage data and current data.

[0009] The coprocessor includes: a data acquisition and caching module, an asynchronous clock source synchronization module, and an FFT processing module; the data acquisition and caching module is used to convert the power parameters into parallel data and cache them; the GPS module is used to provide the asynchronous clock source synchronization module with the absolute time of the output second pulse signal; the asynchronous clock source synchronization module is used to generate a timestamp for each frame of data acquired by the analog-to-digital converter by dynamically calibrating the clock deviation based on the absolute time using a counter; the FFT processing module includes: an FFT IP core; the FFT IP core is used to serially process the time-stamped parallel data using hardware arbitration logic in a time-division multiplexing manner to obtain the FFT processing result.

[0010] The main processor includes a power quality analysis module; the power quality analysis module is used to calculate the power of the power grid based on the FFT processing results, and to send the power back to the data acquisition and caching module.

[0011] In one embodiment, the asynchronous clock source synchronization module specifically includes the following units.

[0012] A latching unit is used to latch a first count value and a second count value; the first count value is the instantaneous count value of the counter when the rising edge of the second pulse signal of the GPS module arrives; the second count value is the instantaneous count value of the counter when the rising edge of the synchronous output signal of the analog-to-digital converter arrives.

[0013] A phase offset calculation unit is used to calculate the phase offset of a heterogeneous clock based on the first count value and the second count value.

[0014] An absolute start time calculation unit is used to calculate the absolute start time of the current sampling frame of the analog-to-digital converter based on the absolute time and the phase deviation.

[0015] The timestamp generation unit is used to calculate the final absolute timestamp of any sampling point within the current sampling frame of the analog-to-digital converter by accumulating the nominal sampling period of the analog-to-digital converter based on the absolute start time.

[0016] In one embodiment, the phase offset is calculated using the following formula.

[0017] φ=T_SYNC_latest-T_PPS_latest; Where φ represents the phase offset; T_PPS_latest represents the first count value; and T_SYNC_latest represents the second count value.

[0018] The formula for calculating the absolute start time is as follows.

[0019] T_Frame_Start=GPS_Time+φ / f_HighSpeed_Counter.

[0020] Where T_Frame_Start represents the absolute start time; GPS_Time represents the absolute time; and f_HighSpeed_Counter represents the clock frequency of the counter.

[0021] The formula for calculating the timestamp is as follows.

[0022] Timestamp_N=T_Frame_Start+N×T_Sample.

[0023] Where Timestamp_N represents the final absolute timestamp of the Nth sampling point within the current sampling frame of the analog-to-digital converter; T_Sample represents the nominal sampling period of the analog-to-digital converter.

[0024] In one embodiment, the power quality analysis module is further configured to calculate the harmonic components and negative sequence components of the power grid based on the FFT processing results, and to transmit the harmonic components and negative sequence components back to the data acquisition and caching module.

[0025] In one embodiment, the main processor further includes a carbon emission analysis module; the carbon emission analysis module is used to calculate the carbon emission amount based on the power, the harmonic component, the negative sequence component and the carbon emission factor, and to transmit the carbon emission amount back to the data acquisition and caching module.

[0026] In one embodiment, the power metering device based on FPGA and GPS synchronization further includes a storage module.

[0027] The storage module is used to store the parallel data, the power, the harmonic components, the negative sequence components, the carbon emissions, and the timestamp.

[0028] In one embodiment, the storage module includes: SRAM and FLASH; the SRAM is used to store the parallel data; the FLASH is used to store the power, the harmonic components, the negative sequence components, the carbon emissions, and the timestamp.

[0029] In one embodiment, the coprocessor further includes an FMC slave interface module; the FFT IP core sends the FFT processing result to the main processor through the FMC slave interface module.

[0030] In one embodiment, the main processor further includes a communication module; the communication module is used to upload the power, the harmonic components, the negative sequence components, and the carbon emissions to a host computer.

[0031] Secondly, this application provides a power metering method based on FPGA and GPS synchronization. The power metering method based on FPGA and GPS synchronization is implemented using the aforementioned power metering device based on FPGA and GPS synchronization. The power metering method based on FPGA and GPS synchronization includes the following steps.

[0032] The power parameters of the power grid are acquired synchronously and in parallel by the analog-to-digital converter; the power parameters include voltage data and current data.

[0033] The electrical energy parameters are converted into parallel data and cached.

[0034] Based on the absolute time of the output second pulse signal provided by the GPS module, a counter is used to dynamically calibrate the clock deviation and generate a timestamp for each frame of data acquired by the analog-to-digital converter.

[0035] For parallel data with timestamps, hardware arbitration logic is used to perform serial processing in a time-division multiplexing manner to obtain FFT processing results; the FFT processing results are used to calculate the power of the power grid.

[0036] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a power metering device and method based on FPGA and GPS synchronization. By generating a timestamp for each frame of data collected by the analog-to-digital converter through an asynchronous clock source synchronization module, the high-precision synchronization problem of heterogeneous clock systems (GPS second pulse signal as absolute time reference, and the analog-to-digital converter using an independent crystal oscillator as sampling clock) is solved, and all collected data is timestamped, thus improving the accuracy of power metering; the FFT processing module uses a single FFT IP core for processing, avoiding the consumption of a large amount of hardware logic resources, and significantly reducing the consumption of hardware resources while ensuring high processing performance, resulting in low cost. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a power metering device based on FPGA and GPS synchronization, provided as an embodiment of this application.

[0039] Figure 2 A schematic diagram of the structure of a high-precision power metering device based on STM32L4S9 and Intel MAX 10 FPGA provided in this application embodiment.

[0040] Figure 3 The data flow diagram of power metering based on FPGA and GPS synchronization is provided for the embodiments of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] like Figure 1 As shown in the embodiment of this application, the power metering device based on FPGA and GPS synchronization includes: a main processor, a coprocessor, an analog-to-digital converter (ADC), and a GPS module; the coprocessor is an FPGA. The coprocessor includes: a data acquisition and caching module, an asynchronous clock source synchronization module, and an FFT processing module.

[0044] The analog-to-digital converter is used to synchronously and in parallel acquire the power parameters of the power grid; the power parameters include voltage data V and current data I.

[0045] The data acquisition and caching module is used to convert the power parameters into parallel data and cache them; the GPS module is used to provide the absolute time of the output pulse-per-second (PPS) signal to the asynchronous clock source synchronization module; the asynchronous clock source synchronization module is used to generate a timestamp for each frame of data acquired by the analog-to-digital converter based on the absolute time and using a counter to dynamically calibrate the clock deviation; the FFT processing module includes an FFT IP core; the FFT IP core is used to serially process the time-stamped parallel data using hardware arbitration logic in a time-division multiplexing manner to obtain the FFT processing result. The timestamp is an absolute timestamp with nanosecond precision.

[0046] The main processor includes a power quality analysis module; the power quality analysis module is used to calculate the power of the power grid based on the FFT processing results, and to send the power back to the data acquisition and caching module.

[0047] This embodiment generates a timestamp for each frame of data acquired by the analog-to-digital converter through an asynchronous clock source synchronization module, solving the high-precision synchronization problem of heterogeneous clock systems. This ensures that all acquired data has a timestamp, improving the accuracy of power metering. The FFT processing module uses a single FFT IP core for processing, avoiding the consumption of a large amount of hardware logic resources. While ensuring high processing performance, it significantly reduces hardware resource consumption and costs. At the same time, the use of the FFT IP core also enables wideband measurement. Therefore, when used in smart grids and industrial monitoring, this embodiment, based on FPGA and GPS synchronization, achieves high-precision, low-cost, and wideband power metering with absolute timestamps.

[0048] In one exemplary embodiment, the asynchronous clock source synchronization module specifically includes the following units.

[0049] A latching unit is used to latch a first count value and a second count value; the first count value is the instantaneous count value of the counter when the rising edge of the second pulse signal of the GPS module arrives; the second count value is the instantaneous count value of the counter when the rising edge of the synchronous output signal of the analog-to-digital converter arrives.

[0050] A phase offset calculation unit is used to calculate the phase offset of the heterogeneous clock based on the first count value and the second count value. The calculation formula for the phase offset is as follows.

[0051] φ=T_SYNC_latest-T_PPS_latest.

[0052] Where φ represents the phase offset; T_PPS_latest represents the first count value; and T_SYNC_latest represents the second count value.

[0053] φ represents the time difference between the sampling pulse of the analog-to-digital converter and the second pulse signal output by the GPS module within one GPS second cycle, indicating whether the sampling pulse is ahead or behind. Since the clock of the GPS module and the crystal oscillator of the analog-to-digital converter are two independent clock sources, there must be a slight frequency and phase offset between them. φ is used to precisely quantify the deviation at the current moment.

[0054] An absolute start time calculation unit is used to calculate the absolute start time of the current sampling frame of the analog-to-digital converter based on the absolute time and the phase deviation. The formula for calculating the absolute start time is as follows.

[0055] T_Frame_Start=GPS_Time+φ / f_HighSpeed_Counter.

[0056] Where T_Frame_Start represents the absolute start time; GPS_Time represents the absolute time; and f_HighSpeed_Counter represents the clock frequency of the counter, which can be 40MHz.

[0057] The timestamp generation unit is used to calculate the final absolute timestamp of any sampling point within the current sampling frame of the analog-to-digital converter by accumulating the nominal sampling period of the analog-to-digital converter based on the absolute start time. The formula for calculating the timestamp is as follows.

[0058] Timestamp_N=T_Frame_Start+N×T_Sample.

[0059] Where Timestamp_N represents the final absolute timestamp of the Nth sampling point within the current sampling frame of the analog-to-digital converter; T_Sample represents the nominal sampling period of the analog-to-digital converter.

[0060] It should be noted that the crystal oscillator frequency is affected by factors such as temperature and voltage, causing it to drift, and the value of φ is not constant. In this embodiment, the asynchronous clock source synchronization module repeats the latching and calculation of φ every time a second pulse signal from the GPS module arrives. This way, even if the crystal oscillator frequency experiences a slight drift, the phase offset can be dynamically updated every second. Ultimately, the timestamp of any sampling point of the analog-to-digital converter can be calculated with high precision.

[0061] In another exemplary embodiment of this application, the main processor may be an STM32 series ARM processor, such as STM32L4S9; the FPGA used by the coprocessor may be a 10M40DCF256.

[0062] In another exemplary embodiment of this application, the power quality analysis module is further configured to calculate the harmonic components and negative sequence components of the power grid based on the FFT processing results, and to send the harmonic components and negative sequence components back to the data acquisition and caching module.

[0063] Traditional electricity meters mainly focus on the measurement of fundamental frequency energy, but have limited ability to analyze power quality parameters such as harmonics and interharmonics. This embodiment can accurately measure the power components of the fundamental frequency and each harmonic, and realize power quality analysis.

[0064] In another exemplary embodiment of this application, such as Figure 1As shown, the main processor further includes a carbon emission analysis module; the carbon emission analysis module is used to calculate the carbon emission amount based on the power, the harmonic component, the negative sequence component and the carbon emission factor, and to transmit the carbon emission amount back to the data acquisition and caching module.

[0065] In another exemplary embodiment of this application, such as Figure 1 As shown, the power metering device based on FPGA and GPS synchronization further includes: a storage module; the storage module is used to store the parallel data, the power, the harmonic components, the negative sequence components, the carbon emissions, and the timestamp.

[0066] In another exemplary embodiment of this application, the storage module includes: SRAM and FLASH; the SRAM is used to store the parallel data; the FLASH is used to store the power, the harmonic components, the negative sequence components, the carbon emissions, and the timestamp.

[0067] In another exemplary embodiment of this application, such as Figure 1 As shown, the coprocessor further includes an FMC slave interface module; the FFT IP core sends the FFT processing result to the main processor through the FMC slave interface module.

[0068] In another exemplary embodiment of this application, such as Figure 1 As shown, the main processor further includes a communication module; the communication module is used to upload the power, the harmonic components, the negative sequence components and the carbon emissions to the host computer.

[0069] In another exemplary embodiment of this application, such as Figure 1 As shown, the main processor further includes a data reading module; the data reading module is used to read the FFT processing result.

[0070] The following section uses the analog-to-digital converter acquiring six channels of data as an example to provide a more detailed explanation of the power metering device based on FPGA and GPS synchronization.

[0071] The power metering device based on FPGA and GPS synchronization includes: a main processor, a coprocessor, an analog-to-digital converter, a GPS module, and a storage module. The coprocessor includes: a data acquisition and caching module, an asynchronous clock source synchronization module, an FFT processing module, and an FMC slave interface module.

[0072] The analog-to-digital converter (ADC) is used to acquire three-phase voltage and three-phase current data, totaling six data channels. Specifically, the ADC synchronously and in parallel acquires voltage and current data from six channels at a rate of 32 ksps, where each data channel is a serial 32-bit data (adc_chx_in), and sends the acquired data to the data acquisition and buffering module.

[0073] The data acquisition and caching module is used to receive, process and cache the 6 channels of data adc_chx_in acquired in parallel. It converts each 32-bit serial data adc_chx_in into 32-bit parallel data datax_received[31..0] and caches the 6 channels of parallel data datax_received[31..0] in the SRAM data block of the storage module in sequence.

[0074] The asynchronous clock source synchronization module dynamically calibrates the clock deviation using an internal high-speed counter (e.g., 40MHz), generating nanosecond-level timestamps for each frame of data. When the rising edge of the second pulse signal output by the GPS module arrives, the instantaneous count value T_PPS_latest of the counter is latched; when the rising edge of the synchronization output signal (SYNC_OUT or DRDY) of the analog-to-digital converter arrives, the instantaneous count value T_SYNC_latest of the counter is latched. T_PPS_latest marks the position of the absolute time base on the high-speed counter, and T_SYNC_latest marks the position of the analog-to-digital converter sampling clock on the high-speed counter. The purpose of the asynchronous clock source synchronization module marking these two values ​​is to use the same high-speed, stable clock as a reference to "capture" and record different events (the second pulse signal output by the GPS module and the pulse signal output by the analog-to-digital converter) when they occur.

[0075] When the device is first started, the asynchronous clock source synchronization module records the initial phase offset φ; thereafter, every second when a new second pulse signal arrives, T_PPS_latest and T_SYNC_latest are remeasured and φ is dynamically corrected to eliminate long-term frequency drift between independent clock sources.

[0076] The FFT processing module instantiates only one high-performance FFT IP core (such as the FFT IP core provided by Intel). Through hardware arbitration logic, data blocks from 6 channels are sent to the FFT IP core in turn in a time-division multiplexing manner for serial processing, which greatly saves FPGA logic element (LE) and digital signal processor (DSP) resources.

[0077] When the FFT processing module sends data blocks from 6 channels into an FFT IP core for serial processing via time-division multiplexing, its inputs and outputs can be explicitly defined as follows.

[0078] Input: The input to the FFT IP core is a serial complex or real number data stream. In this time division multiplexing (TDM) scenario, the input receives data blocks from 6 different channels, which are sent in turn in a fixed order and at fixed time intervals.

[0079] Data type: Input data can be real numbers (if only the amplitude of the signal is processed) or complex numbers (if phase information needs to be preserved). Typically, the FFT IP processes complex data.

[0080] Input stream: A single serial data stream consisting of alternating blocks of data from 6 channels. For example, a complete FFT frame may be composed of [channel 1 data block, channel 2 data block, ..., channel 6 data block] concatenated in sequence.

[0081] Input data format: To support time-division multiplexing, a multiplexer (MUX) or similar logic is required to select a data point from the six channels within each clock cycle or time slice and feed it into the FFT IP core. Each channel's data block (e.g., containing 1024 samples) is fed in completely before switching to the next channel.

[0082] Control signals: Clock signal (CLK), drives the internal logic and data transmission of the FFT core; Enable signal (EN), indicates the validity of the data input; Data selection signal (SEL), used to control the multiplexer to select the channel data that should be sent to the FFT IP core; Frame synchronization signal (FS), indicates the start of a new data frame (i.e., after all 6 channels' data blocks have been executed in turn once).

[0083] Output: The output of the FFT IP core is the frequency domain representation of the corresponding input data block. It is also a serial complex data stream, and the output data corresponds one-to-one with the order of the input data blocks.

[0084] Data type: Output data is usually in complex form, including the amplitude and phase information of each frequency component.

[0085] Output stream: A single serial data stream containing the FFT processing results of all 6 channel data blocks, in the same order as the input. For example, after receiving and processing the first channel's data block, the FFT IP core outputs the frequency domain result for the first channel; then it outputs the result for the second channel, and so on.

[0086] Output data format: Output data points appear in a continuous sequence. After the FFT IP core has completed its operation, a demultiplexer (DEMUX) or similar logic is required to redistribute the serial output data stream to its respective subsequent processing modules according to the original channel order.

[0087] Control signals: Clock signal (CLK), synchronized with the input clock; Output ready signal (READY / VALID), indicating that the FFT IP core has completed calculation and the output data is valid; Output data select signal (SEL), used for demultiplexing to send the data to the correct channel processing module.

[0088] The FMC slave interface module is used to map the FFT processing result buffer and control / status register inside the FPGA to the FMC address space of the main processor.

[0089] The main processor is used for complex calculations, storage, and communication, and includes a data reading module, a power quality analysis module, a carbon emission analysis module, and a communication module.

[0090] The main processor uses the FreeRTOS operating system for complex computation and communication multitasking, including data reading, power quality analysis, carbon emission analysis, and communication tasks. Data flows from the FPGA to the main processor in parallel. After processing, the main processor either uploads the data to the host computer via communication or sends it back to the FPGA via a parallel bus. The FPGA then stores the data in the FLASH memory of the storage module.

[0091] The data reading module is used to read FPGA data (i.e., FFT processing results) at high speed through the FMC slave interface module; the power quality analysis module is used to perform power calculation, harmonic analysis, and negative sequence component calculation; the carbon emission analysis module is used to calculate carbon emissions based on the power quality analysis module and the carbon emission factor received from network communication and locally corrected; the communication module is used to upload data to the host computer via communication and to send data back to the FPGA via a parallel bus, and the FPGA then stores the data in the FLASH memory of the storage module.

[0092] The GPS module employs a high-precision time generator to generate second pulse signals; the host computer is used to receive and display data; the storage module includes SRAM for short-term data caching and FLASH for long-term storage of results such as power, harmonic content, carbon emission data, and timestamps.

[0093] The power metering device based on FPGA and GPS synchronization in this embodiment is mainly implemented through the following steps.

[0094] Step 1: Heterogeneous Hardware Architecture. This embodiment adopts a heterogeneous computing architecture based on FPGA and ARM (STM32). The FPGA side is responsible for high-speed, real-time front-end tasks, including multi-channel data acquisition, heterogeneous clock synchronization, data preprocessing (such as windowing), and frequency domain transformation (FFT). The ARM side is responsible for high-level complex calculations and control, including power, harmonic and negative sequence analysis, carbon emission calculation, data storage, and communication.

[0095] Step 2: High-precision time synchronization. The second pulse signal output by the GPS module and the synchronization output signal of the multi-channel analog-to-digital converter (such as the SYNC_OUT or DRDY signal of AD7768) are simultaneously input into the FPGA.

[0096] Inside the FPGA, a free-running counter driven by a stable high-speed clock such as 40MHz is used. The value of this high-speed counter is latched when the rising edge of the second pulse signal and the rising edge of the analog-to-digital converter synchronization signal arrive.

[0097] The initial phase offset φ between the two is calculated using an FPGA. With each subsequent second pulse signal, the offset φ is dynamically recalculated and used to correct the timestamp, thereby eliminating long-term frequency and temperature drift between the analog-to-digital converter crystal oscillator and the second pulse signal output by the GPS module.

[0098] Step 3: Optimize multi-channel FFT processing resources.

[0099] Only one high-performance FFT IP core is instantiated inside the FPGA.

[0100] The FFT IP core uses time-division multiplexing to sequentially process the buffered data blocks of the six channels (three-phase voltage + three-phase current) through the FPGA's internal arbiter. The FFT IP core's operating clock is much higher than the data acquisition rate, ensuring that it can complete the FFT calculations of all channels before the next frame of data acquisition is completed, thus achieving real-time performance.

[0101] Step 4: High-speed data transmission and frequency domain power calculation.

[0102] The FPGA caches the processed, timestamped frequency domain data (i.e., the FFT processing result) in its internal memory and provides high-speed parallel access to the main processor through the host processor's Flexible Memory Controller (FMC) bus, which simulates an SRAM device interface.

[0103] After reading frequency domain data from the FPGA, the main processor executes complex power quality algorithms, including: calculating the complex power S_complex of each harmonic using the formula S_complex=V×conj(I), where V represents voltage data, I represents current data, and conj represents the complex conjugate; calculating the active power P using the formula P=real(S_complex), where real represents the real part; calculating the reactive power Q using the formula Q=imag(S_complex), where imag represents the imaginary part; and calculating the total harmonic distortion and negative sequence components.

[0104] The following is combined Figure 2 and Figure 3 This paper describes a high-precision power metering device based on STM32L4S9 and Intel MAX 10 FPGA. This device is suitable for applications requiring high-precision measurement of electrical parameters with absolute timestamps. The device employs a master-slave collaborative distributed processing architecture, fully utilizing the parallel processing capabilities of the FPGA and the complex computational and control capabilities of the MCU.

[0105] 1. Hardware platform and core interfaces.

[0106] Main Processor: The STM32L4S9 from the STM32L4 series is selected as the system's main controller, responsible for advanced computing, communication, and human-machine interaction. Coprocessor (FPGA): The Intel MAX 10 (10M40DCF256) from the Intel MAX 10 series is selected, responsible for high-speed data acquisition and preprocessing. ADC: The AD7768 is selected for acquiring six channels of three-phase voltage and three-phase current data. GPS Module: Provides high-precision second pulse signals. SRAM: Responsible for buffering sampled data; SRAM capacity ≥ 2Mbit. FLASH: Responsible for long-term storage of power, carbon emission, and other results; FLASH capacity ≥ 512Mbit. Resistor Divider Network: Responsible for sampling the raw voltage. Current Sensor: Responsible for sampling the raw current data. Conditioning Circuit (Instrument-grade IC): Responsible for converting the raw current and voltage sampling signals into a voltage range that the ADC can process. Display Module: Responsible for displaying power, carbon emission, and other data. Communication Module: Responsible for receiving the initial carbon emission factor and transmitting power, carbon emission, and other data to the concentrator. Core Interface: The host processor's Flexible Memory Controller (FMC) bus connects to the FPGA in 16-bit parallel mode. The FPGA is configured to emulate an SRAM device, allowing direct access to its internal registers and data buffers by the host processor, achieving high-speed, efficient data transfer. The connections between the above components are as follows: Figure 2 As shown.

[0107] 2. FPGA Internal Module Implementation. The following key modules are implemented internally in the FPGA using a Hardware Description Language (HDL).

[0108] (1) Data acquisition and caching module.

[0109] This module acts as the main controller for the AD7768, synchronously and in parallel acquiring voltage and current data from six channels at a rate of 32kHz. The acquired raw data is cached in external SRAM.

[0110] (2) High-precision timestamp generator (core): A 32-bit high-speed counter driven by a 40MHz master clock runs freely inside the FPGA. When the rising edge of the second pulse signal output by the GPS module arrives, the value of the counter, T_PPS_latest, is latched. When the rising edge of the ADC synchronization output signal (SYNC_OUT or DRDY) arrives, the value of the counter, T_SYNC_latest, is latched.

[0111] Dynamic calibration: Upon initial startup, the system records an initial phase offset φ. Subsequently, every second, with the arrival of the rising edge of the new second pulse signal, T_PPS_latest and T_SYNC_latest are remeasured, and φ is dynamically corrected to eliminate long-term frequency drift between independent clock sources.

[0112] Finally, an absolute timestamp with nanosecond precision is generated for each sampled frame.

[0113] (3) FFT processing module.

[0114] Only one high-performance FFT IP core is instantiated within the FPGA. Through hardware arbitration logic, data blocks from 6 channels are fed into the FFT core in turn in a time-division multiplexing manner for serial processing, which greatly saves FPGA logic units and DSP resources.

[0115] (4) FMC slave interface module.

[0116] This module maps the FPGA's internal FFT result buffer and control / status registers to the STM32's FMC address space. For example: FMC address 0x0000: Control register, used by the STM32 to configure the FPGA (e.g., start / stop acquisition). FMC address 0x0004: Status register, used by the STM32 to query the FPGA status (e.g., data ready). FMC addresses 0x1000 and above: FFT result buffer, allowing the STM32 to directly read the frequency domain phasor data from each channel.

[0117] 3. STM32 software implementation.

[0118] The STM32L4S9 main processor runs a FreeRTOS real-time operating system, divided into the following core tasks: FMC_Comm_Task: Highest priority task, reads FFT results and high-precision timestamps from the FPGA via the FMC bus, and performs preliminary data verification. Power_Quality_Task: High-level task, receives FFT processing results and executes core power quality algorithms. For example, it reads voltage data V and current data I, executes complex power calculation formulas, and obtains active power P and reactive power Q. This task also calculates parameters such as total harmonic distortion and negative sequence components. Carbon_Calc_Task: Medium priority task, calculates and accumulates carbon emissions in real time based on the active power data calculated by Power_Quality_Task and a preset carbon emission factor. Network_Task: Low priority task, responsible for uploading calculation results to the cloud platform or host computer via Ethernet or a 4G module.

[0119] 4. Complete data stream.

[0120] like Figure 3 As shown, the data flow of the entire device is as follows.

[0121] Acquisition: The AD7768 synchronously acquires power parameters (three-phase voltage data V and three-phase current data I). ​​The data acquired by the AD7768 is transmitted as analog signals. The AD7768 is a 6-channel, 24-bit ADC. The AD7768 sends the power parameters to the FPGA (Intel MAX 10 10M40) via the parallel data bus ADC_DATA[15:0]&DRDY. Preprocessing: The FPGA uses a timestamp generator to add an absolute timestamp with nanosecond precision to each frame of data, and then performs preprocessing such as windowing on the data. Processing: The FPGA uses its built-in FFT processing module (single FFT IP core) to perform Fourier transform on the multi-channel data in a single-core time-division multiplexing manner, and stores the results in its internal memory. Transmission: The STM32L4S9 directly reads the FFT results and timestamps mapped inside the FPGA via the FMC bus. Calculation: The STM32L4S9 executes complex power, harmonic, and carbon emission analysis algorithms at the software level. Output: The STM32L4S9 will send the final result via the network interface or store it in NAND FLASH for later retrieval.

[0122] The power metering device based on FPGA and GPS synchronization described in the above embodiments balances high precision, high real-time performance, and high cost-effectiveness. It solves the problem of high-precision synchronization of heterogeneous clock systems and achieves nanosecond-level absolute timestamp marking of all measurement data. Through innovative hardware and software architecture, it significantly reduces hardware resource consumption while ensuring high processing performance. It can accurately measure the fundamental and harmonic power components and realize power quality analysis.

[0123] Based on the same inventive concept, this application also provides a power metering method based on FPGA and GPS synchronization implemented using the aforementioned power metering device based on FPGA and GPS synchronization. The solution provided by this method is similar to the implementation described in the aforementioned device. Therefore, the specific limitations in one or more embodiments of the power metering method based on FPGA and GPS synchronization provided below can be found in the limitations of the power metering device based on FPGA and GPS synchronization described above, and will not be repeated here.

[0124] In an exemplary embodiment, a power metering method based on FPGA and GPS synchronization is provided, comprising: acquiring power parameters of the power grid synchronously and in parallel collected by an analog-to-digital converter; the power parameters including voltage data and current data. The power parameters are converted into parallel data and cached. Based on the absolute time of the output second pulse signal provided by the GPS module, a counter is used to dynamically calibrate the clock deviation, generating a timestamp for each frame of data collected by the analog-to-digital converter. For the timestamped parallel data, hardware arbitration logic is used to perform serial processing in a time-division multiplexing manner to obtain an FFT processing result; the FFT processing result is used to calculate the power of the power grid.

[0125] As an optional implementation method, the power metering method based on FPGA and GPS synchronization uses the absolute time of the output second pulse signal provided by the GPS module, and a counter is used to dynamically calibrate the clock deviation to generate a timestamp for each frame of data collected by the analog-to-digital converter. A specific implementation process is as follows.

[0126] This step generates an absolute timestamp based on dynamic phase calibration, which solves the long-term drift and phase deviation problem between the independent crystal oscillator clock source of the analog-to-digital converter and the time reference of the second pulse signal output by GPS. The specific process of implementing the precise timestamp is as follows.

[0127] 1. Synchronization signal latching: Inside the FPGA, a free-running high-speed counter driven by a high-frequency stable clock (e.g., 40MHz) is used as a unified nanosecond-level time base. On this counter, the instantaneous count values ​​of two key events within the same second period are captured and latched: (1) The counter value T_PPS_latest is latched when the rising edge of the second pulse signal output by the GPS arrives. (2) The counter value T_SYNC_latest is latched when the rising edge of the analog-to-digital converter synchronization output signal (e.g., DRDY) arrives.

[0128] 2. Phase Shift Calculation: Calculate the phase shift φ of the heterogeneous clock. This φ value precisely quantifies the nanosecond-level time difference between the starting point of the analog-to-digital converter sampling frame and the second pulse anchor point output by the GPS module. φ can be positive or negative, corresponding to lead or lag.

[0129] 3. Frame start time calibration (eliminating systematic bias): Using the PPS absolute time (GPS_Time) and the calculated φ value, determine the absolute start time T_Frame_Start of the current analog-to-digital converter sampling frame.

[0130] 4. Dynamic correction: Steps 1 to 3 above are repeated once per second to dynamically calibrate the φ value, ensuring that the system can eliminate long-term frequency and phase drift of the independent crystal oscillator clock source of the analog-to-digital converter relative to the GPS module reference in real time.

[0131] 5. Accumulation of sampling point times (generation of final timestamp): Once the start time T_Frame_Start is calibrated, the final absolute timestamp (Timestamp_N) of any Nth sampling point within the frame can be obtained by accumulating the nominal sampling period (T_Sample) of the digital converter.

[0132] The embodiments described above have the following advantages.

[0133] (1) Ultra-high precision synchronization: It solves the synchronization problem of heterogeneous clock systems, realizes nanosecond-level absolute timestamps, and lays the foundation for multi-device collaborative measurement.

[0134] (2) Fine measurement granularity: It can accurately decompose and measure the independent power contribution of the fundamental wave and each harmonic, providing a more comprehensive data analysis capability.

[0135] (3) Optimal resources and performance: By using the heterogeneous architecture of FPGA and ARM and the single FFT IP core reuse strategy, the hardware cost and resource consumption are greatly reduced while meeting the high real-time requirements.

[0136] (4) Flexible software iteration: The complex algorithm operation is placed on the ARM side, which facilitates the subsequent algorithm upgrade and function expansion without redesigning the FPGA hardware logic.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power metering device based on FPGA and GPS synchronization, characterized in that, include: Main processor, coprocessor, analog-to-digital converter, and GPS module; The coprocessor is an FPGA; The analog-to-digital converter is used to synchronously and in parallel acquire the power parameters of the power grid; The electrical energy parameters include: voltage data and current data; The coprocessor includes: a data acquisition and caching module, an asynchronous clock source synchronization module, and an FFT processing module; the data acquisition and caching module is used to convert the power parameters into parallel data and cache them; the GPS module is used to provide the asynchronous clock source synchronization module with the absolute time of the output second pulse signal; the asynchronous clock source synchronization module is used to dynamically calibrate the clock deviation using a counter based on the absolute time, and generate a timestamp for each frame of data acquired by the analog-to-digital converter; the FFT processing module includes: an FFT IP core; the FFT IP core is used to serially process the time-stamped parallel data using hardware arbitration logic in a time-division multiplexing manner to obtain the FFT processing result; The main processor includes a power quality analysis module; the power quality analysis module is used to calculate the power of the power grid based on the FFT processing results, and to send the power back to the data acquisition and caching module.

2. The power metering device based on FPGA and GPS synchronization according to claim 1, characterized in that, The asynchronous clock source synchronization module specifically includes: A latching unit is used to latch a first count value and a second count value; the first count value is the instantaneous count value of the counter when the rising edge of the second pulse signal of the GPS module arrives; the second count value is the instantaneous count value of the counter when the rising edge of the synchronous output signal of the analog-to-digital converter arrives. A phase offset calculation unit is used to calculate the phase offset of the heterogeneous clock based on the first count value and the second count value; An absolute start time calculation unit is used to calculate the absolute start time of the current sampling frame of the analog-to-digital converter based on the absolute time and the phase deviation; The timestamp generation unit is used to calculate the final absolute timestamp of any sampling point within the current sampling frame of the analog-to-digital converter by accumulating the nominal sampling period of the analog-to-digital converter based on the absolute start time.

3. The power metering device based on FPGA and GPS synchronization according to claim 2, characterized in that, The formula for calculating the phase shift is: φ=T_SYNC_latest-T_PPS_latest; Where φ represents the phase offset; T_PPS_latest represents the first count value; and T_SYNC_latest represents the second count value. The formula for calculating the absolute start time is: T_Frame_Start=GPS_Time+φ / f_HighSpeed_Counter; Where T_Frame_Start represents the absolute start time; GPS_Time represents the absolute time; and f_HighSpeed_Counter represents the clock frequency of the counter. The formula for calculating the timestamp is: Timestamp_N=T_Frame_Start+N×T_Sample; Where Timestamp_N represents the final absolute timestamp of the Nth sampling point within the current sampling frame of the analog-to-digital converter; T_Sample represents the nominal sampling period of the analog-to-digital converter.

4. The power metering device based on FPGA and GPS synchronization according to claim 1, characterized in that, The power quality analysis module is also used to calculate the harmonic components and negative sequence components of the power grid based on the FFT processing results, and to send the harmonic components and negative sequence components back to the data acquisition and caching module.

5. The power metering device based on FPGA and GPS synchronization according to claim 4, characterized in that, The main processor also includes: a carbon emission analysis module; The carbon emission analysis module is used to calculate the carbon emission amount based on the power, the harmonic component, the negative sequence component, and the carbon emission factor, and to transmit the carbon emission amount back to the data acquisition and caching module.

6. The power metering device based on FPGA and GPS synchronization according to claim 5, characterized in that, The power metering device based on FPGA and GPS synchronization also includes: a storage module; The storage module is used to store the parallel data, the power, the harmonic components, the negative sequence components, the carbon emissions, and the timestamp.

7. The power metering device based on FPGA and GPS synchronization according to claim 6, characterized in that, The storage module includes: SRAM and FLASH; The SRAM is used to store the parallel data; the FLASH is used to store the power, the harmonic components, the negative sequence components, the carbon emissions, and the timestamp.

8. The power metering device based on FPGA and GPS synchronization according to claim 1, characterized in that, The coprocessor also includes: an FMC slave interface module; The FFT IP core sends the FFT processing result to the main processor through the FMC slave interface module.

9. The power metering device based on FPGA and GPS synchronization according to claim 5, characterized in that, The main processor also includes: a communication module; The communication module is used to upload the power, the harmonic components, the negative sequence components, and the carbon emissions to the host computer.

10. A power metering method based on FPGA and GPS synchronization, characterized in that, The power metering method based on FPGA and GPS synchronization is implemented using the power metering device based on FPGA and GPS synchronization as described in any one of claims 1-9. The power metering method based on FPGA and GPS synchronization includes: The power parameters of the power grid are acquired synchronously and in parallel by the analog-to-digital converter; the power parameters include voltage data and current data. The electrical energy parameters are converted into parallel data and cached. Based on the absolute time of the output second pulse signal provided by the GPS module, a counter is used to dynamically calibrate the clock deviation and generate a timestamp for each frame of data acquired by the analog-to-digital converter. For parallel data with timestamps, hardware arbitration logic is used to perform serial processing in a time-division multiplexing manner to obtain FFT processing results; the FFT processing results are used to calculate the power of the power grid.

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