High-sensitivity heterojunction spectrum detection system and data acquisition method thereof

Abstract

The invention relates to the technical field of semiconductor device photoelectric performance testing, and discloses a high-sensitivity heterojunction spectrum detection system and a data acquisition method thereof, and the system comprises a bias voltage control unit, a signal acquisition unit, a digital processing unit and an upper computer processing unit. The digital processing unit adopts a trapezoidal hysteresis scanning strategy, and utilizes a transient shielding window and asymmetric residence time to induce charge hysteresis; and performing synchronous demodulation on the current response through a parallel channel, extracting differential conductance, differential capacitance and second harmonic components, and correcting a system phase error by using a rotation matrix. The upper computer processing unit constructs an augmented matrix based on multi-dimensional physical parameters, combines a physical kernel function, and utilizes a mixed regularization algorithm with smooth and sparse constraints to invert and calculate an interface state density distribution spectrum. According to the method, the problems of large signal scanning interference and inversion ill-conditioned conditions in general detection are solved, and high-precision quantitative characterization of interface state defects is realized.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic performance testing technology for semiconductor devices, specifically a high-sensitivity heterojunction spectral detection system and its data acquisition method. Background Technology

[0002] The performance of heterojunction devices largely depends on the quality of the heterojunction interface. Dangling bonds, lattice mismatches, or interface state traps introduced by impurities at the interface can become recombination centers for charge carriers, significantly increasing dark current and reducing the device's photoelectric conversion efficiency. Therefore, accurately characterizing the interface state density and its energy level distribution is a key step in optimizing device fabrication. Commonly used electrical characterization methods include capacitance-voltage measurements, admittance spectroscopy, and deep-level transient spectroscopy. These methods primarily deduce the physical parameters of the traps by detecting changes in capacitance and conductance under bias or temperature excitation.

[0003] However, existing technologies have limitations when performing high-sensitivity detection on high-impedance heterojunction devices. Traditional voltage scanning methods typically employ continuous linear scanning or simple step scanning. Continuous scanning leads to the aliasing of displacement current and trap charging / discharging current, making them difficult to distinguish; while simple step scanning, without precise timing control, can cause transient impacts at voltage switching moments to overwhelm weak steady-state response signals, resulting in a reduced signal-to-noise ratio of the measurement data. Furthermore, the charging and discharging process of deep-level defects is often accompanied by significant hysteresis effects, and conventional unidirectional or symmetrical scanning methods struggle to capture these non-equilibrium dynamic characteristics, leading to missed detections of deep defects.

[0004] At the signal processing level, the response current induced by interface states is often overwhelmed by large volume leakage current and background noise. Traditional analog lock-in amplifiers or measurement devices based on simple digital integration are susceptible to the effects of readout circuit propagation delay and anti-aliasing filter phase shift when processing wideband weak signals. This phase error causes confusion in the calculation of capacitive components (stored charge) and conductive components (dissipated charge), resulting in distorted final calculated differential capacitance and differential conductance values ​​that fail to accurately reflect the physical impedance characteristics of the device.

[0005] At the data inversion level, deriving the microscopic interface state density distribution from measured macroscopic physical quantities mathematically falls under the solution process of the first kind of Friedholm integral equation. This is a typical ill-conditioned inverse problem; minute noise in the measurement data is drastically amplified during the direct inversion process, leading to violent, non-physical oscillations in the calculated energy level spectrum. Existing simplified algorithms typically employ depletion layer approximations or differential methods. While computationally simple, these methods neglect the smoothing effect of the kernel function and the coupling relationships between multiple physics fields. Furthermore, they often utilize only single capacitance or conductance data for analysis, wasting the nonlinear information contained in current hysteresis and higher harmonics, making it difficult to maintain solution stability while ensuring energy level resolution. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a high-sensitivity heterojunction spectral detection system and its data acquisition method, which solves the problems of weak signal acquisition due to scanning transient impact interference, impedance parameter mapping distortion caused by hardware transmission phase error, and the limitations of traditional inversion algorithms in solving ill-conditioning problems and utilizing only a single type of information in existing heterojunction interface state detection methods.

[0007] The first aspect of the present invention provides a high-sensitivity heterojunction spectral detection system, which includes a bias control unit, a signal acquisition unit, a digital processing unit, and a host computer processing unit.

[0008] The bias control unit is connected to the detector of the heterojunction under test and is used to apply a scanning voltage signal with a preset timing sequence; the signal acquisition unit is used to acquire the current response signal of the detector under voltage excitation; the digital processing unit generates the control timing sequence and performs synchronous demodulation operation on the current response signal, and outputs multidimensional physical parameter data; the host computer processing unit receives the multidimensional physical parameter data and executes the spectral inversion algorithm to generate the interface state density distribution spectrum.

[0009] The digital processing unit employs a trapezoidal hysteresis scan timing control strategy to control the bias control unit to output discontinuous discrete step voltages. This strategy configures each voltage step cycle as a transient shielding window and a data acquisition window. The duration of the transient shielding window is longer than the time constant of the bias circuit to shield the displacement current surge caused by the voltage step, ensuring subsequent measurements are in a quasi-steady state. Simultaneously, the system sets asymmetrical single-step dwell times during the forward and reverse scan phases. By changing the number of integration cycles within the data acquisition window, a charge hysteresis effect is induced in the heterojunction detector, thereby separating the interface state trap response related to the time constant.

[0010] To eliminate the time-domain mismatch between control commands and acquired data during high-speed scanning, the digital processing unit integrates a first-in-first-out (FIFO) delay queue module. This module is located between the command path of the bias control unit and the packaging path of the multi-dimensional physical parameter data. It delays and buffers the time-leading voltage control commands, aligning them with the delayed physical parameter data after demodulation. The aligned voltage values ​​and physical parameter data are then synchronously packaged and transmitted to the host computer processing unit.

[0011] The digital processing unit is equipped with parallel multi-channel signal processing logic for analyzing the multidimensional components in the current response signal. The DC channel uses a cascaded integrator comb filter or moving average filter to filter out AC components and extract the DC average value. The fundamental channel uses a quadrature demodulator, combined with in-phase and quadrature reference signals, to mix and integrate the current response signal, extracting the original in-phase and quadrature components. The harmonic channel uses a frequency multiplication correlation operator and a frequency multiplication reference signal to extract the second harmonic amplitude and calculates the ratio of the fundamental to the harmonic amplitude to output a nonlinearity index.

[0012] The digital processing unit also includes a phase rotation correction module for compensating for phase errors in the hardware transmission path. This module stores the system phase error angle obtained through calibration using pure resistive standards. It then uses a rotation matrix algorithm to perform a linear transformation on the original in-phase and quadrature components, outputting the corrected in-phase and quadrature components. The digital processing unit performs physical parameter mapping based on a parallel equivalent circuit model, mapping the corrected in-phase components to differential conductance characterizing carrier transport properties, and mapping the corrected quadrature components to differential capacitance characterizing depletion layer width variation and interface state charging / discharging characteristics.

[0013] During the data post-processing stage, the host computer processing unit executes background noise stripping logic. The system performs voltage grid alignment and interpolation on the multidimensional physical parameter data generated by forward and reverse scanning, and calculates the difference between forward and reverse currents to eliminate common-mode leakage current independent of the scanning direction. Simultaneously, it uses measured differential capacitance data to calculate the geometric displacement current component caused by the difference in scanning rate, and subtracts this geometric displacement current component from the difference to obtain the unsteady-state current component originating from the charging and discharging of interface state traps.

[0014] The host computer processing unit analyzes the interface state density distribution by constructing an augmented matrix and performing regularized spectral inversion. The system standardizes the differential conductance, differential capacitance, and hysteresis current data, constructing weighted augmented observation vectors and augmented coefficient matrices based on the signal-to-noise ratio of each physical quantity. The augmented coefficient matrix contains multiple physical kernel function submatrices generated based on Shockley-Read-Hall statistical theory, used to establish the mapping relationship between discrete energy levels and multidimensional physical parameters. The inversion process employs a hybrid regularization objective function, which includes a data fidelity term constraining the inversion results to match experimental observations, a smoothing constraint term using a second-order difference matrix to suppress noise oscillations, and a sparse constraint term using the L1 norm to characterize the discrete features of deep-level defects. The interface state density distribution spectrum is obtained by solving this objective function using a convex optimization algorithm.

[0015] A second aspect of the present invention provides a method for acquiring heterojunction spectral data based on the above-described system, comprising the following steps: The bias voltage is controlled to output the scan voltage of the discrete step, and transient shielding and steady-state perturbation detection are performed sequentially at each voltage step. Different dwell times are set in the forward and reverse scan stages to generate hysteresis data. The acquired signals are processed in parallel through multiple channels. Differential conductance and differential capacitance are extracted using orthogonal demodulation, second harmonics are extracted using frequency doubling correlation, and phase rotation correction is performed on the demodulated data. The forward and reverse scan data are mapped to a unified voltage grid, the volume leakage current is eliminated by differential operation, and the geometric displacement current is compensated by differential capacitance to extract the pure trap current. An augmented matrix containing differential conductance, differential capacitance, and trap current is constructed. Combined with a physical kernel function, a regularization algorithm with smoothing and sparsity constraints is used to invert and calculate the interface state density distribution spectrum.

[0016] This invention provides a high-sensitivity heterojunction spectral detection system and its data acquisition method. It has the following beneficial effects: 1. This invention employs a trapezoidal hysteresis scanning timing control strategy. By setting a transient shielding window within the voltage step cycle, it effectively isolates the transient displacement current impact generated by voltage steps, solving the timing interference problem between large-signal scanning and small-signal perturbation detection. Simultaneously, utilizing the asymmetric dwell time mechanism of forward and reverse scanning, it can induce observable charge hysteresis effects against a large capacitance background, thereby effectively separating the unsteady-state current component related to the charging and discharging characteristics of interface state traps, and improving the detection system's response sensitivity to deep-level defects.

[0017] 2. This invention integrates a FIFO delay queue and a phase rotation correction module into the digital processing unit, achieving strict time-domain alignment of control commands and demodulated data, as well as automatic compensation for hardware transmission phase. This design eliminates read / write timing slippage caused by the difference in command transmission and signal processing time during high-speed scanning, and uses a pure resistance calibration method to correct the inherent transmission delay introduced by the transimpedance amplifier and filter, preventing the aliasing of capacitive and conductive currents and ensuring the accuracy of mapping physical parameters such as differential conductance and differential capacitance.

[0018] 3. This invention utilizes augmented matrix construction and a hybrid regularization inversion algorithm to fuse multi-dimensional physical quantities such as differential conductance, differential capacitance, and hysteresis current, overcoming the information loss and condition number deterioration problems of traditional single-physical-quantity inversion. By introducing data fidelity terms, smoothing constraint terms, and sparse constraint terms, the solution of the ill-conditioned Friedholm integral equation is transformed into a numerically stable convex optimization problem, effectively suppressing non-physical oscillations caused by measurement noise and achieving high signal-to-noise ratio and high energy resolution interface density of states spectral reconstruction. Attached Figure Description

[0019] Figure 1This is a diagram of the main framework of the present invention; Figure 2 This is a flowchart of the data acquisition method of the present invention; Figure 3 A schematic diagram of the timing waveform for the composite drive voltage generated by the precision bias control unit of the present invention; Figure 4 This is a schematic diagram of the wide dynamic range dual-channel signal readout circuit of the present invention. Figure 5 This is a schematic diagram of the internal logic architecture and data flow of the digital processing unit of the present invention; Figure 6 This is a timing logic flowchart of the trapezoidal hysteresis scan timing control strategy of the present invention; Figure 7 This is a flowchart of the signal processing algorithm for the multidimensional complex impedance characteristic synchronous demodulation method of the present invention; Figure 8 This is a schematic flowchart of the background noise stripping method based on bidirectional hysteresis differential of the present invention; Figure 9 This is a flowchart of the augmented matrix construction and regularized spectral inversion algorithm of the present invention; Figure 10 The graph shows the measured data of the hysteresis IV scanning characteristics of the present invention. Figure 11 These are comparative effect diagrams of the present invention; Figure 12 This is a bar chart showing the inversion stability error under different noise levels according to the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] See attached document Figure 1 , Figure 1 This is a structural block diagram of a heterojunction spectral detection system based on dynamic depletion layer scanning and multidimensional decoupling of complex impedance, according to an embodiment of the present invention. The present invention provides a high-sensitivity heterojunction spectral detection system, which mainly includes: a detector, a bias control unit, a readout circuit, and a processing unit.

[0022] The detector serves as the photoelectric conversion front end of the detection system, employing a heterojunction photodiode structure with a germanium / silicon or indium gallium arsenide / indium phosphide material system. The detector exhibits the physical characteristic that its depletion layer width changes with the reverse bias amplitude, and its interface state traps possess specific time constants for carrier capture and release. The detector's signal output is electrically connected to the readout circuit's input, and the detector's bias input is electrically connected to the bias control unit's output.

[0023] The bias control unit is configured to apply a non-steady composite drive voltage to the detector. An integrated digital-to-analog converter (DAC) is located within the bias control unit. The DAC receives digital waveform control commands from the processing unit and converts them into analog voltage signals. The composite drive voltage generated by the bias control unit comprises a time-varying trapezoidal scan voltage component and a high-frequency sinusoidal perturbation voltage component. The trapezoidal scan voltage component has controlled rise and fall slopes, the values ​​of which are limited by the linear operating range of the readout circuitry.

[0024] The readout circuit is configured to acquire the total current signal flowing through the detector. The readout circuit includes a transimpedance amplifier and an analog-to-digital converter (ADC). The input of the transimpedance amplifier is connected to the anode or cathode of the detector to convert the weak current signal generated by the detector into a voltage signal. The transimpedance amplifier has a preset bandwidth and dynamic range that covers the peak displacement current caused by the slope of the trapezoidal scan voltage. The ADC is connected to the output of the transimpedance amplifier to convert the analog voltage signal into a digital signal sequence and transmit it to the processing unit.

[0025] The processing unit is the core control and computation center of the system, specifically employing a field-programmable gate array (FPGA) or a microcontroller with an integrated digital signal processing core. The processing unit is connected to the bias control unit and the readout circuit via a bus. Internally, the processing unit is logically divided into a waveform generation module, a demodulation module, and a computation module.

[0026] The waveform generation module is configured to generate digitally synthesized waveform data that defines the voltage nodes, dwell time, transition slope, and frequency and amplitude of the superimposed high-frequency perturbation signal of the asymmetric trapezoidal wave. The waveform generation module then sends this digital waveform data to the bias control unit in real time.

[0027] The demodulation module is configured to receive a sequence of digital signals from the readout circuit. Internally, the demodulation module contains a multi-channel digital phase-locked loop (PLL) that performs orthogonal operations with the perturbation signal from the waveform generation module to separate the DC current component, fundamental in-phase component, fundamental quadrature component, and second harmonic amplitude component from the total current signal.

[0028] The computation module is configured to perform matrix operations based on the multidimensional data output by the demodulation module. The computation module executes a hysteresis differential algorithm to calculate the difference between the rising and falling data to remove the interface state trap current; the computation module further uses the fundamental conductance data and second harmonic curvature data to construct an augmented observation vector, and combines it with the pre-stored system response matrix to solve for the spectral distribution.

[0029] See attached document Figure 2 , Figure 2 This is a flowchart of a data acquisition method according to an embodiment of the present invention. The present invention provides a data acquisition method for a high-sensitivity heterojunction spectral detection system, comprising the following steps: S100, construct a trapezoidal hysteresis scan sequence; The processing unit generates waveform control data for the composite drive voltage. This composite drive voltage is composed of a large-signal trapezoidal scan component and a small-signal high-frequency perturbation component. The trapezoidal scan component includes a rising and falling phase within one sampling period, and adjacent voltage steps are connected by a linear ramp with a controlled slope. The ramp slope values ​​for the rising and falling phases are different, forming an asymmetric scan path.

[0030] S200, time-domain gating and multidimensional physical quantity acquisition; The bias control unit applies a composite drive voltage to the detector based on waveform control data. The processing unit controls the data acquisition window of the readout circuit according to the timing of the trapezoidal scan components. Within the stable region of each voltage step, the readout circuit acquires the detector's response signal. The demodulation module synchronously demodulates the response signal, extracting the DC current component, fundamental conductance component, fundamental capacitance component, and second harmonic amplitude component at the same voltage point.

[0031] S300, background current stripping based on hysteresis loop; The arithmetic module calculates the hysteresis difference component based on the difference between the DC current components collected at the same voltage point during the rising and falling phases. This hysteresis difference component characterizes the charging and discharging current of the interface state traps inside the detector, and is subtracted from the DC current component. Combined with the fundamental capacitance component to compensate for the displacement current, the net photogenerated response current is obtained.

[0032] S400, constructing an augmented spectral response matrix; The computation module combines the fundamental conductance component and the second harmonic amplitude component at multiple voltage points to construct an augmented observation vector. This augmented observation vector includes both the first-order linear and second-order nonlinear characteristics of the detector's response to incident light.

[0033] S500, regularized spectral reconstruction; The computation module establishes a system of linear equations containing the augmented observation vector and the preset system response matrix. This system of linear equations is solved using the Tikhonov regularization algorithm to calculate the spectral power distribution data of the incident light.

[0034] See attached document Figure 3 , Figure 3 This diagram illustrates the timing waveforms that generate the composite drive voltage for the precision bias control unit. The precision bias control unit is the core hardware for implementing the unsteady-state excitation strategy. Its input is connected to the digital I / O interface of the processing unit, and its output is connected to the bias electrode of the detector. The control logic of this unit is based on a discrete-time stepping mechanism, converting the waveform stream in the digital domain into a drive signal in the analog domain.

[0035] Composite drive voltage generated by the bias control unit It is a time-varying signal. Unlike traditional static DC scanning or single-frequency AC scanning, this embodiment employs a composite control strategy of "DC scanning to set the operating point, AC perturbation detection impedance, and slope control protection circuit". Specifically, the mathematical expression of this composite voltage signal is as follows: ; in, This represents the reference trapezoidal scan voltage, used to vary the depletion layer width of the detector over a wide range. Indicates the amplitude of the AC perturbation signal; Indicates the frequency of the perturbation signal; It is a time-domain gated function.

[0036] For reference trapezoidal scanning voltage The generation employs a piecewise linear trapezoidal wave structure. The physical significance of this structure lies in controlling the rate of voltage change to limit the transient displacement current flowing through the detector junction capacitance. A complete scan cycle of the trapezoidal wave includes a rising scan phase and a falling scan phase.

[0037] During the rising scan phase, the voltage gradually increases from its initial value to its peak value. The transition between each voltage step is achieved through a controlled linear ramp. For any adjacent k-th voltage level... and the voltage of the (k+1)th stage Its transition slope Defined as the ratio of voltage increment to transition time. This slope... This is a programmable parameter whose value is not arbitrarily chosen but must satisfy the boundary conditions for system linearity. The maximum allowable slope must satisfy the following constraints: ; in, To read the saturation current threshold of the transimpedance amplifier in the circuit, this threshold is determined by the amplitude of the supply voltage of the transimpedance amplifier and the feedback resistor. The ratio determines this. Specifically, To determine the saturation current threshold of the transimpedance amplifier in the readout circuit. This threshold is determined by the amplitude of the supply voltage to the transimpedance amplifier and the feedback resistor. The ratio determines this. Specifically, It is approximately equal to the operational amplifier's output voltage swing divided by the feedback resistor value. For example, in this embodiment, if the transimpedance amplifier uses a ±5 ohm power supply, the feedback resistor... Selected as Considering the op-amp output swing limitation, the saturation current threshold is... The current is set to 50nA (i.e., 5V / 100MΩ). When the input current exceeds this value, the amplifier enters the nonlinear saturation region.

[0038] During the descent scan phase, the voltage gradually decreases from its peak value to its initial value. To utilize the difference in charging and discharging characteristics of the interface state traps, the step dwell time or transition slope in the descent phase is set to be different from that in the rise phase, constructing an asymmetric charge trap filling path. Specifically, by changing the scan rate, the probability distribution of carriers being captured and released by the interface states at the same voltage point changes, thus manifesting as a hysteresis loop in the macroscopic current, providing a physical basis for subsequent algorithms to separate the trap current.

[0039] To address the injection of small-signal perturbation components, the bias control unit utilizes a time-domain gating function. Control is implemented. The specific execution logic is as follows: S201, entering the voltage switching transition zone; The control unit output has a fixed slope The linear voltage. During this period, the gate function This involves disconnecting the perturbation signal source in hardware or setting it to zero in the digital domain, outputting only the DC ramp signal. This measure eliminates the modulation interference of rapidly changing DC bias voltage on the phase of the perturbation signal, ensuring the stability of the phase reference for subsequent phase-locked demodulation.

[0040] S202, enters the voltage stabilization zone; When the bias voltage reaches the target value Then, maintain a constant voltage. After a preset stabilization time... Then, the gate function is flipped to The control unit begins to superimpose an amplitude of , frequency is The sinusoidal perturbation signal. Settling time. The value of is at least 3 to 5 times the RC time constant of the readout circuit (i.e. This ensures that the transient impact response of the circuit decays to below the system noise floor level, and that perturbation measurements are performed under steady-state conditions.

[0041] Regarding the selection of perturbation signal parameters, frequency The amplitude is determined based on the interface state response time constant of the detector material, typically set within the range of 1 kHz to 100 kHz. Within this frequency band, the interface state trap can partially respond to AC signals, thus exhibiting complex impedance characteristics. The selection follows the small-signal approximation principle, that is... It should be much smaller than the thermal voltage. (Approximately 26 mV), typically taken as 5 mV to 10 mV. This ensures that the nonlinear current-voltage characteristics of the detector can be approximated as linear within the perturbation range, thus making linear impedance analysis models applicable.

[0042] For the specific implementation of the digital-to-analog converter circuit, a high-resolution (16-bit and above) DAC chip is used in conjunction with a low-noise operational amplifier. For the power drive section, those skilled in the art can select a buffer circuit with high capacitive load driving capability to drive the capacitive load presented by the large-area detector.

[0043] See attached document Figure 4 , Figure 4 This is a schematic diagram of a wide dynamic range dual-channel signal readout circuit according to an embodiment of the present invention. The readout circuit is located between the heterojunction detector and the digital processing unit, and its function is to convert the weak current signal output by the detector into a voltage signal suitable for digital processing. Because the detector generates a large displacement current background during the trapezoidal voltage scanning process, and simultaneously has a weak photocurrent and AC perturbation response superimposed, the readout circuit must possess characteristics that balance a large DC dynamic range and high AC sensitivity.

[0044] The readout circuit mainly consists of a pre-amplifier (TIA), a secondary signal conditioning stage, and an analog-to-digital converter (ADC). The pre-amplifier uses an inverting amplifier configuration, with its non-inverting input grounded or connected to a reference level, and its inverting input connected to the detector's signal output. This virtual ground connection stabilizes the detector's terminal voltage, preventing the actual bias voltage from deviating from the set value due to voltage drop across the load impedance.

[0045] The signal processing and transmission process of the readout circuit specifically includes the following logic levels: S301, current-to-voltage conversion and first-stage gain control; The transimpedance amplifier uses a feedback network to convert the total current generated by the detector. Converted to voltage signal The feedback network consists of high-precision feedback resistors. With compensation capacitor Composed of parallel connections. Among them, the feedback resistor... The resistance value determines the DC and low-frequency gain of the circuit, i.e., the transimpedance gain. To ensure that the circuit does not saturate during the fast ramp phase of the trapezoidal voltage scan, the feedback resistor... The selection of resistance is limited by the maximum allowable displacement current. The specific resistance constraints are as follows: ; in: The linear output voltage swing of the operational amplifier is determined by the supply voltage rail; and These are the high-level and low-level saturation thresholds of the operational amplifier's output voltage, respectively; these two parameters are jointly determined by the positive and negative power rail voltages of the operational amplifier and the output stage voltage drop characteristics of the device itself; in this embodiment, the system's analog front-end uses a dual power supply, with the positive power rail +5... The negative power rail is -5 Considering the output characteristics of the non-rail-to-rail operational amplifier, a high-level saturation threshold is set. +4.8 Low-level saturation threshold -4.8 When the voltage reading acquired by the ADC exceeds... When the range is exceeded, the system determines that the current range has overflowed and triggers an automatic shift or alarm mechanism.

[0046] This represents the maximum displacement current caused by voltage scanning. This is the maximum junction capacitance of the detector; The maximum voltage sweep slope applied to the precision bias control unit; This represents the expected maximum photocurrent.

[0047] This constraint dictates that the gain setting of the readout circuit must match the slope setting of the bias control unit. In the hardware implementation, JFET-input or CMOS-input operational amplifiers with a femtoampere (fA) level input bias current are selected to reduce DC errors introduced by device leakage current.

[0048] S302, Frequency Domain Response Shaping and Phase Compensation; Compensation capacitor Its function is to construct first-order low-pass filter poles to suppress high-frequency noise and compensate for detector junction capacitance. The resulting input phase lag prevents circuit self-oscillation. The closed-loop signal bandwidth of the readout circuit is also considered. Determined by the product of the feedback resistor and the compensation capacitor: ; To ensure the high-frequency perturbation signal superimposed on the bias voltage (frequency: To ensure uninterrupted passage through the readout circuit, the closed-loop bandwidth must be significantly higher than the perturbation frequency. In specific implementations, the configuration... The capacitance value makes , where the coefficient Typically, the value is between 5 and 10. This ensures that the perturbation signal is in the flat region of the passband, avoiding amplitude attenuation and additional phase shift caused by amplifier bandwidth limitations, thereby ensuring the accuracy of subsequent impedance demodulation.

[0049] Meanwhile, to ensure the phase margin of the circuit, a compensation capacitor is used. The value of must also satisfy the stability criterion: ; in, This is the total capacitance at the op-amp input (including detector capacitance, cable capacitance, and op-amp input capacitance). This is the gain-bandwidth product of the operational amplifier. In this embodiment, by comprehensively considering bandwidth and stability requirements, the minimum standard capacitance value that satisfies the above two inequalities is selected as... .

[0050] S303, differential drive and analog-to-digital converter; The single-ended voltage signal output from the transimpedance amplifier is converted into a differential pair signal by a secondary fully differential amplifier. This step is used to filter out common-mode noise interference and match the input dynamic range of the subsequent ADC. The analog-to-digital converter employs a successive approximation (SAR) or... Type architecture, its sampling rate Set to satisfy the Nyquist sampling theorem, and for the perturbation frequency Oversampling is performed. Specifically, the sampling rate is configured as follows: ,in This is the oversampling factor, typically between 20 and 100. A high oversampling factor allows the digital processing unit to effectively improve the signal-to-noise ratio through digital filtering algorithms and accurately capture the waveform characteristics of subtle perturbations. For the quantization bit depth of the analog-to-digital converter, choosing 16 or 18 bits allows for the extraction of weak AC response signals superimposed on the background current while preserving a large dynamic range.

[0051] See attached document Figure 5 , Figure 5This is a schematic diagram of the internal logic architecture and data flow of a digital processing unit according to an embodiment of the present invention. The digital processing unit, as the core of the system's measurement and control, is built based on a field-programmable gate array (FPGA) or a high-performance digital signal processor (DSP). Its input is connected to an analog-to-digital converter (ADC) via a high-speed parallel bus or a serial LVDS interface, and its output is connected to a bias control unit via an internal bus. Logically, this unit belongs to a fully pipelined architecture, capable of processing the input data stream in real time at the system clock frequency and extracting physical characteristic parameters without dead zones.

[0052] The specific signal processing flow and internal logic structure of the digital processing unit are as follows: S401, coherent waveform synthesis and reference signal generation; The digital processing unit is internally equipped with a direct digital frequency synthesis (DDS) logic core. This logic core utilizes a 32-bit or higher precision phase accumulator and a sine wave lookup table (LUT) to simultaneously generate two signal data streams: one is the perturbation drive data sent to the bias control unit. The other path is a quadrature reference signal sequence used for internal demodulation, i.e., an in-phase reference. and orthogonal reference .in, For discrete-time indexing, This is the system master clock frequency. It is used to compensate for the fixed phase delay introduced by the analog circuit path. The internal reference signal incorporates a preset phase offset during generation, i.e. Since both the drive signal and the reference signal originate from the same clock domain, they maintain strict phase locking.

[0053] S402, a multi-channel digital quadrature demodulation logic; this step utilizes the principle of orthogonality to extract weak signals of specific frequencies from broadband noise. Its physical principle is that the integral of the product of sine waves of different frequencies over a complete cycle is zero; the integral result is non-zero only when the reference signal frequency matches the input signal frequency.

[0054] The demodulation module contains a parallel multiply-accumulate (MAC) unit. Raw data stream. Respectively with in-phase reference and orthogonal reference Perform point-by-point multiplication and complete an integration cycle. The accumulation is performed internally. To prevent data overflow during the accumulation process, the bit width of the accumulation register is designed to be... Typically, 48 or 64 bits are used. The integration result is as follows: ; ; in, This represents the number of sampling points within the integration period. It is a configurable parameter, and its value is usually set to . to The order of magnitude is adjusted to ensure that the integration time covers at least 10 perturbation signal cycles, thereby compressing the equivalent noise bandwidth to the 1Hz to 100Hz level. For the DC component... The extraction module uses a cascaded integrator comb (CIC) filter to extract and low-pass filter the original data. This filter can achieve high-order filtering effect without hardware multipliers, saving FPGA logic resources.

[0055] S403, Physical parameter calculation and normalization; the computation module processes the intermediate data obtained from demodulation. , This is mapped to the physical impedance parameters of the detector. Based on the feedback resistance of the transimpedance amplifier. (Unit: Ohms) and amplitude of perturbation signal (Unit: Volt), the calculation formula is as follows: ; ; The above calculations are implemented using the DSP hard core or floating-point unit inside the FPGA. The conductivity component represents the electrical conductivity related to photogenerated carrier recombination and leakage. This represents the capacitance component related to changes in depletion layer thickness and interface state charge storage.

[0056] S404, Time Domain Hysteresis Alignment and Data Packaging; Due to transmission delays in the system, the acquired current response lags behind the voltage excitation. Without alignment, the generated IV or CV curves will exhibit spurious hysteresis. Therefore, the digital processing unit incorporates a first-in-first-out (FIFO) data buffer queue. The processing unit will then process the issued voltage control commands... Write to a FIFO queue with a delay. Delay depth Based on the total group delay of the system loop Set, satisfy ,in This refers to the data update rate. When the demodulation results... During generation, the voltage value, synchronized with its time, is read from the FIFO. Finally, the processing unit will align the data groups The data is categorized and packaged according to its rise and fall phases, and stored in dual-port RAM (BlockRAM) for the backend interface to read.

[0057] See attached document Figure 6 , Figure 6 This is a timing logic flowchart of a trapezoidal hysteresis scan timing control strategy according to an embodiment of the present invention. This control strategy is executed by the timing logic core within the digital processing unit. By precisely controlling the time window of voltage application and signal acquisition, it resolves the timing conflict between large-signal scanning and small-signal measurement. Its core mechanism lies in replacing the traditional continuous linear scanning with a discontinuous discrete scanning method, and introducing configurable time parameter differences between the forward and reverse scanning phases.

[0058] The physical principle of this control strategy is based on a similar mechanism to semiconductor deep-level transient spectrum (DLTS): the interface state traps have specific characteristic time constants for the capture and emission of charge carriers. When the scan rate of the external voltage (equivalent to the movement rate of the Fermi level) is comparable to the characteristic time constant of the trap, the change in the trap charge state lags behind the change in voltage, thus producing a significant hysteresis loop in the current-voltage characteristic curve. By changing the dwell time in the scan sequence, defect types with different time constants can be screened and analyzed.

[0059] The specific execution logic of this timing control strategy flows according to the following timing states: S501, Discrete Voltage Stepping and Transient Shielding; In any of the scan cycles At each test point, the control system first instructs the bias control unit to change the output voltage from... Step adjustment to The voltage step This can cause a transient displacement current surge in the detector junction capacitance. To eliminate the impact of this unsteady-state surge on measurement accuracy, the control strategy sets a forced shielding window. .exist During this period, although the system maintained voltage output, all signal acquisition and demodulation operations were suspended. (Shielding window) The duration setting must meet the following requirements: ; in, This is the total resistance of the bias circuit. For detector capacitance, This is for stray capacitance. Coefficient. To establish the time factor, the value ranges from 5 to 10. This value ensures that the RC charging and discharging process has progressed to over 99.3%, the circuit enters a quasi-steady state, and at this point, the residual displacement current is below the system's noise floor level.

[0060] S502, Steady-state perturbation detection and integral sampling; when the shielded window... After completion, enter the data acquisition window. At this point, the system activates AC perturbation signal injection and starts the digital integrator for measurement. During this stage, the detector operates in a DC steady-state and AC dynamic mode. Acquisition window duration. The length of the signal directly determines the effective bandwidth and signal-to-noise ratio of the measurement, and its calculation formula is as follows: ; in This represents the cumulative number of perturbation signal cycles. This control strategy requires that at each voltage step, It must be an integer to ensure the periodicity of the quadrature demodulation. Typical values ​​range from 10 to 1000. The larger the value, the narrower the measurement bandwidth and the stronger the noise immunity, but the total scan time also increases accordingly.

[0061] S503, Asymmetric Hysteresis Scan Parameter Configuration; To analyze the dynamic characteristics of the interface state trap, the control strategy is configured with independent time parameters for the rise and fall scan phases. The single-step dwell time in the rise phase is defined as... The single-step dwell time during the descent phase is Single-step dwell time It consists of the sum of the shielding time and the acquisition time: ; In the embodiment, the settings are as follows: This constitutes an asymmetric scan. For example, setting... and (in The time constant of the target trap ensures that the trap cannot be filled in time during the ascent phase, but is fully released during the descent phase. This asymmetry maximizes the area of ​​the hysteresis loop, thereby improving the detection sensitivity for defects at specific energy levels.

[0062] S504, Scan Reversal and Boundary State Processing; When the scanning voltage reaches the preset peak value At this time, the control strategy does not immediately enter the reverse scan, but instead inserts a peak hold time. This time period is used to fully fill or empty the deep-level traps and establish the initial charge state for the reverse scan. The value is typically set to 10 to 100 times the single-step dwell time, i.e. The purpose is to eliminate the accumulation of non-equilibrium carriers during the rising scan process and ensure that the falling scan starts from a thermodynamic equilibrium state.

[0063] S505, the definition of dynamic scan rate synthesis; Based on the aforementioned discrete control logic, the macroscopic equivalent scan rate of the entire testing process is... It is a composite physical quantity defined by both the voltage step size and timing parameters. Its mathematical definition is as follows: ; in, This refers to the inherent logic overhead time incurred by system instruction transmission and data packaging. This parameter is determined by the FPGA's clock frequency and the number of clock cycles required for state machine transitions, typically on the order of microseconds. This formula indicates that the present invention adjusts the digital registers... (i.e., changing the number of integration cycles) or step voltage This allows for the achievement of equivalent scan rates. The discrete adjustment range can cover 1mV / s to 10V / s, thus adapting to a wide range of characterization needs from slow interface states to fast volume defects.

[0064] See attached document Figure 7 , Figure 7 This is a flowchart of a signal processing algorithm for a multidimensional complex impedance characteristic synchronous demodulation method according to an embodiment of the present invention. The method is executed by the DSP logic core within a digital processing unit and aims to separate the DC component, the fundamental complex impedance component, and the second harmonic component from a digital sampling sequence.

[0065] This demodulation method, based on the physical characteristics of the detector, employs a parallel equivalent circuit model for parameter calculation. This model... This applies to photodiodes under reverse bias because the device exhibits high impedance characteristics under these conditions, with high junction capacitance and high leakage resistance. The circuit exhibits a parallel connection in its physical structure. The purpose of the demodulation algorithm is to calculate the differential conductance in this equivalent circuit in real time. and differential capacitance .

[0066] The specific execution steps of this method include: S601, multi-channel signal separation operation; The system receives the digitized sequence output by the ADC. This sequence is a DC background. Fundamental response Higher harmonics and broadband noise The superposition of signals. The algorithm constructs three independent signal processing channels in parallel: DC Channel: Using a moving average filter or a cascaded integrator-comb (CIC) filter, the AC component is filtered out, and the DC average value is extracted. ; Fundamental channel: using in-phase reference and orthogonal reference Perform orthogonal demodulation to extract fundamental frequency amplitude information; Harmonic Channel: Utilizing Frequency Doubling Reference Perform relevant calculations to extract second harmonic information.

[0067] S602, Demodulation and integration of the fundamental vector; In the fundamental frequency channel, digital mixing and cumulative integration are performed. This step utilizes the orthogonality of the sine function to shift the measured frequency component to zero frequency while suppressing unrelated noise frequencies. For the... Calculate the original in-phase component at each test point. and original orthogonal components ; ; in, For the length of the integral accumulation, For perturbation frequency, Sampling rate. Coefficient. It is the amplitude normalization factor. Because the integral of a sine wave with itself is... To restore the true amplitude of the signal, it needs to be multiplied by its reciprocal.

[0068] S603, Rotational correction of system phase error; Due to the inherent signal transmission delay of the transimpedance amplifier and anti-aliasing filter in the readout circuit, the demodulated original vector... Includes phase rotation introduced by the system Without correction, some capacitive current will be incorrectly included in the conductive current, leading to distorted measurement results. This step uses a matrix rotation algorithm to perform phase compensation on the original vector. The corrected vector... The calculation is as follows: ; Among them, the phase correction angle These are inherent parameters of the system. The method for obtaining them is as follows: connect a standard pure resistor with a known resistance value to the test port (its resistance should be comparable to the impedance of the detector under test, for example, 10). Up to 1 Since a pure resistor has no capacitance component, its theoretical phase should be 0. In this case, the phase angle output by the measurement system is the system error angle. Invert it and store it in a register for subsequent correction.

[0069] S604, Calculation of physical parameters; Based on the parallel equivalent circuit model, the corrected voltage signal is mapped to physical impedance parameters. Differential conductance (Unit: Siemens S) Characterizes the transport and recombination properties of charge carriers, and the calculation formula is: ; Differential capacitor (Unit: Farads F) Characterizes the variation in depletion layer width and the charge-discharge characteristics of interface states. The calculation formula is: ; in, The applied perturbation voltage amplitude, This is the feedback resistor value of the transimpedance amplifier.

[0070] S605, Nonlinearity index calculation; The nonlinear charging and discharging of interface state traps leads to the appearance of high-order harmonics in the response current. The algorithm extracts the in-phase component of the second harmonic from the harmonic channel. and orthogonal components And calculate the normalized nonlinearity index. : ; This indicator reflects the degree of nonlinearity of the device's IV characteristics. In the voltage range where the interface state density is high, The value will increase significantly.

[0071] See attached document Figure 8 , Figure 8 This is a schematic flowchart of a background noise stripping method based on bidirectional hysteresis differential according to an embodiment of the present invention. The method is executed by post-processing logic within a digital processing unit, and its purpose is to remove the body leakage current, which is independent of the bias direction, and the displacement current, which is linearly related to the scan rate, from the total current, thereby calculating the unsteady current component originating from the charging and discharging of interface state traps.

[0072] The physical principle of this method is based on the time asymmetry of the interface state trap response. The bulk leakage current is mainly determined by interband tunneling and thermal excitation, and its value remains basically constant under the same bias voltage (regardless of the scan direction); while the charging and discharging current of the interface state trap depends on the historical path of the Fermi level sweeping through the trap level. Therefore, by differentially operating on the forward and reverse scan data, the common-mode leakage current background can be canceled, while the differential-mode trap current is preserved.

[0073] The background noise stripping method specifically includes the following logical steps: S701, bidirectional data grid alignment and interpolation; Due to the discreteness of the sampling timing, the voltage point set of data recorded during the rising scan phase... voltage point set during the falling scan phase They typically cannot completely overlap. To perform point-to-point algebraic operations, the bidirectional data must be uniformly mapped to a standard voltage grid. The system first defines the step size as Equally spaced voltage vectors (e.g., 1mV or 5mV). Then, linear interpolation (when sampling points are dense) or piecewise cubic spline interpolation (when sampling points are sparse) is used to interpolate the rise data. and descent data Resampling is performed to generate an aligned sequence. as well as .

[0074] S702, differential elimination of common-mode leakage current; Total current of the detector This can be expressed as volume leakage current. Displacement current and trap current The sum of. Among them It is approximately a single-valued function of voltage and does not change with the scanning direction. The system calculates the difference in bidirectional current. : ; This subtraction operation is used to calculate large quantities that do not contain interface information. The component is effectively removed. For narrow-bandgap semiconductor detectors with large dark current, this step significantly improves the signal-to-noise ratio of weak trap signals.

[0075] S703, Displacement Current Compensation and Trapping Current Extraction; Hysteresis differential current It still contains geometric displacement current components that are not canceled out due to the reversal of the scanning direction. Under ideal symmetrical scanning... The geometric displacement currents are opposites, and their difference is twice the displacement current. However, in practical applications, there may be slight differences in the scanning rate. To obtain the pure trap current... The system utilizes the measured differential capacitance. (i.e., the output result of step S604) is used for compensation calculation: ; in, and The instantaneous scan rates for the rise and fall phases, respectively (with signs). This formula accurately subtracts the displacement charge contribution caused by the scaling of the depletion layer using measured capacitance.

[0076] S704, Quantitative calculation of interface density of states spectrum; Using the Shockley-Read-Hall (SRH) statistical model, the extracted current Converted to interface state density distribution The calculation formula is as follows: ; in: It is the fundamental charge; Let be the junction area of ​​the detector; Band bending scan rate (unit: ), which characterizes the rate at which the Fermi level shifts relative to the band edge.

[0077] For detectors with different structures The methods for obtaining it are as follows: For metal-insulator-semiconductor (MIS) structures: ; in The capacitance of the insulating layer can be determined by measuring the saturation capacitance value of the accumulation region.

[0078] For PN junction or PIN junction detectors: due to the absence of insulating layer capacitance... and surface potential With applied bias Approximately linear correlation (under high inverse bias) can be approximated as Alternatively, the surface potential can be inversely derived by integrating the integrated CV curves. The rate of change.

[0079] System final output Depending on the energy level position The distribution curve is used to quantitatively characterize the defect level at the device interface.

[0080] See attached document Figure 9 , Figure 9 This is a flowchart of an augmented matrix construction and regularized spectral inversion algorithm according to an embodiment of the present invention. The algorithm module runs in a high-performance computing unit on a host computer, and its function is to process the acquired multidimensional physical parameters (…). Converted to interface state density distribution spectrum .

[0081] From a mathematical perspective, the process of detecting interface states can be described by a first-kind Friedholm integral equation. (Observation signal) It is the trap density function With system response kernel function The convolution of the kernel is used. Since the measurement data contains noise and the kernel function has a smoothing effect, directly inverting it is an ill-conditioned problem. This method transforms this ill-conditioned problem into a numerically stable convex optimization problem by constructing an augmented matrix and introducing regularization constraints.

[0082] The specific execution steps of this inversion algorithm are as follows: S801, Normalization of multidimensional eigenvectors and construction of augmented matrix; The system reads different temperatures and different bias voltages The following measurement dataset. Due to the huge differences in the dimensions and orders of magnitude of different physical quantities (e.g., capacitance is...), The order of magnitude, the current is to (on the order of magnitude), direct combination will lead to a deterioration of the matrix condition number.

[0083] The algorithm first performs Z-score normalization on the sequences of physical quantities. Then, it constructs the observation vectors. and augmented coefficient matrix .matrix A modular design is adopted to integrate multi-physics information: ; in, These are the physical kernel function submatrices corresponding to differential conductance, differential capacitance, and hysteresis current, respectively. Weighting coefficients. Used to balance the contributions of different physical mechanisms, its value is determined based on the measurement noise variance of each physical quantity. The reciprocal is determined, that is This is to ensure that data sources with high signal-to-noise ratios dominate the inversion process.

[0084] S802, Physical definition and discretization of kernel functions; kernel functions Characterized by the traps of unit density at energy levels External bias The system's response sensitivity. The system will have a bandgap energy range. Discretize into intervals (e.g.) ), generating the corresponding discrete energy level points The key to constructing the matrix lies in establishing energy levels. With the trap launch time constant The physical relationship. Based on Shockley-Read-Hall (SRH) statistical theory: ; in, To capture the cross section, For thermal motion velocity, This represents the effective density of states. Based on the calculated... With differential conductance function For example, matrix elements The calculation is as follows: ; in Angular frequency, The derivative of the Fermi-Dirac distribution function with respect to energy represents the probability that the trap is scanned by the Fermi level.

[0085] S803, construct the hybrid regularization objective function; To solve for the unknown trap density vector (corresponding to discretization) The algorithm constructs a least-squares objective function with physical constraints. ; The meanings of each item are as follows: Data fidelity item Ensure that the inversion results match the experimental observations; Tikhonov smoothing term : It is a second-order difference matrix used to suppress non-physical oscillations caused by noise and ensure the continuity of the spectrum; Sparse constraint terms The sparse solution is induced using the L1 norm, since deep level defects usually manifest as discrete narrow peaks.

[0086] To provide a more intuitive understanding of the present invention, this embodiment selects an extended-wavelength InGaAsPIN infrared detector with high dark current characteristics as the device under test (DUT). This device is commonly used in gas sensing, with a cutoff wavelength of 2.6 μm and a photosensitive element diameter of 1 mm. Due to lattice mismatch, this type of device typically exhibits a high density of interface state defects at the mesa edges, and has a large bulk leakage current at room temperature, making traditional capacitance spectroscopy methods difficult to apply.

[0087] Test environment configuration: Hardware platform: It adopts a self-developed high-precision source measurement unit (SMU) combined with an FPGA digital phase-locked loop core; Temperature control environment: Liquid nitrogen cryostat, test temperature set to... Temperature control accuracy ; Parameter settings: Scanning voltage range to (Reverse bias); Voltage step ; Perturbation frequency 100kHz; Scan timing parameters: Ascent dwell time Descent dwell time (Constructing asymmetric hysteresis).

[0088] Hysteresis scan (corresponding to S500): The system performs the above-described asymmetric trapezoidal scan. At this location, the upward current was measured. Downstream current Instead of directly taking the difference, the complete dynamic data stream was recorded.

[0089] Synchronous demodulation (corresponding to S600): After phase correction by S603 (calibration resistor is...) Extract Differential capacitance at point .

[0090] Noise stripping (corresponding to S700): The system calculates the hysteresis differential current.

[0091] Direct difference: ; Displacement current correction: The residual term caused by the difference in scanning rate is calculated as follows. ; Corrected pure trap current .

[0092] Note: At this time, the background leakage current is as high as The extracted trap signal is only The signal-to-noise ratio was improved by about two orders of magnitude.

[0093] Inversion and reconstruction (corresponding to S800): Substitute the data processed above across the entire voltage range into the augmented matrix. Set regularization parameters After 35 iterations of contraction, the FISTA algorithm converged and output the interface state density distribution in the bandgap.

[0094] To verify the effectiveness of the proposed method "based on bidirectional hysteresis differential and regularized inversion", it was compared with the traditional high-frequency CV method and the standard DLTS (deep level transient spectrum) method commonly used in the industry under the same environment and device conditions.

[0095] See attached document Figure 10 , Figure 10 This is a graph showing the measured data of the hysteresis IV scan characteristics in an embodiment of the present invention.

[0096] The horizontal axis of the graph represents the bias voltage, and the vertical axis represents the current. The graph contains two curves: The red solid line corresponds to the rapid rise scan process, where the absolute value of the current is large because the interface state trap cannot capture the charge carriers in time. Blue dashed line: corresponds to the slow descent scanning process, where the trap is in a quasi-balanced filling state.

[0097] Shaded area: The area enclosed by the two curves is the hysteresis window, which directly corresponds to the total amount of interface charge being charged and discharged. Through step S700 of this invention, this tiny hysteresis opening (almost invisible to the naked eye) is successfully magnified and separated into an independent trap current spectrum.

[0098] Figure 11 These are comparison images.

[0099] The horizontal axis in the figure represents the energy level position. The vertical axis represents the interface state density. .

[0100] The gray dashed line represents the calculation result of the traditional CV method. Due to the influence of high leakage current and parallel resistance, the curve exhibits a flat and blurry distribution characteristic, making it impossible to distinguish specific defect energy levels, and it is particularly pronounced near the bottom of the conduction band. The false "U-shaped" rise in the region is due to a calculation error caused by leakage current.

[0101] Green dotted line: Represents the standard DLTS method. Although it can distinguish the main defect peak at 0.35 eV, the energy level resolution is low due to the limitation of the temperature scan step size, and a continuous energy state distribution cannot be obtained.

[0102] The red solid line represents the inversion result of the method of this invention. It can be seen that the curve clearly distinguishes two independent defect peaks: PeakA (0.32 eV): corresponds to the interface state of the surface oxide layer; PeakB (0.45 eV): corresponds to the bulk defect energy level unique to InGaAs materials. Comparative conclusion: The method of this invention not only eliminates the spurious background caused by leakage current (compared to the Terman method), but also achieves high-energy-resolution continuous spectrum reconstruction without time-consuming temperature-varying scans (compared to the DLTS method).

[0103] See attached document Figure 12 , Figure 12 This is a bar chart showing the inversion stability error under different noise levels. The horizontal axis represents the signal-to-noise ratio, and the vertical axis represents the relative error of the defect peak density obtained from the inversion.

[0104] The experiment simulated different measurement environments by injecting Gaussian white noise into the raw data.

[0105] Data shows that under low signal-to-noise ratio (SNR=20dB, corresponding to high leakage current conditions), the error of the traditional single-parameter inversion method rises sharply to over 40% (as shown by the dotted line in the figure). The multiphysics augmented matrix (S800) used in this invention integrates complementary information from capacitance and current, and keeps the error within 8% (as shown by the solid line and error bar in the figure).

[0106] This confirms the regularization algorithm's... Operators and The significant role of hysteresis kernel functions in suppressing noise.

[0107] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-sensitivity heterojunction spectral detection system, characterized in that, The system includes: The bias control unit is used to apply a scan voltage signal with a preset timing to the heterojunction detector under test; The signal acquisition unit is used to acquire the current response signal of the heterojunction detector under the excitation of the scanning voltage signal; A digital processing unit, connected to the bias control unit and the signal acquisition unit, is configured to generate control timing and perform synchronous demodulation operations on the current response signal, outputting multi-dimensional physical parameter data; and The host computer processing unit is communicatively connected to the digital processing unit and is configured to receive the multidimensional physical parameter data and execute the spectral inversion algorithm to generate the interface state density distribution spectrum. The digital processing unit is configured with parallel multi-channel signal processing logic, which is used to extract the DC component, fundamental complex impedance component and second harmonic component from the current response signal.

2. The high-sensitivity heterojunction spectral detection system according to claim 1, characterized in that, The digital processing unit executes a trapezoidal hysteresis scan timing control strategy, which controls the bias control unit to output a discontinuous discrete step voltage. Within each voltage step cycle, the timing includes a transient shielding window and a data acquisition window. The duration of the transient shielding window is set to be greater than the time constant of the bias circuit in order to shield the displacement current impact caused by the voltage step. The digital processing unit is configured to set asymmetrical single-step dwell time in the forward and reverse scanning phases, thereby inducing a charge hysteresis effect in the heterojunction detector by changing the number of integration cycles within the data acquisition window.

3. The high-sensitivity heterojunction spectral detection system according to claim 1, wherein the digital processing unit integrates a first-in-first-out (FIFO) delay queue module; The FIFO delay queue module is configured between the instruction path of the bias control unit and the packaging path of the multidimensional physical parameter data. It is used to delay and buffer the voltage control instructions that are ahead in the time domain, so that they are aligned in time with the lagging physical parameter data after demodulation and operation, and synchronously package and transmit the aligned voltage value and physical parameter data to the host computer processing unit.

4. The high-sensitivity heterojunction spectral detection system according to claim 1, wherein the multi-channel signal processing logic of the digital processing unit includes: The DC channel, which includes a cascaded integrating comb filter or moving average filter, is used to filter out AC components to extract the DC average value. The fundamental channel includes a quadrature demodulator, which uses in-phase reference signal and quadrature reference signal to mix and integrate the current response signal to extract the original in-phase component and the original quadrature component. The harmonic channel includes a frequency doubling correlation operator, which uses the frequency doubling reference signal to extract the second harmonic amplitude and calculates the ratio of the fundamental frequency to the harmonic amplitude to output a nonlinearity index.

5. The high-sensitivity heterojunction spectral detection system according to claim 4, characterized in that, The digital processing unit also includes a phase rotation correction module; The phase rotation correction module stores a pre-calibrated system phase error angle, which is obtained by measuring a pure resistance standard. The phase rotation correction module uses a rotation matrix algorithm to perform a linear transformation on the original in-phase component and the original quadrature component to compensate for hardware delay in the signal transmission path, and outputs the corrected in-phase component and quadrature component.

6. The high-sensitivity heterojunction spectral detection system according to claim 5, characterized in that, The digital processing unit performs physical parameter mapping based on the parallel equivalent circuit model; The digital processing unit maps the corrected in-phase component to a differential conductance and the corrected quadrature component to a differential capacitance, wherein the differential conductance characterizes the transport characteristics of charge carriers and the differential capacitance characterizes the depletion layer width variation and the interface state charging and discharging characteristics.

7. The high-sensitivity heterojunction spectral detection system according to claim 1, characterized in that, The host computer processing unit is configured to execute background noise stripping logic; The logic includes: aligning and interpolating the voltage grid of the multidimensional physical parameter data generated by forward and reverse scanning; calculating the difference between forward and reverse current to eliminate common-mode leakage current; calculating the geometric displacement current component caused by the difference in scanning rate using measured differential capacitance data, and subtracting the geometric displacement current component from the difference to extract the unsteady current component originating from the charging and discharging of interface state traps.

8. The high-sensitivity heterojunction spectral detection system according to claim 1, characterized in that, The host computer processing unit is configured to construct an augmented matrix to perform regularized spectral inversion; The host computer processing unit standardizes the differential conductance, differential capacitance, and hysteresis current data, and constructs a weighted augmented observation vector and augmented coefficient matrix based on the signal-to-noise ratio of each physical quantity. The augmented coefficient matrix contains multiple physical kernel function submatrices generated based on Shockley-Read-Hall statistical theory, which are used to establish the mapping relationship between discrete energy levels and multidimensional physical parameters.

9. The high-sensitivity heterojunction spectral detection system according to claim 8, characterized in that, The spectral inversion is solved using a hybrid regularization objective function; The objective function includes: a data fidelity term, used to constrain the inversion results to conform to experimental observations; a smoothing constraint term, including a second-order difference matrix, used to suppress non-physical oscillations caused by noise; and a sparsity constraint term, including an L1 norm, used to characterize the discrete features of deep-level defects; the host computer processing unit minimizes the objective function through a convex optimization algorithm to obtain the interface state density distribution spectrum.

10. A data acquisition method for a high-sensitivity heterojunction spectral detection system, implemented by the high-sensitivity heterojunction spectral detection system according to any one of claims 1-9, characterized in that, Includes the following steps: The bias voltage is controlled to output the scan voltage of the discrete step, and transient shielding and steady-state perturbation detection are performed sequentially at each voltage step. Different dwell times are set in the forward and reverse scan stages to generate hysteresis data. The acquired signals are processed in parallel through multiple channels. Differential conductance and differential capacitance are extracted using orthogonal demodulation, second harmonics are extracted using frequency doubling correlation, and phase rotation correction is performed on the demodulated data. The forward and reverse scan data are mapped to a unified voltage grid, the volume leakage current is eliminated by differential operation, and the geometric displacement current is compensated by differential capacitance to extract the pure trap current. An augmented matrix containing differential conductance, differential capacitance, and trap current is constructed. Combined with a physical kernel function, a regularization algorithm with smoothing and sparsity constraints is used to invert and calculate the interface state density distribution spectrum.

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