Double-edge time-to-digital converter, time domain storage circuit and CIM chip

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a double-edge time-to-digital converter, a time domain storage circuit and a CIM chip. The TDC comprises a symbol judgment module and a numerical calculation module. The symbol judgment module is used for respectively quantizing values of symbol bits of a first calculation result corresponding to a rising edge and a second calculation result corresponding to a falling edge according to an input calculation signal A and a reference signal B; the numerical calculation module comprises a shaping unit, a first delay chain, a second delay chain, a quantization unit, a transcoding unit and a separate storage unit. The method comprises the following steps: shaping A and B to obtain an OR signal C and an AND signal D; obtaining thermometer codes of numerical bits of two calculation results according to C and D through gradient delay of the two delay chains and XOR operation of the quantization unit, and finally completing data transcoding and asynchronous calculation result extraction through a transcoding unit and a separate storage unit. According to the invention, the problems of large area and high power consumption of the existing circuit are solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, specifically relating to a dual-edge time-to-digital converter, and its corresponding time-domain memory circuit and CIM chip. Background Technology

[0002] In recent years, with the widespread application of deep neural networks in artificial intelligence fields such as image recognition and natural language processing, the demand for high-efficiency, low-power computing hardware has been increasing. For in-memory computing architectures, mapping the computation result to the time difference between the computation signal and the reference signal, and then converting the time difference into a digital quantity using a time-to-digital converter (TDC), is a good solution for edge AI applications. Within the time-domain in-memory computing circuit, the value of the sign bit of the computation result can be characterized by the order of the rising or falling edges of the computation signal and the reference signal; the value of the numeric bit of the computation result can be characterized by the ratio of the delay length of the rising or falling edges of the computation signal and the reference signal to a unit delay. The circuit that implements this quantization function is called a time-to-digital converter (TDC). Based on this, in order to further improve the computational performance of the circuit, some engineers have even designed circuit schemes that can simultaneously represent two computation results using a single computation signal. In this scheme, the delay difference between the rising edges of the computation signal and the reference signal is used to represent the first computation result, and the delay difference between the falling edges of the computation signal and the reference signal is used to represent the second computation result. The circuit used to quantize the results of such calculations is called a two-sided edge-time data converter.

[0003] Technicians have provided various solutions for dual-edge time-to-data converters. However, existing dual-edge time-to-data converters typically require two channels to quantize the rising and falling edges separately. For example, in the time-to-digital converter published in August 2021 by Jiahao Song, Yuan Wang, et al., two channels are used to process the rising and falling edges separately. A single-channel time-to-data converter can only process the rising edge. To process the falling edge, the other channel time-to-data converter uses an inverter when the waveform enters the calculation to convert the falling edge into a rising edge. Furthermore, the single-channel time-to-data converter in such solutions consists of three D flip-flops and one selector, a simple structure that can only quantize two unsigned numbers. This circuit can only process binary data from BNN networks and cannot perform more complex calculations. At the same time, the dual-channel design wastes almost half of the area and power consumption. Furthermore, in the time-to-digital converter disclosed in the paper published by Chang Xue, Youming Yang, and others in June 2025, one channel represents the time difference of the high-bit bits at the rising edge of quantization, and another channel represents the time difference of the low-bit bits at the falling edge of quantization. In practical applications, the time-to-digital converter first quantizes the rising edge delay, and only starts quantizing the falling edge delay of the other channel's time data converter when certain conditions are met; this achieves a balance between quantization accuracy and efficiency.

[0004] In addition, most existing dual-channel designs of various double-edge time-to-digital converters use counters for time-to-digital conversion. In order to synchronize the timing, an external oscillation source is required, which introduces new area and power consumption, further affecting the circuit performance. Summary of the Invention

[0005] To address the issues of high area and power consumption commonly found in existing dual-edge time-to-digital converters with dual-channel designs, this invention provides a dual-edge time-to-digital converter, along with its corresponding time-domain memory circuit and CIM chip.

[0006] This invention is achieved using the following technical solution: A dual-edge time-to-digital converter is disclosed, which simultaneously quantizes a first calculation result represented by the rising edge and a second calculation result represented by the falling edge of an input computation signal A in asynchronous timing. Both the first and second calculation results are signed numbers.

[0007] This dual-edge time-to-digital converter includes a sign determination module and a value calculation module. The sign determination module quantizes the sign bits of the first calculation result corresponding to the rising edge and the second calculation result corresponding to the falling edge based on the input signal A and the reference signal B, respectively. The value calculation module quantizes the numerical bits of the first calculation result corresponding to the rising edge and the second calculation result corresponding to the falling edge based on the input signals A and B, respectively.

[0008] In this invention, the numerical calculation module includes a shaping unit, a first delay chain, a second delay chain, a quantization unit, a transcoding unit, and a separate storage unit. The shaping unit performs OR and AND operations on A and B respectively to obtain OR signal C and AND signal D. The first delay chain uses n adjustable delay units to generate n first-class delay signals C1 to Cn with sequentially unit delay intervals based on the input C. The second delay chain uses n fixed delay units to generate n second-class delay signals D1 to Dn with sequentially intrinsic delay intervals based on the input D. The quantization unit includes n XOR gates; the two inputs of the i-th XOR gate are respectively connected to the signals Ci and Di output from the i-th stage of the first and second delay chains, and the output outputs the value of the i-th bit of the thermometer code representing the first or second calculation result, i=1~n. The transcoding unit converts the n-bit thermometer code representing the first or second calculation result output by the quantization unit into an m-bit binary code; m =n. The output of the separate storage unit is connected to the output of the transcoding unit, and is used to latch and output the values ​​of the first and second calculation results through D flip-flops with D and C as clock input signals respectively.

[0009] As a further improvement of the present invention, the fixed delay unit and the adjustable delay unit employ the same delay circuit. This delay circuit includes three PMOS transistors P1-P3 and three NMOS transistors N1-N3. The sources of P1 and P3 are connected to VDD; the drain of P1 is connected to the source of P2; the drains of P2 and N2 are connected to the gates of P3 and N3; the source of N2 is connected to the drain of N1; and the sources of N1 and N3 are connected to VSS. The gates of P2 and N2 are connected and serve as the input terminal IN of the delay circuit; the drains of P3 and N3 are connected and serve as the output terminal OUT of the delay circuit. In the fixed delay unit, the gate of N1 is connected to VDD, and the gate of P1 is connected to VSS. In the adjustable delay unit, the gate of N1 is connected to a first bias voltage BIAS1, and the gate of P1 is connected to a second bias voltage BIAS2.

[0010] As a further improvement of the present invention, the length of the unit delay generated by each adjustable delay unit in the first delay chain is changed by adjusting the voltage values ​​of BIAS1 and BIAS2, thereby realizing the adjustment of the quantization accuracy and range of the numerical calculation module.

[0011] As a further improvement of the present invention, the fixed delay unit and the adjustable delay unit can also be implemented using different delay circuits.

[0012] As a further improvement of the present invention, the range of the numerical calculation module can be adjusted by adjusting the number of delay units in the first delay chain and the second delay chain and the number of input bits n of the transcoding unit.

[0013] As a further improvement of the present invention, the shaping unit includes an OR gate OR0 and an AND gate AND0. The two inputs of OR0 are connected to A and B respectively, and the output is used to output an OR signal C. The two inputs of AND0 are connected to A and B respectively, and the output is used to output an AND signal D.

[0014] As a further improvement of the present invention, the separate storage unit includes 2m D flip-flops; wherein the m D flip-flops constitute the first register unit; and the remaining m D flip-flops constitute the second register unit.

[0015] In the first register unit, the data input terminals of each D flip-flop are connected to the 1st to the mth bits of the binary code output by the transcoding unit, denoted as F1 to Fm; the clock input terminal is used to connect to the AND signal D; and the data output terminal is used to output the 1st to the mth bits of the first calculation result corresponding to the rising edge of the register, denoted as Up1 to Upm. In the second register unit, the data input terminals of each D flip-flop are connected to the 1st to the mth bits of the binary code output by the transcoding unit, denoted as F1 to Fm; the clock input terminal is used to connect to the OR signal C; and the data output terminal is used to output the 1st to the mth bits of the second calculation result corresponding to the falling edge of the register, denoted as Down1 to Downm.

[0016] As a further improvement of the present invention, the sign determination unit includes eight buffers BUFF1~BUFF8, six inverters INV1~INV6, six AND gates AND1~AND6, two OR gates OR1 and OR2, and two D flip-flops DFF1 and DFF2. BUFF1, BUFF2, and BUFF3 are connected in series; the input of BUFF1 is connected to A, and the output signals of BUFF1, BUFF2, and BUFF3 are denoted as A1, A2, and A3, respectively. BUFF4, BUFF5, and BUFF6 are connected in series; the input of BUFF4 is connected to B, and the output signals of BUFF4, BUFF5, and BUFF6 are denoted as B1, B2, and B3, respectively.

[0017] The input of INV1 is connected to B3, and its output is connected to one of the inputs of AND1. The other input of AND1 is connected to A3. The output of AND1 is connected to the input of BUFF7. The output of BUFF7 is connected to the data input of DFF1. The input of INV2 is connected to A1, and its output is connected to one of the inputs of AND2. The other input of AND2 is connected to A2. The output of AND2 is connected to one of the inputs of OR1. The input of INV3 is connected to B1, and its output is connected to one of the inputs of AND3. The other input of AND3 is connected to B2. The output of AND3 is connected to the other input of OR1. The output of OR2 is connected to the clock input of DFF1. The data output of DFF1 is used to output the value of the UpSign bit of the first calculation result corresponding to the rising edge of A and B.

[0018] The input of INV4 is connected to A3, and its output is connected to one of the inputs of AND4. The other input of AND4 is connected to B3. The output of AND4 is connected to the input of BUFF8. The output of BUFF8 is connected to the data input of DFF2. The input of INV5 is connected to A2, and its output is connected to one of the inputs of AND5. The other input of AND5 is connected to A1, and the output of AND5 is connected to one of the inputs of OR1. The input of INV6 is connected to B2, and its output is connected to one of the inputs of AND6. The other input of AND6 is connected to B1. The output of AND6 is connected to the other input of OR2. The output of OR2 is connected to the clock input of DFF2. The data output of DFF2 is used to output the value of the DownSign bit, which represents the first calculation result indicated by the falling edge of A and B.

[0019] The present invention also includes a time-domain in-memory computing circuit, which includes an in-memory computing module. This time-domain in-memory computing circuit employs a dual-edge time-to-digital converter as described above; the dual-edge time-to-digital converter is used to quantize both the first calculation result represented by the rising edge and the second calculation result represented by the falling edge of the calculation signal A output by the in-memory computing module.

[0020] The present invention also includes a CIM chip, which is packaged from the time-domain memory circuit as described above.

[0021] The technical solution provided by this invention has the following beneficial effects: Unlike existing circuits that start from the rising and falling edges, this invention, a novel dual-edge time-to-digital converter (TDC), incorporates two single-channel TDCs that time-division multiplex the first and second calculation results, respectively. This invention provides a novel dual-edge time-to-digital converter with a completely new architecture and circuit principle. It divides the quantization task of the two calculation results into a symbol quantization subtask and a numerical quantization subtask, and designs dedicated symbol determination and numerical calculation modules to complete both subtasks.

[0022] The sign determination module determines the order of the rising and falling edges of the calculated signal A and the reference signal B, and then stores the determination result using the subsequently generated asynchronous signal. The numerical counting module first shapes the signals A and B to obtain an OR signal C and an AND signal D; then, it processes signals C and D using a specially designed adjustable delay unit and a specially designed fixed delay unit, respectively, and uses an XOR gate to obtain an n-bit thermometer code representing the first and second calculation results. After the thermometer code is decoded into binary code by a decoder, the waveforms of C and D are used as trigger signals, and the values ​​of the first and second calculation results generated asynchronously by two sets of D flip-flops are stored respectively.

[0023] Compared to existing circuit solutions, the new solution provided by this invention can simultaneously extract the sign bits and values ​​of the two calculation results represented by the two double edges of the calculation signal in one go (completed in asynchronous timing) within the same circuit. Furthermore, the numerical calculation module supports adaptive settings for quantization precision and quantization. This significantly reduces circuit area and power consumption while ensuring the reliability of the quantization results, overcoming the related shortcomings of traditional TDC (Transmission Controlled Diode). Attached Figure Description

[0024] Figure 1 This is a circuit architecture diagram of the dual-edge time-to-digital converter provided in Embodiment 1 of the present invention.

[0025] Figure 2 This is a typical circuit diagram of the symbol determination module in Embodiment 1 of the present invention.

[0026] Figure 3 This paper compares the different scenarios that may exist between the calculated signal A and the reference signal B in a two-sided edge time-to-data converter with the shaped OR signal C and signal D of the present invention.

[0027] Figure 4 This is a detailed circuit diagram of the shaping unit, the first delay chain, the second delay chain, and the quantization unit in the numerical calculation module of Embodiment 1 of the present invention.

[0028] Figure 5 This is a circuit diagram of the fixed delay unit and the adjustable delay unit in the first delay chain and the second delay chain.

[0029] Figure 6 This is a detailed circuit diagram of the transcoding unit and the separate storage unit in the numerical calculation module of Embodiment 1 of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0031] Example 1 Existing time-domain in-memory computing circuits typically require quantization circuits to quantize the calculation results corresponding to the rising and falling edges separately using two channels of time-division multiplexing (TDC) within the same time period. Furthermore, they may introduce new power consumption and area limitations due to synchronous logic, resulting in high area and power consumption for the quantization circuit section. This embodiment provides a dual-edge time-to-digital converter (DTDC) that can, within a single quantization circuit, asynchronously quantize the sign and value bits of the first calculation result represented by the rising edge and the second calculation result represented by the falling edge, respectively.

[0032] In a time-domain in-memory computing circuit with two edges, the computation signal A is a signal input from an external circuit to characterize the computation result. Both the rising and falling edges of this signal can represent a computation result. The reference signal B serves as a benchmark to assist in quantizing the computation signal A. The order of the rising edges of A and B characterizes the sign of the first computation result, and the delay difference between the rising edges of A and B characterizes the value of the first computation result. Similarly, the order of the falling edges of A and B characterizes the sign of the second computation result, and the delay difference between the falling edges of A and B characterizes the value of the second computation result.

[0033] Unlike existing dual-edge time-to-digital converters (TDCs), this one uses one TDC channel to quantize the first calculation result on the rising edges of A and B, and another TDC channel to quantize the second calculation result on the falling edges of A and B. Figure 1 As shown, the dual-edge time-to-digital converter provided in this embodiment includes a sign determination module and a value calculation module. The sign determination module is used to quantize the value of the sign bit UpSign of the first calculation result corresponding to the rising edge and the value of the sign bit DownSign of the second calculation result corresponding to the falling edge, based on the input calculation signal A and the reference signal B, respectively. The value calculation module is used to quantize the value of the value bit UpValue of the first calculation result corresponding to the rising edge and the value of the value bit DownValue of the second calculation result corresponding to the falling edge, based on the inputs A and B, respectively.

[0034] In the sign determination module, if the rising edge of the calculated signal A is earlier than the rising edge of the reference signal B, the sign bit UpSign of the first calculation result is 1; if the rising edge of the calculated signal A is later than the rising edge of the reference signal B, the sign bit UpSign of the first calculation result is 0. Correspondingly, if the falling edge of the calculated signal A is earlier than the falling edge of the reference signal B, the sign bit DownSign of the second calculation result is 1; if the falling edge of the calculated signal A is later than the falling edge of the reference signal B, the sign bit DownSign of the second calculation result is 0.

[0035] To achieve the above circuit function, the sign determination module designed in this embodiment mainly utilizes multiple buffers to generate three delayed calculation signals and reference signals. Then, it uses the delayed signals of the first and second segments of the calculation signals and the delayed signal of the reference signal to determine whether an edge has occurred. Simultaneously, when an edge occurs, it checks which edge arrives first: the delayed signal of the third segment of the calculation signal or the delayed signal of the reference signal. If the rising or falling edge of the delayed signal of the calculation signal occurs first, the sign bit of the corresponding rising and falling edge is recorded as 1, indicating that the edge of the calculation signal is faster than the edge of the reference signal. The corresponding calculation result is greater than the reference value. If the rising or falling edge of the delayed signal of the reference signal occurs first, the sign bit of the corresponding rising and falling edge is recorded as 0, indicating that the edge of the calculation signal is slower than the edge of the reference signal. The corresponding calculation result is less than the reference value.

[0036] In practical applications, this embodiment provides a typical scheme for the symbol determination module, such as... Figure 2 As shown. This sign determination unit includes 8 buffers BUFF1~BUFF8, 6 inverters INV1~INV6, 6 AND gates AND1~AND6, 2 OR gates OR1, OR2, and 2 D flip-flops DFF1 and DFF2. BUFF1, BUFF2, and BUFF3 are connected in series; the input of BUFF1 is connected to A, and the output signals of BUFF1, BUFF2, and BUFF3 are denoted as A1, A2, and A3, respectively. BUFF4, BUFF5, and BUFF6 are connected in series; the input of BUFF4 is connected to B, and the output signals of BUFF4, BUFF5, and BUFF6 are denoted as B1, B2, and B3, respectively.

[0037] The input of INV1 is connected to B3, and its output is connected to one of the inputs of AND1. The other input of AND1 is connected to A3. The output of AND1 is connected to the input of BUFF7. The output of BUFF7 is connected to the data input of DFF1. The input of INV2 is connected to A1, and its output is connected to one of the inputs of AND2. The other input of AND2 is connected to A2. The output of AND2 is connected to one of the inputs of OR1. The input of INV3 is connected to B1, and its output is connected to one of the inputs of AND3. The other input of AND3 is connected to B2. The output of AND3 is connected to the other input of OR1. The output of OR2 is connected to the clock input of DFF1. The data output of DFF1 is used to output the value of the UpSign bit of the first calculation result corresponding to the rising edge of A and B.

[0038] The input of INV4 is connected to A3, and its output is connected to one of the inputs of AND4. The other input of AND4 is connected to B3. The output of AND4 is connected to the input of BUFF8. The output of BUFF8 is connected to the data input of DFF2. The input of INV5 is connected to A2, and its output is connected to one of the inputs of AND5. The other input of AND5 is connected to A1, and the output of AND5 is connected to one of the inputs of OR1. The input of INV6 is connected to B2, and its output is connected to one of the inputs of AND6. The other input of AND6 is connected to B1. The output of AND6 is connected to the other input of OR2. The output of OR2 is connected to the clock input of DFF2. The data output of DFF2 is used to output the value of the DownSign bit, which represents the first calculation result indicated by the falling edge of A and B.

[0039] The circuit logic for implementing the sign determination module to quantize the signs of the two calculation results represented by the rising edge and falling edge is as follows: After passing A and B through three buffers to obtain A1, A2, A3 and B1, B2, B3 with specified delays, it is possible to utilize... To detect the occurrence of a rising edge in waveform A, use... This allows detection of a falling edge in waveform A, corresponding to... It can detect when the B waveform has a rising edge. It can detect when a falling edge appears in waveform B. Among other things, This means that if either A or B has a rising edge, the corresponding... This indicates the case where either A or B has a falling edge. Therefore, when only considering the rising edges of A and B, This situation will occur twice, that is to say This waveform will produce two square waves. For the D flip-flops DFF1 and DFF2 that store the sign bit, they will also store two values, but the second value will overwrite the first. The second value will be retrieved. At the rising edge of a square wave, there are only two possibilities: A3=1 and B3=0, or A3=0 and B3=1. We take the case of A3=1 and B3=0 as 1, which corresponds to the rising edge of the calculated delay A occurring after the rising edge of the reference delay B. Therefore, when only considering the falling edges of A and B... This situation can also occur twice, because This waveform will produce two square waves. For a D flip-flop storing the sign bit, it will also store two values, but the second value will overwrite the first, and the second value will be used. When the square wave rises, there are only two cases: A3=1 and B3=0 or A3=0 and B3=1. Taking the case of A3=0 and B3=1 as 1, it corresponds to the falling edge of the calculated delay A occurring after the falling edge of the reference delay B.

[0040] The embodiment provided is as follows: Figure 2 The circuit scheme shown is an optimal circuit design for the sign determination module. It can simultaneously quantize and output the values ​​of the sign bit UpSign of the first calculation result and the sign bit DownSign of the second calculation result within a single circuit module, based on the input calculation signal A and the reference signal B. In other embodiments, the sign determination module can also be implemented based on a similar circuit scheme in existing solutions. For example, it can obtain the rising edges and falling edges of A and B respectively through two determination circuits, and determine their order to obtain the value of the sign bit of the two calculation results.

[0041] When handling time-to-digital conversion tasks with two edges, such as Figure 3 As shown, according to the order in which the two edges of the calculated signal A and the reference signal B appear, there are four cases: (1) The rising and falling edges of A are both earlier than the rising and falling edges of B; (2) The rising and falling edges of A are both later than the rising and falling edges of B; (3) The rising edge of A is earlier than the rising edge of B, but the falling edge is later than the falling edge of B; (4) The rising edge of A is later than the rising edge of B, but the falling edge is earlier than the falling edge of B. To address the above complex quantization problem, the traditional dual-edge time-to-digital converter can only process the rising and falling edges separately through two TDC channels, thus simplifying the four cases into two cases; and designing the corresponding TDC circuit.

[0042] In this embodiment, to simplify circuit design and reduce power consumption, the numerical calculation module employs a novel strategy when quantizing the delay difference between the rising and falling edges of A and B. This strategy first shapes A and B using a shaping unit to obtain an OR signal C (C=A+B) and an AND signal D (D=A&B) between A and B. Then, C and D are used to replace A and B for subsequent bit quantization operations.

[0043] Based on the generation methods of OR signal C and AND signal D, it is known that the rising edge of C always precedes the rising edge of D, while the falling edge of C always follows the falling edge of D. Therefore, OR signal C and AND signal D can further simplify the order of the rising and falling edges of the original calculation signal A and reference signal B into a single case. Based on this, the numerical calculation module of this embodiment transforms the task of quantizing the delay difference between the rising and falling edges of A and B into quantizing the delay difference between the rising and falling edges of C and D; this significantly reduces circuit complexity and supports the quantization of two calculation results corresponding to the rising and falling edges within a single circuit, overcoming the shortcomings of traditional circuit schemes.

[0044] Specifically, such as Figure 1 and Figure 4 As shown, the numerical calculation module in this embodiment includes a shaping unit, a first delay chain, a second delay chain, a quantization unit, a transcoding unit, and a separate storage unit. The shaping unit performs OR and AND operations on A and B respectively to obtain an OR signal C and an AND signal D. In practical applications, the shaping unit can be implemented by a circuit including an OR gate OR0 and an AND gate AND0. The two inputs of OR0 are connected to A and B respectively, and its output is used to output the OR signal C; wherein, when either A or B is high, C is high; and when both A and B are low, C is low. The two inputs of AND0 are connected to A and B respectively, and its output is used to output the AND signal D; wherein, when both A and B are high, C is high; and when either A or B is low, C is low.

[0045] In this embodiment, the first delay chain and the second delay chain in the numerical calculation module are used to synchronously introduce delay signals with different delay intervals in C and D, so that the quantization unit can generate a thermometer code representing the delay difference between the rising edges of C and D and the delay difference between the falling edges of C and D based on the two sets of delay signals.

[0046] Specifically, such as Figure 4 As shown, assuming the first and second calculation results to be quantized have a range of 3 bits, i.e., m=3, and the corresponding maximum value is "7", then the required length of the thermometer code to be converted is n=2. 3=8. In this embodiment, the first delay chain can be formed by sequentially connecting n adjustable delay units (denoted as DY1~DY8 when n is 8), which is used to generate n first-class delay signals C1~Cn with sequentially unit delay intervals based on the input C. That is, the delay difference between C1 and C is a unit delay; the delay difference between C2 and C1 is a unit delay, and so on. Correspondingly, the second delay chain is formed by sequentially connecting n fixed delay units (denoted as ID1~ID8 when n is 8), which is used to generate n second-class delay signals D1~Dn with sequentially intrinsic delay intervals based on the input D. That is, the delay difference between D1 and D is the intrinsic delay; the delay difference between C2 and C1 is the intrinsic delay, and so on.

[0047] In practical applications, both fixed-delay units and adjustable-delay units are implemented using the same delay circuit. For example... Figure 5 As shown, the delay circuit includes three PMOS transistors P1 to P3 and three NMOS transistors N1 to N3. The sources of P1 and P3 are connected to VDD; the drain of P1 is connected to the source of P2; the drains of P2 and N2 are connected to the gates of P3 and N3; the source of N2 is connected to the drain of N1; and the sources of N1 and N3 are connected to VSS. The gates of P2 and N2 are connected and serve as the input terminal IN of the delay circuit; the drains of P3 and N3 are connected and serve as the output terminal OUT of the delay circuit.

[0048] In this delay circuit, the first stage uses an inverter with added current-limiting transistors P1 and N1, which allows adjustment of the delay difference between the input signals IN and OUT by adjusting the gate voltage of the current-limiting transistors. The second stage uses a normal inverter to increase the slew rate of the waveform's rising and falling edges.

[0049] Based on this circuit design, in the fixed delay unit, the gate of N1 is connected to VDD, and the gate of P1 is connected to VSS. In the adjustable delay unit, the gate of N1 is connected to the first bias voltage BIAS1, and the gate of P1 is connected to the second bias voltage BIAS2. The fixed delay unit fixes the gate voltages of the current-limiting transistors P1 and N1 in the first stage to VSS and VDD, respectively, forming an intrinsic delay close to that of the delay unit itself. The second stage still uses a normal inverter to resist the error caused by the accumulation of intrinsic delay during long delay counting. The fixed delay unit sets the gate voltages of the current-limiting transistors N1 and P1 in the first stage to the adjustable first bias voltage BIAS1 and second bias voltage BIAS2, thereby obtaining the desired unit delay of any specified length.

[0050] Based on this, and considering the quantization precision of the numerical part: (C2-C1)-(D2-D1), The range is: [(C2-C1)-(D2-D1)]×n; Therefore, by adjusting the voltage values ​​of BIAS1 and BIAS2, the length of the unit delay generated by each adjustable delay unit in the first delay chain is changed, thereby adjusting the quantization accuracy and range of the numerical calculation module.

[0051] In practical applications, in addition to adopting, Figure 5 In addition to the required fixed and adjustable delay units, the extended circuit shown can also be used to implement both types of delay units using different delay circuits. For example, the circuit structure of the two delay units can be adjusted or heterogeneous components can be used according to the actual requirements of different ranges and different accuracies (for example, replacing the current limiting transistor with a high-threshold MOSFET can reduce the mismatch in individual measurement accuracy by replacing the ordinary MOSFET with a high-threshold MOSFET).

[0052] like Figure 4 As shown, the quantization unit includes n XOR gates (denoted as XOR1~XOR8 when n is 8); the two inputs of the i-th XOR gate are connected to the signals Ci and Di output by the i-th stage delay unit in the first and second delay chains, respectively, and the output outputs the value of the i-th bit of the thermometer code representing the first or second calculation result, i=1~n. The transcoding unit is used to convert the n-bit thermometer code representing the first or second calculation result output by the quantization unit into an m-bit binary code; 2 m =n. In this embodiment, the circuit that converts the thermometer code into binary code is a conventional circuit module in this field, and its circuit principle and structure will not be described in detail in this embodiment.

[0053] In this embodiment, the shaping unit, first delay chain, second delay chain, quantization unit, and transcoding unit in the numerical calculation module can output the binary code of the first calculation result represented by the rising edge and the binary code of the second calculation result represented by the falling edge, respectively, in an asynchronous timing sequence based on the original input calculation signal A and reference signal B. To extract the numerical bits of the two calculation results output in the asynchronous timing sequence, the separate storage unit in this embodiment is connected to the output of the transcoding unit and is used to latch and output the values ​​of the numerical bits of the first and second calculation results using D flip-flops with D and C as clock input signals, respectively.

[0054] like Figure 6As shown, the separate storage unit includes 2m D flip-flops; m of these D flip-flops constitute the first register unit; the remaining m D flip-flops constitute the second register unit. In the first register unit, the data input (D terminal) of each D flip-flop is connected to the 1st to the mth bits of the binary code output by the transcoding unit, denoted as F1~Fm; the clock input (CLK terminal) is connected to the AND signal D; and the data output (Q terminal) is used to output the 1st to the mth bits of the first calculation result corresponding to the rising edge of the register, denoted as Up1~Upm. In the second register unit, the data input of each D flip-flop is connected to the 1st to the mth bits of the binary code output by the transcoding unit, denoted as F1~Fm; the clock input is connected to the OR signal C; and the data output is used to output the 1st to the mth bits of the second calculation result corresponding to the falling edge of the register, denoted as Down1~Downm.

[0055] Based on the above circuit design, the circuit principle of the numerical calculation module in the dual-edge time-to-digital converter provided in this embodiment is as follows: Taking n=8 and m=3 as an example, the shaping unit processes A and B to obtain C and D; when the quantization unit performs an XOR operation on the corresponding Ci and Di, as time goes by, the XOR result E1E2E3E4E5E6E7E8 changes from 0000_0001 to 0000_0011, then to 0000_0111, until the final 1111_1111. The corresponding transcoding unit converts the thermometer code into binary code, and the decoding result is F1F2F3.

[0056] Since the rising edge of the waveform output by the shaping unit or signal C always precedes the rising edge of the waveform of signal D, and the falling edge of waveform C always follows the falling edge of waveform D, the rising edge of waveform D can be considered as the end of the rising edge count. Similarly, the falling edge of waveform C can be considered as the end of the falling edge count. In this embodiment, the rising edge of waveform D is used as the trigger signal to store the numerical bits of the second calculation result corresponding to the rising edge into the D flip-flop in the separate storage unit, and the falling edge of waveform C is used as the trigger signal to store the numerical bits of the second calculation result corresponding to the falling edge into the D flip-flop. After the rising edge count of F1F2F3 is completed, the numerical bits of the first calculation result can be stored in one set of D flip-flops and output externally; while after the falling edge count of F1F2F3 is completed, the numerical bits of the second calculation result can be stored in another set of D flip-flops and output externally.

[0057] Example 2 Based on the dual-edge time-to-digital converter with a novel architecture and circuit principle provided in Embodiment 1, this embodiment further provides a time-domain in-memory computing circuit, which includes an in-memory computing module. Specifically, this time-domain in-memory computing circuit employs the aforementioned dual-edge time-to-digital converter; the dual-edge time-to-digital converter is used to quantize the first calculation result represented by the rising edge and the second calculation result represented by the falling edge of the calculation signal A output by the in-memory computing module according to the reference signal B.

[0058] In practical applications, this embodiment also provides a CIM chip, which is packaged from the time-domain memory circuit as described above.

[0059] Simulation test To verify the performance of the novel double-edge time-to-digital converter circuit provided by this invention, technicians introduced the relevant circuit into a time-domain-based in-memory computing circuit based on TSMC's 28nm process and performed simulation tests on the relevant circuit.

[0060] Test results show that the architecture has a single-edge measurement accuracy of 200ps, a single-edge measurement range of 1.6ns, a total range of 3.2ns, and a core area of ​​20.1um (width) * 9.1um (height) at a working voltage of 0.9V.

[0061] Furthermore, experimental data shows that the circuit consumes 29.017uW of power, and the probability of a sign bit error after 3000 Monte Carlo simulations is only 0.0667%, while the probability of a 1-bit difference error after 3000 Monte Carlo simulations is only 0.133%. The circuit's accuracy and reliability meet the design goals, and its circuit area and power consumption are significantly lower than traditional dual-channel, dual-edge time-to-digital converters; its performance is outstanding.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dual-edge time-to-digital converter, characterized in that, It includes: The sign determination module is used to quantize the sign bit values ​​of the first calculation result corresponding to the rising edge and the second calculation result corresponding to the falling edge based on the input calculation signal A and the reference signal B, respectively. The numerical calculation module includes a shaping unit, a first delay chain, a second delay chain, a quantization unit, a transcoding unit, and a separate storage unit. The shaping unit performs OR and AND operations on A and B respectively to obtain OR signal C and AND signal D. The first delay chain uses n adjustable delay units to generate n first-class delay signals C1 to Cn with sequential unit delay intervals based on the input C. The second delay chain uses n fixed delay units to generate n second-class delay signals D1 to Dn with sequential intrinsic delay intervals based on the input D. The quantization unit includes n XOR gates, where the two inputs of the i-th XOR gate are connected to the signals Ci and Di output from the i-th stage of the first and second delay chains, respectively, and the output outputs the value of the i-th bit of the thermometer code representing the first or second calculation result, i=1~n. The transcoding unit converts the n-bit thermometer code output by the quantization unit into an m-bit binary code. m =n; The output terminals of the separate storage unit and the transcoding unit are connected, and are used to latch and output the values ​​of the first calculation result and the second calculation result through D flip-flops with D and C as clock input signals respectively.

2. The dual-edge time-to-digital converter as described in claim 1, characterized in that: The fixed delay unit and the adjustable delay unit use the same delay circuit; the delay circuit includes three PMOS transistors P1 to P3 and three NMOS transistors N1 to N3; the sources of P1 and P3 are connected to VDD; the drain of P1 is connected to the source of P2; the drains of P2 and N2 are connected to the gates of P3 and N3; the source of N2 is connected to the drain of N1; the sources of N1 and N3 are connected to VSS; the gates of P2 and N2 are connected and serve as the input terminal IN of the delay circuit; the drains of P3 and N3 are connected and serve as the output terminal OUT of the delay circuit. In the fixed delay unit, the gate of N1 is connected to VDD, and the gate of P1 is connected to VSS. In the adjustable delay unit, the gate of N1 is connected to the first bias voltage BIAS1, and the gate of P1 is connected to the second bias voltage BIAS2.

3. The dual-edge time-to-digital converter as described in claim 2, characterized in that: By adjusting the voltage values ​​of BIAS1 and BIAS2, the length of the unit delay generated by each adjustable delay unit in the first delay chain is changed, thereby adjusting the quantization accuracy and range of the numerical calculation module.

4. The dual-edge time-to-digital converter as described in claim 1, characterized in that: The fixed delay unit and the adjustable delay unit employ different delay circuits.

5. The dual-edge time-to-digital converter as described in claim 1, characterized in that: The range of the numerical calculation module is adjusted by adjusting the number of delay units in the first and second delay chains and the number of input bits n of the transcoding unit.

6. The dual-edge time-to-digital converter as described in claim 1, characterized in that: The shaping unit includes an OR gate OR0 and an AND gate AND0; the two inputs of OR0 are connected to A and B respectively, and the output is used to output an OR signal C; the two inputs of AND0 are connected to A and B respectively, and the output is used to output an AND signal D.

7. The dual-edge time-to-digital converter as described in claim 1, characterized in that: The separate storage unit includes 2m D flip-flops; m of these D flip-flops constitute the first register unit; and the remaining m D flip-flops constitute the second register unit. In the first register unit, the data input terminals of each D flip-flop are respectively connected to the first to the mth bits of the binary code output by the transcoding unit, denoted as F1~Fm; the clock input terminal is used to connect to the AND signal D; the data output terminal is used to output the first to the mth bits of the numerical value of the first calculation result corresponding to the rising edge of the register, denoted as Up1~Upm. In the second register unit, the data input terminals of each D flip-flop are respectively connected to the first to the mth bits of the binary code output by the transcoding unit, denoted as F1 to Fm; the clock input terminal is used to connect to the OR signal C; the data output terminal is used to output the first to the mth bits of the numerical value of the second calculation result corresponding to the falling edge of the register, denoted as Down1 to Downm.

8. The dual-edge time-to-digital converter as described in claim 1, characterized in that: The symbol determination unit includes 8 buffers BUFF1~BUFF8, 6 inverters INV1~INV6, 6 AND gates AND1~AND6, 2 OR gates OR1 and OR2, and 2 D flip-flops DFF1 and DFF2; BUFF1, BUFF2, and BUFF3 are connected in series; the input terminal of BUFF1 is connected to A, and the output signals of BUFF1, BUFF2, and BUFF3 are denoted as A1, A2, and A3, respectively; BUFF4, BUFF5, and BUFF6 are connected in series; the input terminal of BUFF4 is connected to B, and the output signals of BUFF4, BUFF5, and BUFF6 are denoted as B1, B2, and B3, respectively. The input of INV1 is connected to B3, and its output is connected to one of the inputs of AND1. The other input of AND1 is connected to A3. The output of AND1 is connected to the input of BUFF7. The output of BUFF7 is connected to the data input of DFF1. The input of INV2 is connected to A1, and its output is connected to one of the inputs of AND2. The other input of AND2 is connected to A2. The output of AND2 is connected to one of the inputs of OR1. The input of INV3 is connected to B1, and its output is connected to one of the inputs of AND3. The other input of AND3 is connected to B2. The output of AND3 is connected to the other input of OR1. The output of OR2 is connected to the clock input of DFF1. The data output of DFF1 is used to output the value of the UpSign bit of the first calculation result corresponding to the rising edge of A and B. The input of INV4 is connected to A3, and its output is connected to one of the inputs of AND4. The other input of AND4 is connected to B3. The output of AND4 is connected to the input of BUFF8. The output of BUFF8 is connected to the data input of DFF2. The input of INV5 is connected to A2, and its output is connected to one of the inputs of AND5. The other input of AND5 is connected to A1. The output of AND5 is connected to one of the inputs of OR1. The input of INV6 is connected to B2, and its output is connected to one of the inputs of AND6. The other input of AND6 is connected to B1. The output of AND6 is connected to the other input of OR2. The output of OR2 is connected to the clock input of DFF2. The data output of DFF2 is used to output the value of the sign bit DownSign, which represents the first calculation result indicated by the falling edge of A and B.

9. A time-domain in-memory computing circuit, comprising an in-memory computing module, characterized in that: It employs a dual-edge time-to-digital converter as described in any one of claims 1-8, wherein the dual-edge time-to-digital converter is used to quantize the first calculation result represented by the rising edge and the second calculation result represented by the falling edge of the calculation signal A output by the memory module.

10. A CIM chip, characterized in that: It is packaged from the time-domain memory circuit as described in claim 9.

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