Clock signal generation circuit and method, chip and electronic equipment
By using a first counting module and a second counting module to count input clocks of different frequencies, and adjusting the count value of the second counting module, the problem of the decrease in accuracy of quartz clocks under temperature changes is solved, and a higher precision target clock signal is generated.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPSEA TECH SHENZHEN CO LTD
- Filing Date
- 2024-11-12
- Publication Date
- 2026-05-12
AI Technical Summary
The accuracy of quartz clocks can deviate with temperature changes, causing a decrease in the accuracy of real-time clocks in high-precision application systems.
The first and second counting modules are used to count input clocks of different frequencies, and the counting value of the second counting module is adjusted by the counting adjustment module to achieve temperature compensation for the target clock signal.
The accuracy of the target clock signal has been improved, especially under temperature variations, resulting in higher adjustment accuracy and a more precise time base.
Smart Images
Figure CN122018638A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a clock signal generation circuit, method, chip, and electronic device. Background Technology
[0002] Real-time clocks (RTCs) are a widely used technology in electronic systems. They provide precise real-time time or time bases (such as year / month / day / hour / minute / second) to electronic systems via quartz clocks, enabling functions such as system timekeeping, alarm clocks, and timers. In some applications without network connectivity, the electronic system's time base relies entirely on the accuracy of the real-time clock. Therefore, for applications requiring high-precision clocks, the accuracy of the real-time clock must be guaranteed in the design.
[0003] However, one of the characteristics of quartz clocks is that their accuracy deviates with temperature changes. Typically, the frequency deviation of a clock is smallest at room temperature (around 25°C), while the clock frequency gradually decreases as the temperature changes (from room temperature to higher or lower temperatures), leading to a decrease in real-time clock accuracy. Summary of the Invention
[0004] In view of the above problems, embodiments of this application provide a clock signal generation circuit, method, chip, and electronic device to solve the above technical problems.
[0005] In a first aspect, embodiments of this application provide a clock signal generation circuit, including:
[0006] The first counting module is used to count the first input clock, and reset the count value and output the first enable signal when the count reaches the first preset value.
[0007] The second counting module is used to count the second input clock. When the count reaches the second preset value, the count value is reset and a second enable signal is output.
[0008] The clock output module is used to output a target clock signal according to a first enable signal or a second enable signal.
[0009] A counting adjustment module is used to adjust the counting value of at least the second counting module;
[0010] The frequency of the first input clock is less than the frequency of the second input clock.
[0011] Secondly, embodiments of this application also provide a clock signal generation method, including:
[0012] Measure the ambient temperature of the crystal oscillator at least once within a preset period;
[0013] Based on at least one ambient temperature of the crystal oscillator and a preset crystal oscillator temperature profile, at least a second count adjustment value is determined;
[0014] During the counting process of the first counting module and the second counting module, the counting value of the second counting module is adjusted according to the second counting adjustment value;
[0015] The first counting module is used to count the first input clock, and the second counting module is used to count the second input clock, wherein the frequency of the first input clock is less than the frequency of the second input clock.
[0016] Secondly, embodiments of this application also provide a chip including the aforementioned clock signal generation circuit.
[0017] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or clock signal generation circuit.
[0018] This application utilizes a first counting module to count a first input clock and a second counting module to count a second input clock. The first counting module can reset the count value and output a first enable signal when the count reaches a first preset value, and the second counting module can reset the count value and output a second enable signal when the count reaches a second preset value. Therefore, the clock output module can output a target clock signal according to either the first or the second enable signal. At the same time, since the counting adjustment module can adjust at least the count value of the second counting module, adjusting the count value of the second counting module is equivalent to changing the number of cycles of the second input clock in one cycle of the target clock signal. When the frequency of the first input clock is less than the frequency of the second input clock (i.e., the cycle of the second input clock is smaller), adjusting the count value of the second counting module can achieve higher adjustment accuracy, which is beneficial for obtaining a target clock signal with higher accuracy.
[0019] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A schematic diagram of a crystal oscillator circuit in the related technology is shown.
[0022] Figure 2 A circuit diagram of a real-time clock in the related art is shown.
[0023] Figure 3 A schematic diagram of a clock signal generation circuit in an embodiment of this application is shown.
[0024] Figure 4 Another schematic diagram of the clock signal generation circuit in an embodiment of this application is shown.
[0025] Figure 5 A schematic diagram of a preset crystal oscillator temperature curve is shown in an embodiment of this application.
[0026] Figure 6 Another schematic diagram of the clock signal generation circuit in an embodiment of this application is shown.
[0027] Figure 7 A schematic flowchart of a clock signal generation method in an embodiment of this application is shown.
[0028] Figure 8 A flowchart illustrating a method for determining a count adjustment value is shown in an embodiment of this application.
[0029] Among them, 10 is the first counting module, 11 is the first counter, 20 is the second counting module, 21 is the second counter, 30 is the clock output module, 40 is the counting adjustment module, 41 is the first counting adjustment unit, and 42 is the second counting adjustment unit;
[0030] First input clock CLK1, second input clock CLK2, target clock signal CLKout, first enable signal out1, second enable signal out2. Detailed Implementation
[0031] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0032] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0033] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0034] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0035] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0036] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0037] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0038] Currently, real-time clocks can provide precise real-time time or time references for electronic systems using quartz clocks. However, because the accuracy of quartz clocks deviates with temperature changes, this can lead to a decrease in the accuracy of real-time clocks.
[0039] In related technologies, temperature compensation methods for real-time clocks mainly include two types: analog circuit compensation and software compensation. (See [reference needed]) Figure 1 , Figure 1A schematic diagram of a crystal oscillator circuit in the related art is shown. The crystal oscillator circuit includes a crystal oscillator XATL, an inverter INV, a resistor Rf, a resistor R0, a thermistor Rx, a capacitor C1, and a capacitor C2. In the analog circuit compensation method, since the resistance value of the thermistor Rx changes with temperature, the resonant frequency of the crystal oscillator XATL can be automatically adjusted at different temperatures.
[0040] See Figure 2 , Figure 2 A circuit diagram of a real-time clock in related technologies is shown. The real-time clock includes a crystal oscillator circuit and a 15-bit counter. The crystal oscillator circuit outputs a clock signal with an oscillation frequency of 32768Hz. The count value of the 15-bit counter is exactly 32768 (the binary number 1111111111111111 corresponds to the decimal number 32768). Therefore, the 15-bit counter counts the 32768Hz clock signal to 32768, and can output a clock signal of exactly 1Hz. This allows for counting seconds, minutes, hours, and days using a second counter, a minute counter, an hour counter, and a day counter, respectively. Assuming that the output oscillation frequency of the crystal oscillator circuit changes from 32768Hz to 32767Hz due to temperature, during software compensation, the initial count value of the 15-bit counter can be changed from 0 to 1. At this time, the total count value of the 15-bit counter changes to 32767, thus realizing the temperature compensation process of the real-time clock.
[0041] However, the accuracy of analog circuit compensation is difficult to guarantee due to the inconsistency of resistors and capacitors. On the other hand, the adjustment accuracy of a single count value of a 15-bit counter adjusted by software is 1 / 32768 = 30.5176 ppm (parts per million). In some scenarios with high clock deviation requirements (such as electricity meters requiring a real-time clock deviation of less than 11.6 ppm), the current software compensation adjustment method is also difficult to meet the requirements.
[0042] Therefore, this application provides a clock signal generation circuit, method, chip, and electronic device, which will be described in detail below.
[0043] First, refer to Figure 3 , Figure 3 A schematic diagram of a clock signal generation circuit in an embodiment of this application is shown, wherein the clock signal generation circuit includes a first counting module 10, a second counting module 20, a clock output module 30, and a counting adjustment module 40.
[0044] Specifically, the first counting module 10 is used to count the first input clock CLK1. When the count reaches a first preset value, the first counting module 10 can reset the count value and output a first enable signal out1. In some embodiments of this application, the first input clock CLK1 can be a clock signal output by a crystal oscillator circuit, for example, the first input clock CLK1 is a 32.768kHz clock signal output by the crystal oscillator circuit. In other embodiments of this application, the first input clock CLK1 can be a clock signal after frequency multiplication or division of the clock signal output by the crystal oscillator circuit. For example, the frequency of the first input clock CLK1 after frequency multiplication of the 32.768kHz clock signal output by the crystal oscillator circuit is 65.536kHz; or, for example, the frequency of the first input clock CLK1 after frequency division is 16.384kHz.
[0045] In some embodiments of this application, the first counting module 10 can count in an incremental counting manner. For example, taking the first counting module 10 as including a 15-bit counter, the initial count value of the 15-bit counter is 0000000000000000. When each pulse of the first input clock CLK1 arrives, the 15-bit counter flips until the count value of the 15-bit counter reaches 1111111111111111 (i.e., the first preset value is 32768). The count value of the first counting module 10 is then changed back to the initial count value 000000000000000 and the first enable signal out1 is output.
[0046] In some embodiments of this application, the first counting module 10 can count in a decrementing manner. For example, taking the first counting module 10 as including a 15-bit counter, the initial count value of the 15-bit counter is 111111111111111. When each pulse of the first input clock CLK1 arrives, the 15-bit counter flips until the count value of the 15-bit counter reaches 0000000000000000 (i.e., the first preset value is 0). The count value of the first counting module 10 is then changed back to the initial count value 111111111111111 and the first enable signal out1 is output.
[0047] The second counting module 20 is used to count the second input clock CLK2. When the count reaches a second preset value, the count value is reset and a second enable signal out2 is output. The frequency of the second input clock CLK2 is greater than the frequency of the first input clock CLK1. In some embodiments of this application, for example, in an embodiment where the first input clock CLK1 is a clock signal output by a crystal oscillator circuit, the second input clock CLK2 can be a clock signal after the clock signal output by the crystal oscillator circuit has been up-multiplied. For example, a 32.768kHz clock signal output by the crystal oscillator circuit, after being multiplied, results in a second input clock CLK2 with a frequency of 655.36kHz, meaning the frequency of the second input clock CLK2 signal is 20 times the frequency of the first input clock. In some embodiments of this application, the first input clock CLK1 and the second input clock CLK2 can be independent asynchronous clocks. For example, the first input clock CLK1 is a 32.768kHz clock signal output by a crystal oscillator circuit, and the second input clock CLK2 can be a clock signal with a frequency of 40MHz output after passing through a phase-locked loop circuit, a frequency divider, and other circuits.
[0048] In some embodiments of this application, the second counting module 20 can count in an incremental counting manner. For example, taking the second counting module 20 as including an 11-bit counter, the initial count value of the 11-bit counter is 00000000000. When each pulse of the second input clock CLK2 arrives, the 11-bit counter flips until the count value of the 11-bit counter reaches 10011000101 (i.e., the second preset value is 1221). The count value of the second counting module 20 is then changed back to the initial count value of 00000000000 and the second enable signal out2 is output.
[0049] For example, the initial count value of the 11-bit counter is 01100111011 (corresponding to the decimal number 827). With each pulse of the second input clock CLK2, the 11-bit counter toggles until the count value of the 11-bit counter reaches 11111111111 (i.e., the second preset value is 2048). Then, the count value of the second counting module 20 is changed back to the initial count value 01100111011 and the second enable signal out2 is output.
[0050] In some embodiments of this application, the second counting module 20 can count in a decrementing manner. For example, taking the second counting module 20 as including an 11-bit counter, the initial count value of the 11-bit counter is 10011000101 (corresponding to the decimal number 1221). When each pulse of the second input clock CLK2 arrives, the 11-bit counter flips until the count value of the 11-bit counter reaches 00000000000 (i.e., the second preset value is 0). The count value of the second counting module 20 is then changed back to the initial count value 10011000101 and the second enable signal out2 is output.
[0051] In some embodiments of this application, see Figure 3 The second counting module 20 is connected to the output terminal of the first counting module 10. The second counting module 20 can start counting the second input clock CLK2 in response to the first enable signal out1. For example, taking the first counting module 10 as including a 15-bit counter and the second counting module 20 as including an 11-bit counter, the initial count value of the 15-bit counter is 000000000000000. When the count value of the 15-bit counter reaches 111111111111111, the 15-bit counter outputs the first enable signal out1, causing the 11-bit counter to start counting the second input clock CLK2 from 000000000000 until the 11-bit counter counts to 10011000101 and outputs the second enable signal out2, so that the clock output module 30 outputs the target clock signal CLKout through the second enable signal out2.
[0052] The clock output module 30 is used to output a target clock signal CLKout according to the first enable signal out1 or the second enable signal out2. For example, the clock output module may include, but is not limited to, a pulse circuit that can output pulse signals, such as a pulse generator. The frequency of the target clock signal CLKout can be 1Hz, that is, the target clock signal CLKout is a second clock signal with a period of 1 second.
[0053] Understandably, the frequency of the target clock signal CLKout is not limited to this. The frequency of the target clock signal CLKout can also be 1 / 60Hz (i.e., minute clock), 1 / 3600Hz (instantaneous clock), etc.
[0054] In some embodiments of this application, such as the embodiment where the second counting module 20 starts counting the second input clock CLK2 in response to the first enable signal out1, the clock output module 30 may output the target clock signal CLKout in response to the second enable signal out2. For example, taking the period of the first input clock CLK1 as T1 and the period of the second input clock CLK2 signal as T2, since the second counting module 20 starts counting the second input clock CLK2 in response to the first enable signal out1, and the clock output module 30 outputs the target clock signal CLKout in response to the second enable signal out2, the period of the target clock signal CLKout is the sum of the duration of the counting process of the first counting module 10 and the duration of the counting process of the second counting module 20. Therefore, the period T0 of the target clock signal CLKout can be calculated by the formula T0 = T1*N1 + T2*N2, where N1 is the number of times the first counting module 10 counts from its initial count value to the first preset value (i.e., N1 is the difference between the first preset value and the initial count value of the first counting module 10), and N2 is the number of times the second counting module 20 counts from its initial count value to the second preset value (i.e., N2 is the difference between the second preset value and the initial count value of the first counting module 10).
[0055] The counting adjustment module 40 is used to adjust at least the counting value of the second counting module 20 to facilitate temperature compensation for the target clock signal CLKout. In some embodiments of this application, the counting adjustment module 40 can adjust the initial counting value of the second counting module 20. For example, taking an 11-bit counter with an initial counting value of 00000000000 as an example, after the counting adjustment module 40 adjusts the counting value of the second counting module 20, the initial counting value of the 11-bit counter changes to 00000000001; as another example, taking an 11-bit counter with an initial counting value of 10011000101 (corresponding to the decimal number 1221) as an example, after the counting adjustment module 40 adjusts the counting value of the second counting module 20, the initial counting value of the 11-bit counter is 10011000100 (corresponding to the decimal number 1220).
[0056] In some embodiments of this application, the counting adjustment module 40 can adjust its count value during the counting process of the second counting module 20. For example, taking the second counting module 20 as an example, which includes an 11-bit counter with an initial count value of 00000000000, the 11-bit counter is 10010000100 during the counting process. When the next pulse of the second input clock CLK2 arrives, the 11-bit counter remains at 10010000100 and does not flip to 10010000101. It is understood that the counting adjustment module 40 can also adjust the count value of the first counting module 10, and the adjustment method is similar to that of the second counting module 20, which will not be described again here.
[0057] In some embodiments of this application, the counting adjustment module 40 can also modify the second preset value of the second counting module 20, thereby changing the counting value of the second counting module 20. For example, taking the second counting module 20 as an 11-bit counter with an initial count value of 00000000000, the second preset value of the second counting module 20 is 10011000101 (corresponding to the decimal number 1221), and the counting adjustment module 40 can also modify the second preset value of the second counting module 20 to 10011000100 (corresponding to the decimal number 1220); as another example, taking the second counting module 20 as an 11-bit counter with an initial count value of 10011000101 (corresponding to the decimal number 1221), the second preset value of the second counting module 20 is 00000000000, and the counting adjustment module 40 can also modify the second preset value of the second counting module 20 to 00000000001 (corresponding to the decimal number 1).
[0058] In this embodiment, since the counting adjustment module 40 can adjust the counting value of the second counting module 20, this is equivalent to changing the number of toggles in the counting process of the second counting module 20 to reach the second preset value. According to the period calculation formula of the target clock signal CLKout, T0 = T2 * N2 + T1 * N1, adjusting the counting value of the second counting module 20 is equivalent to adjusting the N2 parameter in the above formula, thereby changing the period of the target clock signal CLKout. Finally, temperature compensation of the target clock signal CLKout can be achieved by adjusting the counting value of the second counting module 20.
[0059] For example, taking the target clock signal CLKout as a second clock with a period of 1 second, the frequency of the first input clock CLK1 as 32.768kHz, and the frequency of the second input clock CLK2 as 40MHz, then the periods of the first input clock CLK1 and the second input clock CLK2 are:
[0060] T1 = 1 / 32768 = 30.5176 ns
[0061] T2=1 / (40*1000*1000)=0.025ns
[0062] For a second clock with a period of 1 second, the adjustment precision corresponding to changing one count value of the first counting module 10 is 30.5176 ppm, while the adjustment precision corresponding to changing one count value of the second counting module 20 is 0.025 ppm. For example, assuming the second clock has a deviation of 20 ppm, the count value of the second counting module 20 can be changed to 20 / 0.025 = 800. As another example, assuming the second clock has a deviation of 71.0352 ppm (71.0352 = 30.5176 * 2 + 10), the count value of the first counting module 10 can be changed to 2, and the count value of the second counting module 20 can be changed to 10 / 0.025 = 800.
[0063] It can be seen that when the frequency of the first input clock CLK1 is less than the frequency of the second input clock CLK2 (i.e., the period of the second input clock CLK2 is smaller), adjusting the count value of the second counting module 20 can achieve higher adjustment accuracy. Compared with the scheme of adjusting the count value of the 15-bit counter corresponding to the 32.768kHz clock signal separately, this application can achieve higher adjustment accuracy and is conducive to obtaining a target clock signal CLKout with higher accuracy.
[0064] In some embodiments of this application, the frequency of the second input clock CLK2 is equal to the frequency of the first input clock CLK1, and the first ratio is equal to the default count value of the second counting module 20.
[0065] It should be noted that the default count value of the second counting module 20 refers to the count value of the second counting module 20 before it is adjusted by the counting adjustment module 40. That is, the counting adjustment module 40 has not adjusted the initial count value of the second counting module 20, nor has it adjusted the second preset value of the second counting module 20. At this time, the default count value is equal to the difference between the initial count value and the second preset value. For example, when the counting adjustment module 40 does not adjust the second counting module 20 (e.g., it does not adjust the initial count value and the second preset value of the second counting module 20), the initial count value of the second counting module 20 is 1100111011 (corresponding to the decimal number 827) and the second preset value is 111111111111 (i.e., the second preset value is 2048). At this time, the default count value of the second counting module 20 is 2048-827=1221. Assuming that the frequency of the first input clock CLK1 is 32.768kHz and the frequency of the second input clock CLK2 is 40MHz, the ratio of the frequency of the second input clock CLK2 to the frequency of the first input clock CLK1 is 40*1000 / 32.768=1220.703125≈1221. Therefore, the first ratio is equal to the default count value of the second counting module 20.
[0066] For example, when the counting adjustment module 40 does not adjust the second counting module 20, the initial counting value of the second counting module 20 is 10011000101 (corresponding to the decimal number 1221) and the second preset value is 00000000000. At this time, the default counting value of the second counting module 20 is 1221-0=1221. Assuming that the frequency of the first input clock CLK1 is 32.768kHz and the frequency of the second input clock CLK2 is 40MHz, then the ratio of the frequency of the second input clock CLK2 to the frequency of the first input clock CLK1 is 40*1000 / 32.768=1220.703125≈1221. Therefore, the first ratio is equal to the default counting value of the second counting module 20.
[0067] It should be noted that since the ratio of the frequency of the second input clock CLK2 to the frequency of the first input clock CLK1 is equal to the default count value of the second counting module 20, the time it takes for the second counting module 20 to flip from the initial count value to the second preset value without adjustment by the counting adjustment module 40 is equal to one cycle of the first input clock CLK1.
[0068] For example, taking the frequency of the first input clock CLK1 as 32.768kHz and the frequency of the second input clock CLK2 as 40MHz, the period of the first input clock CLK1 is 30.5176ns and the period of the second input clock CLK2 is 0.025ns. Then, 0.025 * 1221 = 30.5175 ≈ 30.5176ns. Thus, for the deviation of the second clock, a deviation greater than 30.5176ns (i.e., 30.5176ppm) can be corrected by adjusting the counting values of the first counting module 10 and the second counting module 20, while a deviation less than 30.5176ns can be corrected by adjusting the counting values of the second counting module 20 (or the first counting module 10 and the second counting module 20).
[0069] For example, assuming the deviation of the second clock is 40 ppm, for the above exemplary embodiment, the adjustment of the count values of the first counting module 10 and the second counting module 20 can be calculated according to the following formula:
[0070] △N1=40 / 30.5176=1...9.4824
[0071] △N2=9.4824 / 0.025=379...0.0074
[0072] Wherein, △N1 is the first counting adjustment value that the first counting module 10 needs to adjust, and △N2 is the second counting adjustment value that the second counting module 20 needs to adjust.
[0073] As can be seen, for a second clock deviation of 40ppm, after adjusting the count value of the first counting module 10 to 1 and the count value of the second counting module 20 to 379, the final second clock deviation is 0.0074ppm, which can greatly improve the accuracy of the second clock.
[0074] In some embodiments of this application, such as embodiments where the counting adjustment module 40 can adjust the counting values of the first counting module 10 and the second counting module 20, see [reference]. Figure 4 , Figure 4 Another schematic diagram of the clock signal generation circuit in an embodiment of this application is shown. The counting adjustment module 40 includes a first counting adjustment unit 41 and a second counting adjustment unit 42. The first counting adjustment unit 41 is used to adjust the counting value of the first counting module 10, and the second counting adjustment unit 42 is used to adjust the counting value of the second counting module 20.
[0075] For example, taking the first counting module 10 as having a 15-bit counter with an initial count value of 000000000000000, and the first enable signal out1 output when the count value of the 15-bit counter reaches 111111111111111, the first counting adjustment unit 41 can change the initial count value from 000000000000000 to 000000000000001. Then the number of toggles of the 15-bit counter is reduced from 32768 to 32767. This is equivalent to compensating the period of the target clock signal CLKout by the duration of one period of the first input clock CLK1. Assuming that the frequency of the first input clock CLK1 is 32.768kHz, the compensation duration is 30.5176ns.
[0076] Taking the second counting module 20 as an example, which includes an 11-bit counter with an initial count value of 1100111011 (corresponding to the decimal number 827) and outputs a second enable signal out2 when the count value of the 11-bit counter reaches 11111111111 (i.e., the second preset value is 2048), the second counting adjustment unit 42 can change the initial count value from 1100111011 (corresponding to the decimal number 827) to 10010110110 (corresponding to the decimal number 1206). Then, the number of toggles of the 11-bit counter is reduced from the original 2048-827=1221 to 2048-1206=842. This is equivalent to compensating the period of the target clock signal CLKout by the duration of 379 cycles of the second input clock CLK2. Assuming that the frequency of the second input clock CLK2 is 40MHz, the compensation duration is 9.475ns.
[0077] Understandably, the way to adjust the count value of the first counting module 10 is similar to the way to adjust the count value of the first counting module 10. For example, the initial count value of the first counting module 10 can be adjusted, or the first preset value of the first counting module 10 can be adjusted. This application will not elaborate further here.
[0078] In some embodiments of this application, the first counting adjustment unit 41 and the second counting adjustment unit 42 may include a storage circuit (e.g., a register) for writing data. The first counting adjustment unit 41 is configured to write a first counting adjustment value, and the second counting adjustment unit 42 is configured to write a second counting adjustment value. During the operation of the first counting module 10 and the second counting module 20, the first counting module 10 reads the data from the first counting adjustment unit 41 and performs counting adjustment, and the second counting module 20 reads the data from the second counting adjustment unit 42 and performs counting adjustment. For example, the first counting module 10 can adjust its initial count value or a first preset value according to the first counting adjustment value, and the second counting module 20 can adjust its initial count value or a second preset value according to the second counting adjustment value.
[0079] It should be noted that the first and second count adjustment values can be determined based on the ambient temperature of the crystal oscillator within a preset period and a preset crystal oscillator temperature curve. For example, refer to... Figure 5 , Figure 5 This illustration shows a schematic diagram of a preset crystal oscillator temperature curve in an embodiment of this application. If the ambient temperature is 25°C, the deviation of the target clock signal CLKout can be determined to be 0ppm, and there is no need to adjust the count values of the first counting module 10 and the second counting module 20. If the ambient temperature is -20°C, the deviation of the target clock signal CLKout can be determined to be approximately 80ppm. For an embodiment where the frequency of the first input clock CLK1 is 32.768kHz and the frequency of the second input clock CLK2 is 40MHz, the first count adjustment value and the second count adjustment value can be determined according to the following formula:
[0080] △N1=80 / 30.5176=2...19.4824
[0081] △N2=19.4824 / 0.025≈779
[0082] That is, the first count adjustment value can be determined to be 2, and the second count adjustment value is 779.
[0083] It should be pointed out that, in combination Figure 5 It can be seen that when the ambient temperature is greater than or less than 25℃, the frequency of the target clock signal CLKout decreases, meaning the period of the target clock signal CLKout increases. According to the formula for calculating the period of the target clock signal CLKout, T0 = T1*N1 + T2*N2, it is usually necessary to reduce the parameters N1 and / or N2 in this formula to achieve compensation. That is, the period of the target clock signal CLKout after compensation can be calculated using the following formula:
[0084] T0=T1*(N10-△N1)+T2*(N20-△N2)
[0085] Wherein, N10 is the default count value of the first counting module 10, N20 is the default count value of the second counting module 20, △N1 is the first count adjustment value, and △N2 is the second count adjustment value.
[0086] Understandably, similar to the default count value of the second counting module 20, the default count value of the first counting module 10 in the above formula refers to the count value of the first counting module 10 when it has not been adjusted by the counting adjustment module 40, which will not be elaborated here.
[0087] In some embodiments of this application, the first count adjustment value and the second count adjustment value can be determined once per second. That is, the ambient temperature can be acquired once per second and the first count adjustment value and the second count adjustment value can be determined according to the crystal oscillator temperature curve. Then, the count adjustment is performed during the counting process of the first count module 10 and the second count module 20 in the next second, thereby ensuring the accuracy of the second clock per second.
[0088] In some embodiments of this application, the first count adjustment value and the second count adjustment value can be determined at regular intervals. For example, during a 1024-second interval, the ambient temperature is acquired every second and the deviation of the target clock signal CLKout is determined based on the crystal oscillator temperature curve. Then, the deviation of the target clock signal CLKout within 1024 seconds is accumulated before determining the first count adjustment value and the second count adjustment value. Finally, the count values of the first count module 10 and the second count module 20 are adjusted at the 1024th second to ensure the accuracy of the target clock signal CLKout within the 1024-second span.
[0089] In some embodiments of this application, see Figure 6 , Figure 6 Another schematic diagram of the clock signal generation circuit in an embodiment of this application is shown, wherein the first counting module 10 includes a first counter 11 (e.g., a 15-bit counter), and the second counting module 20 includes a second counter 21 (e.g., an 11-bit counter); the trigger terminal of the first counter 11 is used to connect to the first input clock CLK1, and the load value input terminal val of the first counter 11 is connected to the first counting adjustment unit 41, so the first counter 11 can change its counting value according to the first counting adjustment value stored in the first counting adjustment unit 41; the trigger terminal of the second counter 21 is used to connect to the second input clock CLK2, and the load value input terminal val of the second counter 21 is connected to the second counting adjustment unit 42, so the second counter 21 can change its counting value according to the second counting adjustment value stored in the second counting adjustment unit 42.
[0090] In some embodiments of this application, such as an embodiment where the second counting module 20 can start counting the second input clock CLK2 in response to the first enable signal out1, see [reference]. Figure 7 The output terminal Q of the first counter 11 is connected to the load enable terminal of the second counter 21. The output terminal Q of the second counter 21 is connected to the input terminal of the clock output module 30. Therefore, the second counting module 20 starts counting the second input clock CLK2 in response to the first enable signal out1, and the clock output module 30 can output the target clock signal CLKout in response to the second enable signal out2. Finally, the period of the target clock signal CLKout is the sum of the duration of the counting process of the first counting module 10 and the duration of the counting process of the second counting module 20.
[0091] In some embodiments of this application, the clock signal generation circuit has a first operating mode and a second operating mode; when the clock signal generation circuit is in the first operating mode, the first counting adjustment unit 41 is configured to write a first counting adjustment value determined by the crystal oscillator in the first preset operating period, and the second counting adjustment unit 42 is configured to write a second counting adjustment value determined by the crystal oscillator in the first preset operating period; when the clock signal generation circuit is in the second operating mode, the first counting adjustment unit 41 is configured to write a first counting adjustment value determined by the crystal oscillator in the second preset operating period, where the second preset operating period is N times the first preset operating period, and N is an integer greater than 1.
[0092] For example, taking a first preset working period of 1 second and a second preset working period of 1024 seconds as an example, in the first working mode of the clock signal generation circuit, the first counting adjustment unit 41 can write a first counting adjustment value determined according to the ambient temperature and the preset crystal oscillator temperature curve every second, and the second counting adjustment unit 42 can write a second counting adjustment value determined according to the ambient temperature and the preset crystal oscillator temperature curve every second, thereby performing temperature compensation on the target clock signal CLKout every second, so as to ensure that the deviation of the target clock signal CLKout every second is within one cycle of the second input clock CLK2 (e.g., 0.025ns). In the second working mode of the clock signal generation circuit, the first counting adjustment unit 41 can write a first counting adjustment value every 1024 seconds according to the cumulative deviation of the target clock signal CLKout (accumulating the deviation per second), thereby ensuring that the deviation of the target clock signal CLKout within the 1024-second span is within one cycle of the first input clock CLK1 (e.g., 30.5176ns, i.e., the average deviation per second is 30.5176 / 1024 = 0.03ppm).
[0093] To better implement the clock signal generation circuit in the embodiments of this application, this application also provides a clock signal generation method based on the clock signal generation circuit, see below. Figure 7 , Figure 7 This paper illustrates a flowchart of a clock signal generation method according to an embodiment of the present application, wherein the clock signal generation method includes:
[0094] Step S701: Measure the ambient temperature of the crystal oscillator at least once within a preset period;
[0095] Specifically, the ambient temperature of the crystal oscillator can be obtained through a temperature sensor or a temperature measurement circuit. For example, the temperature sensor may include, but is not limited to, thermocouple sensors, thermistor sensors, resistance temperature detectors (RTDs), IC temperature sensors, etc.
[0096] As an example, the preset period can be 1 second, meaning that step S701 acquires the ambient temperature of the crystal oscillator once per second. As another example, the preset period can be 1024 seconds, meaning that step S701 acquires the ambient temperature of the crystal oscillator once per second within the preset period of 1024 seconds. It is understood that the above embodiments are only exemplary embodiments for acquiring ambient temperature, and this application can also acquire the ambient temperature of the crystal oscillator multiple times per second.
[0097] Step S702: Determine at least a second count adjustment value based on at least one ambient temperature of the crystal oscillator and a preset crystal oscillator temperature curve;
[0098] After measuring the ambient temperature, a second count adjustment value can be determined based on the ambient temperature and a preset crystal oscillator temperature curve. In some embodiments of this application, such as an embodiment that acquires the ambient temperature of the crystal oscillator once per second, the deviation per second of the target clock signal CLKout can be determined based on the ambient temperature of the crystal oscillator and a preset crystal oscillator temperature curve. Then, the second count adjustment value is calculated using the deviation per second of the target clock signal CLKout to perform temperature compensation per second on the target clock signal CLKout.
[0099] In some embodiments of this application, such as an embodiment in which the ambient temperature of the crystal oscillator is acquired once per second within a preset period of 1024 seconds, the cumulative deviation of the target clock signal CLKout can be determined based on the ambient temperature of the crystal oscillator per second during the 1024-second period and a preset crystal oscillator temperature curve. Then, the cumulative deviation of the target clock signal CLKout is used to calculate a second count adjustment value to perform temperature compensation on the target clock signal CLKout at 1024-second intervals.
[0100] Step S703: During the counting process of the first counting module 10 and the second counting module 20, the counting value of the second counting module 20 is adjusted according to the second counting adjustment value;
[0101] Once the second count adjustment value is obtained, the count value of the second count module 20 can be adjusted according to the second count adjustment value during the counting process of the first count module 10 and the second count module 20. For example, the initial count value of the second count module 20 can be changed according to the second count adjustment value. Another example is that the count value of the second count module 20 during the flipping process can be changed according to the second count adjustment value. Yet another example is that the second preset value of the second count module 20 can be changed according to the second count adjustment value. For details on how to adjust the count values of the first count module 10 and the second count module 20, please refer to the foregoing content, which will not be repeated here.
[0102] In this embodiment, the first counting module 10 is used to count the first input clock CLK1, and the second counting module 20 is used to count the second input clock CLK2. Since the frequency of the first input clock CLK1 is lower than the frequency of the second input clock CLK2, adjusting the count value of the second counting module 20 can achieve higher adjustment accuracy. Compared with the scheme of adjusting the counter count value corresponding to the 32.768kHz clock signal separately, this application can achieve higher adjustment accuracy and is conducive to obtaining a target clock signal CLKout with higher accuracy.
[0103] In some embodiments of this application, the frequency of the second input clock CLK2 is equal to the frequency of the first input clock CLK1, which is equal to a first ratio. This first ratio is equal to the default count value of the second counting module 20. For example, taking the frequency of the first input clock CLK1 as 32.768kHz and the frequency of the second input clock CLK2 as 40MHz, the second counting module 20 includes an 11-bit counter with an initial count value of 1100111011 (corresponding to the decimal number 827). When the count value of the 11-bit counter reaches 11111111111 (i.e., the second preset value is 2048), it outputs a second enable signal out2. In this case, the first ratio is 1221, and the default count value of the second counting module 20 is 2048-827=1221. Therefore, the first ratio is equal to the default count value of the second counting module 20.
[0104] In some embodiments of this application, the step of determining at least a second count adjustment value based on at least one ambient temperature of the crystal oscillator and a preset crystal oscillator temperature curve includes: determining a first count adjustment value and a second count adjustment value based on at least one ambient temperature of the crystal oscillator and a preset crystal oscillator temperature curve; the step of adjusting the count value of the second count module 20 based on the second count adjustment value during the counting process of the first count module 10 and the second count module 20 includes: adjusting the count value of the first count module 10 based on the first count adjustment value and adjusting the count value of the second count module 20 based on the second count adjustment value during the counting process of the first count module 10 and the second count module 20.
[0105] In other words, in some possible embodiments, the count values of the first counting module 10 and the second counting module 20 can be adjusted simultaneously. For example, when the deviation of the target clock signal CLKout is 1.5 periods of the first input clock CLK1, one count value of the first counting module 10 can be adjusted, while the count value of the second counting module 20 can be adjusted using 0.5 periods of the first input clock CLK1. Or, for another example, when the deviation of the target clock signal CLKout is 0.5 periods of the first input clock CLK1, the count value of the first counting module 10 can be left unchanged, while the count value of the second counting module 20 can be adjusted using 0.5 periods of the first input clock CLK1.
[0106] In some embodiments of this application, see Figure 8 , Figure 8 This paper illustrates a flowchart of an embodiment of the present application for determining a count adjustment value, wherein the steps of determining a first count adjustment value and a second count adjustment value based on at least one ambient temperature of the crystal oscillator and a preset crystal oscillator temperature curve include:
[0107] Step S801: Determine the clock deviation value based on the ambient temperature of the crystal oscillator at least once and the preset crystal oscillator temperature curve;
[0108] Step S802: Determine the first count adjustment value and compensation margin based on the clock deviation value and the period of the first input clock;
[0109] Step S803: Determine the second count adjustment value based on the compensation margin and the period of the second input clock.
[0110] For example, taking a first input clock CLK1 with a frequency of 32.768kHz and a second input clock CLK2 with a frequency of 40MHz as an example, the period of the first input clock CLK1 is 30.5176ns (30.5176ppm), and the period of the second input clock CLK2 is 0.025ns (0.025ppm). Assuming that the deviation of the second clock is 40ppm based on at least one ambient temperature of the crystal oscillator and a preset crystal oscillator temperature curve, the first count adjustment value and the compensation margin can be calculated according to the following formula:
[0111] △N1=40 / 30.5176=1...9.4824
[0112] In the above formula, 1 is the first count adjustment value, and 9.4824 is the remainder (i.e., compensation margin). Therefore, the second count adjustment value can be calculated as follows:
[0113] △N2=9.4824 / 0.025=379...0.0074
[0114] As can be seen, for a second clock deviation of 40ppm, after adjusting the count value of the first counting module 10 to 1 and the count value of the second counting module 20 to 379, the final second clock deviation is 0.0074ppm, thus ensuring the accuracy of the second clock.
[0115] This application also provides a chip that includes the clock signal generation circuit described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application has the clock signal generation circuit described in the above embodiments, it possesses all the beneficial effects of the clock signal generation circuit in the above embodiments, and will not be repeated here.
[0116] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, an electricity meter, water meter, gas meter, electronic watch, weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.
[0117] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A clock signal generation circuit, characterized in that, include: The first counting module is used to count the first input clock and output a first enable signal when the count reaches a first preset value. The second counting module is used to count the second input clock and output a second enable signal when the count reaches a second preset value. A clock output module, wherein the clock output module is configured to output a target clock signal according to the first enable signal or the second enable signal; A counting adjustment module, wherein the counting adjustment module is used to adjust at least the counting value of the second counting module; The frequency of the first input clock is less than the frequency of the second input clock.
2. The clock signal generation circuit as described in claim 1, characterized in that, The frequency of the second input clock is equal to the frequency of the first input clock by a first ratio, and the first ratio is equal to the default count value of the second counting module.
3. The clock signal generation circuit as described in claim 1, characterized in that, The second counting module starts counting the second input clock in response to the first enable signal, and the clock output module outputs the target clock signal in response to the second enable signal.
4. The clock signal generation circuit as described in claim 1, characterized in that, The counting adjustment module includes a first counting adjustment unit and a second counting adjustment unit; The first counting adjustment unit is configured to write a first counting adjustment value, and the second counting adjustment unit is configured to write a second counting adjustment value; The first count adjustment value and the second count adjustment value are determined based on the ambient temperature of the crystal oscillator within a preset period and a preset crystal oscillator temperature curve.
5. The clock signal generation circuit as described in claim 4, characterized in that, The first counting module includes a first counter, and the second counting module includes a second counter; The trigger terminal of the first counter is used to connect to the first input clock, and the load value input terminal of the first counter is connected to the first counting adjustment unit; The trigger terminal of the second counter is used to connect to the second input clock, and the load value input terminal of the second counter is connected to the second counting adjustment unit.
6. The clock signal generation circuit as described in claim 5, characterized in that, The output terminal of the first counter is connected to the load enable terminal of the second counter, and the output terminal of the second counter is connected to the input terminal of the clock output module.
7. The clock signal generation circuit as described in claim 4, characterized in that, The clock signal generation circuit has a first operating mode and a second operating mode; When the clock signal generation circuit is in the first working mode, the first counting adjustment unit is configured to write the first counting adjustment value determined by the crystal oscillator in the first preset working cycle, and the second counting adjustment unit is configured to write the second counting adjustment value determined by the crystal oscillator in the first preset working cycle. When the clock signal generation circuit is in the second working mode, the first counting adjustment unit is configured to write the first counting adjustment value determined by the crystal oscillator in the second preset working cycle; Wherein, the second preset working cycle is N times the first preset working cycle, where N is an integer greater than 1.
8. A method for generating a clock signal, characterized in that, include: Measure the ambient temperature of the crystal oscillator at least once within a preset period; Based on the ambient temperature of the crystal oscillator at least once and the preset crystal oscillator temperature curve, at least a second count adjustment value is determined; During the counting process of the first counting module and the second counting module, the counting value of the second counting module is adjusted according to the second counting adjustment value; The first counting module is used to count the first input clock, the second counting module is used to count the second input clock, and the frequency of the first input clock is less than the frequency of the second input clock.
9. The clock signal generation method as described in claim 8, characterized in that, The frequency of the second input clock is equal to the frequency of the first input clock by a first ratio, and the first ratio is equal to the default count value of the second counting module.
10. The clock signal generation method as described in claim 8, characterized in that, The step of determining at least the second count adjustment value based on the ambient temperature of the at least one crystal oscillator and a preset crystal oscillator temperature curve includes: Based on the ambient temperature of the at least one crystal oscillator and the preset crystal oscillator temperature curve, determine the first count adjustment value and the second count adjustment value; The step of adjusting the count value of the second counting module according to the second count adjustment value during the counting process of the first counting module and the second counting module includes: During the counting process of the first counting module and the second counting module, the counting value of the first counting module is adjusted according to the first counting adjustment value, and the counting value of the second counting module is adjusted according to the second counting adjustment value.
11. The clock signal generation method as described in claim 10, characterized in that, The step of determining the first count adjustment value and the second count adjustment value based on the ambient temperature of the at least one crystal oscillator and a preset crystal oscillator temperature curve includes: The clock deviation value is determined based on the ambient temperature of the crystal oscillator at least once and the preset crystal oscillator temperature curve; Based on the clock deviation value and the period of the first input clock, determine the first count adjustment value and the compensation margin; The second count adjustment value is determined based on the compensation margin and the period of the second input clock.
12. A chip, characterized in that, Includes the clock signal generation circuit as described in any one of claims 1 to 7.
13. An electronic device, characterized in that, Including the chip as described in claim 12.