Power consumption control circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a power consumption control circuit, a chip and electronic equipment, the circuit comprises a first storage circuit, a state identification circuit and a clock control circuit, the state identification circuit is connected to a transmission channel, and the first storage circuit is connected to the state identification circuit and the clock control circuit; the state identification circuit is used for identifying the state of the transmission channel in each clock cycle and storing the state in the first storage circuit, and the first storage circuit is used for storing the states of multiple clock cycles; the clock control circuit is used for controlling the clock frequency of the transmission channel according to the states in the first storage circuit. The power consumption control circuit is arranged for different transmission channels, and the clock frequency of each transmission channel is adjusted in a self-adaptive mode according to the states of the transmission channels in multiple time periods. Therefore, the power consumption generated by the clock of each transmission channel can be reduced as much as possible, and the power consumption of the whole semiconductor chip can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip technology, and in particular to a power consumption control circuit, chip, and electronic device. Background Technology

[0002] Semiconductor chips are a crucial component of various electronic devices, and their power consumption affects the battery life of these devices. Therefore, power consumption is an important factor to consider when designing semiconductor chips.

[0003] In existing technologies, Dynamic Voltage and Frequency Scaling (DVFS) technology can be used to reduce the power consumption of semiconductor chips. This involves simultaneously reducing both voltage and current when the circuit in the semiconductor chip does not need to operate at full load, thereby reducing both static and dynamic power consumption. When the circuit is not in operation, the voltage is reduced, at which point the clock is completely off, further reducing static power consumption.

[0004] However, the above solutions still suffer from the problem of high power consumption of semiconductor chips. Summary of the Invention

[0005] In view of the above problems, embodiments of this application are proposed to provide a power consumption control circuit that overcomes or at least partially solves the above problems, so as to reduce the power consumption of semiconductor chips.

[0006] Accordingly, embodiments of this application also provide a semiconductor chip and an electronic device to ensure the implementation and application of the above-mentioned power consumption control circuit.

[0007] To address the aforementioned problems, this application discloses a power consumption control circuit, comprising: The system comprises a first storage circuit, a state recognition circuit, and a clock control circuit. The state recognition circuit is connected to a transmission channel, and the first storage circuit is connected to both the state recognition circuit and the clock control circuit. The state recognition circuit is used to identify the state of the transmission channel in each clock cycle and store the state in the first storage circuit. The first storage circuit is used to store the state for multiple clock cycles. The clock control circuit is used to control the clock frequency of the transmission channel based on the multiple states in the first storage circuit.

[0008] Optionally, the state recognition circuit includes: an input counting circuit, an output counting circuit, and a state output circuit. The output terminals of the input counting circuit and the output terminals of the output counting circuit are respectively connected to the two input terminals of the state output circuit. The input counting circuit is used to count the amount of input data of the transmission channel in each clock cycle. The output counting circuit is used to count the amount of output data of the transmission channel in each clock cycle. The state output circuit is used to determine the state of the transmission channel within the clock cycle based on the amount of input data and the amount of output data.

[0009] Optionally, the status output circuit includes a subtraction circuit and a first comparison circuit. The output of the subtraction circuit is connected to one input of the first comparison circuit, and the other input of the first comparison circuit corresponds to a first threshold. The subtraction circuit is used to calculate the difference between the input data and the output data. The first comparison circuit is used to compare the difference with the first threshold to obtain the status of the transmission channel within the clock cycle.

[0010] Optionally, the clock control circuit includes a state counting circuit and a dynamic clock circuit. The input of the state counting circuit is connected to the first storage circuit, and the output of the state counting circuit is connected to the dynamic clock circuit. The state counting circuit is used to count the number of target values ​​in the first storage circuit to obtain the number of target states. The target values ​​indicate that the transmission channel is in a busy state. The dynamic clock circuit is used to generate a dynamic clock signal based on the number of target states. The clock frequency of the dynamic clock signal is related to the number of target states.

[0011] Optionally, the transmission channel includes a clock generation circuit. The dynamic clock circuit includes a clock generation circuit, a control signal generation circuit, and a frequency adjustment circuit. The output terminals of the clock generation circuit and the control signal generation circuit are respectively connected to the two input terminals of the frequency adjustment circuit. The clock generation circuit is used to generate a base clock signal with a base clock frequency. The control signal generation circuit is used to generate a first control signal based on the number of target states. The frequency adjustment circuit is used to adjust the clock frequency of the base clock signal according to the first control signal to obtain a dynamic clock signal.

[0012] Optionally, the control signal generation circuit includes: a second comparison circuit, wherein multiple input terminals of the second comparison circuit are respectively connected to the target state quantity and the second threshold; the second comparison circuit is used to compare the magnitude of the target state quantity and the second threshold to obtain a first control signal.

[0013] Optionally, the second comparison circuit includes at least two second comparison sub-circuits, with different second comparison circuits corresponding to different second thresholds.

[0014] Optionally, the frequency adjustment circuit includes: multiple frequency adjustment sub-circuits, each frequency adjustment sub-circuit being connected to a second comparator sub-circuit; the frequency adjustment sub-circuit is used to adjust the frequency of the basic clock signal by preset frequency modulation parameters to obtain a dynamic clock signal, and different frequency adjustment sub-circuits correspond to different preset frequency modulation parameters.

[0015] Optionally, the dynamic clock circuit further includes a frequency reduction control circuit connected to the state counting circuit, the control signal generation circuit, and the frequency adjustment circuit. The frequency reduction control circuit is used to control the currently running frequency adjustment sub-circuit to continue running for a target duration based on the target number of states when the first control signal indicates that the dynamic clock signal should be reduced in frequency. The target duration is related to the target number of states.

[0016] Optionally, the first storage circuit is a shift register, used to shift the state when a state is received for each clock cycle, so as to store the state in the most significant bit or the least significant bit.

[0017] Secondly, embodiments of this application also provide a semiconductor chip including multiple power control circuits as described above, each power control circuit being used to control the clock frequency of a transmission channel, and each transmission channel being used to transmit data between two routers.

[0018] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned semiconductor chip.

[0019] The embodiments of this application have the following advantages: This application incorporates power control circuits for different transmission channels, adaptively adjusting the clock frequency of each channel based on its state across multiple time periods. This minimizes the power consumption generated by the clock signal of each transmission channel, contributing to a significant reduction in the overall power consumption of the semiconductor chip. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating an application scenario according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a power consumption control circuit according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a state recognition circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a clock control circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of another clock control circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of a frequency reduction control circuit provided in an embodiment of this application; Figure 7This is a schematic diagram of the state switching of a dynamic clock signal provided in an embodiment of this application. Detailed Implementation

[0021] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Reference Figure 1 As shown, this application embodiment is used for power consumption control of semiconductor chips in electronic devices. The routing network in the semiconductor chip includes one or more routers, and each router is equipped with one or more transmission channels. Different transmission channels have different functions and may have different levels of congestion. Taking the AXI (Advanced Dextensible Interface) communication protocol as an example, the transmission channels may include: read address channel (AR-channel), read data channel (R-channel), write address channel (AW-channel), write data channel (W-channel), and write response channel (B-channel). The congestion level of the read data channel and the write data channel may be higher than that of the read address channel, the write address channel, and the write response channel.

[0023] Based on the above findings, this application embodiment performs power consumption control on a per-transmission-channel basis within the router, specifically targeting... Figure 1 Each transmission channel is equipped with a power control circuit to adaptively adjust the clock frequency of the transmission channel based on its state over multiple time periods. This minimizes the power consumption generated by the clock of each transmission channel, contributing to a significant reduction in the overall power consumption of the semiconductor chip.

[0024] The embodiments of this application can be applied to semiconductor chips with one or more transmission channels. One typical application scenario is a multi-core processor that communicates using the AMBA (Advanced Microcontroller Bus Architecture) protocol suite.

[0025] The embodiments of this application can be implemented using a state machine or the following circuit.

[0026] Figure 2This is a schematic diagram of a power consumption control circuit according to this application. Specifically, it may include: a first storage circuit, a state recognition circuit, and a clock control circuit. The state recognition circuit is connected to the transmission channel corresponding to the power consumption control circuit. The first storage circuit is connected to both the state recognition circuit and the clock control circuit. The state recognition circuit is used to identify the state of the transmission channel in each clock cycle and store the state in the first storage circuit. The first storage circuit is used to store the state of multiple clock cycles. The clock control circuit is used to control the clock frequency of the transmission channel according to the multiple states in the first storage circuit.

[0027] Specifically, the two input terminals of the state recognition circuit are connected to the input and output terminals of the transmission channel, respectively. The input terminal of the transmission channel receives data and the output terminal sends data out. Therefore, the state recognition circuit can count the amount of data received by the input terminal of the transmission channel in each clock cycle as the input data amount of the transmission channel in each clock cycle, and count the amount of data sent by the output terminal of the transmission channel in each clock cycle as the output data amount of the transmission channel in each clock cycle. Thus, for one clock cycle, the state of the transmission channel can be obtained by combining the input data amount and the output data amount of the transmission channel.

[0028] The input data volume can be understood as the in-degree, and the output data volume as the out-degree. Each input data entry increments the in-degree by 1, and each output data entry increments the out-degree by 1. The out-degree is less than or equal to the in-degree. When the out-degree is less than the in-degree, it indicates that data is stuck in the transmission channel, and the transmission channel is busy. When the out-degree and in-degree are the same, it indicates that no data is stuck, and the transmission channel is idle. Therefore, the state of the transmission channel in each clock cycle is based on the result of the in-degree and out-degree determination.

[0029] Therefore, the state identification circuit determines the state of the transmission channel based on the input and output data volumes to indicate the degree of congestion. Specifically, the degree of congestion is positively correlated with the difference between the input and output data volumes; that is, the larger the difference, the more severe the congestion, and vice versa. For example, a first threshold can be set, which is greater than 0. When the difference between the input and output data volumes is greater than or equal to the first threshold, the transmission channel is considered to be in a congested state; when the difference is less than the first threshold, the transmission channel is considered to be in an idle state.

[0030] The output of the state recognition circuit is connected to the input of the first storage circuit so that when the state of the transmission channel is recognized in each clock cycle, the state is written into the first storage circuit. Thus, after multiple clock cycles, the first storage circuit can store multiple states, each representing the state of the transmission circuit in one clock cycle. For example, a 1 can represent a busy state, and a 0 can represent an idle state.

[0031] The output of the first storage circuit is connected to the input of the clock control circuit. The clock control circuit can control the clock frequency based on the state of the transmission channel over multiple clock cycles. Specifically, the clock control circuit can increase the clock frequency to reduce congestion when the number of times the transmission channel is in a congested state is greater than or equal to a second threshold; decrease the clock frequency to reduce power consumption when the number of times the transmission channel is in an idle state is greater than or equal to the second threshold; and not adjust the clock frequency when both the number of times the transmission channel is in a congested state and the number of times it is in an idle state are less than the second threshold. The second threshold is greater than 0.

[0032] As can be seen from the above process, when the congestion levels of different transmission channels vary greatly, the embodiments of this application can reduce the power consumption of each transmission channel as much as possible while ensuring normal transmission of each transmission channel, thereby reducing the overall power consumption of the semiconductor chip.

[0033] In some possible implementations, Figure 3 This is a schematic diagram of a state recognition circuit provided in an embodiment of this application, referred to... Figure 3 As shown, the state recognition circuit includes an input counting circuit, an output counting circuit, and a state output circuit. The output terminals of the input counting circuit and the output counting circuit are respectively connected to the two input terminals of the state output circuit. The input counting circuit is used to count the amount of input data of the transmission channel in each clock cycle; the output counting circuit is used to count the amount of output data of the transmission channel in each clock cycle; and the state output circuit is used to determine the state of the transmission channel in each clock cycle based on the amount of input data and the amount of output data. The input terminals of the input counting circuit and the output counting circuit serve as the two input terminals of the state recognition circuit. The input terminal of the input counting circuit is connected to the input terminal of the transmission channel, and the input terminal of the output counting circuit is connected to the output terminal of the transmission channel. The output terminals of the input counting circuit and the output counting circuit are respectively connected to the two input terminals of the state output circuit, and the output terminal of the state output circuit serves as the output terminal of the state recognition circuit and is connected to the input terminal of the first storage circuit.

[0034] It is understandable that the above-mentioned input counting circuit and output counting circuit can be two counters.

[0035] The embodiments of this application can count the amount of data and accurately identify the status of the transmission channel based on the difference between the input data amount and the output data amount.

[0036] The status output circuit can determine the status of the transmission channel within a clock cycle based on the relationship between the input and output data amounts. For details, please refer to the foregoing description, which will not be repeated here. In one possible implementation, the status output circuit includes: a subtraction circuit and a first comparison circuit. The output of the subtraction circuit is connected to one input of the first comparison circuit, and the other input of the first comparison circuit corresponds to a first threshold. The subtraction circuit is used to calculate the difference between the input and output data amounts. The first comparison circuit is used to compare the difference with the first threshold to obtain the status of the transmission channel within a clock cycle. In this circuit, the two input terminals of the subtraction circuit serve as the two input terminals of the state output circuit, and are respectively connected to the output terminals of the input counting circuit and the output counting circuit. The output terminal of the subtraction circuit is connected to one input terminal of the first comparison circuit, and the output terminal of the first comparison circuit serves as the output terminal of the state output circuit, and is connected to the input terminal of the first storage circuit.

[0037] It is understandable that the above subtraction circuit can be a subtractor, the first comparison circuit can be a comparator, and the state of the transmission channel in one clock cycle can be represented by a binary bit. For example, it can be represented by 1 or 0, where 1 indicates that the transmission channel is in a busy state, and 0 indicates that the transmission channel is in an idle state. Of course, the specific mapping relationship between the state and the binary bit can be flexibly set and is not restricted.

[0038] The state of the aforementioned transmission channel is stored in a first storage circuit over multiple clock cycles. In some embodiments, the first storage circuit is a shift register, used to shift the state each time a state is received in a clock cycle, so as to store the state in the most significant bit or the least significant bit. The shift register can be N bits, where N is the number of bits in the shift register and the maximum number of states it can store. Configurable shift registers can also be used, allowing for flexible software configuration of the bit size and other parameters. For example, a 16-bit shift register can be selected to store the states of the transmission channel over a maximum of 16 clock cycles. The initial value of the shift register is set to the idle state. When 1 represents the busy state and 0 represents the idle state, the shift register initially stores 0000000000000000. Upon receiving consecutive states 1, 0, 1, and 1, the shift register shifts right by four bits, resulting in 11010000000000000.

[0039] The embodiments of this application can implement state recording using a simple and commonly used shift register, reducing circuit complexity and development costs.

[0040] The clock control circuit implements clock control based on multiple states in the aforementioned shift register. In one possible implementation, the clock control circuit includes: a state counting circuit and a dynamic clock circuit. The input of the state counting circuit is connected to a first storage circuit, and the output of the state counting circuit is connected to the dynamic clock circuit. The state counting circuit is used to count the number of target values ​​in the first storage circuit to obtain the number of target states, and the target values ​​indicate that the transmission channel is in a busy state. The dynamic clock circuit is used to generate a dynamic clock signal based on the number of target states, and the clock frequency of the dynamic clock signal is related to the number of target states. The input terminal of the state counting circuit serves as the input terminal of the clock control circuit and is connected to the output terminal of the first storage circuit. The output terminal of the state counting circuit is connected to the input terminal of the dynamic clock circuit, and the output terminal of the dynamic clock circuit serves as the output terminal of the power consumption control circuit. The output terminal of the power consumption control circuit is connected to the clock input terminal of the transmission channel, and the power consumption output circuit can output a dynamic clock signal to control the data transmission process of the transmission channel.

[0041] Understandably, the state counting circuit can be a counter used to count the number of target values ​​in the binary sequence stored in the first storage circuit. For example, if the binary sequence is 1101000000000000, where 1 indicates that the transmission channel is busy, then the counted number of target states is 3.

[0042] In some possible implementations, the state counting circuit can be an EMA (Exponential Moving Average) circuit, which uses an exponential moving average of the number of target values ​​in the first storage circuit as the target number of states. This avoids frequent clock frequency updates when the transmission channel experiences sudden busy periods, thus helping to improve clock frequency stability. Specifically, when performing the exponential moving average, the closer the bit is to the current time, i.e., the higher bit in the register circuit, the higher its weight should be.

[0043] A dynamic clock circuit can generate dynamic clock signals with different frequencies based on the number of target states. The clock frequency of the dynamic clock signal can be positively correlated with the number of target states. When there are more target states, it means more busy times, so the clock frequency of the dynamic clock signal is higher; when there are fewer target states, it means fewer busy times, so the clock frequency of the dynamic clock signal is lower.

[0044] As can be seen, the embodiments of this application can dynamically adjust the dynamic clock signal according to the number of target states in the first storage circuit. The dynamic clock signal is the working signal of the transmission channel, used to control the operating frequency of the transmission channel. In this way, power consumption control of the transmission channel can be performed more accurately.

[0045] In some possible implementations, the transmission channel corresponds to a clock generation circuit. The dynamic clock circuit includes a control signal generation circuit and a frequency adjustment circuit. The output terminals of the clock generation circuit and the control signal generation circuit are respectively connected to the input terminal of the frequency adjustment circuit. The clock generation circuit is used to generate a base clock signal with a base clock frequency. The control signal generation circuit is used to generate a first control signal according to the number of target states. The frequency adjustment circuit is used to adjust the clock frequency of the base clock signal according to the first control signal to obtain a dynamic clock signal. The input terminal of the control signal generation circuit serves as the input terminal of the dynamic clock circuit and is connected to the output terminal of the state counting circuit. The output terminal of the frequency adjustment circuit serves as the output terminal of the dynamic clock circuit, used to output the dynamic clock signal.

[0046] The base clock frequency can be set according to actual needs. The clock generation circuit can be a clock oscillator used to generate the base clock signal.

[0047] The aforementioned first control signal is used to indicate the adjustment strategy for the base clock signal. Different target state quantities correspond to different first control signals, and different first control signals correspond to different clock adjustment strategies. One or more value ranges can be set for the number of target states, and each value range corresponds to a first control signal. For example, when the number of target states is within the value range [1,3], the first control signal is 1000, and the clock frequency of the dynamic clock signal (which can be called the dynamic clock frequency) is 1 / 8 of the base clock frequency; when the number of target states is within the value range [4,7], the first control signal is 0100, and the clock frequency of the dynamic clock signal is 1 / 4 of the base clock frequency; when the number of target states is within the value range [8,11], the first control signal is 0010, and the clock frequency of the dynamic clock signal is 1 / 2 of the base clock frequency; when the number of target states is within the value range [12,15], the first control signal is 0001, and the clock frequency of the dynamic clock signal is 1 times the base clock frequency, that is, the transmission channel is running at full load or performing turbo boost operation.

[0048] It is understandable that the number of bits in the first control signal is the same as the number of value ranges for the target state.

[0049] The embodiments of this application can reuse existing clock generation circuits to adjust their clock frequency to achieve dynamic clock signals, thereby minimizing circuit complexity.

[0050] In some possible implementations, the control signal generation circuit includes: a second comparison circuit, wherein multiple input terminals of the second comparison circuit are respectively connected to the target state quantity and the second threshold; the second comparison circuit is used to compare the magnitude of the target state quantity and the second threshold to obtain a first control signal.

[0051] In this circuit, one input terminal of the second comparator circuit serves as the input terminal of the control signal generation circuit and is connected to the output terminal of the state counting circuit. One or more output terminals of the second comparator circuit serve as the output terminals of the control signal generation circuit and are connected to the input terminal of the frequency adjustment circuit. The aforementioned second comparison circuit can have multiple input terminals, one of which is used to receive the target state quantity, and at least one other input terminal of the second comparison circuit is used to receive one or more second thresholds, with each second threshold corresponding to one input terminal. In this way, the generation of the first control signal can be achieved through the comparison circuit, resulting in low complexity.

[0052] In some possible implementations, the second comparison circuit includes at least two second comparison sub-circuits, with different second comparison circuits corresponding to different second thresholds. The second comparator circuit can be a comparator. Multiple second comparator circuits can generate more diverse and richer first control signals, which helps to achieve more precise frequency adjustment and further reduce power consumption.

[0053] Specifically, each second comparator circuit has three input terminals. One input receives the target state count, and the other two input terminals correspond to two second thresholds, which together form a value range. Therefore, the second comparator circuit can be used to determine whether the target state count falls within this value range.

[0054] Corresponding to the second comparator circuit mentioned above, multiple frequency adjustment sub-circuits can be provided. Specifically, the frequency adjustment circuit includes: multiple frequency adjustment sub-circuits, each frequency adjustment sub-circuit connected to a second comparator circuit; the frequency adjustment sub-circuit is used to adjust the frequency of the basic clock signal through preset frequency modulation parameters to obtain a dynamic clock signal, and different frequency adjustment sub-circuits correspond to different preset frequency modulation parameters.

[0055] The first control signal is used to control whether the corresponding frequency adjustment sub-circuit operates. Upon receiving the first control signal, the frequency adjustment sub-circuit determines whether it is at the target level. When the first control signal is at the target level, the frequency adjustment sub-circuit operates to adjust the frequency according to the preset frequency modulation parameters corresponding to that sub-circuit; when the first control signal is not at the target level, the frequency adjustment sub-circuit does not operate. It can be understood that at any given time, each of the second comparison sub-circuits in the second comparison circuit outputs only one first control signal at the target level, thus enabling one of the frequency adjustment sub-circuits to operate.

[0056] Reference Figure 4 As shown, four second comparator sub-circuits A1 to A4 can be set up. The output terminals of the second comparator sub-circuits A1, A2, A3 and A4 are respectively connected to the input terminals of the frequency adjustment sub-circuits B1, B2, B3 and B4 to output the first control signal to the frequency adjustment sub-circuit.

[0057] For example, when the number of target states is within the range [1,3], the first control signal output by the second comparator circuit A1 is 1, and the first control signals output by the second comparator circuits A2, A3, and A4 are 0. At this time, the frequency adjustment circuit B1 operates to adjust the base clock signal according to the preset frequency adjustment parameter 1 / 8 to obtain the dynamic clock signal. The frequency adjustment circuits B2, B3, and B4 do not operate.

[0058] When the number of target states is within the range [4,7], the first control signal output by the second comparator circuit A2 is 1, and the first control signals output by the second comparator circuits A1, A3, and A4 are 0. At this time, the frequency adjustment circuit B2 operates to adjust the base clock signal according to the preset frequency adjustment parameter 1 / 4 to obtain the dynamic clock signal. The frequency adjustment circuits B1, B3, and B4 do not operate.

[0059] When the number of target states is within the range [8, 11], the first control signal output by the second comparator circuit A3 is 1, and the first control signals output by the second comparator circuits A1, A2, and A4 are 0. At this time, the frequency adjustment circuit B3 operates to adjust the basic clock signal according to the preset frequency adjustment parameter 1 / 2 to obtain the dynamic clock signal. The frequency adjustment circuits B1, B2, and B4 do not operate.

[0060] When the number of target states is within the range [12, 15], the first control signal output by the second comparator circuit A4 is 1, and the first control signals output by the second comparator circuits A1, A2, and A3 are 0. At this time, the frequency adjustment circuit B4 operates to adjust the base clock signal according to the preset frequency adjustment parameter 1 to obtain the dynamic clock signal; that is, it does not adjust the base clock signal. The frequency adjustment circuits B1, B2, and B3 do not operate.

[0061] In some possible implementations, refer to Figure 5 As shown, the dynamic clock circuit also includes a frequency reduction control circuit, which is connected to the state counting circuit, the control signal generation circuit, and the frequency adjustment circuit. The frequency reduction control circuit is used to control the currently running frequency adjustment sub-circuit to continue running for a target duration based on the target number of states when the first control signal indicates that the dynamic clock signal should be reduced in frequency. The target duration is related to the target number of states. Specifically, a first input terminal of the frequency reduction control circuit is connected to the output terminal of the state counting circuit to obtain the target number of states. One or more second input terminals of the frequency reduction control circuit are respectively connected to one or more output terminals of the control signal generation circuit, and each second input terminal is used to receive a first control signal. One or more output terminals of the frequency reduction control circuit are connected to one or more input terminals of the frequency adjustment circuit.

[0062] When the control signal generation circuit includes multiple second comparator sub-circuits and the frequency adjustment circuit includes multiple frequency adjustment sub-circuits, each second input terminal of the frequency reduction control circuit is connected to the output terminal of a second comparator sub-circuit, and each output terminal of the frequency reduction control circuit is connected to the input terminal of a frequency adjustment sub-circuit.

[0063] The aforementioned frequency reduction control circuit can record a set of first control signals corresponding to two adjacent time points to determine whether to reduce the frequency. When reducing the frequency, the first control signal before frequency reduction is output as the second control signal to the frequency adjustment circuit; when not reducing the frequency, the first control signal currently output by the control signal generation circuit is output as the second control signal to the frequency adjustment circuit.

[0064] The aforementioned frequency reduction refers to the reduction of the clock frequency of the dynamic clock signal from the first clock frequency to the second clock frequency. Whether to reduce the frequency can be determined based on the preset frequency modulation parameter corresponding to the first control signal at the target level at two adjacent time points. If the preset frequency modulation parameter corresponding to the first control signal at the target level at the previous time point is greater than the preset frequency modulation parameter corresponding to the first control signal at the target level at the current time point, frequency reduction is determined; otherwise, no frequency reduction is determined.

[0065] For example, if the four first control signals at the previous time point were 0010, and the preset frequency modulation parameter corresponding to the first control signal at the target level was 1 / 2, and the four first control signals at the current time point were 0100, and the preset frequency modulation parameter corresponding to the first control signal at the target level was 1 / 4, then the clock frequency of the dynamic clock signal is reduced from 1 / 2 of the base clock frequency to 1 / 4 of the base clock frequency. At this time, the frequency reduction control circuit can output the second control signal 0001 throughout the target duration, so that the frequency adjustment circuit continues to adjust the clock frequency of the dynamic clock signal to 1 / 2, that is... Figure 5 The frequency adjustment sub-circuit B3 shown continues to operate.

[0066] The number of time periods included in the aforementioned target duration can be the same as the number of target states at the current time point. In this way, the hold-up duration before frequency reduction can be dynamically implemented, so that when the congestion level is high, a longer period can be maintained to reduce the clock frequency as much as possible after the congestion level is reduced.

[0067] In some possible implementations, refer to Figure 6 As shown, the frequency reduction control circuit described above may include a second storage circuit, a third comparison circuit, an expansion circuit, and a selection circuit.

[0068] The input of the second storage circuit is connected to the output of the control signal generation circuit to store the first control signal from the previous time point. This connection can be direct or indirect. Figure 1 An example is given of indirect connection via a switching circuit.

[0069] The two inputs of the third comparator circuit are connected to the output of the second storage circuit and the output of the control signal generation circuit, respectively, and are used to generate a frequency reduction indication signal based on the first control signal at the previous time point and the first control signal at the current time point.

[0070] The output of the third comparator circuit is connected to one input of the expansion circuit, and the other input of the expansion circuit is connected to the output of the state counting circuit, which is used to extend the frequency reduction indication signal to the target duration according to the target number of states.

[0071] The two data input terminals of the selection circuit are connected to the output terminals of the control signal generation circuit and the second storage circuit. When the frequency reduction indication signal output by the expansion circuit indicates frequency reduction, the first control signal at the previous time point is output as the second control signal. When the frequency reduction indication signal output by the expansion circuit indicates no frequency reduction, the first control signal at the current time point is output as the second control signal.

[0072] A switching circuit is located on the line connecting the output of the control signal generation circuit and the input of the second storage circuit. One input of the switching circuit is connected to the output of the expansion circuit. When the frequency reduction indicator signal output by the expansion circuit indicates frequency reduction, the switching circuit is open to keep the first control signal at the previous time point in the second storage circuit unchanged within the target duration. When the frequency reduction indicator signal output by the expansion circuit indicates no frequency reduction, the switching circuit is closed, and the first control signal at the previous time point in the second storage circuit changes over time.

[0073] Figure 7 This is a schematic diagram illustrating the state switching of a dynamic clock signal according to an embodiment of this application. (Refer to...) Figure 7 As shown, the dynamic clock signal can include five states: off, 1 / 8 of the base clock frequency, 1 / 4 of the base clock frequency, 1 / 2 of the base clock frequency, and the base clock frequency. Any two states can be switched between each other. Figure 7Only some of the switching relationships are shown: switching between the off state and 1 / 8 of the base clock frequency, switching between 1 / 8 of the base clock frequency and 1 / 4 of the base clock frequency, switching between 1 / 4 of the base clock frequency and 1 / 2 of the base clock frequency, switching between 1 / 2 of the base clock frequency and the base clock frequency, switching between the off state and 1 / 4 of the base clock frequency, switching between the off state and 1 / 2 of the base clock frequency, and switching between the off state and the base clock frequency.

[0074] In some possible implementations, the third comparator circuit can also be controlled to stop operating during frequency reduction to further reduce power consumption.

[0075] In some possible implementations, during the aforementioned holding process, the clock generation circuit can be turned on or off based on the target bit in the first storage circuit. The target bit is typically the most significant bit or the least significant bit. For example, if the target bit is 0, the clock generation circuit is turned off using a clock gating circuit to stop generating the basic clock signal; if the target bit is 1, the clock generation circuit is controlled to continue generating the basic clock signal. In this case, the aforementioned number of target states is the number of target values ​​in the first storage circuit excluding the target bit. For example, when the binary sequence stored in the first storage circuit is 1101000000000000, the most significant bit is the target bit, and thus the number of target states is 2; when the binary sequence stored in the first storage circuit is 01010000000000000, the most significant bit is the target bit, and thus the number of target states is still 2.

[0076] It is understandable that the smaller the number of target states, the lower the clock frequency. Adjusting the clock frequency can effectively reduce power consumption, while turning off the clock generation circuit can save power consumption to the greatest extent.

[0077] In one possible implementation, the outputs of the power consumption control circuit and the clock generation circuit of the transmission channel can be connected to the transmission channel via a configurable switch circuit. This configurable switch is flexibly configured to output either the dynamic clock signal from the power consumption control circuit to the transmission channel, or the base clock signal from the clock generation circuit to the transmission channel. This achieves flexible clock control.

[0078] Of course, when selecting the base clock signal output by the aforementioned clock generation circuit, the power consumption control circuit can be stopped to further reduce power consumption.

[0079] This application also provides a semiconductor chip including multiple power control circuits, each power control circuit being used to control the clock frequency of a transmission channel, and each transmission channel being used to transmit data between two routers.

[0080] This application also provides an electronic device, including the above-described semiconductor chip.

[0081] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0082] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0084] These computer program instructions may also be stored in a computer-understandable memory that can direct a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-understandable memory produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0087] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0088] The above provides a detailed description of a power consumption control circuit and device, an electronic device, and a storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power consumption control circuit, characterized in that, include: The system comprises a first storage circuit, a state recognition circuit, and a clock control circuit, wherein the state recognition circuit is connected to a transmission channel, and the first storage circuit is connected to both the state recognition circuit and the clock control circuit. The state recognition circuit is used to identify the state of the transmission channel in each clock cycle and store the state in the first storage circuit, which is used to store the state of multiple clock cycles. The clock control circuit is used to control the clock frequency of the transmission channel according to the multiple states in the first storage circuit.

2. The power consumption control circuit according to claim 1, characterized in that, The state recognition circuit includes an input counting circuit, an output counting circuit, and a state output circuit, wherein the output terminal of the input counting circuit and the output terminal of the output counting circuit are respectively connected to the two input terminals of the state output circuit. The input counting circuit is used to count the amount of input data into the transmission channel in each clock cycle; The output counting circuit is used to count the amount of output data of the transmission channel in each clock cycle; The status output circuit is used to determine the status of the transmission channel within the clock cycle based on the amount of input data and the amount of output data.

3. The power consumption control circuit according to claim 2, characterized in that, The state output circuit includes a subtraction circuit and a first comparison circuit. The output terminal of the subtraction circuit is connected to one input terminal of the first comparison circuit, and the other input terminal of the first comparison circuit corresponds to a first threshold. The subtraction circuit is used to calculate the difference between the input data amount and the output data amount; The first comparison circuit is used to compare the difference with the first threshold to obtain the state of the transmission channel within the clock cycle.

4. The power consumption control circuit according to any one of claims 1 to 3, characterized in that, The clock control circuit includes a state counting circuit and a dynamic clock circuit. The input terminal of the state counting circuit is connected to the first storage circuit, and the output terminal of the state counting circuit is connected to the dynamic clock circuit. The state counting circuit is used to count the number of target values ​​in the first storage circuit to obtain the number of target states. The target value indicates that the transmission channel is in a busy state. The dynamic clock circuit is used to generate a dynamic clock signal based on the number of target states, and the clock frequency of the dynamic clock signal is related to the number of target states.

5. The power consumption control circuit according to claim 4, characterized in that, The transmission channel is equipped with a clock generation circuit. The dynamic clock circuit includes a clock generation circuit, a control signal generation circuit, and a frequency adjustment circuit. The output terminal of the clock generation circuit and the output terminal of the control signal generation circuit are respectively connected to the two input terminals of the frequency adjustment circuit. The clock generation circuit is used to generate a base clock signal with a base clock frequency. The control signal generation circuit is used to generate a first control signal based on the number of target states; The frequency adjustment circuit is used to adjust the clock frequency of the base clock signal according to the first control signal to obtain a dynamic clock signal.

6. The power consumption control circuit according to claim 5, characterized in that, The control signal generation circuit includes: a second comparison circuit, wherein multiple input terminals of the second comparison circuit are respectively connected to the target state number and the second threshold; The second comparison circuit is used to compare the number of target states with the magnitude of the second threshold to obtain the first control signal.

7. The power consumption control circuit according to claim 6, characterized in that, The second comparison circuit includes at least two second comparison sub-circuits, with different second comparison circuits corresponding to different second thresholds.

8. The power consumption control circuit according to claim 7, characterized in that, The frequency adjustment circuit includes: a plurality of frequency adjustment sub-circuits, each of the frequency adjustment sub-circuits being connected to a second comparator sub-circuit; The frequency adjustment sub-circuit is used to adjust the frequency of the basic clock signal by a preset frequency modulation parameter to obtain a dynamic clock signal. Different frequency adjustment sub-circuits correspond to different preset frequency modulation parameters.

9. The power consumption control circuit according to claim 8, characterized in that, The dynamic clock circuit further includes a frequency reduction control circuit connected to the state counting circuit, the control signal generation circuit, and the frequency adjustment circuit. The frequency reduction control circuit is used to control the currently running frequency adjustment sub-circuit to continue running for a target duration based on the target number of states when the first control signal instructs the dynamic clock signal to reduce its frequency. The target duration is related to the target number of states.

10. The power consumption control circuit according to any one of claims 1 to 3, characterized in that, The first storage circuit is a shift register, used to shift the state each time a state of one clock cycle is received, so as to store the state in the most significant bit or the least significant bit.

11. A semiconductor chip, characterized in that, It includes multiple power control circuits as described in any one of claims 1 to 10, each power control circuit being used to control the clock frequency of a transmission channel, each transmission channel being used to transmit data between two routers.

12. An electronic device, characterized in that, Includes the semiconductor chip as described in claim 11.

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