Storage device and method for operating storage device

Abstract

A memory device and a method for operating the memory device are disclosed. A storage device according to some example embodiments may include a non-volatile memory device including a plurality of memory cells configured to store user data and metadata; and a storage controller including a plurality of cores, the storage controller configured to issue metadata to one of the plurality of memory cells based on whether each of a plurality of paths corresponding to the plurality of cores is in a busy state.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0160244, filed on November 12, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Some exemplary embodiments of the present invention relate to storage devices and methods for operating storage devices. Background Technology

[0003] Non-volatile memory devices are memory devices that retain stored data even when the power supply is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0004] Among them, flash memory devices store a set of address mapping information in memory blocks for operations such as reading or writing data. When storing data, metadata representing the address mapping information of the data can be stored in the flash memory.

[0005] Meanwhile, the number of NAND dies included in high-capacity SSDs (Solid State Drives) has been increasing recently, leading to issues such as increased buffering and longer channel occupancy times when storing metadata. However, currently, metadata is stored sequentially without scheduling, which can degrade and / or reduce SSD performance. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide a storage device and a method for operating the storage device with improved performance by setting the storage order of metadata.

[0007] According to some exemplary embodiments of the present invention, a storage device may include: a non-volatile memory device including a plurality of memory cells configured to store user data and metadata; and a storage controller including a plurality of cores, the storage controller being configured to issue metadata to one of the plurality of memory cells based on whether each of a plurality of paths corresponding to each of the plurality of cores is busy.

[0008] A storage device according to some example embodiments may include: a non-volatile memory device including a plurality of memory cells configured to store user data and metadata; and a storage controller configured to issue metadata to a plurality of first memory cells among the plurality of memory cells based on whether each of the plurality of memory cells is busy.

[0009] A method of operating a storage device according to some example embodiments may include: constructing metadata based on user data; determining the location where the metadata will be stored based on whether each of a plurality of paths corresponding to each of a plurality of cores included in a storage controller is busy, whether each of a plurality of channels connected to each of the plurality of cores is busy, and whether each of a plurality of memory cells of a non-volatile memory device is busy; issuing the metadata to the location; and updating the location of the metadata.

[0010] According to some example embodiments, a storage system may include a host and a storage device. The storage device may include: a non-volatile memory device including a plurality of memory cells configured to store user data and metadata received from the host; and a storage controller including a plurality of cores. The storage controller may be configured to issue metadata to one of the plurality of memory cells based on whether each of a plurality of paths corresponding to each of the plurality of cores is busy. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a storage system according to some example embodiments.

[0012] Figure 2 This is an exemplary block diagram illustrating the software layer of a storage system according to some example embodiments.

[0013] Figure 3 This is a block diagram illustrating a storage device according to some example embodiments.

[0014] Figure 4 This is a block diagram illustrating a storage device according to some example embodiments.

[0015] Figure 5 This is a block diagram illustrating a storage controller according to some example embodiments.

[0016] Figure 6 This is a block diagram illustrating a non-volatile memory device according to some example embodiments.

[0017] Figure 7 This is an exemplary circuit diagram illustrating one of a plurality of memory blocks included in a memory cell array according to some example embodiments.

[0018] Figure 8 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0019] Figure 9 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0020] Figure 10 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0021] Figure 11 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0022] Figure 12 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0023] Figure 13 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0024] Figure 14 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0025] Figure 15 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0026] Figure 16 This is a flowchart illustrating the operation of a storage device according to some example embodiments.

[0027] Figure 17 This is an exemplary block diagram illustrating a mobile system employing a storage device according to some example embodiments.

[0028] Figure 18 This is an exemplary block diagram of a computing device that applies a storage device according to some example embodiments.

[0029] Figure 19 This is a block diagram illustrating, by way of example, a system employing a storage device according to some example embodiments.

[0030] Figure 20 This is a block diagram illustrating, by way of example, a system employing a storage device according to some example embodiments. Detailed Implementation

[0031] In the following detailed description, only a few exemplary embodiments of the inventive concept have been shown and described by way of illustration only. As those skilled in the art will recognize, the described exemplary embodiments can be modified in various ways without departing from the spirit or scope of the inventive concept.

[0032] Therefore, the accompanying drawings and descriptions are intended to be illustrative rather than restrictive. Throughout the disclosure, the same reference numerals denote the same elements. In the flowcharts described with reference to the accompanying drawings, the order of operations may be changed, operations may be combined, operations may be divided, and some operations may not be performed.

[0033] Furthermore, unless an explicit expression such as “a,” “one,” or “single” is used, a statement written in the singular form may be understood as either singular or plural. Terms including ordinal numbers (such as first and second) are used to describe various constituent elements, but the constituent elements are not limited by the terms. These terms are only used to distinguish one constituent element from others.

[0034] In the following sections, some exemplary embodiments of the inventive concept will be described in more detail by way of examples. These exemplary embodiments are for illustrative purposes only, and the scope of protection of the inventive concept is not limited to the exemplary embodiments.

[0035] Figure 1 This is a block diagram illustrating a storage system according to some example embodiments.

[0036] Reference Figure 1 The storage system 10 may include a host 100 and a storage device 200. The host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory for temporarily storing data DATA_h that will be transferred or sent to the storage device 200 or data DATA_h transferred or sent from the storage device 200.

[0037] Storage device 200 may include storage controller 210 and non-volatile memory device (NVM) 220. Each of storage controller 210 and non-volatile memory device 220 may be provided as a different chip, a different package, and / or a different module, in which case storage controller 210 and non-volatile memory device 220 may be electrically connected.

[0038] Optionally, in some exemplary embodiments, the memory controller 210 and the non-volatile memory device 220 may be mounted on a package (such as a package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle-packaged die, wafer-type die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stack package (WSP), etc.) and may be provided as a non-volatile memory system.

[0039] The storage controller 210 can receive a request REQ, an address ADDR_log, and data DATA_h from the host 100, and control the non-volatile memory device 220 in response to the received signals. For example, the storage controller 210 can transmit or send a command CMD and an address ADDR to the non-volatile memory device 220 to write data DATA to the non-volatile memory device 220 or to read data DATA stored in the non-volatile memory device 220.

[0040] A request REQ from host 100 may include a read or write request for data. According to some example embodiments, a request REQ may include a sequential write request, a discard request, etc., but the example embodiments are not necessarily limited to this.

[0041] The address ADDR_log received from host 100 can be, for example, a logical address, and the address ADDR transmitted or sent to non-volatile memory device 220 can be a physical address of non-volatile memory device 220. A logical address can represent location information of a data unit defined or managed by host 100. A physical address can represent location information of a data unit defined according to the operating characteristics of non-volatile memory device 220.

[0042] The non-volatile memory device 220 can write data DATA received from the memory controller 210 and / or transmit or send stored data DATA to the memory controller 210 under the control of the memory controller 210. In some example embodiments, the non-volatile memory device 220 may include NAND flash memory, but the example embodiments are not limited to this, and the non-volatile memory device 220 may also include non-volatile memory elements with a three-dimensional structure (such as NAND flash memory, PRAM, ReRAM, MRAM, FRAM, etc.).

[0043] The non-volatile memory device 220 may include a user region 221 and a metadata region 222. The user region 221 may correspond to the region storing user data UD, and the metadata region 222 may correspond to the region storing metadata MD.

[0044] User data UD may include data (such as program code, files, etc.) used or generated in a software layer (such as host 100). Metadata MD may include structured information about user data UD stored in user area 221. In some example embodiments, metadata MD may include an address mapping table that includes multiple sub-address mapping tables, which, according to some example embodiments, are mapping information between logical addresses and physical addresses as described above. In some example embodiments, data DATA transferred between storage controller 210 and non-volatile memory device 220 may include user data UD and metadata MD.

[0045] In some example embodiments, the non-volatile memory device 220 may program the user data UD in the user region 221 based on multi-level cell, three-level cell, and / or four-level cell programming methods. In some example embodiments, the non-volatile memory device 220 may program the metadata MD into the meta region 222 based on a single-level cell programming method to increase the reliability of the data stored in the meta region 222, but the example embodiments are not limited thereto.

[0046] Figure 2 This is an exemplary block diagram illustrating the software layer of a storage system according to some example embodiments.

[0047] Reference Figure 1 and Figure 2 The software layer of the storage system 10 may include application 101, file system 102 and flash conversion layer 211.

[0048] Application 101 may represent various applications running on host 100. For example, application 101 may include an operating system, a document editor, a web browser, a video player, and / or a game program, but the example embodiments are not limited thereto.

[0049] The file system 102 can organize the files and / or data used by the application 101 when storing the files and / or data used by the application 101 in the non-volatile memory device 220.

[0050] For example, file system 102 can provide the logical address ADDR_log of a file or data to storage device 200, and file system 102 can have various forms depending on the operating system of host 100. File system 102 can define data in units of sector or logical block addresses.

[0051] In some example embodiments, application 101 and / or file system 102 may be driven by host 100, and application 101 and / or file system 102 may be loaded into host memory 120.

[0052] The flash translation layer (FTL) 211 provides an interface between the host 100 and the non-volatile memory device 220, enabling the non-volatile memory device 220 to be used effectively.

[0053] According to some example embodiments, since the non-volatile memory device 220 can write and read data in units of pages, while the file system 102 manages data and / or files in units of sector or logical block addresses as described above in some example embodiments, the FTL 211 can receive the logical address ADDR_log and translate the logical address ADDR_log into a physical address ADDR that can be used in the non-volatile memory device 220. The FTL 211 can manage these address mapping operations through the address mapping table included in the metadata MD described above.

[0054] Figure 3 This is a block diagram illustrating a storage device according to some example embodiments.

[0055] Reference Figure 3 The storage device 200 may include a non-volatile memory device 220 and a storage controller 210.

[0056] Storage device 200 may support multiple channels CH1 to CHm (where m is an integer greater than 1), and non-volatile memory device 220 and storage controller 210 may be connected via multiple channels CH1 to CHm. For example, storage device 200 may be implemented as a storage device such as a solid-state drive (SSD).

[0057] The non-volatile memory device 220 may include a plurality of non-volatile memory devices NVM11 to NVMmn (where n is an integer greater than 1). Each of the non-volatile memory devices NVM11 to NVMmn can be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n can be connected to a first channel CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n can be connected to a second channel CH2 via paths W21 to W2n.

[0058] In some example embodiments, each of the non-volatile memory devices NVM11 to NVMmn may be implemented as an arbitrary memory cell operable according to various commands from the memory controller 210. For example, each of the non-volatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, but the example embodiments are not limited thereto.

[0059] The storage controller 210 can transmit or send and receive signals with the non-volatile memory device 220 through multiple channels CH1 to CHm. For example, the storage controller 210 can transmit or send commands CMD1 to CMDm, addresses ADDR1 to ADDRm, and data DATA1 to DATAm to the non-volatile memory device 220 through multiple channels CH1 to CHm, and / or receive data DATA1 to DATAm from the non-volatile memory device 220.

[0060] The storage controller 210 can select one of the non-volatile memory devices NVM11 to NVMmn connected to each channel, and transmit or send and receive signals with the selected non-volatile memory device.

[0061] For example, the storage controller 210 may selectively connect to one of the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The storage controller 210 may transmit or send command CMD1, address ADDR1, and data DATA1 to the selected non-volatile memory device NVM11 via the first channel CH1, and / or receive data DATA1 from the selected non-volatile memory device NVM11.

[0062] The storage controller 210 can transmit or send and receive signals with the non-volatile memory device 220 in parallel through different channels. For example, the storage controller 210 can transmit or send command CMD2 to the non-volatile memory device 220 through the second channel CH2, while simultaneously transmitting or sending command CMD1 to the non-volatile memory device 220 through the first channel CH1. For example, the storage controller 210 can receive data DATA2 from the non-volatile memory device 220 through the second channel CH2, while simultaneously receiving data DATA1 from the non-volatile memory device 220 through the first channel CH1.

[0063] The memory controller 210 controls the overall operation of the non-volatile memory device 220. The memory controller 210 can control each of the non-volatile memory devices NVM11 to NVM1n connected to channels CH1 to CHm by transmitting or sending signals to channels CH1 to CHm. For example, the memory controller 210 can control a selected non-volatile memory device from NVM11 to NVM1n by transmitting or sending command CMD1 and address ADDR1 to the first channel CH1.

[0064] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 210. For example, non-volatile memory device NVM11 can program data DATA1 according to command CMD1 and address ADDR1 provided to the first channel CH1. For example, non-volatile memory device NVM21 can read data DATA2 according to command CMD2 and address ADDR2 provided to the second channel CH2, and transmit or send the read data DATA2 to the memory controller 210.

[0065] At the same time, Figure 3 In the example, non-volatile memory device 220 is shown communicating with memory controller 210 via m channels, and non-volatile memory device 220 includes n non-volatile memory devices corresponding to each channel. However, the example embodiment is not limited to this, and in some example embodiments, the number of channels and the number of non-volatile memory devices connected to a channel may be varied.

[0066] Figure 4 This is a block diagram illustrating a storage device according to some example embodiments.

[0067] Reference Figure 4 The storage device 200 may include a storage controller 210 and a non-volatile memory device 220. The non-volatile memory device 220 may correspond to a storage controller based on... Figure 3 One of the multiple channels CH1 to CHm of the non-volatile memory device NVM11 to NVMmn that communicates with the memory controller 210.

[0068] The non-volatile memory device 220 may include first pins P11 to eighth pins P18, memory interface circuitry 212b, memory cell array 223, and control logic circuitry 225.

[0069] The memory interface circuit 212b can receive the chip enable signal nCE from the memory controller 210 via the first pin P11. The memory interface circuit 212b can transmit or receive signals with the memory controller 210 via the second pin P12 to the eighth pin P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 212b can transmit or receive signals with the memory controller 210 via the second pin P12 to the eighth pin P18.

[0070] The memory interface circuit 212b can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 210 via pins P12 to P14, respectively. The memory interface circuit 212b can receive and / or transmit the data signal DQ from the memory controller 210 via pin P17. Command CMD, address ADDR, and data DATA can be transmitted or sent via the data signal DQ.

[0071] For example, data signals DQ can be transmitted or sent via multiple data signal lines. In some example embodiments, the seventh pin P17 may include multiple pins corresponding to multiple data signals DQ.

[0072] The memory interface circuit 212b can obtain the command CMD from the data signal DQ received during an enable period (e.g., a period when the command latch enable signal CLE is high) based on the switching timing of the write enable signal nWE. The memory interface circuit 212b can also obtain the address ADDR from the data signal DQ received during an enable period (e.g., a period when the address latch enable signal ALE is high) based on the switching timing of the write enable signal nWE.

[0073] In some example embodiments, the write enable signal nWE may remain in a static state (e.g., at a high or low level) and toggle between high and low levels. For example, the write enable signal nWE may be toggled during the period when the command CMD or address ADDR is transmitted or sent. Therefore, the memory interface circuit 212b may obtain the command CMD or address ADDR based on the toggling timing of the write enable signal nWE.

[0074] The memory interface circuit 212b can receive the read enable signal nRE from the memory controller 210 via pin 5 P15. The memory interface circuit 212b can receive the data strobe signal DQS from the memory controller 210 via pin 6 P16, and / or transmit or send the data strobe signal DQS to the memory controller 210.

[0075] In the data DATA output operation of the non-volatile memory device 220, the memory interface circuit 212b may receive a switched read enable signal nRE via pin 5 P15 before outputting the data DATA. The memory interface circuit 212b may generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, the memory interface circuit 212b may generate a data strobe signal DQS that begins switching after a predetermined (or optionally, desired) delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The memory interface circuit 212b may transmit or send a data signal DQ including the data DATA based on the switching timing of the data strobe signal DQS. Therefore, the data DATA may be transmitted or sent to the memory controller 210 in alignment with the switching timing of the data strobe signal DQS.

[0076] In the data input operation of the non-volatile memory device 220, when the data signal DQ including the data DATA is received from the memory controller 210, the memory interface circuit 212b can receive the data strobe signal DQS, which switches along with the data DATA, from the memory controller 210. The memory interface circuit 212b can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 212b can obtain the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0077] The memory interface circuit 212b can transmit or send the ready / busy output signal nR / B to the memory controller 210 via pin 8 P18. The memory interface circuit 212b can also transmit or send the status information of the non-volatile memory device 220 to the memory controller 210 via the ready / busy output signal nR / B. When the non-volatile memory device 220 is in a busy state (e.g., when internal operations of the non-volatile memory device 220 are being performed), the memory interface circuit 212b can transmit or send the ready / busy output signal nR / B indicating the busy state to the memory controller 210. When the non-volatile memory device 220 is in a ready state (e.g., when internal operations of the non-volatile memory device 220 are not being performed or have been completed), the memory interface circuit 212b can transmit or send the ready / busy output signal nR / B indicating the ready state to the memory controller 210. For example, when the non-volatile memory device 220 reads data DATA from the memory cell array 223 in response to a page read command, the memory interface circuit 212b may transmit or send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 210. Similarly, when the non-volatile memory device 300 programs data DATA into the memory cell array 223 in response to a programming command, the memory interface circuit 212b may transmit or send a ready / busy output signal nR / B indicating a busy state to the memory controller 210.

[0078] Control logic circuit 225 controls the overall operation of non-volatile memory device 220. Control logic circuit 225 receives commands / addresses (CMD / ADDR) obtained from memory interface circuit 212b. Control logic circuit 225 generates control signals for controlling other components of non-volatile memory device 220 based on the received commands / addresses (CMD / ADDR). For example, control logic circuit 225 generates various control signals for programming data DATA into and / or reading data DATA from memory cell array 223.

[0079] The memory cell array 223 can store data DATA obtained from the memory interface circuit 212b under the control of the control logic circuit 225. The memory cell array 223 can also output the stored data DATA to the memory interface circuit 212b under the control of the control logic circuit 225.

[0080] The memory cell array 223 may include multiple memory cells. For example, the multiple memory cells may be flash memory cells. However, the exemplary embodiments of the present invention are not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, TRAM (thyristor random access memory) cells, and MRAM cells. Hereinafter, the memory cells will be described as NAND flash memory cells.

[0081] The storage controller 210 may include first pins P21 to eighth pins P28 and controller interface circuitry 212a. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the non-volatile memory device 220.

[0082] The controller interface circuit 212a can transmit or send the chip enable signal nCE to the non-volatile memory device 220 via the first pin P21. The controller interface circuit 212a can transmit or send signals to the selected non-volatile memory device 220 and / or receive signals from the selected non-volatile memory device 220 via the chip enable signal nCE and the second pins P22 to the eighth pin P28.

[0083] The controller interface circuit 212a can transmit or send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory device 220 via pins P22 to P24. The controller interface circuit 212a can transmit or send the data signal DQ to the non-volatile memory device 220 and / or receive the data signal DQ from the non-volatile memory device 220 via pin P27.

[0084] The controller interface circuit 212a can transmit or send the data signal DQ, including the command CMD and / or the address ADDR, together with the write enable signal nWE to the non-volatile memory device 220. The controller interface circuit 212a can transmit or send the data signal DQ, including the command CMD, to the non-volatile memory device 220 by transmitting or sending the command latch enable signal CLE with an enabled state, and can transmit or send the data signal DQ, including the address ADDR, to the non-volatile memory device 220 by transmitting or sending the address latch enable signal ALE with an enabled state.

[0085] The controller interface circuit 212a can transmit or send the read enable signal nRE to the non-volatile memory device 220 via its fifth pin P25. The controller interface circuit 212a can receive the data strobe signal DQS from the non-volatile memory device 220 and / or transmit or send the data strobe signal DQS to the non-volatile memory device 220 via its sixth pin P26.

[0086] In the data output operation of the non-volatile memory device 220, the controller interface circuit 212a can generate a switching read enable signal nRE and transmit or send the read enable signal nRE to the non-volatile memory device 220. For example, the controller interface circuit 212a can generate a read enable signal nRE that changes from a fixed state (e.g., high or low level) to a switching state before the data DATA is output. Therefore, a data strobe signal DQS that switches based on the read enable signal nRE in the non-volatile memory device 220 can be generated. The controller interface circuit 212a can receive a data signal DQ containing the data DATA and the switching data strobe signal DQS from the non-volatile memory device 220. The controller interface circuit 212a can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0087] In data input operations of the non-volatile memory device 220, the controller interface circuit 212a can generate a switching data strobe signal DQS. For example, the controller interface circuit 212a can generate a data strobe signal DQS that changes from a fixed state (e.g., high or low level) to a switching state before transmitting or sending data DATA. The controller interface circuit 212a can transmit or send a data signal DQ containing data DATA to the non-volatile memory device 220 based on the switching timing of the data strobe signal DQS.

[0088] The controller interface circuit 212a can receive the ready / busy output signal nR / B from the non-volatile memory device 220 via pin 8 P28. The controller interface circuit 212a can determine the status information of the non-volatile memory device 220 based on the ready / busy output signal nR / B.

[0089] Figure 5 This is a block diagram illustrating a storage controller according to some example embodiments.

[0090] Reference Figure 5 The storage controller 210 may include an FTL 211, a memory interface 212, a host interface 213, a processor 214, a NAND controller 215, and a memory 216.

[0091] FTL 211 may be provided in hardware and / or software form and may be driven by processor 214. If FTL 211 is provided in software form, FTL 211 may be loaded into memory 216 and operated by processor 214. In some example embodiments, FTL 211 may be provided in hardware form (such as dedicated circuitry).

[0092] In addition to reference Figure 2Beyond the functions described in detail, in some example embodiments, FTL 211 may perform operations such as garbage collection, wear leveling, etc., but the example embodiments are not limited thereto. For example, FTL 211 may manage the number of program / erase cycles for multiple memory blocks included in non-volatile memory device 220, and perform wear leveling accordingly, such that the number of program / erase cycles for the multiple memory blocks is balanced.

[0093] For reference Figure 3 and Figure 4 The storage controller 210 can communicate with the non-volatile memory device 220 via the storage interface 212. The storage controller 210 can also communicate with the host 100 via the host interface 213.

[0094] In some example embodiments, host interface 213 may include various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI Express, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), Mobile Industrial Processor Interface (MIPI), NVMe, etc., but example embodiments are not limited thereto.

[0095] Processor 214 controls all operations of storage controller 210. Processor 214 may be implemented as a CPU, AP, GPU, etc., but the example embodiment is not limited to this.

[0096] NAND controller 215 can issue metadata to any one of the plurality of NAND dies in non-volatile memory device 220. NAND controller 215 can monitor whether the plurality of cores and their corresponding paths included in NAND controller 215 are busy, whether the plurality of channels connected to non-volatile memory device 220 are busy, and whether the plurality of NAND dies are busy, in order to issue metadata. According to some example embodiments, in Figure 8 The following section will explain the specific details.

[0097] The memory 216 may operate as a buffer memory, cache memory, and / or operational memory of the processor 214. According to some example embodiments, the memory 216 may include DRAM, SRAM, etc., but the example embodiments are not limited thereto.

[0098] Figure 6 This is a block diagram illustrating a non-volatile memory device according to some example embodiments.

[0099] Reference Figure 6The non-volatile memory device 220 may include a memory cell array 223, a row decoder 224, control logic circuitry 225, a page buffer circuitry 226, and a voltage generator 227. Meanwhile, although... Figure 6 Not shown in the figure, but in some example embodiments, the non-volatile memory device 220 may also include memory interface circuitry (e.g., Figure 4 (212b), and may also include column logic, pre-decoder, temperature sensor, command decoder, address decoder, etc.

[0100] The memory cell array 223 can be connected to the page buffer circuit 226 via the bit line BL, and can be connected to the line decoder 224 via multiple word lines WL, multiple serial select lines SSL, and multiple ground select lines GSL.

[0101] The memory cell array 223 may include a user area 221 and a metadata area 222. The user area 221 may correspond to the area storing user data UD, and the metadata area 222 may correspond to the area storing metadata MD.

[0102] Each of user region 221 and meta region 222 may include multiple memory blocks. Each of the multiple memory blocks may include multiple pages, and each of the multiple pages may include multiple memory cells.

[0103] In some example embodiments, the memory block included in user region 221 may be a multilevel cell block including a multilevel cell (MLC) storing at least 2 bits of data, a three-level cell block including a three-level cell (TLC), or a four-level cell block including a four-level cell (QLC). In some example embodiments, the memory block included in meta region 222 may be a single-level cell block including a single-level cell (SLC) storing 1 bit of data.

[0104] Control logic circuitry 225 can control various operations within the non-volatile memory device 220. Control logic circuitry 225 can respond to input from a memory controller (e.g., ...). Figure 4 The control logic circuit 225 can output various control signals in response to the received command CMD and / or address ADDR. The control logic circuit 225 can output control signals for writing or programming data DATA into or from the memory cell array 223, reading data DATA from the memory cell array 223, and / or erasing data stored in the memory cell array 223. For example, the control logic circuit 225 can output voltage control signal CTRL_vol, row address X_ADDR, and column address Y_ADDR.

[0105] Various control signals output from control logic circuit 225 can be provided to voltage generator 227, row decoder 224, and page buffer circuit 226. Control logic circuit 225 can provide voltage control signal CTRL_vol to voltage generator 227.

[0106] Voltage generator 227 can be connected to memory cell array 223 via multiple word lines WL. Voltage generator 227 can generate various types of voltages for performing programming, reading, and erasing operations on memory cell array 223 based on the voltage control signal CTRL_vol. Voltage generator 227 can generate, for example, programming voltage Vpgm, pass voltage Vpass, and erase voltage Vers. In some example embodiments, the pass voltage Vpass can be a voltage applied to an unselected word line during a read or verification operation.

[0107] The line decoder 224 can select a specific (or optionally, desired) word line among the word lines WL in response to the line address X_ADDR received from the control logic circuitry 225. For example, during a programming operation, the line decoder 224 can provide a programming voltage Vpgm to the selected word line. In some example embodiments, the line decoder 224 can select a portion of the string select lines SSL or a portion of the ground select lines GSL in response to the line address X_ADDR received from the control logic circuitry 225.

[0108] Page buffer circuit 226 can be connected to memory cell array 223 via multiple bit lines BL. Page buffer circuit 226 can select a portion of the multiple bit lines BL in response to column address Y_ADDR received from control logic circuit 225. During programming or reading operations, page buffer circuit 226 can operate as a sense amplifier to sense data DATA stored in memory cell array 223.

[0109] In some example embodiments, when the program is running, the page buffer circuit 226 can operate as a write driver to input data DATA that will be stored in the memory cell array 223. The page buffer circuit 226 can store data DATA read from the memory cell array 223 and / or data DATA to be written to the memory cell array 223.

[0110] Figure 7 This is an exemplary circuit diagram illustrating one of a plurality of memory blocks included in a memory cell array according to some example embodiments.

[0111] Reference Figure 7The memory block BLK may include multiple cell strings CS11 to CS12 and CS21 to CS22. The multiple cell strings CS11 to CS12 and CS21 to CS22 may be connected between bit lines BL1 and BL2 and the common-source line CSL. Each of the multiple cell strings CS11 to CS12 and CS21 to CS22 may include a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST.

[0112] The string select transistor SST can be connected to string select lines SSL1 to SSL2 respectively. Multiple memory cells MC1 to MC8 can be connected to multiple word lines WL1 to WL8. The ground select transistor GST can be connected to the ground select line GSL. The string select transistor SST can be connected to bit lines BL1 and BL2, and the ground select transistor GST can be connected to the common source line CSL. Word lines of the same height (e.g., WL1) can be connected together. For example, when programming a memory cell connected to the first word line WL1 and included in cell strings CS11 and CS12, the first word line WL1 and the first string select line SSL1 can be selected.

[0113] In some example embodiments, programming or reading operations can be performed line by line on the cell strings CS11 to CS22. Cell strings CS11 to CS22 can be selected line by line using string selection lines SSL1 to SSL2.

[0114] Within the selected rows of cell strings CS11 to CS22, programming or reading operations can be performed page by page. A page can be a single row of memory cells connected to a single word line. Within the selected rows of cell strings CS11 to CS22, memory cells can be selected in page units via word lines WL1 to WL8.

[0115] In some example embodiments, multiple cell strings CS11 to CS12, CS21 to CS22 may be formed in a direction perpendicular to the substrate (not shown), and string selection transistors SST, multiple memory cells MC1 to MC8 and ground selection transistors GST may be stacked in a direction perpendicular to the substrate (not shown).

[0116] For example, a memory block (BLK) can be a memory block with a three-dimensional structure. The memory cells included in a memory block with a three-dimensional structure can be charge-capture flash memory cells. Charge-capture flash memory cells store data by capturing charge in a charge storage film.

[0117] Figure 7 The memory block BLK shown is exemplary, and the example embodiments are not necessarily limited thereto. For example, with Figure 7Compared to the memory block BLK shown, the number of rows of cell strings can be increased or decreased, and as the number of rows of cell strings is changed, the number of string select lines or ground select lines connected to the rows of cell strings, as well as the number of cell strings connected to a bit line, can also be changed.

[0118] In addition, with Figure 7 Compared to the memory block BLK shown, in some example embodiments, the number of columns of the cell string can be increased or decreased, and as the number of columns of the cell string is changed, the number of bit lines connected to the columns of the cell string and the number of cell strings connected to a string select line can also be changed.

[0119] In some example embodiments, with Figure 7 Compared to the memory block BLK shown, the height of the cell string can be increased or decreased, and the number of memory cells in each stacked cell string can be increased or decreased. As the number of memory cells stacked in each cell string changes, the number of word lines can also change.

[0120] In some example embodiments, the number of string select transistors or ground select transistors provided for each of the cell strings can be increased. As the number of string select transistors or ground select transistors provided for each of the cell strings changes, the number of string select lines or ground select lines can also change. As the number of string select transistors or ground select transistors increases, the string select transistors or ground select transistors can be stacked in the same manner as memory cells MC1 to MC8.

[0121] Figure 8 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0122] Reference Figure 8 The NAND controller 215 may include multiple cores from CORE1 to CORE8. The NAND controller 215 may correspond to... Figure 5 The NAND controller 215 is shown in the figure. Multiple paths PATH1 to PATH8 corresponding to multiple cores CORE1 to CORE8 can be connected to multiple cores CORE1 to CORE8, and user data UD and metadata MD can be transmitted or sent to any of the multiple cores CORE1 to CORE8 corresponding to multiple paths PATH1 to PATH8.

[0123] For example, user data (UD) and metadata (MD) can be transmitted via the third path (PATH3) or sent to the corresponding third core (CORE3). This can be based on pending requests in the task queue of the third core (e.g., from references). Figure 1 The task sequence of the request REQ from host 100 is used to process user data UD and metadata MD.

[0124] Each of the multiple cores CORE1 through CORE8 can be connected to multiple channels. In some example embodiments, each of the multiple channels can be connected to multiple NAND dies. For example, the third core CORE3 can be connected to the first channel CH1 and the second channel CH2, the first channel CH1 can be connected to the eleventh NAND die ND11 through the eighteenth NAND die ND18, and the second channel CH2 can be connected to the twenty-first NAND die N21 through the twenty-eighth NAND die N28. For ease of explanation, the paths, channels, and multiple NAND dies for the third core CORE3 have been described; however, according to some example embodiments, substantially the same configuration can be applied to the other remaining cores.

[0125] Each of the multiple cores CORE1 to CORE8 has executable software to monitor whether multiple paths PATH1 to PATH8 are busy, whether multiple channels CH1 to CH2 connected to each of the multiple cores CORE1 to CORE8 are busy, and / or whether multiple NAND dies ND11 to ND18 and ND21 to ND28 connected to the multiple channels CH1 to CH2 are busy. Therefore, in some example embodiments, improved performance of the storage device can be provided by checking the traffic status along the transmission path of user data UD and determining the storage location and / or emission location of metadata. Specific details according to some example embodiments are as follows... Figure 9 The explanation below is as follows.

[0126] Figure 9 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0127] Reference Figure 9 User data (UD) and metadata (MD) can be transmitted via the first path PATH1 or the second path PATH2, or sent to the first core CORE1 corresponding to the first path PATH1 or the second core CORE2 corresponding to the second path PATH2. For example, Figure 9 As shown, user data UD can be transmitted via the first path PATH1 or sent to the first core CORE1.

[0128] The busyness of the first path PATH1 can be determined based on the number of pending requests REQ1 in the task queue TQ1 of the first core CORE1 corresponding to the first path PATH1. For example, Figure 9 As shown, the first core CORE1 corresponding to the first path PATH1 may have five pending requests for user data UD, and the first core CORE1 may be determined to be busy if the number of pending requests is greater than (or optionally, greater than or equal to) a predetermined (or optionally, desired) threshold, or if there are more pending requests than the number of pending requests in other cores.

[0129] In some example embodiments, it can be determined that the second path PATH2 corresponding to the second core CORE2 is in a normal state. For example, it can be determined whether the second path PATH2 is in a normal state based on the number of pending requests REQ2 in the task queue TQ2 of the second core CORE2 corresponding to the second path PATH2. Based on the determination that the first path PATH1 is busy and the second path PATH2 is in a normal state, metadata MD can be transmitted or sent to the second core CORE2 through the second path PATH2.

[0130] Figure 10 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0131] Reference Figure 10 Multiple channels CH1 to CH8 can be connected to the second core CORE2, and multiple NAND dies can be connected to each of the multiple channels CH1 to CH8. The second core CORE2 can monitor the busy status of each of the multiple channels CH1 to CH8.

[0132] For example, the second core CORE2 can monitor the number of busy NAND dies among the multiple NAND dies connected to each of multiple channels CH1 to CH8. The second core CORE2 can determine that a channel is busy when the number of busy NAND dies among the multiple NAND dies connected to a particular channel exceeds (or optionally, is greater than or equal to) a predetermined (or optionally, desired) threshold, and / or when a relatively large number of NAND dies are busy compared to other channels.

[0133] For example, when the predetermined (or optionally, desired) threshold is 6, the second core CORE2 can determine that the first channel CH1 (eight NAND dies busy), the third channel CH3 (seven NAND dies busy), the fifth channel CH5 (six NAND dies busy), and the seventh channel CH7 (six NAND dies busy) are busy. In some example embodiments, when the predetermined (or optionally, desired) threshold is 6, the second core CORE2 can determine that the second channel CH2 (five NAND dies busy), the fourth channel CH4 and the eighth channel CH8 (three NAND dies busy), and the sixth channel CH6 (two NAND dies busy) are normal.

[0134] Figure 11 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0135] Reference Figure 11 , such as regarding Figure 10The second core CORE2 can monitor whether each of the multiple NAND dies connected to each of the "second channel CH2, fourth channel CH4, sixth channel CH6, and eighth channel CH8, which are determined to be in a normal state" is in a busy state. The second core CORE2 can send metadata MD to the NAND die in the normal state among the monitored multiple NAND dies.

[0136] For example, such as Figure 11 As shown, metadata can be preferentially sent to any one of the following: "A" NAND die connected to the second channel CH2, "B" NAND die connected to the fourth channel CH4, "C" NAND die connected to the sixth channel CH6, and "D" NAND die connected to the eighth channel CH8. For example, if the weight is high for channels with lower busy levels, the metadata MD can be preferentially sent to the "C" NAND die of the sixth channel CH6, which has the fewest busy NAND dies and the highest weight.

[0137] In some example embodiments, when the number of busy NAND dies (such as channel 4 CH4 and channel 8 CH8) is equal, the second core CORE2 can monitor the number of metadata sent for each of the plurality of NAND dies connected to each of channel 4 CH4 and channel 8 CH8. In some example embodiments, the number of metadata sent for a particular NAND die can represent the number of times metadata is sent for a particular NAND die. For example, the second core CORE2 can monitor the number of metadata sent for NAND die "B" and NAND die "D", and if the number of metadata sent for NAND die "B" is greater than the number of metadata sent for NAND die "D", then metadata MD can be sent to NAND die "D". However, the example embodiments are not limited to this, and in some example embodiments, the priority of metadata MD sending can be implemented in various different ways. In some example embodiments, in response to a greater number of metadata issued by a third memory cell among a plurality of first memory cells connected to a channel in a normal state than the number of metadata issued by a second memory cell among a plurality of first memory cells connected to the channel, the storage controller 210 may be configured to issue metadata MD to the second memory cell and update the metadata issuance table MDIT, wherein the third memory cell and the second memory cell are in a normal state.

[0138] Figures 12 to 15 This is a diagram used to explain the operation of a storage device according to some example embodiments.

[0139] Reference Figure 12 , Figure 5The NAND controller 215 can be used as described in the following text. Figures 8 to 11 The method determines whether each of the multiple paths is busy, and information regarding the busy status of each path can be stored in a path status table (PST). For example, the path status table (PST) can be temporarily stored during operation of the storage device. Figure 5 The memory 216 is used, but the example embodiment is not limited thereto.

[0140] Reference Figure 13 NAND controllers can be as follows: Figures 8 to 11 The method determines whether each of the multiple channels and each of the multiple NAND dies is in a busy state, and information regarding whether each of the multiple channels and each of the multiple NAND dies is in a busy state can be stored in a die status table (DST). For example, the die status table (DST) may be temporarily stored in memory during operation of the storage device, but the example embodiment is not limited thereto.

[0141] Reference Figure 14 NAND controllers can be as follows: Figures 8 to 11 The NAND controller monitors the number of metadata issued for each of the multiple NAND dies. The NAND controller can monitor the number of metadata issued for each of the multiple NAND dies by referring to the Metadata Issuance Table (MDIT). When the NAND controller issues specific metadata to a particular NAND die, the NAND controller can update the Metadata Issuance Table (MDIT) by updating the issuance count and meta-index corresponding to that particular NAND die.

[0142] Reference Figure 15 NAND controllers can be as follows: Figures 8 to 11 The location of the metadata transmission is sent to any one of the multiple NAND dies. The location of the metadata transmission can be stored as a Metadata Location Table (MDLT). Figure 1 In the non-volatile memory device 220. When specific metadata is issued to a specific NAND die, the NAND controller can update the storage location (e.g., blocks and pages with a given meta-index).

[0143] Figure 16 This is a flowchart illustrating the operation of a storage device according to some example embodiments.

[0144] Reference Figure 16 The operation method S10 of the storage device may include the step S11 of configuring metadata. For example, Figure 1 The storage device 200 in the middle can be based on the storage device 200 from Figure 1 The host 100 provided Figure 1 Use the data in DATA_h to configure metadata.

[0145] The operation method S10 of the storage device may include step S12 of determining the location where metadata will be stored. For example, Figure 5 The NAND controller 215 can determine the NAND die on which metadata will be stored based on whether multiple paths are busy, multiple channels are busy, and / or multiple NAND dies are busy. In some example embodiments, the NAND controller can further determine the NAND die on which metadata will be stored based on the number of metadata issued for each of the multiple NAND dies.

[0146] The operation method S10 of the storage device may include the step S13 of issuing metadata. For example, the NAND controller may issue metadata to the NAND die determined in step S12.

[0147] The operation method S10 of the storage device may include a step S14 of updating the location of metadata. For example, the NAND controller may update the stored metadata and the location where the metadata is stored. Figure 15 The metadata location table MDLT, and make the metadata location table MDLT stored in Figure 1 In the non-volatile memory device 220.

[0148] Figure 17 This is an exemplary block diagram illustrating a mobile system employing a storage device according to some example embodiments.

[0149] Reference Figure 17 The mobile system 1000 may include an application processor 1100, a network module 1200, a memory module 1300, a storage module 1400, and a user interface 1500. The application processor 1100 may have... Figure 1 The configuration corresponding to host 100, and a detailed description of application processor 1100 are available. Figure 1 Replace it with the description.

[0150] Network module 1200 can communicate with external devices. For example, network module 1200 may support wireless communications (such as Code Division Multiple Access (CDMA), Global System for Mobile Communications, Wideband CDMA, CDMA-2000, Time Division Multiple Access, Long Term Evolution, Global System for Microwave Access (WiMAX), Wireless Local Area Network (WLAN), Ultra Wideband (UWB), Bluetooth, Wireless Digital Interface (WI-DI), etc.), but the example embodiments are not limited thereto.

[0151] The memory module 1300 may operate as the main memory, operating memory, buffer memory, and / or cache memory of the mobile system 1000. The memory module 1300 may include volatile random access memory (such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR3 SDRAM, LPDDR3 SDRAM, etc.) or non-volatile random access memory (such as PRAM, ReRAM, MRAM, FRAM, etc.), but the example embodiments are not limited thereto.

[0152] Storage module 1400 can store data. For example, storage module 1400 can store data received from an external source (e.g., data received from outside mobile system 1000). Storage module 1400 can transfer or send the data stored in storage module 1400 to application processor 1100. For example, storage module 1400 can be implemented using a non-volatile semiconductor memory device (such as PRAM, MRAM, RRAM, NAND flash memory, NOR flash memory, and / or three-dimensional structured NAND flash memory). For example, storage module 1400 can be provided as a solid-state drive (SSD), multimedia card (MMC), embedded multimedia card (eMMC), universal flash storage (UFS), etc., but the example embodiments are not limited thereto.

[0153] As shown in some example embodiments Figures 1 to 16 As described above, the storage module 1400 can store metadata based on the path, channel, and whether each NAND die is busy, according to the processing of user data.

[0154] In some example embodiments, the storage module 1400 can improve the performance of the storage module 1400 by uniformly storing metadata in multiple NAND flash memory by taking into account the flow of user data UD through the metadata storage method described above according to some example embodiments.

[0155] Figure 18 This is an exemplary block diagram of a computing device that applies a storage device according to some example embodiments.

[0156] Reference Figure 18 The computing device 2000 may include a processor 2100, a memory 2200, a memory controller 2300, a storage device 2400, a communication interface 2500, and a bus 2600. In some example embodiments, the computing device 2000 may also include other general-purpose components (not shown).

[0157] Processor 2100 can control the overall operation of each component of computing device 2000. Processor 2100 can be implemented as at least one of various processors (such as CPU, AP and / or GPU), but the example embodiment is not limited thereto.

[0158] Memory 2200 can store various data and / or commands. Memory controller 2300 can control the transfer of data and / or commands to and from memory 2200. In some example embodiments, memory controller 2300 may be provided as a separate chip from processor 2100. In some example embodiments, memory controller 2300 may be provided as an internal component of processor 2100.

[0159] Storage device 2400 stores programs and / or data non-temporarily. In some example embodiments, storage device 2400 may be implemented as non-volatile memory. In some example embodiments, storage device 2400 may be implemented as described in reference... Figures 1 to 16 The aforementioned storage device.

[0160] The communication interface 2500 can support wired and wireless Internet communication of the computing device 2000. According to some example embodiments, the communication interface 2500 can support various communication methods other than Internet communication.

[0161] Bus 2600 provides communication capabilities between components of computing device 2000. Depending on the communication protocol between components, bus 2600 may include at least one type of bus.

[0162] Figure 19 This is a block diagram illustrating, by way of example, a system employing a storage device according to some example embodiments.

[0163] Reference Figure 19 System 3000 can be a mobile system (such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, and / or Internet of Things (IoT) device). However, the example embodiments are not limited to this, and in some example embodiments, Figure 19 The system 3000 can be a personal computer, laptop computer, server, media player, and / or automotive device (such as a navigation device).

[0164] System 3000 may include a main processor 3100, memory 3200a, 3200b and storage devices 3300a, 3300b, and may additionally include one or more of the following: image capturing device 3410, user input device 3420, sensor 3430, communication device 3440, display 3450, speaker 3460, power supply device 3470 and connection interface 3480.

[0165] The main processor 3100 controls the overall operation of the system 3000 (more specifically, the operation of other components that make up the system 3000). Such a main processor 3100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0166] The main processor 3100 may include one or more CPU cores 3110, and may also include a controller 3120 for controlling memories 3200a, 3200b and / or storage devices 3300a, 3300b. In some example embodiments, the main processor 3100 may also include an accelerator 3130, which is dedicated circuitry for high-speed data operations, such as AI artificial intelligence data operations. Such an accelerator 3130 may include a GPU, NPU, and / or DPU, and may be implemented as a separate chip physically independent of other components of the main processor 3100.

[0167] Memory 3200a and 3200b may be used as the main memory device of system 3000 and may include volatile memory (such as SRAM and / or DRAM), but may also include non-volatile memory (such as flash memory, PRAM and / or RRAM). Memory 3200a and 3200b may also be implemented in the same package as main processor 3100.

[0168] Storage devices 3300a and 3300b can be used as non-volatile storage devices that store data regardless of whether power is supplied, and can have a relatively large storage capacity compared to memories 3200a and 3200b. Storage devices 3300a and 3300b may include storage controllers (STRG CTRL) 3310a and 3310b and non-volatile memories 3320a and 3320b that store data under the control of storage controllers 3310a and 3310b. Non-volatile memories 3320a and 3320b may include flash memory with a 2D (2D) structure or a 3D (3D) V-NAND (vertical NAND) structure, but may also include other types of non-volatile memories (such as PRAM and / or RRAM).

[0169] Storage devices 3300a and 3300b may be included in a system 3000 physically separate from the main processor 3100, or may be implemented within the same package as the main processor 3100. In some example embodiments, storage devices 3300a and 3300b may be in the form of solid-state devices such as SSDs or memory cards, and may be detachably connected to other components of the system 3000 via an interface (such as connection interface 3480, described later). Such storage devices 3300a and 3300b may be devices that apply standard specifications (such as UFS (Universal Flash Memory), eMMC (Embedded Multimedia Card), and / or NVMe (Non-Volatile Memory Faster)), but the example embodiments are not necessarily limited thereto. Storage devices 3300a and 3300b may include, for example, Figures 1 to 16 The storage device described herein.

[0170] The image capturing device 3410 can capture still images and / or moving images, and can be a camera, a portable video camera, and / or a webcam.

[0171] User input device 3420 can receive various types of data input from the user of system 3000, and can be a touchpad, keypad, keyboard, mouse and / or microphone.

[0172] Sensor 3430 can detect various types of physical quantities that can be obtained from outside the system 3000 and convert the detected physical quantities into electrical signals. Such sensor 1430 can be a temperature sensor, pressure sensor, light sensor, position sensor, acceleration sensor, biosensor, and / or gyroscope sensor.

[0173] The communication device 3440 can transmit or send and / or receive signals between other devices outside the system 3000 according to various communication protocols. Such a communication device 3440 can be implemented as including an antenna, a transceiver, and / or a modem.

[0174] The display 3450 and speaker 3460 can be used as output devices for users to output visual and auditory information to the system 3000, respectively.

[0175] The power supply unit 3470 can appropriately convert and supply power from a battery (not shown) built into the system 3000 and / or an external power source to each component of the system 3000.

[0176] The connection interface 3480 provides a connection between the system 3000 and an external device connected to and capable of exchanging data with the system 3000. The connection interface 3480 may be implemented in various interface methods, such as Advanced Technology Accessories, Serial ATA, e-SATA (External SATA), Small Computer Small Interface, Peripheral Component Interconnect, PCIe (PCI Fast), NVMe, IEEE 1394, USB (Universal Serial Bus), SD (Secure Digital) card, MMC (Multimedia Card), eMMC, UFS, Embedded Universal Flash Memory, CF (Compact Flash Memory) card interface, etc., but the example embodiments are not limited thereto.

[0177] Figure 20 This is a block diagram illustrating, by way of example, a system employing a storage device according to some example embodiments.

[0178] Reference Figure 20 A data center 4000 is a facility that collects and provides services for various types of data, and can also be referred to as a data storage center. A data center 4000 can be a system used to operate search engines and databases, and can be a computing system used by a company (such as a bank or government agency).

[0179] Data center 4000 may include application servers 4100_1 (application server 1) to 4100_n (application server N) and storage servers 4200_1 (storage server 1) to 4200_m (storage server M). The number of application servers 4100_1 to 4100_n and the number of storage servers 4200_1 to 4200_m may be selected differently according to some example embodiments, and the number of application servers 4100_1 to 4100_n and the number of storage servers 4200_1 to 4200_m may be different from each other.

[0180] Application servers 4100_1 to 4100_n and / or storage servers 4200_1 to 4200_m may include at least one of processors 4110_1 to 4110_n, 4210_1 to 4210_m and memory 4120_1 to 4120_n, 4220_1 to 4220_m. Taking storage server 4200_1 as an example, processor 4210_1 may control the overall operation of storage server 4200_1 and access memory 4220_1 to execute commands and / or data loaded into memory 4220_1. Memory 4220_1 may be DDR SDRAM, HBM, hybrid memory cube, dual in-line memory module, Optane DIMM and / or NVM DIMM (non-volatile DIMM), but the example embodiment is not limited thereto. According to some example embodiments, the number of processors 4210_1 and the number of memories 4220_1 included in the storage server 4200_1 can be selected in various different ways.

[0181] In some example embodiments, processor 4210_1 and memory 4220_1 may provide a processor-memory pair. In some example embodiments, the number of processors 4210_1 and memory 4220_1 may differ from each other. Processor 4210_1 may include a single-core processor or a multi-core processor. The above description of storage server 4200_1 according to some example embodiments can be similarly applied to application server 4100_1. According to some example embodiments, application server 4100_1 may not include storage device 4150_1. Storage server 4200_1 may include at least one storage device 4250_1. According to some example embodiments, the number of storage devices 4250_1 included in storage server 4200_1 may be selected in various ways. Storage device 4250_1 may include, for example... Figures 1 to 16The storage device described herein. In some example embodiments, application server 4100_1 may further include switch 4130_1 and network interface card (NIC) 4140_1, and similarly, application server 4100_n may further include switch 4130_n and network interface card (NIC) 4140_n. In some example embodiments, storage server 4200_1 may further include switch 4230_1 and network interface card (NIC) 4240_1, and similarly, storage server 4200_m may further include switch 4230_m and network interface card (NIC) 4240_m. In some example embodiments, storage device 4250_1 may include interface (I / F) 4254_1, DRAM 4253_1, controller (CTRL) 4251_1, and NAND 4252_1, and similarly, storage device 4250_m may include interface (I / F) 4254_m, DRAM 4253_m, controller (CTRL) 4251_m, and NAND 4252_m. In some example embodiments, multiple network interface cards (NICs) 4140_1, 4240_1, 4140_n, and 4240_m communicate via network 4300.

[0182] One or more of the elements disclosed above may include one or more processing circuitry systems (such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof) or implemented in one or more processing circuitry systems (such as hardware including logic circuitry; hardware / software combinations (such as a processor executing software); or combinations thereof). For example, processing circuitry systems may more specifically include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), graphics processing units (GPUs), application processors (APs), digital signal processors (DSPs), microcomputers, field-programmable gate arrays (FPGAs) and programmable logic units, microprocessors, application-specific integrated circuits (ASICs), neural network processors (NPUs), electronic control units (ECUs), image signal processors (ISPs), etc. In some example embodiments, processing circuitry systems may include non-transitory computer-readable storage devices (e.g., memory) storing programs of instructions (e.g., solid-state drives (SSDs)) and processors (e.g., CPUs) configured to execute instructions to implement functions and / or methods performed by some or all of any means, electronic devices, modules, units, and / or portions thereof according to any example embodiment.

[0183] Any of the memories described herein may be non-volatile memories (such as flash memory, phase-change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM) or ferroelectric RAM (FRAM)) or volatile memories (such as static RAM (SRAM), dynamic RAM (DRAM) or synchronous DRAM (SDRAM)).

[0184] Any or all of the elements described with reference to the accompanying drawings may communicate with any or all of the other elements described with reference to the accompanying drawings. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcast with any or all of the other elements in the drawings to transmit and / or exchange and / or receive information (such as, but not limited to, data and / or commands) via a bus (such as, a wireless bus and / or a wired bus (not shown)) in a manner such as serial and / or parallel. The information may be encoded in various formats (such as analog and / or digital formats).

[0185] Although some exemplary embodiments of the inventive concept have been described in detail above, the scope of the inventive concept is not limited thereto, and various modifications and improvements made by those skilled in the art using some exemplary embodiments of the inventive concept as defined in the appended claims also fall within the scope of the inventive concept.

Claims

1. A storage device, comprising: A non-volatile memory device comprising multiple memory cells configured to store user data and metadata; as well as A storage controller, comprising multiple cores, is configured to issue metadata to one of the multiple memory cells based on whether each of the multiple paths corresponding to the multiple cores is busy.

2. The storage device according to claim 1, wherein: The busy status of each of the plurality of paths is determined based on the number of pending requests in the task queue of the core corresponding to each of the plurality of paths.

3. The storage device according to claim 1, wherein: In response to a first path being busy and a second path being normal, the storage controller is configured to monitor whether each of the multiple channels connected to the core corresponding to the second path is busy.

4. The storage device according to claim 3, wherein: The busy state of each of the plurality of channels is determined based on the number of memory cells among the plurality of memory cells that are connected to each of the plurality of channels and are in a busy state.

5. The storage device according to claim 3, wherein: In response to a first channel among the plurality of channels connected to the core corresponding to the second path being busy and a second channel among the plurality of channels being normal, the memory controller is configured to monitor whether each of the plurality of first memory cells among the plurality of memory cells connected to the second channel is busy.

6. The storage device according to claim 5, wherein: In response to a third memory cell among the plurality of first memory cells being busy and a second memory cell among the plurality of first memory cells being in a normal state, the storage controller is configured to send metadata to the second memory cell.

7. The storage device according to claim 6, wherein: In response to the metadata being sent to the second memory unit, the storage controller is configured to update the metadata location table.

8. The storage device according to claim 5, wherein: The storage controller is configured to issue metadata based on the number of metadata issued by each of the plurality of first memory cells connected to the second channel.

9. The storage device according to claim 8, wherein: In response to a situation where the number of metadata issued by the third memory cell among the plurality of first memory cells is greater than the number of metadata issued by the second memory cell among the plurality of first memory cells, the storage controller is configured to issue metadata to the second memory cell and update the metadata issuance table.

10. The storage device according to any one of claims 1 to 9, wherein: The plurality of memory units include a plurality of first memory blocks configured to store user data and a plurality of second memory blocks configured to store metadata and different from the plurality of first memory blocks.

11. The storage device according to claim 10, wherein: The plurality of second memory blocks are single-level cell blocks.

12. A storage device, comprising: A non-volatile memory device comprising multiple memory cells configured to store user data and metadata; as well as The storage controller is configured to send metadata to a plurality of first memory cells among the plurality of memory cells based on whether each of the plurality of memory cells is busy.

13. The storage device according to claim 12, wherein: The plurality of first memory cells are connected to a first channel in normal condition among a plurality of channels connected to a non-volatile memory device.

14. The storage device according to claim 12, wherein: The plurality of first memory units include a third memory unit and a second memory unit in a normal state, and The storage controller is configured to issue metadata to one of the third and second memory units based on the amount of metadata issued by the third and second memory units.

15. The storage device according to claim 14, wherein: In response to the fact that the number of metadata issued by the third memory unit is greater than the number of metadata issued by the second memory unit, the storage controller is configured to issue metadata to the second memory unit and update the metadata issuance table and the metadata location table.

16. The storage device according to claim 13, wherein: The number of busy first memory cells among the plurality of first memory cells connected to the first channel is less than or equal to a threshold.

17. The storage device according to claim 13, wherein: The storage controller includes multiple cores, and a first channel is connected to a first core among the multiple cores that corresponds to a first path in a normal state.

18. The storage device according to claim 17, wherein: The number of pending requests in the task queue of the first core is less than the threshold.

19. A method of operating a storage device, comprising: Metadata is built based on user data; The location where the metadata will be stored is determined based on whether each of the multiple paths corresponding to the multiple cores included in the storage controller is busy, whether each of the multiple channels connected to each of the multiple cores is busy, and whether each of the multiple memory cells of the non-volatile memory device is busy. Send metadata to the location; as well as The location for updating metadata.

20. The method of operating a storage device according to claim 19, further comprising: The location where the metadata will be stored is determined based on the number of metadata emitted by each of the plurality of memory units.

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