Storage device and method for completion

Abstract

A storage device and method for completion. A storage device configured for connection to a host device includes a non-volatile memory and a storage controller configured to receive a write command for the non-volatile memory from the host device and control programming of write data corresponding to the write command in the non-volatile memory. The storage controller may be configured to transmit a completion signal indicating completion of the write command to the host device based on at least one of program state information indicating a program state of the write command or device state information of the storage device.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0160450, filed on November 12, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments generally relate to storage devices and methods for implementation. Background Technology

[0004] Storage devices store data under the control of host devices such as computers, smartphones, or tablets. Most storage devices are powered by an external power source. However, storage devices are vulnerable to damage, including data loss, due to external power source failures or power outages such as sudden power outages (SPO).

[0005] To address the aforementioned power-related issues, storage devices can support power loss protection (PLP). PLP enables storage devices to back up (or dump) data stored in buffer memory (or cache memory) to non-volatile memory in the event of a power outage.

[0006] Storage devices can perform write command completion by buffering data in a buffer and then sending the completion status of the write command to the host. In the event of a power outage after command completion, the storage device should fully guarantee data backup. Therefore, adjusting the completion time can be considered to reduce the amount of backup required. Summary of the Invention

[0007] An example embodiment provides a storage device that can reduce the amount of backups by setting a completion time for sending data, and a method for doing so.

[0008] According to an example embodiment, a storage device includes non-volatile memory and a storage controller configured to receive a write command for the non-volatile memory from a host device and to control the programming of write data corresponding to the write command into the non-volatile memory. The storage controller may be configured to send a completion message of the write command to the host device based on at least one of programming state information indicating the program state of the write command or device state information of the storage device.

[0009] According to an example embodiment, a method for a storage device includes: receiving a write command from a host device, obtaining programming state information indicating the programming state of the write command and device state information of the storage device, and sending the completion of the write command to the host device based on at least one of the programming state information or the device state information.

[0010] According to an example embodiment, a storage device includes: non-volatile memory; a storage controller configured to receive a write command for the non-volatile memory from a host device and control the programming of write data corresponding to the write command into the non-volatile memory; a buffer memory configured to buffer the write data; and a power-loss protection (PLP) circuit configured to detect a sudden power outage (SPO) from the storage device. The storage controller may also be configured to send completion of the write command to the host device based on at least one of programming status information indicating the programming state of the write command or device status information of the storage device, and to omit backing up the buffered write data to the non-volatile memory when an SPO is detected before sending completion to the host device. Attached Figure Description

[0011] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) indicate corresponding elements in several views, and wherein:

[0012] Figure 1 This is a block diagram illustrating at least a portion of a storage system according to an example embodiment;

[0013] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of an example storage controller;

[0014] Figure 3 According to the example embodiment Figure 1 A block diagram of non-volatile memory;

[0015] Figure 4 This illustrates an example embodiment. Figure 3 A circuit diagram of an example memory block within a memory cell array;

[0016] Figure 5 It is a diagram illustrating the data state before and after the programming and reprogramming operations according to an example embodiment;

[0017] Figure 6 This is a timing diagram illustrating the backup operation under a sudden power outage (SPO) event;

[0018] Figure 7This is a timing diagram illustrating the operation of setting the completion sending time in a pre-programmed state according to an example embodiment;

[0019] Figure 8 This is a timing diagram illustrating the operation of setting the completion sending time within a reprogrammed state according to an example embodiment;

[0020] Figure 9 This is a timing diagram illustrating the operation of completing the sending time according to the settings of the example embodiment;

[0021] Figure 10 This is a diagram illustrating the backup size based on the completion time of sending according to an example embodiment;

[0022] Figure 11 This is a flowchart illustrating a method of operating a storage device according to an example embodiment;

[0023] Figure 12 This is a flowchart illustrating a backup method for a storage device according to an example embodiment;

[0024] Figure 13 This is a flowchart illustrating a method for setting the transmission timing of a storage device according to an example embodiment;

[0025] Figure 14 This is a flowchart illustrating a method for verifying the programming state of a storage device according to an example embodiment;

[0026] Figure 15 This illustrates a model based on an example embodiment. Figure 14 A flowchart illustrating the method of verifying programming status to execute write commands;

[0027] Figure 16 This illustrates a model based on an example embodiment. Figure 14 A flowchart illustrating the method for completing commands by verifying programming status;

[0028] Figure 17 This is a flowchart illustrating a method for setting the transmission timing of a storage device according to an example embodiment; and

[0029] Figure 18 This is a block diagram of a storage device according to an example embodiment. Detailed Implementation

[0030] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0031] Figure 1 This is a block diagram illustrating a storage system according to an example embodiment.

[0032] refer to Figure 1The storage system 1000 according to the example embodiment may include a host device 1100 and a storage device 1200. For example, the storage system 1000 may be a computing system configured to process various types of information, such as a personal computer (PC), a laptop computer, a server, a workstation, a tablet PC, a smartphone, etc.

[0033] The host device 1100 can be configured to control the overall operation of the storage device 1200. The host device 1100 can generate commands, control the storage device 1200 based on the commands, or instruct the storage device 1200 to perform the required operations.

[0034] Host device 1100 may include a submission queue SQ and a completion queue CQ.

[0035] The commit queue SQ can be used by host device 1100 to commit commands to be executed in storage device 1200. For example, the commit queue SQ can be implemented as a circular buffer of a certain slot size. When a new command is available, host device 1100 can update the tail doorbell, a register used to manage the commit queue SQ. Storage device 1200 can identify the new command based on the update via the tail pointer. Storage device 1200 can fetch commit queue entries from the commit queue SQ sequentially and execute commands based on these fetches.

[0036] The Completion Queue (CQ) can publish the status of completed commands. For example, the Completion Queue (CQ) can be implemented as a circular buffer of a specific slot size. After a completion command is executed, storage device 1200 can locate the next empty completion queue entry via the tail pointer of the completion queue and create and publish the completion entry. Host device 1100 can process completion queue entries indicating available completion queue (CQ) slots and then update the completion queue (CQ) head pointer. Host device 1100 can process completion queue entries via the completion queue head pointer. When the head pointer position changes, host device 1100 can notify storage device 1200 of the new position via a head doorbell.

[0037] Storage device 1200 may include storage controller 1210, non-volatile memory (NVM) 1220 and buffer memory 1230.

[0038] The storage controller 1210 can be configured to control the non-volatile memory 1220 and the buffer memory 1230 according to commands or controls from the host device 1100. The storage controller 1210 can write data to or read data stored in the non-volatile memory 1220 based on requests from the host device 1100. For example, the storage controller 1210 can be configured to receive a write command for the non-volatile memory 1220 from the host device 1100 and control the programming of write data corresponding to the write command into the non-volatile memory 1220.

[0039] Storage controller 1210 can schedule the processing order of commands received from host device 1100. Storage controller 1210 can store commands based on scheduling in a command queue (CMDQ). The command queue (CMDQ) can temporarily store (e.g., buffer) commands retrieved from the host. For example, the command queue (CMDQ) can be implemented as a circular buffer of a specific slot size.

[0040] The non-volatile memory 1220 can store data or transfer stored data to the memory controller 1210 under the control of the memory controller 1210. For example, the non-volatile memory 1220 can be a NAND flash memory device, but the example embodiment is not limited thereto.

[0041] In an example embodiment, the non-volatile memory 1220 can be provided as a plurality of non-volatile memories 1220, and the plurality of non-volatile memories 1220 can be connected to the storage controller 1210 through a plurality of channels and a plurality of ways respectively connected to the plurality of channels. The storage controller 1210 can access the plurality of non-volatile memories 1220 through the plurality of channels and the plurality of ways. Furthermore, the storage controller 1210 can perform processing on the plurality of non-volatile memories 1220 in parallel by generating and / or setting a stripe policy.

[0042] Buffer memory 1230 is a data buffer used for data exchange between storage device 1200 and host device 1100 connected to storage device 1200. Write data provided from host device 1100 or data read from non-volatile memory 1220 can be buffered (e.g., temporarily stored) in buffer memory 1230.

[0043] When a write request is made by host device 1100, buffer memory 1230 can buffer the write data to be stored (e.g., programmed) in non-volatile memory 1220. The term "buffer" refers to the operation in which storage controller 1210 stores write data corresponding to a write command in buffer memory 1230, and can also be considered as the operation in which storage controller 1210 registers cache entries in buffer memory 1230. Alternatively, when a read request is made by host device 1100 and data existing in non-volatile memory 1220 is cached, buffer memory 1230 can support the caching function of directly providing the cached data to host device 1100.

[0044] For example, buffer memory 1230 can be a volatile memory, such as DRAM, SRAM, etc., and can be implemented as synchronous DRAM to provide sufficient buffering performance.

[0045] The following section will describe an example of the storage controller 1210 in more detail.

[0046] In an example embodiment, the memory controller 1210 may manage or control programming operations on multi-bit cells included in each of a plurality of non-volatile memories 1220. For example, a multi-bit cell may include a multi-level cell (MLC), a three-level cell (TLC), and / or a four-level cell (QLC), and may include cells capable of storing more bits in a single cell than a QLC. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0047] In an example embodiment, the storage controller 1210 can program written data or multi-bit data into the non-volatile memory 1220 using a reprogramming scheme. The reprogramming scheme is a scheme that programs the same data N times, where N is a positive integer. For example, N can be a predetermined value.

[0048] The storage controller 1210 can store data in the buffer memory 1230 before executing the reprogramming scheme and retain the data stored in the buffer memory 1230 until the reprogramming scheme is completed (e.g., after N programming operations).

[0049] A reprogramming scheme can be executed through preprogramming and reprogramming operations. Preprogramming and / or reprogramming operations can be performed once or multiple times. The total number of preprogramming and reprogramming operations can be N, where N is a positive integer. The storage controller 1210 can preprogram the write data into multiple non-volatile memories 1220. After preprogramming is complete, the storage controller 1210 can reprogram the write data into the multiple non-volatile memories 1220.

[0050] In an example embodiment, when a power failure event such as SPO is detected during programming operations, the storage controller 1210 can back up buffered write data to non-volatile memory 1220.

[0051] In an example embodiment, state group data (or digest data) indicating state information of the pre-programmed data can be generated during (or after) the pre-programming operation.

[0052] When generating state group data, the storage controller 1210 according to the example embodiment can back up (or dump) the state group data under events occurring during the period between the completion of the pre-programming operation and the execution of the reprogramming operation of the SPO. The storage controller 1210 can restore the written data based on the backed-up state group data and perform the reprogramming operation based on the restored data.

[0053] In an example embodiment, the storage controller 1210 can be configured to dynamically set or adjust the completion transmission time within the cycle of a write command to be processed based on the reprogramming scheme described above. For example, the storage controller 1210 can retrieve a command from the commit queue SQ included in the host device 1100 and send a completion signal indicating the completion of the command to the host device 1100 to execute the command completion. The tail pointer of the completion queue CQ can be moved by the completion signal sent from the storage controller 1210. The storage controller 1210 can take various types of information into account when adjusting the completion transmission time.

[0054] In an example embodiment, the storage controller 1210 may include a programming status monitor 1213, a device status monitor 1214, and a completion manager 1215.

[0055] The programming status monitor 1213 can be configured to monitor the programming status of write commands and obtain programming status information (PSI) indicating the programming status. The programming status obtained by the programming status monitor 1213 can be defined in various ways.

[0056] In an example embodiment, the programming state may indicate a single processing stage among multiple processing stages of a write command. A processing stage may correspond to a unit operation executed by storage device 1200 within the cycle of a write command to process the write command generated from host device 1100.

[0057] For example, the processing stage corresponding to the unit operation may include at least one of the following stages: a write command retrieval stage, a buffering stage for the buffer memory 1230 for input data, a stage for transferring write data for a pre-programming operation to the non-volatile memory 1220, a pre-programming stage, a stage for transferring write data for a reprogramming operation to the non-volatile memory 1220, or a reprogramming stage. For example, an exemplary processing stage may correspond to a unit operation for a reprogramming operation for a write command performed by the storage device 1200.

[0058] In an example embodiment, the programming state can indicate a single processing sequence among multiple processing sequences, each of which includes one or more processing stages. For example, each processing sequence may include multiple processing stages, and the processing stages may correspond to the unit operations described above. Processing sequences can be defined based on the required backup size for each of the processing sequences. For example, some processing sequences may be set or defined to have the same backup size or different backup sizes.

[0059] In an example embodiment, the programming state can indicate the number of pathways activated in each of the processing sequences of a write command. For example, the number of pathways activated in each processing sequence can be set or defined based on a striping strategy.

[0060] The programming status monitor 1213 can obtain programming status information PSI indicating the programming status according to the above embodiment, and provide the programming status information PSI to the completion manager 1215.

[0061] Device status monitor 1214 can be configured to monitor storage device 1200 and obtain device status information (DSI) indicating the settings and current status of storage device 1200. The device status information (DSI) obtained by device status monitor 1214 can be defined in various ways.

[0062] In an example embodiment, the device status information (DSI) may include at least one of the following: the maximum queue depth of the command queue (CMDQ), the queue depth of the command queue (CMDQ) used for writing commands at any given time (e.g., the current queue depth), or the size of the write command. The maximum queue depth may indicate the maximum number of commands that can be stored in the command queue (CMDQ). The current queue depth may indicate the number of commands currently stored in the command queue (CMDQ). The size of data transferred from the host device 1100 to the storage device 1200 may be defined based on the current queue depth and the size of the write command.

[0063] The device status monitor 1214 can obtain device status information DSI according to the above embodiment and provide the device status information DSI to the completion manager 1215.

[0064] The completion manager 1215 can be configured to send a completion signal to the host device 1100 indicating the completion of a command from the submission queue SQ based on at least one of programming status information PSI provided from programming status monitor 1213 or device status information DSI provided from device status monitor 1214.

[0065] In an example embodiment, the completion manager 1215 can dynamically set, determine, or adjust the time at which a command is sent upon completion. Taking into account the processing stages defined by the programming state, the processing sequence, the number of paths activated in each stage or sequence, and / or the device status information (DSI), the completion manager 1215 can set an optimal completion sending time to reduce backup size under SPO events.

[0066] Initially, the completion transmission time can be set to the time after the write data corresponding to the write command has been buffered in buffer memory 1230 and before storage device 1200 begins full-scale programming operations. Upon receiving a completion signal, host device 1100 can be confident that storage device 1200 has at least guaranteed the write data corresponding to the write command. For example, storage device 1200 should guarantee that the write data stored in buffer memory 1230 (e.g., data to be programmed) has been successfully backed up to non-volatile memory 1220.

[0067] According to the above embodiment, the completion manager 1215 can set the completion sending time to any processing sequence that needs to be backed up when an SPO occurs after buffering. For example, the completion manager 1215 can set the sending time to a processing sequence that needs to be backed up when an SPO occurs after buffering. The completion manager 1215 can send completion in the programming state corresponding to the last processing stage within the processing sequence that is set to send time. Therefore, even if an SPO occurs during a processing sequence that needs to be backed up, a completion signal can be sent in the last programming state, so that the storage device 1200 does not need to guarantee the data to be programmed. As a result, the backup size of the processing sequence can be reduced.

[0068] In an example embodiment, the completion manager 1215 can set the sending time for any processing stage following a programming stage (e.g., a pre-programming stage, a reprogramming stage) that may be included in the processing stages of the processing sequence. For example, once the programming stage ends, the completion manager 1215 can send a completion signal indicating the completion of the command. Therefore, even if an SPO occurs during the processing sequence, a completion signal can be sent after the data has been programmed through at least the programming stage, so that the storage device 1200 does not need to guarantee the data to be programmed. As a result, the backup size of the processing sequence can be reduced.

[0069] The completion manager 1215 can dynamically set the send time to significantly reduce the backup size, and the completion manager 1215 can send a completion signal to the host device 1100 according to the set send time. The completion manager 1215 can check whether the current time is the set send time for completion based on the programming status information PSI, and can send a completion signal when the current time matches the send time.

[0070] Furthermore, when the processing sequence indicated by the programming status matches the set transmission time, the completion manager 1215 does not need to guarantee the data. Therefore, the completion manager 1215 can omit the backup for that processing sequence.

[0071] The aforementioned storage system 1000 can reduce the backup size when an SPO occurs by setting the completion time of transmission to the optimal time via the storage device 1200.

[0072] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of an example storage controller 1210. In the following text, [the following will omit the reference to the storage controller 1210]. Figure 1 A detailed description of overlapping configurations.

[0073] refer to Figure 2 The storage controller 1210 according to an example embodiment may include a central processing unit (CPU) 1211, a power-loss protection (PLP) circuit 1212, a programming status monitor 1213, a device status monitor 1214, a completion manager 1215, a host interface (I / F) 1216, a programming manager 1217, a buffer manager 1218, and a memory interface 1219. Components within the storage controller 1210 can be connected via a system bus.

[0074] CPU 1211 may include a processing unit such as a microprocessor. CPU 1211 can control the overall operation of memory controller 1210. CPU 1211 can execute firmware for driving memory controller 1210. For example, CPU 1211 can execute various types of firmware loaded in code memory, not explicitly shown (but implied).

[0075] In an example embodiment, at least one of the programming status monitor 1213, device status monitor 1214, completion manager 1215, or programming manager 1217 may be provided as a software module. The CPU 1211 may execute the software module corresponding to the programming status monitor 1213, device status monitor 1214, completion manager 1215, and / or programming manager 1217 to perform the operation of the storage controller 1210 of this application. Alternatively, the CPU 1211 may control at least one of the programming status monitor 1213, device status monitor 1214, completion manager 1215, or programming manager 1217.

[0076] In an example embodiment, CPU 1211 can control device status monitor 1214 to obtain device status information, control programming status monitor 1213 to obtain programming status information, or control completion manager 1215 to set the command completion sending time. CPU 1211 can execute command completion based on the set sending time.

[0077] In an example embodiment, CPU 1211 may include multiple cores. Each of the multiple cores may be implemented as a separate processor core. The multiple cores may include host cores, flash translation layer (FTL) cores, and NAND cores.

[0078] A host core can be defined as a core within a storage device that performs operations related to the Host Interface Layer (HIL). For example, a host core can handle requests input from the host via host interface 1216. For instance, a host core can manage requests from host devices (e.g.,...) via command queues (CMDQ). Figure 1 The command received by 1100 in the middle.

[0079] An FTL core can be defined as a core within a storage device that performs operations related to the FTL. For example, an FTL core can control a NAND core, allowing read, write, or erase operations to be performed by the non-volatile memory based on requests received from the host core. Alternatively, an FTL core can also use the FTL to perform address mapping operations that map logical block addresses (LBAs) sent from the host to physical block addresses (PBAs) (the physical locations of the non-volatile memory).

[0080] A NAND core can be defined as a core within a storage device that performs operations related to the Flash Memory Interface Layer (FTL). For example, a NAND core can control memory interface 1219 to perform operations on non-volatile memory under the control of an FTL core. For instance, a NAND core can control memory interface 1219 based on a queue for controlling the non-volatile memory. Commands for controlling the non-volatile memory can be queued.

[0081] PLP circuit 1212 can monitor the external power supply and detect power failure events such as SPO. When SPO occurs, PLP circuit 1212 can detect SPO and generate a detection signal based on the detection and provide the detection signal to programming manager 1217.

[0082] Programming status monitor 1213 can obtain programming status information and provide it to completion manager 1215, and device status monitor 1214 can obtain device status information and provide it to completion manager 1215. Completion manager 1215 can set the command completion sending time by taking into account the processing stage, processing sequence, number of paths activated in each stage or sequence, and / or device status information defined in the programming status, and execute command completion based on the set sending time.

[0083] Host interface 1216 can provide host devices ( Figure 1 The interface between the host device (1100) and the storage controller 1210. The host device and the storage controller 1210 can be connected via a single interface among various standardized interfaces. Standard interfaces may include various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small (or System) Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), IEEE 1394, Universal Flash Memory (UFS), or card interfaces, but embodiments are not limited to these.

[0084] Programming manager 1217 can generate, set, and manage programming strategies for reprogramming operations. For example, the programming strategy may include the stripe strategy described above. When a detection signal of SPO is received from PLP circuit 1212, programming manager 1217 can pause the ongoing programming operation. Then, programming manager 1217 can control buffer manager 1218 to back up data stored in buffer memory to non-volatile memory via memory interface 1219.

[0085] In an example embodiment, when an SPO is detected during a preprogramming or reprogramming operation, the programming manager 1217 can control the buffer manager 1218 to back up the write data to be preprogrammed or reprogrammed to non-volatile memory.

[0086] In an example embodiment, when there is a waiting phase between a pre-programming operation and a reprogramming operation, and the SPO occurs during the waiting phase, the programming manager 1217 can control the buffer manager 1218 to back up the state group data. Furthermore, the programming manager 1217 can restore the written data based on the backed-up state group data and the pre-programmed data.

[0087] The buffer manager 1218 can control read and write operations to the buffer memory. For example, the buffer manager 1218 can buffer write or read data in the buffer memory under the control of the CPU 1211 or the programming manager 1217. When a SPO occurs, the buffer manager 1218 can buffer the write data corresponding to the programming operation at the time of the SPO in the buffer memory.

[0088] In an example embodiment, when an SPO occurs during a preprogramming operation, the buffer manager 1218 may buffer the write data to be preprogrammed in a buffer memory. In an example embodiment, when an SPO occurs after the preprogramming operation is complete, the buffer manager 1218 may buffer the status group data in a buffer memory. In an example embodiment, when an SPO occurs during a reprogramming operation, the buffer manager 1218 may back up the write data to be reprogrammed to non-volatile memory.

[0089] In the example embodiment, when the completion send time is set by the completion manager 1215 to a time after any programming stage (e.g., a pre-programming stage or a reprogramming stage), the buffer manager 1218 does not back up the write data to be programmed before the set send time. This is because the storage controller 1210 is not required to guarantee the write data to be programmed before the command completion has been executed. Therefore, the backup size for SPOs occurring before the completion signal is sent can be reduced.

[0090] The memory interface 1219 can provide an interface between the memory controller 1210 and the non-volatile memory. For example, data processed by the CPU 1211 can be stored in the non-volatile memory through the memory interface 1219. For example, write data to be backed up can be backed up to the non-volatile memory through the memory interface 1219.

[0091] According to the above embodiment, the storage controller 1210 can set the completion transmission time to reduce the backup size when an SPO occurs before the completion transmission signal is sent.

[0092] Figure 3 According to the example embodiment Figure 1 Block diagram of non-volatile memory 1220.

[0093] refer to Figure 3The non-volatile memory 1220a may include a memory cell array 1221, a row decoder 1222, a page buffer circuit 1223, a control logic circuit 1224, and a voltage generation circuit 1225. Although not explicitly stated... Figure 3 As explicitly shown, the non-volatile memory 1220a may also include data input / output circuitry or input / output interfaces. The non-volatile memory 1220a may also include components such as column logic, a pre-decoder, a temperature sensor, a command decoder, or an address decoder. The non-volatile memory 1220a may be... Figure 1 One of the multiple non-volatile memories 1220 shown.

[0094] The memory cell array 1221 may include multiple memory blocks BLK0 to BLKm-1, where m is a positive integer. Each of the multiple memory blocks BLK0 to BLKm-1 may include multiple memory cells. The multiple memory blocks BLK0 to BLKm-1 may be included in a single memory plane, but the example embodiment is not limited thereto. The memory cell array 1221 can be connected to the page buffer circuit 1223 via bit lines BL, and can be connected to the row decoder 1222 via word lines WL, serial select lines SSL, and ground select lines GSL.

[0095] In an example embodiment, the memory cell array 1221 may include a three-dimensional memory cell array 1221. The three-dimensional memory cell array may be configured with multiple levels and may have word lines or bit lines shared between levels.

[0096] The row decoder 1222 can select one of the memory blocks in the memory cell array 1221 in response to the row address CADDR. The row decoder 1222 can select one of the word lines of the selected memory block in response to the row address CADDR. The row decoder 1222 can deliver a voltage VWL, corresponding to the operating mode, provided by the voltage generation circuit 1225, to the word line of the selected memory block. During programming operations, the row decoder 1222 can deliver programming and verification voltages to the selected word line and pass voltages to unselected word lines. During read operations, the row decoder 1222 can deliver read voltages to the selected word line and pass read voltages to unselected word lines.

[0097] Page buffer circuit 1223 may include multiple page buffers PB0 to PBn-1, where n is a positive integer. The multiple page buffers PB0 to PBn-1 may be connected to memory cells via multiple bit lines BL. Page buffer circuit 1223 may select at least one bit line among the multiple bit lines BL in response to a column address. Page buffer circuit 1223 may operate as a write driver or a sense amplifier depending on the operating mode. For example, page buffer circuit 1223 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line during a programming operation. Page buffer circuit 1223 may sense the current or voltage of the selected bit line during a read operation to sense the data stored in the memory cell.

[0098] The control logic circuit 1224 can control the overall operation within the non-volatile memory 1220a. The control logic circuit 1224 can output various control signals in response to the control signal CTRL, the command CMD, and / or the address ADDR for programming data into the memory cell array 1221, reading data from the memory cell array 1221, or erasing data stored in the memory cell array 1221. For example, the control logic circuit 1224 can output a voltage control signal VTG_C, an address CADDR, etc.

[0099] In an example embodiment, the control logic circuit 1224 may output control signals for programming multi-bit data based on received control signals CTRL, command CMD, and / or address ADDR. For example, the control logic circuit 1224 may output control signals for pre-programming and reprogramming operations, output control signals for backing up state group data, or output control signals for reading pre-programmed or reprogrammed multi-bit data.

[0100] The voltage generation circuit 1225 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal VTG_C provided to the voltage generation circuit 1225. For example, the voltage generation circuit 1225 can generate programming voltage, reading voltage, and programming verification voltage as word line voltage VWL. For example, the programming voltage can be generated using an incremental step pulse programming (ISPP) scheme.

[0101] In programming operations involving multi-bit data, the voltage generation circuit 1225 can generate a pre-programming verification voltage for pre-programming operations and a reprogramming verification voltage for reprogramming operations. The pre-programming verification voltage can be lower than the reprogramming verification voltage.

[0102] Figure 4 This illustrates an example embodiment. Figure 3A circuit diagram of an example memory block within the memory cell array 1221 is provided. For ease of description, an example is provided where a single memory block comprises four strings STR1 to STR4.

[0103] refer to Figure 4 The memory block BLKa may include multiple strings STR1 to STR4 vertically stacked (i.e., in the Z-axis direction) on a substrate. Each of the multiple strings STR1 to STR4 may be positioned in a first direction (X-axis direction) and a second direction (Y-axis direction).

[0104] Strings in the same column from STR1 to STR4 can be connected to the same bit line. For example, the first string STR1 and the second string STR2 can be connected to the first bit line BL1, and the third string STR3 and the fourth string STR4 can be connected to the second bit line BL2.

[0105] Each of the multiple strings STR1 through STR4 may include multiple cell transistors. Each of the multiple cell transistors may be a charge-trap flash (CTF) memory cell, but the example embodiment is not limited thereto. The multiple cell transistors may be stacked in a third direction (Z-axis direction).

[0106] Multiple strings STR1 through STR4 can be connected together to a common source line CSL. For example, as shown below. Figure 4 As shown, the common source line CSL can be publicly connected to the lower ends of multiple strings STR1 to STR4. However, this is just an example; it is sufficient for the common source line CSL to be electrically connected to the lower ends of strings STR1 to STR4, and it is not limited to being physically located at the lower ends of strings STR1 to STR4. In the following description, for ease of description, the structure and configuration of the strings will be described based on the first string STR1. The other strings STR2, STR3, and STR4 may have a similar structure to the first string STR1, and their detailed descriptions will be omitted.

[0107] Multiple unit transistors can be connected in series between the first bit line BL1 and the common source line CSL. For example, multiple unit transistors may include gate-induced drain leakage (GIDL) transistors GDT1 and GDT2, a string select transistor SST, memory cells MC1 to MC5, a dummy memory cell DMC, and a ground select transistor GST.

[0108] The first GIDL transistor GDT1 may be located at the bottom end of the string STR1. For example, the first GIDL transistor GDT1 may be connected to the common source line CSL at the bottom end of the string STR1. However, this is only an example, and the example embodiment is not limited thereto. The gate of the first GIDL transistor GDT1 may be connected to the first GIDL line GIDL1a.

[0109] The second GIDL transistor GDT2 can be positioned at the top of string STR1, but it can also be positioned between string select transistor SST and memory cell MC5. For example, the second GIDL transistor GDT2 can be connected to the first bit line BL1 via string select transistor SST. The gate of the second GIDL transistor GDT2 can be connected to the second GIDL line GIDL2a.

[0110] exist Figure 4 In the diagram, GIDL transistors GDT1 and GDT2 are shown as being provided at the lower and upper ends of string STR1, respectively. However, this is merely an example. In some embodiments, GIDL transistors may be provided only at the upper end of string STR1 or only at the lower end of string STR1.

[0111] A single string select transistor SST can be positioned at the top of the string STR. The string select transistor SST can be connected to the first line BL1 at the top of the string STR1. The gate of the string select transistor SST can be connected to the string select line SSLa. However, this is merely an example. In some embodiments, multiple string select transistors connected in series can be provided between the first line BL1 and the second GIDL transistor GDT2.

[0112] A single ground select transistor GST can be provided between the dummy memory cell DMC and the first GIDL transistor GDT1. The gate of the ground select transistor GST can be connected to the ground select line GSLa. However, this is only an example. In some embodiments, multiple ground select transistors connected in series can be provided between the dummy memory cell DMC and the first GIDL transistor GDT1.

[0113] The first memory cell MC1 to the fifth memory cell MC5 can be connected in series between the serial select transistor SST and the dummy memory cell DMC. The gates of the first memory cell MC1 to the fifth memory cell MC5 can be connected to the first word line WL1 to the fifth word line WL5, respectively.

[0114] A single dummy memory cell (DMC) may be provided between the first memory cell MC1 and the first GIDL transistor GDT1. The gate of the dummy memory cell DMC may be connected to the dummy word line (DWL). However, this is only an example. In some embodiments, multiple dummy memory cells connected in series may be provided between the first memory cell MC1 and the first GIDL transistor GDT1. Alternatively, additional dummy memory cells may be provided between the string select transistor SST and the fifth memory cell MC5. Alternatively, additional dummy memory cells may be provided between memory cells MC1 through MC5. Alternatively, the dummy memory cell DMC may not be provided.

[0115] According to the example embodiment, a programming voltage can be applied to the gate of each of the first memory cells MC1 to the fifth memory cells MC5 via the first word line WL1 to the fifth word line WL5, and a pre-programming operation or a reprogramming operation can be performed by applying the programming voltage.

[0116] Figure 5 It is a diagram showing the data state before and after the programming and reprogramming operations according to the example embodiment.

[0117] refer to Figure 5 When programming begins, the storage device according to the example embodiment can pre-program (or coarsely program) multiple bits of data in a memory cell of non-volatile memory. For example, when the multiple bits of data are 4 bits (e.g., when the memory cell is a QLC), the pre-programmed memory cell may have a threshold voltage (Vth) corresponding to a single state among 16 threshold voltage states E0 and P1 to P15, as shown in the figure. The 16 threshold voltage states E0 and P1 to P15 may each correspond to 16 values ​​that the multiple bits of data may have. For example, the pre-programmed memory cell may correspond to one of the 16 threshold voltage states E0 and P1 to P15 based on the multiple bits of data value. The threshold voltage of the memory cell may fluctuate due to capacitive coupling between adjacent memory cells, resulting in an increase in the width of the threshold voltage distribution. Therefore, adjacent threshold voltage distributions may overlap each other.

[0118] The threshold voltage distribution of pre-programmed memory cells can be divided into multiple state groups. For example, the threshold voltage states corresponding to the erase state E0 and the programming states P1 to P15 can be divided into a first state group GR1 and a second state group GR2.

[0119] In an example embodiment, each of the state groups may include a different threshold voltage distribution, and the threshold voltage distributions of each of the state groups may not overlap with each other. For example, the first state group GR1 may include threshold voltage distributions corresponding to the erase state E0, the second programming state P2, the fourth programming state P4, the sixth programming state P6, the eighth programming state P8, the tenth programming state P10, the twelfth programming state P12, and the fourteenth programming state P14. The second state group GR2 may include threshold voltage distributions corresponding to the first programming state P1, the third programming state P3, the fifth programming state P5, the seventh programming state P7, the ninth programming state P9, the eleventh programming state P11, the thirteenth programming state P13, and the fifteenth programming state P15.

[0120] The number of state groups is merely an example, and the example implementation is not limited thereto.

[0121] Each state in a state group can be represented by state group data.

[0122] For example, when the threshold voltage distribution is divided into four state groups, the state group data can be 2 bits. Alternatively, the number of bits in the state group data can be less than the number of bits in the multi-bit data.

[0123] Preprogrammed multi-bit data can correspond to state group data indicating one of multiple state groups based on the data value. For example, multi-bit data corresponding to the erase state E0 can correspond to state group data indicating the first state group, and multi-bit data corresponding to the first programming state P1 can correspond to state group data indicating the second state group.

[0124] When an SPO occurs after the preprogramming operation is completed, the storage device can back up the state group data corresponding to the preprogrammed memory cell in the non-volatile memory. For example, when multiple bits of data corresponding to the first programming state P1 are preprogrammed, the storage device can back up the state group data indicating the second state group GR2 corresponding to the preprogrammed memory cell to the non-volatile memory.

[0125] When power is restored from an SPO, the storage device can recover multiple bits of data based on backed-up state group data. For example, the storage device can read multiple bits of data from pre-programmed memory cells based on state group data. As shown in the figure, even when there are overlapping regions in the threshold voltage distribution of the pre-programmed memory cells, the read operation performed on each state group based on the state group data can determine which threshold voltage distribution the overlapping region belongs to. Therefore, the reliability of the recovered multiple bits of data can be improved.

[0126] Storage devices can reprogram (or fine-program) multiple bits of data in memory cells based on recovered multiple bits of data. Programming multiple bits of data can be accomplished through a reprogramming operation. As shown in the figure, the width of the threshold voltage distribution in a memory cell can be reduced by performing a reprogramming operation.

[0127] The fluctuation range of the programming voltage used for reprogramming operations can be lower than that of the programming voltage used for preprogramming operations. For example, a storage device can perform a reprogramming operation based on injecting a programming voltage with a smaller fluctuation range.

[0128] Due to the variation in the programming voltage range, the increase in threshold voltage of a memory cell caused by a reprogramming operation may be less than the increase caused by a preprogramming operation. Therefore, the threshold voltage distribution based on a reprogramming operation is less affected by coupling, resulting in a narrower threshold voltage distribution and a reduced overlap area for the memory cell based on the reprogramming operation. Consequently, the reliability of multi-bit data can be improved when reading multi-bit data from a reprogrammed memory cell.

[0129] In an example embodiment, the reprogramming verification voltage used for reprogramming multi-bit data operations can be higher than the preprogramming verification voltage used for preprogramming multi-bit data operations. For example, the reprogramming verification voltage applied to any programming state during a reprogramming operation can be higher than the preprogramming verification voltage applied to any programming state during a preprogramming operation. For example, a preprogramming verification voltage corresponding to a threshold voltage below a desired threshold voltage can be used to perform a preprogramming operation. During a reprogramming operation, a reprogramming verification voltage higher than the preprogramming verification voltage can be used to program the memory cell to the desired threshold voltage.

[0130] although Figure 5 The example shows the threshold voltage state resulting from a single reprogramming operation, but the example embodiment is not limited to this. For example, several reprogramming operations can be performed to generate a finer threshold voltage.

[0131] Figure 6 This is a timing diagram illustrating an example of a backup operation in the case of SPO.

[0132] refer to Figure 6 In operation S110, the storage device can receive write commands from the host device. The storage device can retrieve write commands from the commit queue and enqueue them into the command queue included in the storage device.

[0133] In operation S120, the storage device can receive and store write data corresponding to a write command from the host device. For example, the storage device can access the host device's memory medium via direct memory access (DAM) and load the write data stored in the memory medium. The storage device can buffer the loaded write data in a buffer memory.

[0134] After the buffered data is written according to operation S120, the process proceeds to operation S130, where the storage device executes the command to complete. The storage device can send a completion signal to the host device, or write and publish a completion entry in the completion queue. After operation S130, the storage device can guarantee the buffered data is written.

[0135] The storage device can pre-program the data to be written to the non-volatile memory via operation S140, and can perform a reprogramming operation via operation S150. When an SPO occurs during operation S140 or operation S150, the storage device should back up the written data to the non-volatile memory to ensure the buffered written data.

[0136] Figure 7 This is a timing diagram illustrating the operation of setting the completion sending time in a pre-programmed state according to an example embodiment.

[0137] First refer to Figure 7 According to the example embodiment, the programming state can be defined as a processing stage or a processing sequence. The processing sequence can be defined based on the backup size, and each processing stage included in the processing sequence can be defined based on unit operations.

[0138] The storage device can receive write commands from the host device and buffer the write data by operating S210 and S220. Figure 6 Unlike the previous example, the storage device according to the example embodiment can set the completion transmission time to a time after the completion of any programming stage. A completion signal has not yet been transmitted in the first processing sequence SEQ1, and no backup is required in the first processing sequence SEQ1 (e.g., the backup size is 0). Operation S210 can be defined as the fetching stage of the write command, and operation S220 can be defined as the buffering stage of the write data.

[0139] The storage device can perform a pre-programming operation via the second processing sequence SEQ2. In an example embodiment, the second processing sequence SEQ2 may include operations S231 to S234.

[0140] In operation S231, the storage device can determine a striping strategy. In operation S232, the storage device can provide the write data to be pre-programmed to the non-volatile memory. In operation S233, the write data can be pre-programmed in the non-volatile memory. Operation S232 is the stage for transferring the write data, and operation S233 can be defined as the pre-programming stage. The duration of operation S233 can be tPROG1.

[0141] In operation S234, the storage device may send a completion signal indicating the completion of a command to the host device. For example, the time of sending the completion of the command according to the example embodiment may be included in the second processing sequence SEQ2, and may be a time after operation S233 is completed. When a completion signal is sent in the first processing sequence SEQ1, if an SPO occurs in the second processing sequence SEQ2, which includes a pre-programming phase, a backup of the write data for the entire buffer is required under the event of an SPO occurring in the second processing sequence SEQ2 (e.g., the backup size for the second processing sequence SEQ2 is the buffer data size).

[0142] According to the example embodiment, the completion time of transmission is set to operation S234, such that even if SPO occurs in the second processing sequence SEQ2, the storage device does not need to back up the written data. For example, the backup size is 0.

[0143] In an example embodiment, during operation S234, the storage device can check whether the current programming state (e.g., after the pre-programming stage is completed or the programming state in the second processing sequence SEQ2) matches the set transmission time based on programming state information. When the current programming state matches the set transmission time, the storage device can send a completion signal to the host device.

[0144] Then, the storage device can perform a reprogramming operation via the third processing sequence SEQ3.

[0145] The storage device according to the above embodiments can reduce the backup size when an SPO occurs by setting the command completion sending time to the second processing sequence SEQ2 (e.g., a processing sequence requiring backup of the entire buffer data in an example where the processing sequence is executed after the completion signal is sent). Furthermore, compared to the case where the completion signal is sent after the second processing sequence SEQ2, the latency caused by the completion delay can be reduced.

[0146] Figure 8 This is a timing diagram illustrating the operation of setting the completion sending time within a reprogrammed state according to an example embodiment. In the following text, [the details will be omitted]. Figure 7 A detailed description of overlapping configurations.

[0147] refer to Figure 8 The storage device can receive write commands from the host device and buffer the write data by operating S310 and S320. Figure 7 Unlike the example embodiment, the storage device can set the completion time of transmission as the third processing sequence SEQ3.

[0148] The storage device can perform a pre-programming operation via the second processing sequence SEQ2, and a reprogramming operation via the third processing sequence SEQ3 after the pre-programming operation is completed. In an example embodiment, the third processing sequence SEQ3 may include operations S331 to S333.

[0149] In operation S331, the storage device can provide the write data to be reprogrammed to the non-volatile memory. In operation S332, the write data can be reprogrammed in the non-volatile memory. Operation S331 is the stage for transferring write data, and operation S332 can be defined as the reprogramming stage. Operation S332 can be executed for a duration tPROG2.

[0150] In operation S333, the storage device may send a completion signal indicating the completion of a command to the host device. For example, according to the example embodiment, the time of sending the completion of the command is included in the third processing sequence SEQ3, and is a time after operation S332 is completed. When a completion signal is sent in the first processing sequence SEQ1 or the second processing sequence SEQ2, if an event of SPO occurs in the third processing sequence SEQ3, which includes the reprogramming phase, a backup of the written data for the entire buffer is required.

[0151] According to the example embodiment, the completion time of transmission is set to operation S333, such that even if an SPO occurs in the third processing sequence SEQ3, the storage device does not need to back up the written data. For example, the backup size is 0.

[0152] In the example embodiment, during operation S333, the storage device can check whether the current programming state (e.g., after the reprogramming phase is completed or the programming state in the third processing sequence SEQ3) matches the set transmission time using programming state information. When the current programming state matches the set transmission time, the storage device can send a completion signal to the host device.

[0153] The storage device according to the above embodiments can reduce the backup size when an SPO occurs by setting the command completion sending time to the third processing sequence SEQ3 (e.g., a processing sequence that requires backup of the entire buffer data in an example where the processing sequence is executed after the completion signal is sent). Furthermore, compared to the case where the completion signal is sent after the third processing sequence SEQ3, the latency caused by the completion delay can be reduced.

[0154] Figure 9 This is a timing diagram illustrating the operation of completing the sending time according to the settings of the example embodiment.

[0155] refer to Figure 9 The storage device can process write commands through the first processing sequence SEQ1 to the fourth processing sequence SEQ4. According to an example embodiment, the storage device may have a waiting phase (third processing sequence SEQ3) prior to the fourth processing sequence SEQ4. When an SPO occurs in the third processing sequence SEQ3, the storage device can back up the state group data and restore the write data based on the backed-up state group data and pre-programmed data through the second processing sequence SEQ2.

[0156] In an example embodiment, the storage device may set the completion time of transmission to one of the second processing sequences SEQ2 to the fourth processing sequence SEQ4. The size of the buffer memory in the processing sequences (e.g., the size of the data stored in the buffer memory) may be the same or different. The size of the buffer memory may correspond to the backup size. According to an example embodiment, when performing a backup based on state group data in the third processing sequence SEQ3, the backup size in the third processing sequence SEQ3 may be smaller than the size of the buffer memory.

[0157] The storage device may also set one of the processing sequences SEQ2 to SEQ4, wherein the backup size is the same as the size of the buffer memory, as the completion transmission time. When the programming state matches the set transmission time (e.g., the corresponding processing sequence), the storage device may send a completion signal to the host device. For example, the storage device may send a completion signal in the programming state corresponding to the last processing stage in the corresponding processing sequence.

[0158] Furthermore, if the corresponding processing sequence coincides with the transmission time, the storage device can omit backups for SPOs occurring within that processing sequence. Therefore, when an SPO occurs, the backup size can be reduced.

[0159] The above-described embodiments can be performed based on the storage controller, non-volatile memory, and / or buffer memory according to the above embodiments. Figures 6 to 9 The operation of storage devices.

[0160] Figure 10 This is a diagram illustrating the backup size based on the completion time of sending, according to an example embodiment.

[0161] refer to Figure 10The buffer size, backup size for case 1, and backup size for case 2 are compared and shown for each of the second processing sequences SEQ2 to the fourth processing sequences SEQ4. Case 1 is the case where the command is completed in the first processing sequence SEQ1, and case 2 is the case where the command is completed in the second processing sequence SEQ2. The buffer size is the size of the buffer memory.

[0162] For both cases 1 and 2, the second processing sequence SEQ2 is executed. Figures 5 to 9 The pre-programmed operation is performed and executed in the fourth processing sequence SEQ4. Figures 5 to 9 The reprogramming operation. The third processing sequence SEQ3 is the stage executed between the pre-programming operation and the reprogramming operation. In the third processing sequence SEQ3, it is also possible to perform operations based on the division of the programming state into state groups (e.g., Figure 5 Recovery of state group data (GR1, GR2).

[0163] Regardless of the programming or verification voltage, the required buffer size in the second processing sequence SEQ2 and the fourth processing sequence SEQ4 can be set based on a striping strategy according to the number of channels, paths, planes, page size, etc. For example, each processing sequence buffers the same multi-bit data as the programming, so that the required buffer size for each processing sequence is the same as V1.

[0164] In the case of the third processing sequence SEQ3, V2, which may be the same as or different from V1, can be defined as the buffer size according to the example embodiment. V2 may be the buffer size required during the waiting phase after the pre-programming operation and before the reprogramming operation.

[0165] According to Case 1, when an SPO occurs in each processing sequence, the backup size is the buffer size. For example, the backup size for the second processing sequence SEQ2 and the fourth processing sequence SEQ4 is V1, which is the same as the buffer size. In the case of the third processing sequence SEQ3, when using the state group data described above, it is also possible not to perform backups for all buffer sizes. The backup size can be V3, which is smaller than the buffer size V2. When the state group data is not used, the backup size can be V2, which is the same as the buffer size.

[0166] According to scenario 2, the programming phase to be performed in the second processing sequence SEQ2 is the phase prior to sending the completion signal. Therefore, no guarantee is needed for the data to be backed up. As a result, the backup size for the second processing sequence SEQ2 is 0.

[0167] Unlike the implementation described above, a completion signal can be sent in the third processing sequence SEQ3. Even if an SPO occurs in the processing sequence and the previous processing sequence, the backup size can be 0. As a result, the backup size can be reduced by setting an optimal completion sending time.

[0168] Figure 11 This is a flowchart illustrating a method of operating a storage device according to an example embodiment.

[0169] refer to Figure 11 In operation S1010, the storage device can receive write commands from the host device. The storage device can retrieve write commands from the commit queue included in the host device. The storage device can manage the received write commands through the command queue.

[0170] In operation S1020, the storage device can obtain programming status information indicating the programming status of a write command and device status information of the storage device. In an example embodiment, operation S1020 can be repeated periodically or non-periodically. In an example embodiment, operation S1020 can be performed whenever there is a change in the information that may be included in the programming status information and / or device status information.

[0171] In operation S1030, the storage device may send a completion signal indicating the completion of a write command to the host device based on at least one of programming state information or device state information. In an example embodiment, the storage device may consider information related to the programming state (e.g., processing stage, processing sequence, etc.) and the device state information to set the command completion sending time to reduce the backup size. The storage device may check whether the current time matches the sending time based on the programming state information. When the current time matches the sending time, the storage device may send a completion signal.

[0172] According to the above embodiments, the optimal completion time for sending can be set by operating the storage device to reduce the backup size when an SPO occurs.

[0173] Figure 12 This is a flowchart illustrating a backup method for a storage device according to an example embodiment.

[0174] refer to Figure 12 In operation S1110, the storage device can detect the SPO (Special Purpose) of the storage device. For example, the storage device can detect the SPO by monitoring external power. When no SPO is detected, the SPO detection operation in operation S1110 can be repeated.

[0175] When an SPO is detected during any processing sequence via operation S1110, the process proceeds to operation S1120, where the storage device checks whether the processing sequence in which the SPO was detected matches the sending time set for the completion of the command.

[0176] When the processing sequence matches the sending time in operation S1120, the process proceeds to operation S1130, where the storage device omits backups for the processing sequence. For example, command completion can be performed within the processing sequence, eliminating the need for data guarantees for that sequence. Therefore, backups can be omitted from the storage device's scope.

[0177] When the processing sequence and transmission time do not match in operation S1120, the process proceeds to operation S1140, where the storage device checks whether a completion signal has been sent. If a completion signal has been sent, for example, when a completion signal has been sent in a processing sequence preceding the processing sequence in which the SPO was detected ("Yes" in operation S1140), the process proceeds to operation S1150, where the storage device performs a backup of the SPO.

[0178] If a completion signal has not yet been sent (No in operation S1140), the process proceeds to operation S1160, where the storage device backup can be omitted.

[0179] Based on the backup method described above, backups can be omitted if a completion signal is not sent. As a result, the backup size can be reduced when an SPO is detected.

[0180] Figure 13 This is a flowchart illustrating a method for setting the transmission timing of a storage device according to an example embodiment.

[0181] refer to Figure 13 In operation S1210, the storage device can select a single processing sequence from each processing stage that includes a write command, wherein the backup size is the same as the buffer memory size. For example, operation S1210 can be used to select the processing sequence that requires a backup of the entire write data stored in the buffer memory.

[0182] In operation S1220, the storage device can set the selected single processing sequence as the time for sending the command completion signal. The storage device can then send a completion signal within the processing sequence.

[0183] Figure 14 This is a flowchart illustrating a method for verifying the programming status of a storage device according to an example embodiment.

[0184] refer to Figure 14In operation S1310, the storage device can retrieve a write command from the host device's commit queue. In operation S1320, the storage device can monitor the programming status of the retrieved write command based on programming status information. The programming status information can indicate one of the processing stages and processing sequences used for the aforementioned write command operation. Monitoring enables the storage device to check the current programming status.

[0185] Figure 15 This illustrates a model based on an example embodiment. Figure 14 The flowchart shows the method of verifying programming status to operate the write command.

[0186] refer to Figure 15 During operation S1330a, the storage device can perform operations similar to those in... Figure 14 The operation corresponding to the current programming state checked in operation S1320. For example, the operation may correspond to one of the processing stages or processing sequences described above.

[0187] In operation S1340a, the storage device checks whether the current programming state is the final state. The final state may correspond to the final processing stage within the above processing sequence or the final processing sequence within the processing sequence used for the write command.

[0188] When the programming state is the final state, the process proceeds to operation S1350a, where the storage device can complete the write command operation. When the programming state is not the final state, the storage device can repeat operations S1330a to S1340a.

[0189] Figure 16 This illustrates a model based on an example embodiment. Figure 14 The flowchart shows the method for completing commands by verifying the programming status.

[0190] refer to Figure 16 During operation S1330b, the storage device can check in Figure 14 In operation S1320, the current programming status is checked to see if it matches the sending time for the completion settings.

[0191] When the current programming state matches the transmission time, the process proceeds to operation S1340b, where the storage device can send a completion signal to the host device. For example, operation S1340b can be performed only when the programming state matches the transmission time. When the programming state and the transmission time do not match, the storage device can repeat operation S1330b.

[0192] Figure 17 This is a flowchart illustrating a method for setting the transmission timing of a storage device according to an example embodiment.

[0193] refer to Figure 17In operation S1410, the storage device can compare a first data size and a second data size. The first data size is defined based on at least one of the depth of the command queue or the size of the write command, and may refer to the size of the data transferred from the host device to the storage device. Each of the processing sequences of write commands may require the second data size. For example, the second data size may be the minimum data size required to process the sequence of processing commands.

[0194] By operating S1410, the storage device can compare the size of the data transmitted in each processing sequence with the size of the data required to process each processing sequence.

[0195] In operation S1420, the storage device can set the transmission time based on one or more processing sequences that have a second data size less than or equal to the first data size. For example, in the processing sequences, only processing sequences with a sufficient size of data to be transmitted from the host device can be considered as the transmission time setting target.

[0196] When the size of the first data is smaller than the size of the second data, programming operations based on the processing sequence may result in waste equivalent to the size of the data that does not reach the processing capacity of the processing sequence. The storage device can reduce this waste by using the configuration method according to the embodiments described above. Furthermore, the storage device can also dynamically set the transmission time based on device status information.

[0197] Figure 18 This is a block diagram of a storage device 3000 according to an example embodiment.

[0198] refer to Figure 18 The storage device 3000 according to the example embodiment may include an auxiliary power supply 3100, a PLP circuit 3200, a storage controller 3300, a plurality of non-volatile memories 3400 and a buffer memory 3500.

[0199] The auxiliary power supply 3100 can supply accumulated energy to the storage device 3000 in the event of a SPO (Special Purpose) where external power is cut off. The storage device 3000 can use the energy from the auxiliary power supply 3100 to complete ongoing operations and perform data backup operations. The greater the amount of backup, the more energy may be required to accumulate in the auxiliary power supply 3100.

[0200] The PLP circuit 3200 can be configured to prevent power interruption to the storage device 3000. The PLP circuit 3200 can be implemented as an integrated circuit (IC), chip, or component. When external power is normally supplied, the PLP circuit 3200 can supply external power for use by the storage device 3000. When external power is interrupted, the PLP circuit 3200 can provide the output of an auxiliary power supply 3100 as power for use by the storage device 3000.

[0201] The PLP circuit 3200 can detect SPO events, such as the interruption of external power or a severe voltage drop. When an SPO event is detected, the PLP circuit 3200 can provide a power failure detection signal DET to the storage controller 3300. Additionally, the PLP circuit 3200 can switch the power supply for driving the storage device 3000 from the external power supply to the auxiliary power supply 3100.

[0202] The storage controller 3300 can be configured to control multiple non-volatile memories 3400 and buffer memories 3500 according to commands or controls from a host. For example, the storage controller 3300 can write data to or read data stored in the multiple non-volatile memories 3400 in response to a request from the host. The storage controller 3300 can provide commands, addresses, data, and control signals to the multiple non-volatile memories 3400 to access them.

[0203] The storage controller 3300 can set a completion transmission time according to the above embodiments, and send a completion signal to the host device based on the set transmission time. In the example embodiment, when an SPO is detected from the PLP circuit 3200 before the completion signal is sent to the host device based on the set transmission time, the storage controller 3300 may omit backing up the buffered write data to the non-volatile memory 3400.

[0204] Multiple non-volatile memories 3400 and buffer memories 3500 are related to the above. Figure 1 They are largely the same; detailed explanations are omitted.

[0205] The storage device 3000 according to the above embodiment can complete the transmission time setting in a way that can reduce the backup size, thereby reducing the dependency of the backup size and the capacity of the PLP circuit.

[0206] As described above, according to the example embodiment, a storage device and a method for reducing the amount of backups can be provided by setting a completion time for sending data.

[0207] Various aspects of the invention are described herein with reference to flowchart illustrations and / or block diagrams of methods and apparatus (systems) according to embodiments of the invention. It should be understood that the flowchart illustrations and / or block diagrams in the drawings illustrate the architecture, functionality, and / or operation of possible implementations of systems and methods according to various embodiments of the invention. In this respect, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function(s). In some alternative embodiments, the functions marked in the blocks may occur in a non-consecutive order. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagram and / or flowchart illustrations, and combinations of blocks in the block diagram and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0208] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, the storage device comprising: Non-volatile memory; and A storage controller configured to receive write commands for the non-volatile memory from a host device and to control the programming of write data corresponding to the write commands into the non-volatile memory. in: The storage controller is configured to send a completion signal indicating the completion of the write command to the host device based on at least one of programming status information indicating the programming status of the write command or device status information of the storage device.

2. The storage device according to claim 1, wherein: The programming state indicates a single processing stage among multiple processing stages of the write command.

3. The storage device according to claim 2, wherein: The plurality of processing stages include at least one of the following: a write command extraction stage, a write data buffering stage, a stage for transferring the write data for pre-programming operations to the non-volatile memory, a pre-programming stage, a stage for transferring the write data for reprogramming operations to the non-volatile memory, or a reprogramming stage.

4. The storage device according to claim 1, further comprising: A buffer memory configured to buffer the written data. in: The storage controller is configured to back up buffered write data to the non-volatile memory when a sudden power failure (SPO) is detected from the storage device.

5. The storage device according to claim 4, wherein: The programming state indicates a single processing sequence among a plurality of processing sequences, each of which includes a processing phase of the write command, and The plurality of processing sequences are defined based on the required backup size for each of the plurality of processing sequences.

6. The storage device according to claim 5, wherein: The storage controller is configured to set the single processing sequence having a backup size equal to the size of the buffer memory as the completion sending time of the write command among the plurality of processing sequences.

7. The storage device according to claim 1, wherein: The storage controller is configured to send a completion signal to the host device when the programming state matches a send time set for the completion of the write command.

8. The storage device according to claim 5, wherein: The storage controller is configured to omit backups for a single processing sequence when the single processing sequence matches a transmission time set for the completion of the write command.

9. The storage device according to claim 1, wherein: The device status information includes at least one of the following: the queue depth of the command queue for the write command at any time or the size of the write command.

10. The storage device according to claim 9, wherein: The storage controller is configured as follows: A first data size, defined based on at least one of the queue depth of the command queue or the size of the write command, is compared with a second data size required for each of the plurality of processing sequences of the write command; and The completion sending time of the write command is set based on one or more processing sequences among the plurality of processing sequences that have a second data size that is less than or equal to the first data size.

11. The storage device according to claim 1, wherein: The programming state indicates the number of pathways activated in each processing sequence of the write command.

12. A method of operating a storage controller of a storage device, the storage device comprising non-volatile memory, the method comprising: Receive write commands from the host device; Obtain programming status information indicating the programming status of the write command and device status information of the storage device; and Based on at least one of the programming status information or the device status information, a completion signal indicating the completion of the write command is sent to the host device.

13. The method according to claim 12, wherein: The programming state indicates a single processing stage among multiple processing stages of the write command, and The plurality of processing stages include at least one of the following: a write command extraction stage, a write data buffering stage, a stage for transferring the write data for pre-programming operations to the non-volatile memory, a pre-programming stage, a stage for transferring the write data for reprogramming operations to the non-volatile memory, or a reprogramming stage.

14. The method of claim 12, further comprising: Select a single processing sequence having a backup size equal to the size of the buffer memory from a processing sequence that includes multiple processing stages of the write command. and Set the selected single processing sequence to the time of completion of the write command.

15. The method of claim 12, further comprising: Check whether the programming status matches the send time set for the completion of the write command. in: When the programming state matches the transmission time, the transmission of the completion signal to the host device is performed.

16. The method of claim 15, further comprising: When a single processing sequence indicated by the programming state matches the sending time, backups for that single processing sequence are omitted.

17. The method according to claim 12, wherein: The device status information includes at least one of the following: the queue depth of the command queue for the write command at any time or the size of the write command.

18. The method of claim 17, further comprising: A first data size, defined based on at least one of the queue depth of the command queue or the size of the write command, is compared with a second data size required for each of the plurality of processing sequences of the write command; and The completion sending time of the write command is set based on one or more processing sequences among the plurality of processing sequences that have a second data size that is less than or equal to the first data size.

19. A storage device, the storage device comprising: Non-volatile memory; A storage controller configured to receive write commands for the non-volatile memory from a host device and to control the programming of write data corresponding to the write commands into the non-volatile memory; A buffer memory configured to buffer the written data; and A power failure protection PLP circuit, configured to detect a sudden power failure (SPO) from the storage device. The storage controller is configured as follows: Based on at least one of programming status information indicating the programming status of the write command or device status information of the storage device, a completion signal indicating the completion of the write command is sent to the host device. and When the SPO is detected before the completion signal is sent to the host device, backing up the buffered write data to the non-volatile memory is omitted.

20. The storage device according to claim 19, wherein: The storage controller is configured to send a completion signal to the host device when the programming state matches a send time set for the completion of the write command.

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