Compiler-free embedded program construction system, method and device based on large language model

Abstract

The invention discloses a compiler-free embedded program construction system, method and device based on a large language model, and the method comprises the steps: receiving a structured hardware demand description through a large language model subjected to instruction set architecture knowledge enhancement, and carrying out the direct reasoning to generate an assembly instruction sequence for specific target hardware; and then mapping the assembly instruction into a binary machine code, executing in target hardware or a simulation environment, capturing input and output logs and state data during operation in real time, carrying out semantic comparison with a preset acceptance standard, and when the comparison fails, constructing a feedback prompt word containing difference characteristics, and driving a model to carry out targeted logic correction, so as to complete the verification of the assembly instruction. And checking and accepting. In the construction process, the compilation step of converting a high-level language into an intermediate code is completely abandoned, and code feedback correction is achieved. According to the method, the code volume can be reduced by more than 90% on the premise of ensuring the logic consistency, and the method is particularly suitable for the development of an embedded system with limited resources.

Description

Technical Field

[0001] This invention relates to the fields of computer software engineering and artificial intelligence technology, specifically to a compilerless embedded program construction system, method, and apparatus based on a large language model. Background Technology

[0002] The current embedded development process has long followed a lengthy chain: "High-level language (C / C++) → Compiler front-end → Intermediate code (IR) → Compiler back-end → Assembly code → Machine code." This model has the following core flaws: 1. Compiler efficiency bottleneck: General-purpose compilers (such as GCC and LLVM) often generate redundant instruction sequences for compatibility, making it difficult to perform extreme optimization for the non-standard hardware characteristics of specific microcontrollers (MCUs) (such as specific bit manipulation instructions and hardware accelerators).

[0003] 2. Semantic Gap: The high-level intent of developers (such as "precise delay of 10us") often cannot guarantee the determinism of the underlying layer after multiple layers of compilation and transformation, and requires repeated disassembly and debugging.

[0004] 3. Toolchain dependency: The development environment setup is complex and heavily reliant on specific vendors' IDE and compiler licenses.

[0005] Furthermore, existing embedded development processes face significant challenges when directly generating low-level embedded code (assembly / machine code), including: 1. Inoperability caused by “illusion”: AI is prone to generating syntactically correct but logically flawed code (such as incorrect delay loop counts or incorrect register addresses), and the model itself is unaware of these errors.

[0006] 2. Limitations of Open-Loop Generation: Existing AI programming tools are mostly "one-time generation" tools, lacking the ability to automatically modify in a closed-loop manner based on the running results. Developers must manually intervene to download, debug, and provide feedback, which is inefficient.

[0007] 3. High debugging threshold: Errors in embedded systems often manifest as timing anomalies or unresponsive peripherals, which are difficult to detect through static code analysis. Summary of the Invention

[0008] The purpose of this invention is to address the shortcomings of existing technologies by proposing a compiler-free embedded program construction system, method, and apparatus based on a large language model. It proposes a "Direct Neural Synthesis" paradigm, completely abandoning traditional compiler components. Utilizing a large language model (LLM) enhanced with knowledge of a specific instruction set architecture (ISA), it directly maps structured hardware requirements into assembly instructions or machine code, and uses the "real feedback" from the hardware as an objective basis for correcting AI logic.

[0009] The objective of this invention is achieved through the following technical solution: a compilerless embedded program construction system based on a large language model, the system comprising: The requirements parsing module is used to obtain a structured hardware requirements description of the target hardware platform, which includes hardware specifications and functional logic requirements. The neural assembler engine is used to combine the instruction set architecture data and register mapping relationship of the target hardware platform, and based on the pre-trained large language model, infer and generate the corresponding assembly instruction sequence according to the structured hardware requirement description of the target hardware platform. A transparent transcoder is used to receive the assembly instruction sequence and generate a binary format file executable by the target hardware platform through the mapping conversion between mnemonics and machine code.

[0010] Furthermore, the system does not include a compilation processing unit that converts high-level programming language source files into intermediate code representations (IRs) during its construction.

[0011] Furthermore, the pre-trained large language model integrates a retrieval enhancement generation (RAG) mechanism to obtain the accurate register base address and offset of the target hardware platform and the instruction encoding table in real time, and inputs the retrieval results as context into the large language model.

[0012] Furthermore, the structured hardware requirements description adopts JSON or XML format, and the content includes at least clock frequency constraints, peripheral pin mapping, and interrupt priority configuration.

[0013] Furthermore, the system also includes an assembly instruction correction module, which is used to obtain the runtime status data of the binary format file in the hardware or simulation environment; and feed the runtime status data back to the large language model, which corrects the assembly instruction sequence based on the feedback data.

[0014] Furthermore, the assembly instruction correction module is implemented as follows: (1) Convert the assembly instruction sequence into machine code, load it into the target hardware environment for execution, and capture the runtime status log of the target hardware environment within a preset time window; (2) Compare the runtime status log with the preset acceptance criteria and calculate the semantic difference between the actual running result and the expected result; the semantic difference includes the frequency of occurrence of a specific string pattern in the character stream data by matching the regular expression. (3) When the comparison result fails, feedback prompt information containing error features is constructed based on the semantic differences, including: extracting the expected output pattern in the acceptance criteria and the actual output pattern in the runtime status log, and combining the two to generate a natural language prompt word containing the description of "the expected does not match the actual"; inputting the feedback prompt information into the large language model, driving it to regenerate the assembly instruction sequence, and returning to the execution step (1) until the comparison passes or the maximum number of iterations is reached. In a second aspect, the present invention also provides a compilerless embedded program construction method based on a large language model, the method comprising: (1) Obtain a structured hardware requirements description of the target hardware platform, including hardware specifications and functional logic requirements; (2) Input the structured hardware requirements description of the target hardware platform into the pre-trained large language model, and combine it with the instruction set architecture data and register mapping relationship of the target hardware platform to infer and generate the corresponding assembly instruction sequence; (3) The assembly instruction sequence is converted according to the mapping relationship between mnemonics and machine code to generate a binary format file executable by the target hardware platform.

[0015] Thirdly, the present invention also provides a compilerless embedded program construction device based on a large language model, including a memory and one or more processors, wherein the memory stores executable code, and when the processor executes the executable code, it implements the compilerless embedded program construction method based on a large language model.

[0016] Fourthly, the present invention also provides a computer-readable storage medium having a program stored thereon, wherein when the program is executed by a processor, it implements the aforementioned method for constructing a compilerless embedded program based on a large language model.

[0017] Fifthly, the present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the aforementioned method for constructing a compilerless embedded program based on a large language model.

[0018] The beneficial effects of this invention are: 1. Extreme code size optimization: While ensuring complete consistency of functional logic, this invention achieves a 97.8% reduction in code size (see example data), effectively solving the storage bottleneck of resource-constrained devices.

[0019] 2. Eliminating the semantic gap: It achieves end-to-end mapping from requirements to machine instructions, avoiding uncontrollable redundancy introduced by the compiler.

[0020] 3. Simplified development process: Eliminates the dependence on complex cross-compilation toolchains.

[0021] 4. Achieve unattended automated debugging: This invention can replace human engineers in completing repetitive debugging work of "run-observe-modify", which significantly improves development efficiency.

[0022] 5. Solving the AI ​​illusion problem: By introducing objective hardware operation results as feedback (Grounding), the logical illusion of the model is effectively suppressed, ensuring that the generated firmware is real and usable.

[0023] 6. High-precision timing control capability: Experiments have shown that the system can automatically calibrate the number of software delay loops through feedback iteration, thereby achieving precise hardware control. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 System Architecture Diagram. This diagram illustrates the complete process from structured requirements to AI-generated assembly, transparent transcoding, and hardware execution.

[0026] Figure 2 Comparison diagram of traditional compilation process and the process of this invention. The diagram compares the lengthy compilation chain of existing technologies with the end-to-end generation path of this invention, highlighting the advantage of eliminating intermediate steps in this invention.

[0027] Figure 3 : Implementation Detail of RAG-based Neural Assembler Generation. This demonstrates the internal process of how the neural assembler engine combines a vector database to retrieve instruction set specifications and register addresses to guide the model in generating accurate assembly instructions.

[0028] Figure 4 HIL-RL Closed-Loop Feedback Flowchart. It illustrates the cyclical process of generation, execution, monitoring, and feedback.

[0029] Figure 5This diagram illustrates the working principle of the state monitoring and semantic analysis module. It demonstrates how a feedback prompt is generated by comparing Log and Acceptance Criteria.

[0030] Figure 6 Sequence Diagram of the Automatic Iterative Correction Process. This diagram illustrates the specific interactive process in the example where the error "AB" is corrected to "DNS_ALIVE".

[0031] Figure 7 This invention provides a schematic diagram of a compilerless embedded program building device based on a large language model. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are merely illustrative and not intended to limit the invention.

[0033] like Figure 1 As shown, the present invention provides a compilerless embedded program building system based on a large language model, which does not include a compilation processing unit that converts high-level programming language source files into intermediate code representations (IRs) during the building process. Figure 1 The overall architecture of the compilerless embedded program building system proposed in this invention is demonstrated. The system receives a structured requirement description (HRD), directly generates assembly code through a large language model (neural assembler engine) with an ISA knowledge base, converts it into machine code through a transparent transcoder, and finally runs it on the target hardware.

[0034] This system mainly consists of three core processing units: Requirements parsing module: Used to receive and parse hardware requirement descriptions (HRDs) in structured formats (such as JSON). The HRDs are in JSON or XML format and explicitly constrain clock frequency, chip model, peripheral address mapping, functional logic, and interrupt priority configuration.

[0035] Neural-Assembler Engine: such as Figure 3As shown, the specific workflow inside the neural assembler engine is as follows: First, it parses the hardware requirements, then retrieves the instruction set specification and register addresses of the corresponding chip from the vector database. These "hard constraints" are used as context input to the large language model, thereby guiding the model to generate accurate assembly instruction sequences. The pre-trained large language model integrates a retrieval-enhanced generation (RAG) mechanism, which can retrieve the target chip's reference manual in real time to obtain accurate register base addresses and offsets; it is configured to directly output assembly mnemonics instead of high-level language code. The large language model combines the instruction set architecture data and register mapping relationships of the target hardware platform, and infers and generates the corresponding assembly instruction sequences based on the structured hardware requirement description of the target hardware platform.

[0036] Transparent Transcoder: A tool that performs only mnemonic-to-binary mapping conversion. It receives the assembly instruction sequence and generates a binary format file executable by the target hardware platform through the mapping conversion between mnemonics and machine code. Its key feature is that it does not perform any control flow analysis, loop unrolling, or instruction rearrangement, ensuring that the logic generated by the AI ​​is 100% preserved.

[0037] The assembly instruction correction module is used to obtain the runtime status data of the binary format file in the hardware or simulation environment; and to feed back the runtime status data to the large language model, which then corrects the assembly instruction sequence based on the feedback data.

[0038] Figure 2 The diagram illustrates the process differences between the prior art and the present invention. The prior art (top) relies on a complex compiler front-end, intermediate code generation, and back-end optimization, resulting in a lengthy path and semantic loss. The present invention (bottom) utilizes a large model to directly bridge the semantic gap, achieving end-to-end generation from requirements to assembly instructions and eliminating intermediate compilation steps.

[0039] like Figure 4 and Figure 5 As shown, the assembly instruction correction module generates a machine code binary format file after mapping and converting the assembly instruction sequence according to hardware requirements and loads it into the target hardware environment, including a full system simulator based on QEMU, or a physical microcontroller chip connected through the debugging interface JTAG / SWD; iterative correction is achieved through the following process; Listen to the UART port, JTAG interface, or memory-mapped file, and capture the runtime status log of the target hardware environment within a preset time window (e.g., 3 seconds); including character stream data output through the Universal Asynchronous Receiver / Transmitter (UART).

[0040] The runtime status log is compared with preset acceptance criteria to calculate the semantic difference between the actual and expected results. Specifically, regular expressions are used to match the frequency of occurrence of specific string patterns in the character stream data. It not only detects program crashes but also uses regular expressions to compare whether business logic meets the standards (e.g., whether a specific heartbeat string was output).

[0041] When the comparison result fails, feedback prompt information containing error features is constructed based on the semantic differences. The expected output pattern in the acceptance criteria and the actual output pattern in the runtime status log are extracted and combined to generate a natural language prompt word containing the description of "the expected does not match the actual". This prompt word is input into the large language model to drive it to regenerate the assembly instruction sequence for mapping and transcoding until the comparison passes or the maximum number of iterations is reached.

[0042] Figure 5 This diagram illustrates the working principle of status monitoring and semantic analysis. It captures the hardware's runtime log stream in real time, compares it with preset acceptance criteria using a regular expression matching engine, and generates natural language feedback prompts containing the "difference between expected and actual patterns" using a difference calculator.

[0043] Example: Code size optimization verification To verify the build efficiency of this system, in a specific implementation scenario based on a RISC-V 32-bit architecture, the tasks completed were: "1. Initialize UART0 (115200 baud rate). 2. Send the string 'DNS_ALIVE\n' in an infinite loop. 3. Do not use long-delayed loops; continuous output at the fastest speed is required." We compared the build process using the system of this invention with that using the traditional GCC toolchain.

[0044] Control group (existing technology): Using the riscv64-unknown-elf-gcc toolchain, configured with -O3 (highest optimization) and -nostdlib (no linking to the standard library), the compiled binary file size was 4136 bytes. Analysis revealed that it still contained a large number of stack frame initialization and segment alignment instructions.

[0045] Experimental group (this invention): The compilerless construction system described in this invention is used to directly generate instruction sequences and transcode them using a neural assembler engine, resulting in a binary file size of only 92 bytes.

[0046] The experimental results show that, while ensuring complete consistency of functional logic, this invention achieves a 97.8% reduction in code size compared to traditional methods with maximum optimization. Specific results are shown in the table below: like Figure 6 The diagram illustrates the timing of the automatic iterative correction process of this invention when handling UART heartbeat tasks. In the second iteration, the model generated incorrect "AB" alternating output logic; after detecting this error, the system automatically injected feedback information; in the third iteration, the model successfully corrected the code logic based on the feedback, outputting the correct "DNS_ALIVE" sequence. Details are as follows: To verify the self-healing capability of this method, in an implementation scenario based on a RISC-V architecture, the task was set as "periodically sending the string 'DNS_ALIVE' via UART".

[0047] First iteration (generation and execution): The AI ​​generated the first version of assembly code. After running in the simulation environment, the logs captured by the status monitoring module were garbled or blank, and the semantic analysis module judged it as "failure".

[0048] Second iteration (illusion and error): The system reports the error to the AI. The AI ​​regenerates the code, but due to a misunderstanding, the logic is incorrectly modified to alternately output the characters 'A' and 'B'.

[0049] Monitoring results: The log content captured was a continuous string of "ABABABAB...".

[0050] Semantic decision: The acceptance criteria require the output to be "DNS_ALIVE", but the actual output is "AB". This is judged as a "logical mismatch".

[0051] Third iteration (feedback and correction): Feedback Construction: The system generates the following message: "[FAIL] Output mismatch. Expected 'DNS_ALIVE', found 'AB'. Please fix the logic." Corrected Generation: After receiving feedback, the AI ​​analyzed and corrected the data loading instructions.

[0052] Final result: The new code successfully output a stable "DNS_ALIVE" sequence in the simulation and passed the acceptance test.

[0053] Conclusion: This invention successfully fixed a logical error in the code through three closed-loop iterations without human intervention, proving the effectiveness of the iterative correction method based on runtime feedback.

[0054] Corresponding to the aforementioned embodiment of a compilerless embedded program construction system based on a large language model, this invention also provides an embodiment of a compilerless embedded program construction method based on a large language model. The method includes: (1) Obtain a structured hardware requirements description of the target hardware platform, including hardware specifications and functional logic requirements; (2) Input the structured hardware requirements description of the target hardware platform into the pre-trained large language model, and combine it with the instruction set architecture data and register mapping relationship of the target hardware platform to infer and generate the corresponding assembly instruction sequence; (3) The assembly instruction sequence is converted according to the mapping relationship between mnemonics and machine code to generate a binary format file executable by the target hardware platform.

[0055] Corresponding to the aforementioned embodiment of a compilerless embedded program construction method based on a large language model, the present invention also provides an embodiment of a compilerless embedded program construction device based on a large language model.

[0056] See Figure 7 The present invention provides a compilerless embedded program construction device based on a large language model, comprising a memory and one or more processors. The memory stores executable code, and when the processor executes the executable code, it is used to implement a compilerless embedded program construction method based on a large language model as described in the above embodiments.

[0057] The present invention provides an embodiment of a compiler-free embedded program construction device based on a large language model, which can be applied to any device with data processing capabilities, such as a computer. The device embodiment can be implemented in software, hardware, or a combination of both. Taking software implementation as an example, as a logical device, it is formed by the processor of any data processing device loading the corresponding computer program instructions from non-volatile memory into memory for execution. From a hardware perspective, such as... Figure 7 The diagram shown is a hardware structure diagram of any data processing-capable device, where the compilerless embedded program construction device based on a large language model provided by the present invention is located. (Except for...) Figure 7 In addition to the processor, memory, network interface, and non-volatile memory shown, any data processing device in the embodiment may also include other hardware depending on the actual function of the data processing device, which will not be described in detail here.

[0058] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0059] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the present invention according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0060] This invention also provides a computer-readable storage medium storing a program thereon, which, when executed by a processor, implements a compilerless embedded program construction method based on a large language model as described in the above embodiments.

[0061] The computer-readable storage medium can be an internal storage unit of any data processing device described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be an external storage device of any data processing device, such as a plug-in hard disk, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units and external storage devices of any data processing device. The computer-readable storage medium is used to store the computer program and other programs and data required by the data processing device, and can also be used to temporarily store data that has been output or will be output.

[0062] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the aforementioned method for constructing a compilerless embedded program based on a large language model.

[0063] The above embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A compilerless embedded program construction system based on a large language model, characterized in that, The system includes: The requirements parsing module is used to obtain a structured hardware requirements description of the target hardware platform, which includes hardware specifications and functional logic requirements. The neural assembler engine is used to combine the instruction set architecture data and register mapping relationship of the target hardware platform, and based on the pre-trained large language model, infer and generate the corresponding assembly instruction sequence according to the structured hardware requirement description of the target hardware platform. A transparent transcoder is used to receive the assembly instruction sequence and generate a binary format file executable by the target hardware platform through the mapping conversion between mnemonics and machine code.

2. The compilerless embedded program construction system based on a large language model according to claim 1, characterized in that, The system does not include a compilation processing unit that converts high-level programming language source files into intermediate code representations (IRs) during its construction.

3. The compilerless embedded program construction system based on a large language model according to claim 1, characterized in that, The pre-trained large language model integrates a retrieval enhancement generation (RAG) mechanism to obtain accurate register base addresses and offsets, as well as instruction encoding tables, of the target hardware platform in real time, and uses the retrieval results as context input to the large language model.

4. The compilerless embedded program construction system based on a large language model according to claim 1, characterized in that, The structured hardware requirements description shall be in JSON or XML format and shall include at least clock frequency constraints, peripheral pin mappings and interrupt priority configurations.

5. The compilerless embedded program construction system based on a large language model according to claim 1, characterized in that, The system also includes an assembly instruction correction module, which is used to obtain the runtime status data of the binary format file in the hardware or simulation environment; and feed the runtime status data back to the large language model, which corrects the assembly instruction sequence based on the feedback data.

6. The compilerless embedded program construction system based on a large language model according to claim 1, characterized in that, The assembly instruction correction module is implemented as follows: (1) Convert the assembly instruction sequence into machine code, load it into the target hardware environment for execution, and capture the runtime status log of the target hardware environment within a preset time window; (2) Compare the runtime status log with the preset acceptance criteria and calculate the semantic difference between the actual running result and the expected result; the semantic difference includes the frequency of occurrence of a specific string pattern in the character stream data by matching the regular expression. (3) When the comparison result fails, construct feedback prompt information containing error features based on the semantic differences, including: extracting the expected output pattern in the acceptance criteria and the actual output pattern in the runtime status log, and combining the two to generate a natural language prompt word containing the description of "the expected and the actual do not match"; inputting the feedback prompt information into the large language model, driving it to regenerate the assembly instruction sequence, and returning to the execution step (1) until the comparison passes or the maximum number of iterations is reached.

7. A method for constructing compilerless embedded programs based on a large language model according to any one of claims 1-6, characterized in that, The method includes: (1) Obtain a structured hardware requirements description of the target hardware platform, including hardware specifications and functional logic requirements; (2) Input the structured hardware requirements description of the target hardware platform into the pre-trained large language model, and combine it with the instruction set architecture data and register mapping relationship of the target hardware platform to infer and generate the corresponding assembly instruction sequence; (3) The assembly instruction sequence is converted according to the mapping relationship between mnemonics and machine code to generate a binary format file executable by the target hardware platform.

8. A compilerless embedded program building device based on a large language model, comprising a memory and one or more processors, wherein the memory stores executable code, characterized in that, When the processor executes the executable code, it implements the compilerless embedded program construction method based on a large language model as described in claim 5.

9. A computer-readable storage medium having a program stored thereon, characterized in that, When the program is executed by the processor, it implements the compilerless embedded program construction method based on a large language model as described in claim 5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the compilerless embedded program construction method based on a large language model as described in claim 5.

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