Data verification method, system and equipment for interlocking product
By constructing a multi-branch data tree and performing multi-dimensional array expansion and logical verification, the problems of automation and accuracy in data verification of interlocking systems in existing technologies are solved, achieving efficient and reliable data verification and ensuring the safety of railway signaling systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CRSC RESEARCH & DESIGN INSTITUTE GROUP CO LTD
- Filing Date
- 2026-01-04
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, data verification methods for interlocking systems cannot fully cover implicit data errors, rely on manual operation which is inefficient and unreliable, cannot delve into the internal structure of the data for verification, and the verification process is complex and not automated enough, making it difficult to guarantee the safety and reliability of the interlocking system.
By employing a stack-based post-order traversal algorithm and a progressive multidimensional array expansion algorithm, a data multi-branch tree is constructed by parsing the engineering data configuration file of the interlocking software. The multidimensional array nodes are progressively expanded hierarchically, and consistency and logical relationship verification are performed with the standard design data to achieve full-process automation.
It significantly improves the sufficiency and accuracy of data verification, increases verification efficiency, reduces the risk of human error, and ensures the safety and reliability of the interlocking system. It is applicable to different types of interlocking systems and railway signaling equipment.
Smart Images
Figure CN122018912A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of railway signal safety control technology, and in particular to a data verification method, system and equipment for interlocking products. Background Technology
[0002] Interlocking equipment is a key safety device in railway signaling systems. Its main function is to control routes, switches, and signals within stations through technical means, and to ensure strict control relationships between these devices, thereby guaranteeing train operation safety, improving operational efficiency, and reducing labor intensity. As a core high-safety device for control signals in railway systems, interlocking systems can take timely countermeasures in the event of equipment or system failures to prevent accidents from escalating, playing a vital role in safe production.
[0003] Failure of interlocking systems can lead to serious consequences and incalculable economic losses, making thorough testing and inspection of interlocking systems extremely important. Currently, all interlocking equipment manufacturers conduct various technical and management tests and verifications of their interlocking systems before product delivery to ensure functional correctness and data configuration accuracy. Testing and verification mainly includes two parts: functional verification and data verification. Data verification, as a crucial step in user acceptance, is particularly critical—even if the software functions correctly, incorrect underlying data configuration can still trigger erroneous signal commands, causing interlocking equipment failure, thus creating safety hazards and even leading to catastrophic consequences.
[0004] In existing technologies, the software of a computer interlocking system consists of two parts: application software and engineering data. Assuming the logical functions of the application software have been verified, different stations need to generate corresponding engineering data based on actual survey and engineering design data, such as attributes and relationships of routes, sections, signals, and turnouts. Currently, manufacturers mainly rely on black-box testing methods to verify explicit data, such as checking the correctness of data configuration by testing route settings item by item. However, black-box testing cannot fully cover implicit data errors (such as redundant configurations, incorrect associations, and data out-of-bounds errors). Data validity checks and logical consistency verification still heavily rely on manual work, which is not only inefficient but also makes it difficult to guarantee the sufficiency and reliability of verification. Furthermore, existing verification methods have a significant contradiction between the sufficiency of data verification and execution efficiency, which has become a bottleneck restricting the production efficiency of interlocking products.
[0005] Chinese patent CN119718888A discloses a method for verifying interlocking software data. It uses two independent software tools (DataVerisoft and AutoStampTool) to process interlocking data from different sources, and ultimately verifies data consistency by comparing the text reports generated by the two tools. Specifically, DataVerisoft (developed in C++) reads the interlocking table, IO bitmap, and DGG file, and generates a text report according to predefined rules; AutoStampTool (developed in Python) parses the PDF design document, extracts data based on the same rules, and generates another text report. The two reports are then compared manually or automatically to determine data accuracy. However, this method has the following drawbacks in practical applications: 1. Inability to delve into the internal data structure: This method only performs text-level comparison of the final report content, which is a black-box verification. It cannot parse and verify details such as the internal structure, type, nesting relationships, or multidimensional array values of the data, making it difficult to discover logical errors, correlation errors, or configuration redundancies hidden deep within the data structure, resulting in insufficient verification sufficiency. 2. The AutoStampTool heavily relies on PDF input documents, and its parsing performance is directly affected by changes in PDF document format and layout. If the document structure or content presentation changes, the tool may fail to extract information correctly, requiring adjustments or development of parsing rules, resulting in high maintenance costs and poor adaptability. 3. The verification process involves a complex workflow with multiple tools, formats, and steps (including PDF parsing, text generation, and report comparison). The numerous intermediate steps increase the possibility of introducing errors. The stability and reliability of the overall process depend on the correctness of each independent component, leading to high system complexity. 4. The core of this method lies in consistency checks between different data sources (binary files / PDF documents), rather than verifying whether the data itself conforms to interlocking business logic. It cannot effectively verify the legality, rationality, and logical correctness of data at the business level, resulting in functional limitations. 5. Although it claims to replace manual labor, manual judgment is still required after report comparison to determine if there is a "complete match," and subsequent processing of the verification results (such as stamping confirmation) still requires manual intervention, failing to achieve a fully automated closed loop.
[0006] Therefore, with the rapid development of the railway industry, how to improve the automation, accuracy and efficiency of data verification, and provide a method that can comprehensively and automatically verify the data configuration of interlocking products, so as to improve the safety and reliability of the interlocking system from the source, has become an urgent technical problem to be solved. Summary of the Invention
[0007] In view of this, in order to overcome the shortcomings of the prior art, the present invention aims to provide a data verification method, system and device for interlocking products.
[0008] According to a first aspect of the present invention, a data verification method for interlocking products is provided, the method comprising: Step S1: Parse the engineering data configuration file of the interlocking software and construct a data multi-branch tree; Step S2: Perform progressive hierarchical expansion of the multidimensional array nodes in the data multi-way tree; including: Initialize the stack oriStack, push the head node of the multi-way tree onto the stack, check if the stack oriStack is empty, and if the stack oriStack is not empty, get the top element of the stack oriStack. If the top element of the stack is a non-leaf node and the node has not been fully traversed, push all child nodes of that node onto the stack; if the top element is a leaf node, pop the stack oriStack. If the popped node has an array flag, construct an extended traversal stack exdStack and add the node with the array flag to the constructed extended traversal stack exdStack. Check if the extended traversal stack exdStack is empty. If the extended traversal stack exdStack is not empty, perform a pop operation and obtain the structure type name and structure variable name of the popped element top variable. Get the current dimension, dimension number, and remaining dimension of the array based on the structure type name and structure variable name. Build the corresponding number of child nodes on the current node based on the current dimension. Continue to check whether the extended traversal stack exdStack is empty until all nodes have been processed. Step S3: Verify the expanded data multi-way tree with the standard design data and output the verification results.
[0009] Furthermore, in step S1, constructing a data multi-way tree includes: constructing a type multi-way tree according to the data type definition, creating a node for each data type, using basic types as leaf nodes, using composite types as intermediate nodes, representing the data nesting structure through parent-child relationships, and adding dimension attributes to array type nodes.
[0010] Furthermore, a data multi-branch tree is constructed based on variable definitions and type multi-branch trees. A post-order traversal algorithm is used to traverse the type multi-branch tree, and a node stack is used to manage the traversal process. By monitoring the traStack to match curly braces, the data in the data list is assigned to the corresponding nodes according to the type structure.
[0011] Furthermore, if the currently read data element is a number, and the node popped from the node stack is a leaf node, assign the number to that node and move the access position of the data list forward by one position. If the currently read data element is a left curly brace and the currently traversed node is a non-leaf node, assign the left curly brace to the node, move the access position of the data list forward by one position, and push the current node onto the watch stack. If the currently read data element is a left curly brace and the currently traversed node is a leaf node, check if there is only one data element immediately following it until the next right curly brace. If so, assign the unique value to the current leaf node and move the data list access point to the position after the right curly brace. Otherwise, it is determined that the data is incorrect and the process is terminated. If the currently read data element is a right curly brace and the currently traversed node is a leaf node, assign the value 0 to that node; If the currently read data element is a right curly brace and the currently traversed node is a non-leaf node, check if the top element of the watch stack traStack is the current node. If it is, perform a pop operation and move the data list access position forward by one position. Otherwise, ignore the right curly brace and traverse the next node.
[0012] Furthermore, in step S2, when constructing the corresponding number of child nodes on the current node based on the current dimension, if the remaining dimension is 0, the child node is directly assigned the value of the top variable; if the remaining dimension is not 0, a new node is constructed, the remaining dimension is updated and recorded, and the parameter of the top variable is copied to the newly constructed node.
[0013] Further, step S3 includes: The consistency between the expanded data multi-way tree and the standard design data is checked. If the two are inconsistent, the check is deemed to have failed. When both are consistent, the extended data multi-branch tree and the standard design data are logically verified. If the logical relationship between the two conforms to the interlocking logic rules, the verification is deemed successful; if the logical relationship does not conform to the interlocking logic rules, the verification is deemed unsuccessful, and the verification result is output. According to a second aspect of the present invention, a data verification system for interlocking products is provided. This system includes a verification server, which includes: The parsing module is used to parse the engineering data configuration file of the interlocking software and build a data multi-branch tree; The extension module is used to progressively expand the multidimensional array nodes in the data multi-way tree; The verification module is used to verify the expanded data multi-way tree against the standard design data and output the verification results.
[0014] Furthermore, the extended module includes: The initialization unit is used to initialize the stack oriStack, push the head node of the multi-branch tree onto the stack, check if the stack oriStack is empty, and if the stack oriStack is not empty, get the top element of the stack oriStack. In the main traversal unit, if the top element of the stack is a non-leaf node and the node has not been traversed, push all child nodes of that node onto the stack; if the top element of the stack is a leaf node, perform a pop operation on the stack oriStack. The array detection unit, if the popped node has an array flag, constructs an extended traversal stack exdStack and adds the node with the array flag to the constructed extended traversal stack exdStack. An extended processing unit is used to determine whether the extended traversal stack exdStack is empty. If the extended traversal stack exdStack is not empty, a pop operation is performed to obtain the structure type name and structure variable name of the popped element top variable. The dynamic loop unit is used to obtain the current dimension, dimension number, and remaining dimension of the array based on the structure type name and structure variable name. It constructs the corresponding number of child nodes on the current node according to the current dimension, and continues to check whether the extended traversal stack exdStack is empty, until all nodes have been processed.
[0015] Furthermore, when constructing the corresponding number of child nodes on the current node based on the current dimension, if the remaining dimension is 0, the child node is directly assigned the value of the top variable; if the remaining dimension is not 0, a new node is constructed, the remaining dimension is updated and recorded, and the parameter of the top variable is copied to the newly constructed node.
[0016] According to a third aspect of the present invention, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the first aspect of the present invention.
[0017] The data verification method, system, and equipment for interlocking products of this invention are based on a stack-structured post-order traversal algorithm and a progressive multidimensional array expansion algorithm, which improves the accuracy and efficiency of verification, ensures the reliability of interlocking data configuration, realizes efficient and accurate data mapping and verification, greatly improves verification efficiency and automation, and overcomes the limitations of traditional black-box testing and manual verification. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is an example architecture diagram of a data verification system for an interlocking product according to an embodiment of the present invention; Figure 2 This is an example architecture diagram of the verification server of a data verification system for an interlocking product according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the steps of a data verification method for an interlocking product according to an embodiment of the present invention. Figure 4 This is an example diagram of another data multi-way tree obtained after the assignment processing according to the method of the embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the device provided by the present invention. Detailed Implementation
[0020] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0021] It should be noted that, in the absence of conflict, the following embodiments and features can be combined with each other; and, based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0022] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0023] Figure 1 This is an example architecture diagram of a data verification system for an interlocking product according to an embodiment of the present invention, such as... Figure 1 As shown, the system may include a verification server 101, a communication network 102, and / or one or more verification clients 103. Figure 1The example in the text shows multiple verification clients 103.
[0024] The verification server 101 can be any suitable server for storing information, data, programs, and / or any other suitable type of content. In some embodiments, the verification server 101 can perform appropriate functions. For example, in some embodiments, the verification server 101 can be used for data verification of interlocking products. As an optional example, in some embodiments, the verification server 101 can be used to: parse the engineering data configuration file of the interlocking software, extract data type definitions and variable definitions; construct a type multi-way tree based on the data type definitions, and construct a data multi-way tree based on the variable definitions and the type multi-way tree; progressively expand the multidimensional array nodes in the data multi-way tree; verify the expanded data multi-way tree against standard design data, and output the verification results.
[0025] Figure 2 This is an example architecture diagram of the verification server of a data verification system for interlocking products according to an embodiment of the present invention, as shown below. Figure 2 As shown, in this embodiment, the verification server includes: The parsing module is used to parse the engineering data configuration file of the interlocking software and build a data multi-branch tree; The extension module is used to progressively expand the multidimensional array nodes in the data multi-way tree; The verification module is used to verify the expanded data multi-way tree against the standard design data and output the verification results.
[0026] As another example, in some embodiments, the verification server 101 may send the data verification method of the interlocking product to the verification client 103 for user use, based on the request of the verification client 103.
[0027] As an optional example, in some embodiments, the verification client 103 is used to provide a visual verification interface, which is used to receive a user's selection input operation for verifying the data of the interlocking product, and to obtain from the verification server 101 the verification interface corresponding to the option selected by the selection input operation and display the verification interface in response to the selection input operation. The verification interface displays at least information about the data of the interlocking product to be verified and operation options for verifying the data of the interlocking product.
[0028] In some embodiments, communication network 102 may be any suitable combination of one or more wired and / or wireless networks. For example, communication network 102 may include any one or more of the following: the Internet, intranet, wide area network (WAN), local area network (LAN), wireless network, digital subscriber line (DSL) network, frame relay network, asynchronous transfer mode (ATM) network, virtual private network (VPN), and / or any other suitable communication network. Verification client 103 may connect to communication network 102 via one or more communication links (e.g., communication link 104), which may be linked to verification server 101 via one or more communication links (e.g., communication link 105). Communication links may be any communication link suitable for transmitting data between verification client 103 and verification server 101, such as network links, dial-up links, wireless links, hardwired links, any other suitable communication links, or any suitable combination of such links.
[0029] Verification client 103 may include any one or more clients that present an interface related to the verification of interlocking products in a suitable manner for user use and operation. In some embodiments, verification client 103 may include any suitable type of device. For example, in some embodiments, verification client 103 may include a mobile device, tablet computer, laptop computer, desktop computer, and / or any other suitable type of client device.
[0030] Although the verification server 101 is illustrated as a single device, in some embodiments, any suitable number of devices may be used to perform the functions performed by the verification server 101. For example, in some embodiments, multiple devices may be used to implement the functions performed by the verification server 101. Alternatively, cloud services may be used to implement the functions of the verification server 101.
[0031] Based on the above system, embodiments of the present invention provide a data verification method for interlocking products, which will be described below through the following embodiments.
[0032] Figure 3 This is a flowchart illustrating the steps of a data verification method for an interlocking product according to an embodiment of the present invention. The data verification method for the interlocking product in this embodiment can be executed on a verification server, and includes the following steps: Step S1: Parse the engineering data configuration file of the interlocking software and construct a data multi-branch tree; Step S2: Perform progressive hierarchical expansion on the multidimensional array nodes in the data multi-way tree.
[0033] As an optional example, this embodiment uses a post-order traversal algorithm to traverse the type multi-way tree, uses a node stack to manage the traversal process, and uses the watch stack traStack to match curly braces to assign data in the data list to the corresponding nodes according to the type structure.
[0034] Specifically, if the currently read data element is a number, and the node popped from the node stack is a leaf node, the number is assigned to that node, and the access position of the data list is moved forward one position. If the currently read data element is a left curly brace and the currently traversed node is a non-leaf node, assign the left curly brace to the node, move the access position of the data list forward by one position, and push the current node onto the watch stack. If the currently read data element is a left curly brace and the currently traversed node is a leaf node, check if there is only one data element immediately following it until the next right curly brace. If so, assign the unique value to the current leaf node and move the data list access point to the position after the right curly brace. Otherwise, it is determined that the data is incorrect and the process is terminated. If the currently read data element is a right curly brace and the currently traversed node is a leaf node, assign the value 0 to the node and pad it with zeros for the compiler. If the currently read data element is a right curly brace and the currently traversed node is a non-leaf node, check if the top element of the watch stack traStack is the current node. If it is, perform a pop operation and move the data list access position forward by one position. Otherwise, ignore the right curly brace and traverse the next node.
[0035] For example, in this embodiment, the data is given in the form of a list, such as Data=[3,4,{,5,{,6,7,},8,},9]. Values are assigned sequentially according to the data in the list, and a multi-way tree node stack (treeStack) is used to assist in completing the multi-way tree traversal. A watch stack (traStack) is used to match left parenthesis nodes with right parenthesis nodes during the traversal. The principle is as follows: 1. If the current element in the list is a number, and the node popped from the treeStack is a leaf node, then the current value is assigned to this node, and the access point in the list is moved forward. For example, if the node popped from the stack for 3 is a non-leaf node, then the traversal continues. 2. If the list is currently enclosed in a left curly brace {, and the node being traversed is not a leaf node, then this node is assigned the value {, the list access point is moved forward (e.g., {), and this node is pushed onto the watch stack traStack; If the list is currently under a left curly brace { and the node being iterated over is a leaf node, if the data in the next right curly brace is exactly 1, then assign this data and move the list to the position after this right curly brace; otherwise, an error will occur. 3. If the list element is a closing curly brace, and the node being iterated is... 1) For leaf nodes, assign a value of 0, which is padded with zeros by the compiler; 2) For non-leaf nodes, if the node is at the top of the watch stack, pop it from the watch stack and move the list access point accordingly; otherwise, ignore it. 3) Traverse the next node.
[0036] For example, struct A a={3,4,{5,{{6},{7}},8},9}; The corresponding definition is: struct A{ int x; int y; struct B b; int z; }; struct B{ int d; struct C e; int f; }; struct C{ int g; int h; int i; }; After assignment, a multi-way tree is obtained. In this embodiment, if a node contains an array, or if a structure variable is an array, then the array nodes need to be expanded. The expanded nodes are then assigned values using the algorithm described above. The expansion principle is as follows: given a parsed multi-way tree, nodes with array markers are expanded sequentially through a preorder traversal. This process is assisted by a stack. This is a progressive expansion method, expanding the multi-way tree level by level according to the array dimension. This expansion method avoids a large amount of data copying, saving efficiency. The specific steps are as follows: Initialize the stack oriStack, push the head node of the multi-way tree onto the stack, check if the stack oriStack is empty, and if the stack oriStack is not empty, get the top element of the stack oriStack. If the top element of the stack is a non-leaf node and the node has not been fully traversed, push all child nodes of that node onto the stack; if the top element is a leaf node, pop the stack oriStack. If the popped node has an array flag, construct an extended traversal stack exdStack and add the node with the array flag to the constructed extended traversal stack exdStack. Check if the extended traversal stack exdStack is empty. If the extended traversal stack exdStack is not empty, perform a pop operation and obtain the structure type name and structure variable name of the popped element top variable. Retrieve the current dimension, dimension number, and remaining dimension of the array based on the structure type name and structure variable name. For the current node, construct the corresponding number of child nodes based on the current dimension. When constructing child nodes for the current node, if the remaining dimension is 0, directly assign the child node to the `top` variable; if the remaining dimension is not 0, construct a new node, update and record the remaining dimension, and copy the parameters of the `top` variable to the newly constructed node. Continue checking if the expanded traversal stack `exdStack` is empty until all nodes have been processed.
[0037] For example, follow these steps: 1. Initialize the stack oriStack, and push the head node of the multi-way tree onto the stack; 2. Check if the oriStack is empty. If it is not empty, proceed to the next step; otherwise, exit. 3. Retrieve the top element of the oriStack. If it is not a leaf node and has not been fully traversed, push all its child nodes onto the stack; otherwise, pop the element from the oriStack. Check if the popped element is an array identifier. If it is, then: 1) Construct an extended traversal stack exdStack, and push this node onto the stack; 2) Check if exdStack is empty. If it is not empty, perform a pop operation to obtain the structure type name and variable name of the popped element top. According to C language rules, obtain the current dimension, dimension number, and remaining dimension of the array (for example, a[3][4][5], then the current dimension is [3], the dimension number is 3, and the remaining dimension is [4][5]); if the stack is empty, exit. 3) Construct the corresponding number of child nodes on the current node based on the current dimension. If the remaining dimension is 0, directly assign the value of top to the child node; otherwise, construct a new node, record the dimension as the remaining dimension, and copy the parameter of top to this new node. 4) Return to step 2).
[0038] For example, struct A a={3,4,{5,{{6},{7}},8},9}, The corresponding definition is: struct A{ int x; int y; struct B b; int z; } struct B{ int d; struct C e[2]; int f; }; struct C{ int g; int h; int i; }; After assignment, a multi-branch tree of data is obtained. Figure 4 This is an example diagram of another data multi-branch tree obtained after the assignment processing according to the method of the embodiment of the present invention.
[0039] For all types of data currently used in interlocking products, whether one-dimensional or multi-dimensional, they can be parsed according to the steps described above in this embodiment, and combined with the interlocking input data, a final data validity check can be performed.
[0040] Step S3: Verify the expanded data multi-way tree with the standard design data and output the verification results.
[0041] The extended data multi-branch tree is checked for consistency with the standard design data. If they are inconsistent, the check fails. If they are consistent, the extended data multi-branch tree and the standard design data are checked for logical relationship. If the logical relationship between them conforms to the interlocking logic rules, the check passes. If the logical relationship between them does not conform to the interlocking logic rules, the check fails. The check result is then output.
[0042] In practical applications, when verifying the expanded multi-way data tree against standard design data, the multi-way data tree can be converted into a standardized intermediate representation format. The survey and design data can then be parsed into the same intermediate representation format. The values and attributes of the two data structures are compared node by node to check for consistency. The logical relationships between the data are verified according to interlocking business rules, and all inconsistent nodes and rule-violating relationships are recorded. In this embodiment, the logical rule verification specifically includes: verifying the continuity and legality of the segment sequence in the route table; verifying the consistency between the turnout position status and route requirements; verifying the matching relationship between signal display and route status; verifying the track section occupancy status and route locking relationship; and verifying the integrity and consistency of all interlocking relationships.
[0043] The data verification method and system for interlocking products in this embodiment, by introducing a systematic and automated data parsing and verification mechanism, have the following beneficial technical effects: I. Significantly improve the sufficiency and completeness of data validation Traditional black-box testing methods primarily verify explicit data (such as route and turnout numbers), making it difficult to detect implicit errors hidden in complex data structures (such as redundant turnout configurations, incorrect correlations, array out-of-bounds errors, and inconsistent data logic). This invention comprehensively analyzes the data type definitions (including structures, enumerations, and multidimensional arrays) and variable assignments in interlocking software engineering data, constructing precise type multi-way trees and data multi-way trees, achieving deep traversal and mapping of the data structure. This enables the systematic identification and detection of hidden data errors, significantly improving the coverage and thoroughness of data verification and reducing the safety risk of interlocking failures due to data configuration errors.
[0044] II. Significantly improve the efficiency and automation of data verification. Existing technologies heavily rely on manual verification of hidden data, which is not only inefficient but also prone to missed detections due to human error. This invention automates the entire process, from data parsing and tree structure construction to multidimensional array expansion and final data comparison. Through a stack-based post-order traversal algorithm and a progressive multidimensional array expansion algorithm, it can efficiently handle large-scale, highly complex engineering data, avoiding tedious manual verification, significantly shortening the verification cycle, improving the efficiency of interlocking product factory testing, and meeting the demands of a rapidly evolving market.
[0045] III. Enhancing the accuracy and reliability of the verification process Multi-branch tree assignment algorithms (including one-dimensional and multi-dimensional data processing) are a non-compiled data analysis technique that can accurately map values in a data list to corresponding type nodes and strictly follow the syntax and semantic rules of programming languages such as C. This reduces secondary errors caused by manual interpretation or improper tool processing, ensuring the consistency and repeatability of verification results, thus providing a reliable guarantee for the data correctness of interlocking software.
[0046] IV. Possesses good versatility and scalability. It is not designed for specific manufacturers or models of interlocking products, but is based on general programming language syntax rules (such as structure definition, array declaration, typedef usage, etc.), and has good versatility. It is not only applicable to different types of computer interlocking systems, but its core algorithm can also be extended to other equipment in the railway signaling field that require complex data verification (such as train control centers, ATP systems, etc.), and has broad application prospects and high promotion value.
[0047] V. Provides underlying technical safeguards for the security of interlocking systems. By ensuring the correctness of the underlying engineering data of the interlocking software, potential safety hazards caused by data configuration errors are eliminated at the source, such as incorrect turnout driving, incorrect route locking, and abnormal signal display. This builds a solid technical defense line for railway traffic safety and helps prevent major accidents and economic losses caused by interlocking system failures.
[0048] like Figure 5 As shown, the present invention also provides a device including a processor 210, a communication interface 220, a memory 230 for storing a processor-executable computer program, and a communication bus 240. The processor 210, communication interface 220, and memory 330 communicate with each other via the communication bus 240. The processor 210 implements the aforementioned data verification method for interlocking products by running the executable computer program.
[0049] The computer program in memory 230, when implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0050] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected based on actual needs to achieve the purpose of this embodiment. Those skilled in the art can understand and implement this without any creative effort.
[0051] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.
[0052] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A data verification method for interlocking products, characterized in that, The method includes: Step S1: Parse the engineering data configuration file of the interlocking software and construct a data multi-branch tree; Step S2: Perform progressive hierarchical expansion of the multidimensional array nodes in the data multi-way tree; including: Initialize the stack oriStack, push the head node of the multi-way tree onto the stack, check if the stack oriStack is empty, and if the stack oriStack is not empty, get the top element of the stack oriStack. If the top element of the stack is a non-leaf node and the node has not been fully traversed, push all child nodes of that node onto the stack; if the top element is a leaf node, pop the stack oriStack. If the popped node has an array flag, construct an extended traversal stack exdStack and add the node with the array flag to the constructed extended traversal stack exdStack. Check if the extended traversal stack exdStack is empty. If the extended traversal stack exdStack is not empty, perform a pop operation and obtain the structure type name and structure variable name of the popped element top variable. Get the current dimension, dimension number, and remaining dimension of the array based on the structure type name and structure variable name. Build the corresponding number of child nodes on the current node based on the current dimension. Continue to check whether the extended traversal stack exdStack is empty until all nodes have been processed. Step S3: Verify the expanded data multi-way tree with the standard design data and output the verification results.
2. The data verification method for interlocking products according to claim 1, characterized in that, In step S1, constructing a data multi-way tree includes: constructing a type multi-way tree according to the data type definition, creating a node for each data type, using basic types as leaf nodes, using composite types as intermediate nodes, representing the data nesting structure through parent-child relationships, and adding dimension attributes to array type nodes.
3. The data verification method for interlocking products according to claim 1, characterized in that, A data multi-branch tree is constructed based on variable definitions and type multi-branch trees. A post-order traversal algorithm is used to traverse the type multi-branch tree. A node stack is used to manage the traversal process. By monitoring the traStack to match curly braces, the data in the data list is assigned to the corresponding nodes according to the type structure.
4. The data verification method for interlocking products according to claim 3, characterized in that, If the currently read data element is a number, and the node popped from the node stack is a leaf node, assign the number to that node and move the access position of the data list forward by one position. If the currently read data element is a left curly brace and the currently traversed node is a non-leaf node, assign the left curly brace to the node, move the access position of the data list forward by one position, and push the current node onto the watch stack. If the currently read data element is a left curly brace and the currently traversed node is a leaf node, check if there is only one data element immediately following it until the next right curly brace. If so, assign the unique value to the current leaf node and move the data list access point to the position after the right curly brace. Otherwise, it is determined that the data is incorrect and the process is terminated. If the currently read data element is a right curly brace and the currently traversed node is a leaf node, assign the value 0 to that node; If the currently read data element is a right curly brace and the currently traversed node is a non-leaf node, check if the top element of the watch stack traStack is the current node. If it is, perform a pop operation and move the data list access position forward by one position. Otherwise, ignore the right curly brace and traverse the next node.
5. The data verification method for interlocking products according to claim 1, characterized in that, In step S2, when constructing the corresponding number of child nodes on the current node based on the current dimension, if the remaining dimension is 0, the child node is directly assigned the value of the top variable; if the remaining dimension is not 0, a new node is constructed, the remaining dimension is updated and recorded, and the parameters of the top variable are copied to the newly constructed node.
6. The interlocking product data verification method according to claim 1, characterized in that, Step S3 includes: The consistency between the expanded data multi-way tree and the standard design data is checked. If the two are inconsistent, the check is deemed to have failed. When both are consistent, the logical relationship between the expanded data multi-branch tree and the standard design data is checked. If the logical relationship between the two conforms to the interlocking logic rules, the check is deemed to have passed. If the logical relationship between the two does not conform to the interlocking logic rules, the check is deemed to have failed, and the check result is output.
7. A data verification system for interlocking products, characterized in that, The system includes a verification server, which includes: The parsing module is used to parse the engineering data configuration file of the interlocking software and build a data multi-branch tree; The extension module is used to progressively expand the multidimensional array nodes in the data multi-way tree; The verification module is used to verify the expanded data multi-way tree against the standard design data and output the verification results.
8. The interlocking product data verification system according to claim 7, characterized in that, The extension module includes: The initialization unit is used to initialize the stack oriStack, push the head node of the multi-branch tree onto the stack, check if the stack oriStack is empty, and if the stack oriStack is not empty, get the top element of the stack oriStack. In the main traversal unit, if the top element of the stack is a non-leaf node and the node has not been traversed, push all child nodes of that node onto the stack; if the top element of the stack is a leaf node, perform a pop operation on the stack oriStack. The array detection unit, if the popped node has an array flag, constructs an extended traversal stack exdStack and adds the node with the array flag to the constructed extended traversal stack exdStack. An extended processing unit is used to determine whether the extended traversal stack exdStack is empty. If the extended traversal stack exdStack is not empty, a pop operation is performed to obtain the structure type name and structure variable name of the popped element top variable. The dynamic loop unit is used to obtain the current dimension, dimension number, and remaining dimension of the array based on the structure type name and structure variable name. It constructs the corresponding number of child nodes on the current node according to the current dimension, and continues to check whether the extended traversal stack exdStack is empty, until all nodes have been processed.
9. The data verification system for interlocking products according to claim 8, characterized in that, When constructing the corresponding number of child nodes on the current node based on the current dimension, if the remaining dimension is 0, directly assign the child node to the top variable; if the remaining dimension is not 0, construct a new node, update and record the remaining dimension, and copy the parameters of the top variable to the newly constructed node.
10. A computer device, characterized in that, The computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method according to any one of claims 1-6.