Flash memory decoding method, flash memory decoding device and computer storage medium

Abstract

The invention provides a flash memory decoding method, a flash memory decoding device and a computer storage medium. The flash memory decoding method comprises the steps that in response to hard decision failure, the current check state of a check node is obtained, and the check node is connected with a plurality of variable nodes; obtaining the variable states of a plurality of variable nodes in the previous stage; traversing and updating each variable node in the plurality of variable nodes: acquiring an updating factor of the current stage, the updating factor being iteratively changed according to the updating stage; determining a target variable node in the plurality of variable nodes and residual variable nodes; obtaining a residual log-likelihood ratio sent to the check node by the residual variable node; and according to the residual log-likelihood ratio and the update factor of the current stage, calculating a target residual log-likelihood ratio sent to the target variable node by the check node. According to the flash memory decoding method, the updating factor of iteration change is introduced, the error correction performance of soft decoding is improved, and soft decoding convergence is accelerated.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a flash memory decoding method, a flash memory decoding device, and a computer storage medium. Background Technology

[0002] As flash memory density increases, the raw bit error rate (RBER) becomes increasingly higher. LDPC (Low-density Parity-check) codes offer powerful soft decoding error correction capabilities and are widely used in flash memory systems. To maintain data reliability, flash memory systems employ various measures for read recovery. Traditionally, when decoding failure occurs, a retry process is first performed, adjusting the read voltage offset according to the retry table (hard read), followed by hard decoding. If retry still fails to correct errors, a soft reading process is used to obtain soft information, which is then mapped to an LLR (Log-Likelihood Ratio) value and input into the soft decoder (soft decoding).

[0003] The error correction performance of LDPC codes determines the reliability of NAND data, while the error correction performance of LDPC soft decoding determines the upper limit of data reliability. The soft decoding algorithm corrects erroneous codewords by iteratively updating the LLR value of codeword bits between variable nodes and check nodes.

[0004] Depending on the function used to update the check nodes (c-nodes), soft decoding algorithms are categorized into BP (Belief Propagation), NMS (Normalized Min-Sum), OMS (Offset Min-Sum), and MS (Min-Sum). In practice, LDPC soft decoders typically require high throughput. BP decoding involves significant computation, while MS has poor error correction performance. Therefore, NMS and OMS algorithms are commonly used in storage systems to correct erroneous codewords. In existing soft decoders, the NMS algorithm uses only a single normalization factor alpha to optimize performance during decoding, and the OMS algorithm similarly uses only an offset factor beta. This approach offers limited improvement to the error correction performance of soft decoding. Summary of the Invention

[0005] To address the aforementioned technical problems, this application proposes a flash memory decoding method, a flash memory decoding device, and a computer storage medium.

[0006] To address the aforementioned technical problems, this application proposes a flash memory decoding method, which includes: In response to a hard decision failure, the current verification status of the verification node is obtained, wherein the verification node is connected to several variable nodes; Obtain the variable state of the aforementioned variable nodes in the previous stage; Iterate through and update each of the aforementioned variable nodes: Obtain the update factor for the current stage, wherein the update factor changes iteratively according to the update stage; Determine the target variable node and the remaining variable nodes among the aforementioned variable nodes; Obtain the remaining log-likelihood ratio value sent by the remaining variable node to the verification node; The target residual log-likelihood ratio is calculated by comparing the residual log-likelihood ratio with the update factor of the current stage. The target residual log-likelihood ratio sent by the verification node to the target variable node is then calculated.

[0007] The step of obtaining the update factor for the current stage includes: The update factor for the current stage is calculated based on the log-likelihood ratio sent from the variable node to the verification node in the previous stage.

[0008] The step of calculating the update factor for the current stage based on the log-likelihood ratio sent by the variable node to the verification node in the previous stage includes: Obtain the log-likelihood ratio value of the variable node received by each verification node; Based on the log-likelihood ratio received by each verification node, the update factor of each verification node in the current stage is calculated.

[0009] The step of calculating the update factor for each verification node in the current stage based on the log-likelihood ratio received by each verification node includes: Traverse the several variable nodes connected to each verification node and obtain the log-likelihood ratio of other variable nodes corresponding to each variable node. Based on the log-likelihood ratio of the other variable nodes, calculate the update factor of the verification node for each variable node in the current stage.

[0010] The step of calculating the update factor of the verification node for each variable node in the current stage based on the log-likelihood ratio of the other variable nodes includes: Based on the mean of the log-likelihood ratios of the other variable nodes, the update factor of the verification node for each variable node in the current stage is determined.

[0011] The step of obtaining the update factor for the current stage includes: Obtain the number of iterations for the current stage; The update factor for the current stage is determined based on the number of iterations already performed.

[0012] Wherein, determining the update factor for the current stage based on the number of iterations includes: Calculate the iteration factor based on the number of iterations and the preset update parameters; The larger value between the iteration factor and the preset upper limit value is used to determine the update factor for the current stage; Alternatively, the larger of the iteration factor and the preset lower limit value can be used to determine the update factor for the current stage.

[0013] The step of obtaining the update factor for the current stage includes: The first update factor for the current stage is obtained according to the first soft decoding algorithm; The second update factor for the current stage is obtained according to the second soft decoding algorithm; The update factor for the current stage is determined based on the first update factor and the second update factor; The first soft decoding algorithm and the second soft decoding algorithm are different, and at least one of the first update factor and the second update factor undergoes iterative changes according to the update stage; The step of calculating the target residual log-likelihood ratio sent by the verification node to the target variable node based on the residual log-likelihood ratio and the update factor of the current stage includes: The update function is determined based on the first soft decoding algorithm and the second soft decoding algorithm; Substitute the update factor of the current stage and the residual log-likelihood ratio into the update function to calculate the target residual log-likelihood ratio sent by the verification node to the target variable node.

[0014] To address the aforementioned technical problems, this application also proposes a flash memory decoding device, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the flash memory decoding method described above.

[0015] To address the aforementioned technical problems, this application also proposes a computer storage medium for storing program data, which, when executed by a computer, is used to implement the aforementioned flash memory decoding method.

[0016] Compared with the prior art, the beneficial effects of this application are: the update factor changes iteratively according to the update stage, so that when the verification node transmits the message to the variable node at each stage, it performs normalization processing or offset processing according to different update factors, thereby improving the soft decoding error correction performance; by iteratively changing the factor through the update stage, it is also beneficial to accelerate the convergence speed of the soft decoder, thereby enhancing the reliability of the NAND system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating an embodiment of the software decoding algorithm provided in this application; Figure 2 This is a flowchart illustrating an embodiment of the flash memory decoding method provided in this application; Figure 3 This is a flowchart illustrating another embodiment of the flash memory decoding method provided in this application; Figure 4 This is a schematic diagram of the structure of an embodiment of the flash memory decoding device provided in this application; Figure 5 This is a schematic diagram of the structure of an embodiment of the computer storage medium provided in this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Solid-state storage, such as solid-state drives (SSDs) and USB cards, is currently in high demand. It stores data using non-volatile flash memory chips, preserving data even when power is lost. However, in SSDs, the optimal read voltage of the flash memory shifts with storage time and the number of erase / write cycles, leading to reduced data reliability.

[0021] As storage density increases, from SLC (Single-Level Cell) to MLC (Multi-Level Cell), TLC (Triple-Level Cell), and even QLC (Quad-Level Cell), the number of bits of data stored per flash memory cell increases, and data reliability gradually decreases. To maintain data reliability, LDPC soft decoding technology is typically used. Soft decoding requires performing multiple read operations (i.e., soft reading) on ​​both sides of the hard read voltage to obtain soft information, which is then mapped to an LLR (log-likelihood ratio) value and input into the soft decoder for decoding.

[0022] This application addresses read data recovery in solid-state storage by optimizing the node update steps in the LDPC software decoder, thereby increasing the software decoding error correction capability and enhancing system reliability.

[0023] Please refer to details. Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the software decoding algorithm provided in this application.

[0024] like Figure 1 As shown, in storage media such as NAND flash memory, hard decision uses only a single threshold voltage to distinguish states (such as 0 / 1). Soft read, on the other hand, requires applying multiple reference voltages on both sides of the hard decision voltage and obtaining probabilistic information about the voltage distribution through multiple reads.

[0025] For each memory cell, at the hard decision voltage Set on both sides An additional reference voltage (e.g.) , ), a total of Each read generates a binary bit, which is combined into a bit tag (e.g., 3 reads generate a 3-bit tag "101"), reflecting the range of the unit voltage.

[0026] By statistically analyzing a large number of cells, a conditional probability density function (PDF) for the voltage distribution is constructed. ,in, The voltage to be read is the stored bit state (0 or 1). In practice, PDFs are often modeled as Gaussian distributions or Gaussian mixture models, with parameters calibrated experimentally.

[0027] Where vector v represents the hard decoding result, H is the LDPC parity check matrix, and t represents the number of iterations. Soft decoding mainly consists of three computational modules: the V2C (VN to CN) information update module for the CN (verification node), the C2V (CN to VN) information update module for the VN (variable node), and the posterior information P update module for the VN.

[0028] based on Figure 1 The soft decoding algorithm scheme shown in this application proposes an improved LDPC soft decoding algorithm, which can reduce the bit error rate, accelerate soft decoding convergence, and increase the soft decoding error correction performance.

[0029] Please continue reading for details. Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the flash memory decoding method provided in this application.

[0030] The flash memory decoding method of this application is applied to a flash memory decoding device, which can be a server, a terminal device, or a system in which the server and the terminal device cooperate with each other. Accordingly, the various parts of the flash memory decoding device, such as each unit, subunit, module, and submodule, can all be set in the server, all in the terminal device, or separately in the server and the terminal device.

[0031] Furthermore, the aforementioned server can be either hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or as a single server. When the server is software, it can be implemented as multiple software programs or software modules, such as software or software modules used to provide distributed server functionality, or as a single software program or software module; no specific limitations are made here.

[0032] like Figure 2 As shown, the specific steps are as follows: Step S11: In response to a hard decision failure, obtain the current verification status of the verification node, wherein the verification node is connected to several variable nodes.

[0033] In the embodiments of this application, such as Figure 1 As shown, in the case of hard-decision decoding failure, i.e. If the condition is not met, the flash memory decoding device can determine the current verification state of the verification node. The current verification state of the verification node is mainly determined by messages passed from the previous node's variable node or by initialization.

[0034] Among them, the check node (CN) represents the check equation (i.e. the coded constraint, such as parity check). Its function is to check whether the connected variable nodes satisfy the preset check equation (such as the modulo 2 sum is 0); and to calculate the influence of the constraint on the adjacent variables based on the message of the variable node.

[0035] Step S12: Obtain the variable state of several variable nodes in the previous stage.

[0036] In this embodiment of the application, during the soft decoding initialization phase, the variable node (VN) is initialized to the LLR value of the corresponding bit:

[0037] in, For the first The initial LLR of 1 bit is mainly derived from channel measurements.

[0038] In phases other than the soft decoding initialization phase, the LLR value of a variable node (VN) is determined by the LLR value of the variable node in the previous phase and the messages passed by all check nodes connected to that variable node in the current phase.

[0039] In a specific LDPC decoding, if the variable node The initial LLR is 1.5. If messages from two check nodes are received with values ​​of 0.8 and -0.3 respectively, the updated confidence level is:

[0040] Step S13: Iterate through and update each variable node in the set of variable nodes.

[0041] In this embodiment of the application, the flash memory decoding device updates each variable node through the following steps S14 to S17.

[0042] Step S14: Obtain the update factor for the current stage, wherein the update factor changes iteratively according to the update stage.

[0043] In this application embodiment, in order to improve the soft decoding error correction performance of the soft decoding algorithm, this application proposes a novel soft decoding algorithm in which the soft decoding factor changes with the number of iterations.

[0044] The factor update schemes for various implementation methods are described below: First, the embodiments of this application use the same update factor in the same stage.

[0045] Specifically, the flash decoding device acquires all LLR values ​​received by all verification nodes from the previous stage variable nodes, and then calculates the update factor for the current stage using all LLR values. The calculation methods include, but are not limited to: function calculation, mapping relationship calculation, mean calculation, maximum value calculation, minimum value calculation, etc.

[0046] Second, in this embodiment, each verification node uses a different update factor in the same stage, and each verification node uses the same update factor when transmitting messages to all connected variable nodes. Specifically, the flash memory decoding device obtains the LLR value transmitted by the connected variable node in the previous stage received by any verification node, and then uses this LLR value to calculate the update factor used by the verification node when transmitting messages to all connected variable nodes in the current stage. The calculation method includes, but is not limited to: function calculation, mapping relationship calculation, mean calculation, maximum value calculation, minimum value calculation, etc.

[0047] For example, verification node Connect variable nodes , , In the previous stage, the variable node , , The LLR values ​​of 1.2, -0.5, and 0.8 are respectively transmitted to the verification node c1. At this time, the verification node... At the current stage, move to the variable node , , The same update factor is used when transmitting messages, and it is calculated based on the LLR values ​​of 1.2, -0.5, and 0.8 mentioned above.

[0048] Third, in this embodiment, each verification node uses a different update factor in the same stage, and each verification node uses a different update factor when transmitting messages to all connected variable nodes. Specifically, the flash memory decoding device obtains the LLR value transmitted by the connected variable node to any verification node in the previous stage. For one of the connected variable nodes, the update factor used by the verification node to transmit messages to the variable node is calculated based on the LLR values ​​transmitted by other variable nodes.

[0049] For example, verification node Connect variable nodes , , In the previous stage, the variable node , , The LLR values ​​of 1.2, -0.5, and 0.8 are respectively transmitted to the verification node c1. At this time, the verification node... At the current stage, move to the variable node , , Different update factors are used when transmitting messages. At the verification node... To variable node When transmitting messages, the update factor used is calculated based on the LLR values ​​of -0.5 and 0.8 mentioned above.

[0050] Fourth, the embodiments of this application use the same update factor in the same stage.

[0051] Specifically, the flash memory decoding device first obtains the optimal update factor for each iteration through offline simulation, and then stores all update factors using a mapping table, as shown in the table below:

[0052] Therefore, the flash memory decoding device determines the number of iterations for the current node, i.e. Figure 1 The t value shown can be used to determine the update factor used for message transmission in the current stage by looking up a table.

[0053] Fifth, the embodiments of this application use the same update factor in the same stage.

[0054] Specifically, the flash memory decoding device determines the update factor through a function. In one specific implementation, the function used can be expressed as: alpha_iter = max(iter * 0.6, 1). Here, alpha_iter is the update factor, and iter is the number of iterations. In other embodiments, the function parameter 0.6 for the step size and the function parameter 1 for the preset upper limit can be set to other values ​​according to the needs of the operator; these are not listed here.

[0055] Specifically, the flash memory decoding device determines the update factor through a function. In one specific implementation, the function used can be expressed as: alpha_iter = max(iter * 0.2, 0.6). Here, alpha_iter is the update factor, and iter is the number of iterations. In other embodiments, the function parameter 0.2 for the step size and the function parameter 0.6 for the preset lower limit can be set to other values ​​according to the operator's needs, which will not be listed here.

[0056] Step S15: Determine the target variable node and the remaining variable nodes among the several variable nodes.

[0057] Step S16: Obtain the remaining log-likelihood ratio sent by the remaining variable node to the verification node.

[0058] Step S17: Calculate the target residual log-likelihood ratio sent by the verification node to the target variable node based on the residual log-likelihood ratio and the update factor of the current stage.

[0059] In this embodiment of the application, the flash memory decoding device uses the update factor determined in step S14 to calculate the message passed by the verification node to each of the connected variable nodes.

[0060] Specifically, the function for calculating the transmitted message is mainly determined by the software decoding algorithm. For example, in the NMS algorithm mentioned above, the expression for the check node to update the C2V message using alpha_iter (update factor) is as follows:

[0061] in, Represents variable nodes The LLR value sent to check node i, where alpha_iter represents the normalization factor alpha_iter for different iterations. This represents the set of adjacent variable nodes of node i. This represents the LLR value sent by check node i to variable node j. This indicates the exclusion of the current target variable node. .

[0062] The alpha_iter normalization factor is dynamically adjusted with the number of iterations to compensate for the overestimation problem of the Min-Sum algorithm.

[0063] In one specific implementation, the verification node Connect variable nodes Current calculation sent to News .

[0064] The V2C messages for the (t-1)th iteration are as follows:

[0065]

[0066] The normalization factor alpha_iter = 0.8.

[0067] In conclusion,

[0068] Therefore, it can be concluded that the verification node Suggested variable nodes Prefer bit 1 (because LLR is negative).

[0069] For example, in the OMS algorithm mentioned above, the expression for the verification node to update the C2V message using beta_iter (update factor) is as follows:

[0070] in, This represents the LLR value sent from the variable node to the check node i, and beta_iter represents the offset factor beta_iter for different iterations. This represents the set of adjacent variable nodes of node i. This represents the LLR value sent by verification node i to variable node j.

[0071] Furthermore, this application is based on Figure 2 Steps S14 and S17 of the flash memory decoding method shown are used to propose another flash memory decoding method. Please refer to [link to relevant documentation] for details. Figure 3 , Figure 3 This is a flowchart illustrating another embodiment of the flash memory decoding method provided in this application.

[0072] like Figure 3 As shown, the specific steps are as follows: Step S21: Obtain the first update factor for the current stage according to the first soft decoding algorithm.

[0073] In this embodiment of the application, the flash memory decoding device can determine the normalization factor alpha_iter of the current node according to the NMS algorithm.

[0074] Step S22: Obtain the second update factor for the current stage according to the second soft decoding algorithm.

[0075] In this embodiment of the application, the flash memory decoding device can determine the offset factor beta_iter of the current node according to the OMS algorithm.

[0076] Step S23: Determine the update factor for the current stage based on the first update factor and the second update factor.

[0077] In this embodiment of the application, at least one of the normalization factor alpha_iter in step S21 and the offset factor beta_iter in step S22 is iteratively changed according to the update stage, that is, the update factor is determined by the content of step S14 above.

[0078] Step S24: Determine the update function based on the first soft decoding algorithm and the second soft decoding algorithm.

[0079] Step S25: Substitute the update factor and the residual log-likelihood ratio of the current stage into the update function to calculate the target residual log-likelihood ratio sent by the verification node to the target variable node.

[0080] In this embodiment, combining the NMS and OMS algorithms, the expression for the verification node to update the C2V message using alpha_iter (normalization factor) and offset factor (beta_iter) is as follows:

[0081] It should be noted that the iterative changes of the update factor in this application are also applicable to any soft decoding algorithm and its combination, which will not be elaborated here.

[0082] The flash memory decoding method of this application reduces the soft decoding error rate and accelerates the convergence speed of the soft decoder by designing a scheme to change the factors of the OMS and NMS algorithms at runtime, thereby enhancing the reliability of the NAND system.

[0083] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0084] To implement the above flash memory decoding method, this application also proposes a flash memory decoding apparatus, for details please refer to [link to details]. Figure 4 , Figure 4 This is a schematic diagram of an embodiment of the flash memory decoding device provided in this application.

[0085] The flash memory decoding device 400 in this embodiment includes a processor 41, a memory 42, an input / output device 43, and a bus 44.

[0086] The processor 41, memory 42, and input / output device 43 are respectively connected to the bus 44. The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the flash memory decoding method described in the above embodiment.

[0087] In this embodiment, processor 41 can also be referred to as a CPU (Central Processing Unit). Processor 41 may be an integrated circuit chip with signal processing capabilities. Processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 41 can be any conventional processor.

[0088] This application also provides a computer storage medium; please refer to the following: Figure 5 , Figure 5 This is a schematic diagram of a computer storage medium according to an embodiment of the present application. The computer storage medium 600 stores a computer program 61, which, when executed by a processor, is used to implement the flash memory decoding method of the above embodiment.

[0089] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A flash memory decoding method, characterized in that, The flash memory decoding method includes: In response to a hard decision failure, the current verification status of the verification node is obtained, wherein the verification node is connected to several variable nodes; Obtain the variable state of the aforementioned variable nodes in the previous stage; Iterate through and update each of the aforementioned variable nodes: Obtain the update factor for the current stage, wherein the update factor changes iteratively according to the update stage; Determine the target variable node and the remaining variable nodes among the aforementioned variable nodes; Obtain the remaining log-likelihood ratio value sent by the remaining variable node to the verification node; The target residual log-likelihood ratio is calculated by comparing the residual log-likelihood ratio with the update factor of the current stage. The target residual log-likelihood ratio sent by the verification node to the target variable node is then calculated.

2. The flash memory decoding method according to claim 1, characterized in that, The step of obtaining the update factor for the current stage includes: The update factor for the current stage is calculated based on the log-likelihood ratio sent from the variable node to the verification node in the previous stage.

3. The flash memory decoding method according to claim 2, characterized in that, The step of calculating the update factor for the current stage based on the log-likelihood ratio sent by the variable node to the verification node in the previous stage includes: Obtain the log-likelihood ratio value of the variable node received by each verification node; Based on the log-likelihood ratio received by each verification node, the update factor of each verification node in the current stage is calculated.

4. The flash memory decoding method according to claim 3, characterized in that, The step of calculating the update factor for each verification node in the current stage based on the log-likelihood ratio received by each verification node includes: Traverse the several variable nodes connected to each verification node and obtain the log-likelihood ratio of other variable nodes corresponding to each variable node. Based on the log-likelihood ratio of the other variable nodes, calculate the update factor of the verification node for each variable node in the current stage.

5. The flash memory decoding method according to claim 4, characterized in that, The step of calculating the update factor of the verification node for each of the variable nodes in the current stage based on the log-likelihood ratio of the other variable nodes includes: Based on the mean of the log-likelihood ratios of the other variable nodes, the update factor of the verification node for each variable node in the current stage is determined.

6. The flash memory decoding method according to claim 1, characterized in that, The step of obtaining the update factor for the current stage includes: Obtain the number of iterations for the current stage; The update factor for the current stage is determined based on the number of iterations already performed.

7. The flash memory decoding method according to claim 6, characterized in that, Determining the update factor for the current stage based on the number of iterations includes: Calculate the iteration factor based on the number of iterations and the preset update parameters; The larger value between the iteration factor and the preset upper limit value is used to determine the update factor for the current stage; Alternatively, the larger of the iteration factor and the preset lower limit value can be used to determine the update factor for the current stage.

8. The flash memory decoding method according to claim 1, characterized in that, The step of obtaining the update factor for the current stage includes: The first update factor for the current stage is obtained according to the first soft decoding algorithm; The second update factor for the current stage is obtained according to the second soft decoding algorithm; The update factor for the current stage is determined based on the first update factor and the second update factor; The first soft decoding algorithm and the second soft decoding algorithm are different, and at least one of the first update factor and the second update factor undergoes iterative changes according to the update stage; The step of calculating the target residual log-likelihood ratio sent by the verification node to the target variable node based on the residual log-likelihood ratio and the update factor of the current stage includes: The update function is determined based on the first soft decoding algorithm and the second soft decoding algorithm; Substitute the update factor of the current stage and the residual log-likelihood ratio into the update function to calculate the target residual log-likelihood ratio sent by the verification node to the target variable node.

9. A flash memory decoding device, characterized in that, The flash memory decoding device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the flash memory decoding method as described in any one of claims 1 to 8.

10. A computer storage medium, characterized in that, The computer storage medium is used to store program data, which, when executed by the computer, is used to implement the flash memory decoding method as described in any one of claims 1 to 8.

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