Data transceiving and high-speed storage system based on domestic PSOC

Abstract

The invention provides a data transceiving and high-speed storage system based on a domestic PSOC (programmable system on chip), which comprises a PSOC control layer which takes a Feidan micro PSOC as a core arithmetic unit and provides bottom computing power support for efficient operation of the system by means of excellent hardware acceleration capability and flexible programmable characteristics; the high-speed data interaction layer carries a multi-protocol receiving and transmitting module composed of RS422, CANFD, 4M 1553B, a gigabit Ethernet and an optical module, can be compatible with multi-scene data transmission requirements, realizes high-speed stable receiving and transmitting of multi-type data, and breaks the bandwidth bottleneck; according to the high-speed data storage layer, EMMC, SATA and NVMe SSD multi-element media are creatively integrated, a hierarchical high-capacity high-speed storage architecture is constructed, the requirement for real-time storage of mass data is met, data calling instantaneity is guaranteed, and guarantee is provided for high-throughput scene data processing and storage. Through various communication protocols and various high-speed storage devices, the compatibility and universality of the control system are improved.

Description

Technical Field

[0001] This invention relates to the field of data transceiver and high-speed storage, specifically to a data transceiver and high-speed storage system based on a domestically produced PSOC. Background Technology

[0002] A PSOC (System-on-a-Chip) data transceiver and high-speed storage system is an integrated hardware and software solution based on a programmable system-on-a-chip (PSOC). Its core function is to achieve efficient data acquisition, real-time transmission, and high-capacity, fast storage. This system typically utilizes the PSOC's configurable digital and analog modules to flexibly adapt to various sensors or communication interfaces (such as UART, SPI, USB, etc.) for data reception. Through internal high-performance processing units or Direct Memory Access (DMA) technology, it ensures low latency and high throughput during data transmission and reception. Simultaneously, combined with external high-speed storage media (such as SD cards, SSDs, or SRAM), along with optimized file systems and cache management, it enables real-time writing and reliable storage of massive amounts of data. It is widely used in fields requiring real-time processing and recording of streaming data, such as the Internet of Things (IoT), industrial monitoring, and high-speed testing instruments.

[0003] Currently, in high-throughput data processing scenarios—such as high-end equipment status data acquisition and multi-source information interaction of intelligent terminals—traditional data processing systems are gradually revealing significant shortcomings. On the one hand, insufficient protocol compatibility makes it difficult for the system to adapt to various bus types such as RS422, CANFD, and 1553B, as well as transmission interfaces such as Ethernet and optical modules, thus failing to achieve unified reception and transmission of multi-source heterogeneous data. On the other hand, the storage architecture is singular, relying heavily on traditional mechanical hard drives or a single type of flash memory, which is insufficient to meet the real-time storage requirements of massive amounts of data, nor can it satisfy the demand for rapid retrieval of high-priority data. Existing systems cannot meet the integrated and highly reliable requirements for high-speed transmission and reception of multiple types of data and stable storage of massive amounts of information. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a data transceiver and high-speed storage system based on a domestically produced PSOC, thereby solving the problems mentioned in the background. This invention is compatible with data transmission needs in multiple scenarios, enabling high-speed and stable transmission and reception of various types of data and breaking through bandwidth bottlenecks. It can also use multi-media high-speed storage to construct a hierarchical, large-capacity, high-speed storage architecture, meeting the real-time storage needs of massive amounts of data and ensuring the immediacy of data retrieval.

[0005] To achieve the above objectives, the present invention provides a data transceiver and high-speed storage system based on a domestically produced PSOC, comprising a PSOC control layer, a high-speed data interaction layer, and a high-speed data storage layer. The PSOC control layer is the smallest control unit. The high-speed data interaction layer is equipped with an RS422 transceiver unit, a 4M 1553B transceiver unit, a CANFD transceiver unit, a gigabit network transceiver unit, and an optical module transceiver unit. The high-speed data storage layer is equipped with a SATA storage unit, an eMMC storage unit, and an NVMe SSD storage unit.

[0006] Furthermore, the PSOC control layer includes a DDR3 unit, a crystal oscillator, a NORFLASH, a debugging interface, and a power supply module; the high-speed data interaction layer is used to achieve high-speed and stable transmission and reception of multiple types of data; and the high-speed data storage layer is used to construct a hierarchical, large-capacity, high-speed storage architecture.

[0007] Furthermore, the high-speed data interaction layer is connected to the Gigabit Ethernet physical layer chip through a simplified Gigabit Media Independent Interface integrated into the UltraScale+MPSoC processing system.

[0008] Furthermore, the 4M 1553B interface adopts a dual redundancy design, using transceiver chips and transformers to build the circuit.

[0009] Furthermore, the high-speed data interaction layer uses the SRIO interface of the main controller to connect with the optical module, and the GTH high-speed port of the main controller directly outputs the parallel receiving and transmitting light modules to the outside.

[0010] Furthermore, in the high-speed data storage layer, the UltraScale+MPSoC processing system is equipped with multiple SD control interfaces for connecting SDIO drivers, SD memory cards and eMMC cards, and supports both 1-bit and 4-bit working modes, and stores data through external eMMC memory.

[0011] Furthermore, in the PSOC control layer, the UltraScale+MPSoC loads and boots via Quad-SPI, SD, eMMC, USB 2.0, or NAND.

[0012] Furthermore, the PSOC control layer uses external memory, including DDR3 and DDR2.

[0013] Furthermore, the external debugging interface of the high-speed storage system includes an RS232 interface and a JTAG interface for system debugging.

[0014] The beneficial effects of this invention are:

[0015] 1. This data transceiver and high-speed storage system based on domestic PSOC has a unique "processor + FPGA" heterogeneous architecture, which combines excellent hardware acceleration capabilities with flexible programmability. The hardware acceleration capability can significantly improve data throughput efficiency and meet the real-time computing needs in high-concurrency scenarios.

[0016] 2. This data transceiver and high-speed storage system based on domestic PSOC is equipped with a multi-protocol transceiver module consisting of RS422, CANFD, 4M 1553B, Gigabit Ethernet and optical modules in the high-speed data interaction layer. It can be compatible with data transmission needs in multiple scenarios, realize high-speed and stable transmission and reception of multiple types of data, and break through the bandwidth bottleneck.

[0017] 3. This data transceiver and high-speed storage system based on domestic PSOC innovatively integrates eMMC, SATA and NVMe SSD multi-media in the high-speed data storage layer to build a hierarchical large-capacity high-speed storage architecture, meet the real-time storage needs of massive data, ensure the immediacy of data retrieval, and provide a guarantee for data processing and storage in high-throughput scenarios. Attached Figure Description

[0018] Figure 1 This is a general block diagram of a data transceiver and high-speed storage system based on a domestically produced PSOC according to the present invention;

[0019] Figure 2 This is a circuit diagram of a data transceiver and high-speed storage system based on a domestically produced PSOC, according to the present invention. Detailed Implementation

[0020] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0021] Please see Figures 1 to 2 This invention provides the following technical solution: a data transceiver and high-speed storage system based on a domestically produced PSOC, comprising a main control layer with the Fudan Micro ZYNQ chip as the smallest control unit of the core computing unit. Leveraging its unique "processor + FPGA" heterogeneous architecture, it possesses both excellent hardware acceleration capabilities and flexible programmability. The hardware acceleration capability significantly improves data throughput efficiency, meeting the real-time computing needs of high-concurrency scenarios. A high-speed data interaction layer is equipped with a multi-protocol transceiver module consisting of RS422, CANFD, 4M 1553B, Gigabit Ethernet, and optical modules, compatible with data transmission needs in multiple scenarios, enabling high-speed and stable transmission and reception of various types of data, breaking through bandwidth bottlenecks. A high-speed data storage layer innovatively integrates eMMC, SATA, and NVMe SSD media to construct a hierarchical, large-capacity, high-speed storage architecture, meeting the real-time storage needs of massive amounts of data, ensuring the immediacy of data retrieval, and providing assurance for data processing and storage in high-throughput scenarios.

[0022] Specifically, the overall system block diagram is as follows: Figure 1 As shown, it consists of three parts:

[0023] ①PSOC Control Layer (Minimum Control Unit): The smallest control unit with Fudan Micro ZYNQ chip as the core computing unit. With its unique "processor + FPGA" heterogeneous architecture, it has both excellent hardware acceleration capabilities and flexible programmability. The hardware acceleration capability can greatly improve data throughput efficiency and meet the real-time computing needs in high-concurrency scenarios.

[0024] ② High-speed data interaction layer: Equipped with a multi-protocol transceiver module consisting of RS422, CANFD, 4M 1553B, Gigabit Ethernet and optical modules, it can be compatible with data transmission needs in multiple scenarios and realize high-speed and stable transmission and reception of multiple types of data;

[0025] High-speed data storage layer: Innovatively integrates eMMC, SATA and NVMe SSD multi-media to build a hierarchical high-capacity high-speed storage architecture, meeting the real-time storage needs of massive data, ensuring the immediacy of data retrieval, and providing a guarantee for data processing and storage in high-throughput scenarios.

[0026] System circuit diagram as follows Figure 2 As shown, the specific content is as follows:

[0027] 1. High-speed data interaction layer:

[0028] 01. By connecting the RGMII (Simplified Gigabit Media Independent Interface) integrated on the PS (Processing System) side of the UltraScale+MPSoC to the Gigabit Ethernet PHY (Physical Layer) chip, a single Gigabit Ethernet signal output is ultimately achieved;

[0029] The 02.4M 1553B interface features a dual-redundancy design, utilizing transceiver chips and transformers to build the circuit.

[0030] 03. Connect the transceiver using the controller's CAN FD IP core, and use the ADI ADM3055E CAN FD transceiver with its own isolated power supply. The maximum communication rate is up to 12Mbps, and it supports CAN and CAN FD.

[0031] 04. In this embodiment, the Analog Devices (ADI) RS422 transceiver ADM2682 is used to connect to the main controller. This chip is a high-performance signal isolation device with its own isolated power supply, possessing extremely strong anti-interference capabilities and a maximum communication rate of up to 16Mbps;

[0032] 05. The main control unit uses its SRIO interface to connect to the optical module. The main control unit's GTH high-speed port directly outputs parallel transceiver modules. The optical module model is 4EOLTR-85-512 x23M. From a hardware core configuration perspective, this optical module integrates four independent transmit channels and four independent receive channels, forming a multi-channel parallel fiber optic transmission architecture. The high-speed signal pins use AC CML level, and the optical interface is an MT / MPO interface with a pigtail.

[0033] 2. High-speed data storage layer:

[0034] 06. In this embodiment, the SATA solid-state drive selected is the HTUSU128G-WM from Hongqin Technology. The chip storage capacity is 128G, and it adopts the SATA3.0 interface, which can realize the storage of large-capacity data. The maximum continuous read speed can reach 500MB / s, and the maximum continuous write speed can reach 420MB / s.

[0035] 07. The UltraScale+MPSoC's PS (processing system) is equipped with two SD control interfaces. These interfaces are highly compatible and can connect to SDIO drivers, SD memory cards, and eMMC cards. They also support both 1-bit and 4-bit working modes to adapt to the transmission needs of different scenarios. To meet the data storage function, an external eMMC memory with a storage size of 128G is selected for data storage in the design.

[0036] 08. In this embodiment, the NVMe SSD uses an M.2 interface card. The M.2 interface is a compact physical interface. The M.2 interface SSD can support the NVMe protocol (using the PCIe channel). The NVMe protocol is a high-speed transmission protocol specifically designed for SSDs (not the traditional SATA protocol). It works based on the PCIe bus and can fully utilize the parallel read and write capabilities of the SSD.

[0037] 3. PSOC Control Layer (Minimum Control Unit):

[0038] 09. The UltraScale+ MPSoC can load boot methods via Quad-SPI, SD, eMMC, USB2.0 or NAND. In this system, Quad-SPI is used for boot loading, with a storage capacity of 64MB.

[0039] 010. The PSOC can process and transmit data quickly. To ensure the system runs fast, efficiently, and smoothly, external memory, such as DDR3 or DDR2, is usually required. The host interface supports DDR3, DDR3L, DDR2, and LPDDR2, with 8, 16, and 32-bit bit widths and a maximum memory capacity of 1GB. In this system, a DDR3 memory interface with a 32-bit width and a speed of 1600MT / s is used.

[0040] 011. The system's external debugging interface includes one RS232 interface and one JTAG interface for system debugging;

[0041] 012. In this embodiment, the FMQL series programmable fusion chip is a fully programmable PSOC chip from Fudan Microelectronics. It integrates a processing system (PS) based on a feature-rich quad-core high-performance processor and programmable logic (PL) on a single chip. The system uses the FMQL45T900 from Shanghai Fudan Microelectronics. The quad-core high-performance CPU is the core of the processor system. It works in conjunction with on-chip memory, external memory interface DDR, various system functional components, I / O peripherals, and the programmable logic section (containing 350K logic resources) to form the minimum control unit of the system, jointly creating a feature-rich on-chip programmable system, providing a more flexible solution for embedded systems.

[0042] The foregoing has shown and described the basic principles and main features of the present invention and its advantages. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0043] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A data transceiver and high-speed storage system based on a domestically produced PSOC, characterized in that: It includes a PSOC control layer, a high-speed data interaction layer, and a high-speed data storage layer. The PSOC control layer is the smallest control unit. The high-speed data interaction layer is equipped with an RS422 transceiver unit, a 4M 1553B transceiver unit, a CANFD transceiver unit, a gigabit network transceiver unit, and an optical module transceiver unit. The high-speed data storage layer is equipped with a SATA storage unit, an eMMC storage unit, and an NVMe SSD storage unit.

2. The data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 1, characterized in that: The PSOC control layer includes a DDR3 unit, a crystal oscillator, a NORFLASH, a debugging interface, and a power supply module; the high-speed data interaction layer is used to achieve high-speed and stable transmission and reception of multiple types of data; and the high-speed data storage layer is used to construct a hierarchical, large-capacity, high-speed storage architecture.

3. The data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 1, characterized in that: The high-speed data interaction layer is connected to the Gigabit Ethernet physical layer chip through a simplified Gigabit Media Independent Interface integrated into the UltraScale+MPSoC processing system.

4. A data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 3, characterized in that: The 4M 1553B interface adopts a dual redundancy design, using transceiver chips and transformers to build the circuit.

5. A data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 3, characterized in that: The high-speed data interaction layer uses the SRIO interface of the main controller to connect with the optical module, and the GTH high-speed port of the main controller directly outputs the parallel receiving and transmitting optical modules to the outside.

6. A data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 1, characterized in that: In the high-speed data storage layer, the UltraScale+MPSoC processing system is equipped with multiple SD control interfaces for connecting SDIO drivers, SD memory cards and eMMC cards, and supports both 1-bit and 4-bit working modes, and stores data through external eMMC memory.

7. A data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 1, characterized in that: In the PSOC control layer, the UltraScale+MPSoC loads and boots via Quad-SPI, SD, eMMC, USB 2.0, or NAND.

8. A data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 7, characterized in that: The PSOC control layer uses external memory, including DDR3 and DDR2.

9. A data transceiver and high-speed storage system based on a domestically produced PSOC according to claim 1, characterized in that: The external debugging interfaces of the high-speed storage system include RS232 and JTAG interfaces for system debugging.

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