Communication method for SPI bus controller and screen IC based on LK stage

Abstract

The invention discloses a communication method for an SPI bus controller and a screen IC based on an LK stage. The communication method comprises the following steps that a, SPI controller hardware is configured, a GPIO function mode function is dynamically configured, and a register structural body is created; b, an SPI controller initialization function is configured, SPI communication behaviors are customized based on SPI controller parameters, and a data sending end sequence mode is configured; c, a data receiving function and a data sending function are packaged, the data receiving function directly reads the data from the receiving register, and the data sending function processes the data and then sends the data to the screen IC; and d, initializing the screen IC. According to the method, register access and control, read and write function packaging and platform embedding of the SPI bus controller are carried out in the LK stage, so that the SPI bus controller is called to receive and send data in the LK stage, the purpose of efficiently and accurately completing data receiving and sending is achieved, and the method has the advantages of being high in transmission rate, short in overall startup time and the like.

Description

Technical Field

[0001] This invention relates to the field of embedded systems and display driver technology, and in particular to a communication method between an LK-stage SPI bus controller and a screen IC. Background Technology

[0002] During the boot process of embedded devices (such as smartphones and tablets), the bootloader (such as LittleKernel, LK) stage needs to quickly initialize the display screen to show the boot logo or debugging information. Traditional GPIO-simulated SPI communication protocols, when receiving and sending data, use GPIO to simulate the SPI communication protocol for follower communication. This requires strict adherence to the SPI communication protocol timing, controlling the high and low levels of the GPIOs corresponding to the MISO / MOSI / CS / SCLK signal lines connected to the follower device through GPIO operation functions. This requires numerous GPIO operations, resulting in low transmission rates, poor waveform signal accuracy, and insufficient or excessively long GPIO level durations, all of which can lead to abnormal data reception and transmission. Using a logic analyzer to capture signal waveforms, the highest clock signal simulated by GPIO can only reach 1.25MHz, causing significant latency in high-speed, high-throughput scenarios such as displaying images on a screen. Actual testing showed that it takes 1060ms to process a 320*240 resolution RGB565 format logo image. This time is included in the boot time, which cannot meet the boot time requirement. Furthermore, since each transmission is done one byte at a time, the image on the screen is refreshed gradually, affecting the viewing experience.

[0003] Therefore, existing technologies cannot achieve both high performance and high flexibility. There is an urgent need for a technical solution to achieve high-speed and stable SPI communication in the LK stage in order to optimize boot time and improve the initial display experience. Summary of the Invention

[0004] This invention provides a communication method between an LK-stage SPI bus controller and a screen IC to solve the problems of low SPI protocol transmission rate, excessively long boot logo display time, and overall boot time delay caused by traditional GPIO simulation schemes.

[0005] To achieve the objectives of this invention, this invention provides a communication method between an LK-stage SPI bus controller and a screen IC, the method comprising the following steps: a. Configure the SPI controller hardware, dynamically configure GPIO function modes and create register structures; b. Configure the SPI controller initialization function to receive the SPI controller parameters passed by the user, customize the SPI communication behavior, and configure the data transmission end sequence mode; c. Encapsulate data receiving and data sending functions. The data receiving function reads directly from the receiving register, and the data sending function processes the data before sending it to the screen IC. d. Initialize the screen IC, including receiving the SPI communication parameters passed by the user, calling the GPIO dynamic configuration function in step a and the SPI controller initialization function in step b, and performing read and write operations on the registers of the SPI controller based on the parameters passed by the user. The operation is implemented by adding the register offset to the base address of the register structure created in step a. After the SPI controller is ready, the data receiving function and data sending function encapsulated in step c are called according to the current terminal sequence mode to communicate with the screen IC and complete the initialization of the screen IC.

[0006] In step a, the method for dynamically configuring the GPIO function mode is to configure the function mode of the GPIO pins corresponding to the four signal lines MISO, MOSI, CS, and SCLK used by the SPI controller to the SPI function mode.

[0007] Furthermore, it also includes: when it is necessary to switch back to the traditional GPIO emulation SPI communication mode, the pin mode can be switched back to the normal GPIO mode through the same configuration function.

[0008] In step a, the register structure is consistent with the hardware register layout of the SPI controller, containing 13 32-bit unsigned integer members, each of which maps to a physical register; a pointer SPI2_REGS is defined to point to the structure and to point to the mapped virtual address, and the hardware register is directly accessed by operating on the SPI2_REGS pointer.

[0009] In step b, the parameters of the SPI controller include SPI communication rate, SPI working mode, clock polarity, and clock phase. The upper limit of the SPI communication rate is 27MHz. If the input value is greater than this upper limit, it will be automatically reset to 27MHz. The SPI working mode is SPI mode 3, and the clock polarity and clock phase are configured by the SPI working mode.

[0010] In step b, the method for configuring the end-to-end sequence mode for data transmission is as follows: In the data sent by the SPI controller to the screen IC, the data containing the screen initialization code is configured in little-endian mode, and the data containing the screen display content is configured in big-endian mode. In little-endian mode, the least significant byte is sent first, followed by the most significant byte; in big-endian mode, the most significant byte is sent first, followed by the least significant byte.

[0011] In step c, the data sending function processes the data as follows: The data transmission function calls a for loop to write the incoming data into the SPI_TX_DATA register in groups of 4 bytes. For data that is less than 4 bytes, the starting address of the remaining bytes is located first. Through a loop, these bytes are precisely combined into a 32-bit variable according to their natural order in memory. The number of loop iterations is equal to the number of remaining bytes. The combined 32-bit variable is then written into the transmission register.

[0012] In step d, After the user inputs the SPI communication parameters, the input SPI rate parameter is written to the SPI_CFG2 register to control the transmission rate; the input SPI mode parameter needs to be written to the SPI_CMD register, and register access and operation are realized based on the base address pointed to by the first member of the structure created in step a plus the corresponding offset.

[0013] After the SPI controller initialization function processes the incoming SPI communication parameters, it writes 0 to the corresponding bit of the SPI_CMD register to make the chip select signal valid, thereby pulling the chip select pin low to select the target screen IC and realizing the hardware handshake between the SPI controller and the screen IC.

[0014] In step d, the step of calling the data receiving function and data sending function encapsulated in step c according to the current terminal sequence mode to communicate with the screen IC and complete the initialization of the screen IC includes: When sending initialization code, the SPI controller is set to little-endian mode, and then the encapsulated send function is called to send the initialization code to the screen. When sending the power-on logo image data, the SPI controller is set to big-endian mode, and the encapsulated send function is called to send the image data to the display buffer register of the screen IC. Before each call to the transmit function, first read the status of the SPI_STATUS1 register to confirm that the SPI controller is in an idle state. If it is in an idle state; Each time data is sent, the high and low level times of the clock in the clock control register are configured according to the incoming communication rate; The receive function is used to read the ID of the screen IC, sends a read command through a send function consistent with the current terminal sequence mode, and reads the data returned by the screen IC from the SPI_RX_DATA register.

[0015] The beneficial effects of this invention are as follows: 1) This invention encapsulates the register access and control of the SPI bus controller in the LK phase into read and write functions, embedding them into the platform process. This enables the SPI bus controller to be called to receive and send data in the LK phase, achieving efficient and accurate data transmission and reception. The data transmission and reception rate is 27MHz, far exceeding the rate of traditional GPIO-simulated SPI protocol. Furthermore, it offers significant advantages for scenarios with large data volumes. A traditional GPIO-simulated SPI protocol solution requires 1060ms to send a 320*240 resolution RGB565 format logo image, while this invention only requires 79ms. When the screen resolution doubles, theoretically, the traditional solution requires 2120ms, while this invention only requires 158ms.

[0016] 2) This invention creates a structure in a register, and all data and corresponding clock parameters are sent to the structure in the register at the same time. That is, the structure stores the data and the execution method of the data at the same time. Therefore, the device changes from a loop of receiving single data and executing single data to a loop of receiving partial data and executing partial data. In this way, while receiving partial data, the previously received partial data can be executed at the same time, without waiting for the data to be received completely before execution. This further improves the SPI protocol transmission rate, and the boot logo display time is short and the overall boot time is short.

[0017] 3) The entire software process of this invention involves operating registers. The software solution is responsible for controlling the SPI bus controller, which is equivalent to the role of "commander". The work of sending data to the slave device is handled by the underlying hardware, realizing the combination of software and hardware. The software handles logic, configuration and monitoring tasks, while the SPI bus controller is responsible for transmitting data. Each plays its own role, thereby reducing the weight of the software and making reasonable use of hardware resources.

[0018] 4) The SPI communication protocol standard of this invention provides a universal interface for high-speed SPI communication in the LK stage, and can be widely used in embedded intelligent terminal devices with SPI interface displays on MTK series platforms, with a wide range of applications. Attached Figure Description

[0019] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] See Figure 1 When debugging an SPI interface display screen, it is necessary to implement SPI protocol communication between the CPU (master device) and the screen IC (slave device) in the LK phase. This invention presents a method for screen initialization based on the SPI bus controller in the LK phase. By accessing and controlling the SPI bus controller's registers in the LK phase, encapsulating these into read and write functions, and embedding them into the platform process, this method enables the SPI bus controller to receive and send data in the LK phase, achieving efficient and accurate data transmission and reception. This invention can be widely applied to embedded intelligent terminal devices equipped with SPI interface displays, effectively solving the problems of low SPI protocol transmission rate, excessively long boot logo display time, and overall boot time delay caused by traditional GPIO simulation schemes.

[0022] like Figure 1 As shown, the communication method between the LK-stage SPI bus controller and the screen IC in this embodiment includes the following steps: S10. Configure the SPI controller hardware. This embodiment uses the MT8765 embedded platform as its hardware foundation for detailed explanation. The MT8765 is an ARM architecture SoC widely used in mid-to-high-end smart devices, integrating multiple SPI controllers. This embodiment focuses on the SPI2 controller, which achieves complete control through 13 32-bit registers. Specifically, the steps include: S11, Dynamic Configuration of GPIO Function Mode Functions In this step, since the SPI bus controller needs to directly drive the CPU pins to physically connect with the screen IC, the control of the relevant GPIO pins must first be switched from general-purpose input / output mode to dedicated SPI function mode. In this embodiment, the GPIO pins corresponding to the four signal lines used by the SPI2 controller are MISO, MOSI, CS, and SCLK. By configuring the function mode of the above four GPIOs to SPI function mode, this operation essentially configures the CPU's internal multiplexer, connecting the GPIO pins to the internal signal path of the SPI2 controller, thereby completely handing over the pin level control to the SPI hardware controller.

[0023] It should be noted that, to maintain the flexibility and compatibility of the system design, this embodiment incorporates a mode switching mechanism in the GPIO configuration logic design. When it is necessary to switch back to the traditional GPIO-simulated SPI communication mode (e.g., for debugging or compatibility with older firmware), the pin mode can be switched back to the normal GPIO mode using the same configuration function, thereby restoring the ability of software to directly control the pin level through GPIO operation functions. S12. Create register structure To efficiently and securely access the physical registers of the SPI controller, this embodiment defines a structure that perfectly corresponds to the hardware register layout of the SPI2 controller. Since the SPI controller in this embodiment has 13 32-bit control and status registers, this structure consists of 13 32-bit unsigned integer variables, each mapping to exactly one physical register. Next, using the physical address mapping function provided in the LK stage, the physical base address of the SPI2 controller (0x11012000) is mapped to the kernel's virtual address space. Then, a pointer to the structure, SPI2_REGS, is defined and points to this mapped virtual address. Afterward, operations on the SPI2_REGS pointer are equivalent to directly manipulating the hardware registers. For example, SPI2_REGS->SPI_CMD = 0x1; indicates writing the value 0x1 to the command register (physical address 0x11012018). Because the structure members are arranged contiguously in memory and strictly aligned with the physical offset of the registers, SPI2_REGS+1 will naturally point to the next register (i.e., SPI_CFG1). This greatly simplifies the code, avoids tedious address calculations, and improves the readability and maintainability of the code.

[0024] S20. Configure the SPI controller initialization function. In this step, the SPI controller initialization function is the main interface for configuring the hardware in the upper-layer software. Users customize the SPI communication behavior by passing in the parameters of the SPI controller to be configured. The SPI bus controller initialization function adopts a modular design, providing a complete configuration interface, allowing users to flexibly configure SPI communication parameters in the LK stage. These SPI communication parameters include SPI communication rate, SPI operating mode, clock frequency, and clock phase.

[0025] The SPI controller initialization function also includes configuring the data transmission end-order mode, which determines whether the data is transmitted byte-first or byte-first, to achieve dynamic endianness switching. The communication process in this embodiment employs refined mode differentiation and processing based on the different types of data being transmitted to ensure the accuracy and efficiency of data exchange.

[0026] Specifically, the data sent by the SPI controller to the screen IC is divided into two categories based on its function and target register, each with strict requirements for the byte order of data transmission. The first category is screen initialization code, which consists of control instructions or configuration parameters. This code is written to the screen IC's control register and used for waking the screen, setting the operating mode, adjusting brightness / contrast, etc. The screen IC's control register typically requires data transmission in little-endian mode. In little-endian mode, the least significant byte is sent first, and the most significant byte is sent last. The second category is display image data, which is the pixel information to be displayed, such as RGB values. This data is written to the screen IC's display buffer register. The screen IC's display buffer register typically requires data transmission in big-endian mode. In big-endian mode, the most significant byte is sent first, and the least significant byte is sent last.

[0027] Endianness specifies the byte order in which multi-byte data is sent in serial communication, and the rules for reconstructing and interpreting the received byte stream by both communicating parties. Specifically: Big-endian: When the master device sends a 32-bit data (e.g., 0x12345678), it starts with the most significant byte 0x12, then sends 0x34, 0x56, and finally the least significant byte 0x78. If the slave device also parses in big-endian, it will recognize the first received byte 0x12 as the most significant byte, thus correctly reconstructing 0x12345678. Little-endian: When sending the same data 0x12345678, it starts with the least significant byte 0x78, then sends 0x56, 0x34, and finally the most significant byte 0x12. The slave device can correctly reconstruct the data by parsing in little-endian. If the master device's sending endianness does not match the slave device's expected receiving endianness, it will lead to severe data misalignment. For example, if the master device sends 0x12345678 in big-endian mode, but the slave device parses it in little-endian mode, the received data will be incorrectly interpreted as 0x78563412, resulting in garbled text on the screen or complete failure of control commands. Therefore, the endianness mode of the SPI controller must be precisely configured according to the target register type before each communication.

[0028] S30, Encapsulate data receiving and data sending functions. In this step, the low-level register operations are encapsulated into core data transmission and reception functions that are easy for upper-level layers to call. These functions are the direct interface between the screen driver and the SPI controller during the LK stage, enabling the SPI bus controller to be called to receive and send data during the LK stage. The design takes into account efficiency, versatility, and precise handling of data boundaries.

[0029] Specifically, the receive function reads directly from the receive register. The transmit function, however, needs to process the data before sending it to the screen IC. Since the SPI controller's transmit data register (SPI_TX_DATA) is 32 bits wide (4 bytes), and the length of the data stream to be transmitted can be any number of bytes, not necessarily aligned to 4 bytes, converting the uint8_t pointer to a uint32_t pointer allows the compiler to generate more efficient load instructions when accessing aligned memory areas, reducing memory accesses and significantly improving efficiency compared to writing byte by byte. Directly using a loop to process the remaining bytes might result in sending invalid data due to zero padding, interfering with the slave device. Specifically, in the transmit function, the incoming data needs to be written to the SPI_TX_DATA register in groups of 4 bytes (1 byte is 8 bits). Any remaining data less than 4 bytes needs to be written separately to the transmit register outside the loop. Because the loop writes 4 bytes to the register each time, processing this within the loop would result in the remaining bytes being padded with zeros to make up 4 bytes before being sent, leading to the transmission of useless data and affecting reception from the device. Therefore, outside the loop, the remaining bytes (which could be 1 / 2 / 3 bytes) after taking the total transmission length modulo 4 are written to the register. For data with less than 4 bytes remaining, the starting address of the remaining bytes is located first. Then, through a loop, these bytes are precisely combined into a 32-bit variable according to their natural order in memory, where the number of loop iterations equals the number of remaining bytes. The combined 32-bit variable is then written to the transmit register.

[0030] By encapsulating send and receive functions, the upper-layer driver code is greatly simplified. It only needs to focus on what data to send, without worrying about low-level details such as how to interact with 32-bit registers or handle boundary bytes. Furthermore, both 4-byte aligned blocks of data and byte streams of arbitrary length can be sent and received accurately, ensuring data transmission precision.

[0031] S40 and SPI controllers initialize the screen IC. After completing the encapsulation of receive and transmit functions, the SPI controller can communicate with the screen IC to initialize it. This process includes: S41. When the user inputs SPI communication parameters, the SPI controller calls the GPIO dynamic configuration function in step S11 and the SPI controller initialization function in step S20. The SPI controller initialization function reads and writes the key registers of the SPI controller according to the parameters input by the user, and implements register access and operation based on the base address pointed to by the first member of the structure created in step S12 plus the corresponding offset.

[0032] Specifically, when the user inputs SPI communication parameters, the GPIO dynamic configuration function in step S11 is called in the LK platform initialization function `platform_init()` to configure GPIO27, GPIO28, GPIO29, and GPIO30 to SPI mode, transferring control of these four GPIOs to the SPI controller. Then, the SPI controller initialization function in step S20 is called to perform basic configuration of the SPI controller, requiring the input parameters of SPI rate and SPI mode. In this embodiment, the maximum operating clock of the hardware platform SPI2 controller is 27MHz. If the input value exceeds this limit, the function will automatically reset it to 27MHz to ensure that the configuration does not exceed the hardware capability and cause communication failure. The SPI operating mode parameter determines the clock polarity and clock phase of SPI communication, with a value range of 0-3. The selection of the SPI operating mode is related to the slave device; this embodiment uses mode 3.

[0033] Within the SPI controller initialization function, key registers of the SPI controller are read and written according to user-input parameters. Register access and operations are implemented by adding the corresponding offset to the base address pointed to by the first member of the structure created in step S12. User-input SPI mode parameters need to be written to the SPI_CMD (0x11012018) register. That is, accessing the address corresponding to the first member of the structure plus six offsets in the code controls the SPI_CMD register. Subsequent operations on other registers use the same method, with the main offsets changing. The operations on the SPI_CMD register here correspond to the clock polarity, phase, and SPI mode control implementation in step S20. User-input SPI rate parameters need to be written to the SPI_CFG2 (0x11012028) register to control the transmission rate. Additionally, a key operation in the initialization function is activating the chip select signal to select the target screen IC, achieved by writing 0 to bit 7 of the SPI_CMD (0x11012018) register. This operation will cause the CS pin associated with the SPI controller to output a low level, thereby effectively selecting the screen driver IC and putting it into "listening for master device commands" state. This enables hardware handshaking between the master and slave devices, providing the conditions for subsequent SPI protocol communication.

[0034] S42, SPI controller and screen IC communication Once the SPI controller is ready, it needs to communicate with the screen IC. The SPI controller will call the encapsulated transmit function to send data to the screen IC according to the currently configured end sequence mode.

[0035] Specifically, the data sent by the SPI controller to the screen IC falls into two categories. The first is ordinary initialization code, which consists of control commands or configuration parameters. This code is written to the screen IC's control register and used for functions such as waking the screen, setting the operating mode, and adjusting brightness / contrast. The screen IC's control register typically requires data transmission in little-endian mode. In little-endian mode, the least significant byte is sent first, and the most significant byte is sent last. The second category is display image data, which is the pixel information to be displayed, such as RGB values. This data is written to the screen IC's display buffer register. The screen IC's display buffer register typically requires data transmission in big-endian mode. In big-endian mode, the most significant byte is sent first, and the least significant byte is sent last.

[0036] When the SPI controller sends initialization code to the screen IC, it is set to little-endian mode. Then, the send function encapsulated in step S30 is called to send the initialization code to the screen. The SPI controller is in little-endian mode by default, but this can be configured. Explicit processing in the code is to better reflect the special characteristics of the slave device. Then, the boot logo image data is obtained from the platform, the SPI controller is set to big-endian mode, and the send function encapsulated in step S30 is called to send the image data to the display buffer register of the screen IC. In the send function, the SPI_STATUS1 (0x11012020) register status is first read to confirm that the SPI controller is in an idle state to avoid contention caused by the previous data not being sent. Then, a for loop is called, writing 4 bytes of data into the send register (SPI_TX_DATA: 0x11012010) in each iteration. Any remaining data less than 4 bytes needs to be written to the send register separately outside the loop. Because the loop writes 4 bytes to the register each time, processing within the loop would result in the remaining bytes being padded with 0s to make up 4 bytes before being sent, leading to the transmission of useless data and affecting the slave device's reception. Therefore, outside the loop, the remaining bytes (possibly 1 / 2 / 3 bytes) modulo 4 based on the total transmission length need to be written to the register. After all the data to be sent has been written, a 1 is written to bit 0 of SPI_CMD (0x11012018). This operation wakes up the SPI bus controller to send the data to the slave device, thus completing one data transmission. The receive function is only used during the ID reading process. It calls the send function to send out the slave device register that needs to be read. The endianness is determined according to the send function's settings—big-endian mode for big-endian transmission and little-endian mode for little-endian transmission. Then, it reads from the SPI_RX_DATA (0x11012014) register, and the master device can then receive the data sent by the slave device.

[0037] This embodiment creates a structure in the register, and all data and corresponding clock parameters are simultaneously sent to this structure. The structure stores both the data and the execution method, thus transforming the device's loop from receiving and executing single data points into receiving and executing partial data points. This allows for simultaneous execution of previously received data while receiving partial data, eliminating the need to wait for complete data reception. This further improves the SPI protocol transmission rate and reduces the time required for the boot logo display and overall boot time. Furthermore, this invention transforms complex SPI controller register operations into a simple, reliable, and efficient API, enabling high-speed and accurate screen initialization and logo display during the LK phase, directly contributing significantly to the optimization of boot time.

[0038] In summary, this embodiment enables the startup and utilization of the SPI bus controller hardware resource during the LK phase. The software only needs to write data to the SPI_TX_DATA register. The step of sending data from the SPI controller to the screen IC is delegated to the SPI bus controller. After startup, the SPI bus controller automatically sends data to the MOSI line through its internal hardware resources. The SPI bus controller has a shift register that sends data at a set SPI rate of 27MHz. The entire software flow of this solution involves operating registers. The software controls the SPI bus controller, acting as the "commander," while the task of sending data to slave devices is handled by the underlying hardware, achieving a combination of software and hardware. The software handles logic, configuration, and monitoring tasks, while the SPI bus controller is responsible for data transmission. Each component plays its strength, reducing the software's reliance on hardware resources and making efficient use of hardware resources. Traditional GPIO-based SPI protocol emulation schemes require the software to handle both parsing the user's data (resolving it into 0s or 1s) and transmitting it. Based on the parsed data, the software controls the GPIO corresponding to the SCLK chip select pin to generate a clock. Within one clock cycle, transmitting a 0 pulls the corresponding GPIO low on the MOSI line, and transmitting a 1 pulls it high, thus sending data to the slave device. This operation is performed for each bit of data transmitted—transmitting 320*240*2*16 bits of data (the size of one frame of a logo image in this example) requires 2,457,600 GPIO operations, all implemented by software, resulting in very low efficiency. In this embodiment, the software doesn't need to handle the transmission details; it only needs to call the encapsulated transmission function to send the 320*240*2*16 bits of data. The data is transmitted by the SPI bus controller. Therefore, the data transmission and reception rate here, the 27MHz rate set by the user, is far higher than the rate of traditional GPIO-based SPI protocol emulation. It should be noted that this embodiment has more advantages for scenarios with larger data volumes. The traditional GPIO emulation SPI protocol solution takes 1060ms to send a frame of 320*240 resolution RGB565 format LOGO image data, while this embodiment only takes 79ms. When the screen resolution is doubled, the traditional solution would theoretically take 2120ms, while this embodiment only takes 158ms.

[0039] Although the present invention has been disclosed through the above embodiments, the scope of protection of the present invention is not limited thereto. Any modifications or substitutions made to the above components without departing from the concept of the present invention shall fall within the scope of the claims of the present invention.

Claims

1. A communication method between an LK-stage SPI bus controller and a screen IC, characterized in that, The method includes the following steps: a. Configure the SPI controller hardware, dynamically configure GPIO function modes and create register structures; b. Configure the SPI controller initialization function to receive the SPI controller parameters passed by the user, customize the SPI communication behavior, and configure the data transmission end sequence mode; c. Encapsulate data receiving and data sending functions. The data receiving function reads directly from the receiving register, and the data sending function processes the data before sending it to the screen IC. d. Initialize the screen IC, including receiving the SPI communication parameters passed by the user, calling the GPIO dynamic configuration function in step a and the SPI controller initialization function in step b, and performing read and write operations on the registers of the SPI controller based on the parameters passed by the user. The operation is implemented by adding the register offset to the base address of the register structure created in step a. After the SPI controller is ready, the data receiving function and data sending function encapsulated in step c are called according to the current terminal sequence mode to communicate with the screen IC and complete the initialization of the screen IC.

2. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step a, the method for dynamically configuring the GPIO function mode is to configure the function mode of the GPIO pins corresponding to the four signal lines MISO, MOSI, CS, and SCLK used by the SPI controller to the SPI function mode.

3. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 2, characterized in that, Also includes: When it is necessary to switch back to the traditional GPIO-simulated SPI communication mode, the pin mode can be switched back to the normal GPIO mode using the same configuration function.

4. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step a, the register structure is consistent with the hardware register layout of the SPI controller, containing 13 32-bit unsigned integer members, each of which maps to a physical register; a pointer SPI2_REGS is defined to point to the structure and to point to the mapped virtual address, and the hardware register is directly accessed by operating on the SPI2_REGS pointer.

5. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step b, the parameters of the SPI controller include SPI communication rate, SPI working mode, clock polarity, and clock phase. The upper limit of the SPI communication rate is 27MHz. If the input value is greater than this upper limit, it will be automatically reset to 27MHz. The SPI working mode is SPI mode 3, and the clock polarity and clock phase are configured by the SPI working mode.

6. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step b, the method for configuring the end-to-end sequence mode for data transmission is as follows: In the data sent by the SPI controller to the screen IC, the data containing the screen initialization code is configured in little-endian mode, and the data containing the screen display content is configured in big-endian mode. In little-endian mode, the least significant byte is sent first, followed by the most significant byte; in big-endian mode, the most significant byte is sent first, followed by the least significant byte.

7. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step c, the data sending function processes the data as follows: The data transmission function calls a for loop to write the incoming data into the SPI_TX_DATA register in groups of 4 bytes. For data that is less than 4 bytes, the starting address of the remaining bytes is located first. Through a loop, these bytes are precisely combined into a 32-bit variable according to their natural order in memory. The number of loop iterations is equal to the number of remaining bytes. The combined 32-bit variable is then written into the transmission register.

8. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step d, After the user inputs the SPI communication parameters, the input SPI rate parameter is written to the SPI_CFG2 register to control the transmission rate; the input SPI mode parameter needs to be written to the SPI_CMD register, and register access and operation are realized based on the base address pointed to by the first member of the structure created in step a plus the corresponding offset.

9. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 8, characterized in that, After the SPI controller initialization function processes the incoming SPI communication parameters, it writes 0 to the corresponding bit of the SPI_CMD register to make the chip select signal valid, thereby pulling the chip select pin low to select the target screen IC and realizing the hardware handshake between the SPI controller and the screen IC.

10. The communication method between the LK-stage SPI bus controller and the screen IC as described in claim 1, characterized in that, In step d, the step of calling the data receiving function and data sending function encapsulated in step c according to the current terminal sequence mode to communicate with the screen IC and complete the initialization of the screen IC includes: When sending initialization code, the SPI controller is set to little-endian mode, and then the encapsulated send function is called to send the initialization code to the screen. When sending the power-on logo image data, the SPI controller is set to big-endian mode, and the encapsulated send function is called to send the image data to the display buffer register of the screen IC. Before each call to the transmit function, first read the status of the SPI_STATUS1 register to confirm that the SPI controller is in an idle state. If it is in an idle state; Each time data is sent, the high and low level times of the clock in the clock control register are configured according to the incoming communication rate; The receive function is used to read the ID of the screen IC, sends a read command through a send function consistent with the current terminal sequence mode, and reads the data returned by the screen IC from the SPI_RX_DATA register.

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