Waveform recognition implementation method based on waveform template matching of FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a waveform recognition implementation method based on waveform template matching of an FPGA (Field Programmable Gate Array), which adopts a flexible template configuration mechanism to support self-defined waveform recognition, does not need to depend on deep learning and large-scale data training, and meanwhile, through a configurable frequency parameter and a dynamic zero calibration mechanism, the waveform recognition can be realized. And the method is suitable for different precision, frequency range and direct current bias scenes. On the hardware implementation level, the parallelism and assembly line characteristics of the FPGA are fully exerted, an n-path parallel processing architecture is constructed, a lightweight result processing strategy of intra-group iteration updating to inter-path preferential selection is matched, storage resource occupation is remarkably reduced, and the recognition speed and reliability are guaranteed through a dual-mode judgment mechanism of rapid matching and full-quantity matching. According to the method, the defects of a traditional template matching method are overcome, meanwhile, the problems that a deep learning scheme is difficult to deploy, high in computing power requirement and high in data dependence are solved, and the practical value of the system in multiple scenes is remarkably improved.

Description

Technical Field

[0001] This application belongs to the field of signal recognition technology, specifically relating to a waveform recognition implementation method based on FPGA waveform template matching. Background Technology

[0002] Waveform recognition is a core technology in the field of electronic information, widely used in industrial control, communication demodulation, portable testing, and other scenarios. The core requirement is to accurately determine the waveform type and extract parameters, while also meeting requirements for real-time performance, miniaturization, and anti-interference capabilities. The development of portable devices and high-speed signal scenarios (such as 20MHz sampling rates) urgently demand microsecond-level recognition response, driving the integration of recognition algorithms with platforms such as Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs), and Microcontrollers (MCUs). However, existing solutions still have significant bottlenecks.

[0003] Current waveform recognition technology faces three major challenges: First, it lacks scene adaptability and is difficult to support custom waveform recognition; second, it is limited in miniaturized deployment, with a prominent contradiction between resource consumption and computing power requirements; and third, it has poor real-time performance, and the processing latency cannot meet the requirements in high-speed signal scenarios.

[0004] Currently, mainstream waveform recognition solutions are mainly based on microcontrollers, digital signal processors (DSPs), central processing units (CPUs) / graphics processing units (GPUs), and hardware template matching platforms.

[0005] However, the relevant technical solutions have significant drawbacks in terms of cost, real-time performance, adaptability, and resource consumption. 1) Disadvantages of microcontroller / DSP platforms: Performance improvements rely on increasing clock frequency, the number of boards, and the number of cores, which has obvious limitations. Increasing the clock frequency leads to a sharp increase in power consumption and heat dissipation pressure, increasing hardware design complexity and reducing system stability. For example, after the STM32H7 is increased to 480MHz, an additional heatsink is required. Increasing the number of boards increases equipment cost, and the scheduling, coordination, and data synchronization between multiple boards are technically difficult, easily forming performance bottlenecks. Even after optimization, the serial processing architecture still cannot meet the microsecond-level recognition requirements of 20MHz signals, and the single-channel recognition delay generally exceeds 1ms.

[0006] 2) Disadvantages of CPU / GPU platforms and deep learning solutions: CPU / GPU-based servers have high procurement and maintenance costs, and high economic burden when deploying high-performance clusters; most algorithms are written in traditional serial C / C++, requiring hundreds of microseconds to process 100 data points, resulting in low efficiency when processing large-scale data; deep learning solutions require GPU or AI accelerator cards, and models such as ResNet have over a million parameters, occupying over 100MB of memory, making them unsuitable for small devices such as mobile devices, and requiring at least 100,000 labeled data points for training. Summary of the Invention

[0007] To address the aforementioned problems in the existing technology, this application provides a waveform recognition method based on FPGA waveform template matching. The technical problem to be solved by this application is achieved through the following technical solution: A waveform recognition method based on FPGA waveform template matching includes: S100, Input an analog signal, perform ADC processing on the analog signal to obtain an unsigned digital signal, and perform preprocessing on the unsigned digital signal to obtain preprocessed data; S200, The preprocessed data is dynamically zero-point adjusted and the whole cycle is extracted to obtain the original number of sampling points for the whole cycle; S300, the original number of sampling points in the whole cycle is standardized by 100 points to obtain 100 data points, which are then stored in the dual-port RAM; S400, traverse the 100 data points in the dual-port RAM, normalize them, and then store the normalized data in the dual-port RAM; S500 loads the COE file and uses a pipelined reading architecture to read three standard waveforms from the COE file; S600, the normalized data is matched with the three standard waveforms to obtain the SAD of the three channels. If one of the three SADs is less than the threshold, fast matching is triggered and the corresponding waveform type is locked. If all three SADs are less than the threshold, the historical minimum SAD and the corresponding group number of each channel are updated, and the next group judgment is entered until the normalized data of all groups are traversed. S700: If the normalized data for all groups has been evaluated, the global minimum value of the SAD and its corresponding waveform are selected from all SAD values, and a calibration trigger signal is generated, thus returning to S200. Beneficial effects: This application discloses a waveform recognition method based on FPGA-based waveform template matching. It employs a flexible template configuration mechanism to support custom waveform recognition, eliminating the need for deep learning and large-scale data training. Furthermore, through configurable frequency parameters and a dynamic zero-point calibration mechanism, it adapts to different precision, frequency ranges, and DC bias scenarios. At the hardware implementation level, it fully leverages the parallel and pipelined characteristics of FPGA to construct an n-way parallel processing architecture. Combined with a lightweight result processing strategy that iterates within groups and selects the best among different paths, it significantly reduces storage resource consumption. A dual-mode decision mechanism of fast matching and full matching ensures both recognition speed and reliability. This application addresses the shortcomings of traditional template matching methods in terms of scalability, adaptability, and resource consumption, while avoiding the difficulties in deploying deep learning solutions, high computational requirements, and strong data dependencies. It achieves high-speed, high-precision, and highly adaptable waveform recognition on miniaturized devices, significantly enhancing the system's practical value in various scenarios.

[0008] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating a waveform recognition implementation method based on FPGA waveform template matching provided in this application. Figure 2 This is a schematic diagram of the algorithm implementation flow of the waveform recognition method based on FPGA waveform template matching provided in this application; Figure 3 This is a schematic diagram of the COE file generation process provided in this application; Figure 4 This is a schematic diagram illustrating the specific process of BRAM reading and matching provided in this application. Detailed Implementation

[0010] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0011] This application proposes a waveform recognition method based on FPGA waveform template matching. At the algorithm level, a flexible template configuration mechanism supports custom waveform recognition, eliminating the need for large dataset training in deep learning. Configurable frequency parameters (step values, frequency range) and a dynamic zero-point calibration mechanism are designed to adapt to different accuracy, range requirements, and DC bias scenarios. At the hardware implementation level, the parallel computing and pipeline characteristics of FPGAs are fully utilized to construct an n-channel parallel processing architecture (n waveforms correspond to n channels). Combined with an intra-group iterative update to inter-channel optimization result processing strategy, the method eliminates the need to store all matching data, significantly reducing resource consumption. Furthermore, a dual-mode decision mechanism combining fast matching and full matching (with flexibly configurable thresholds, typically 500) balances recognition speed and reliability. This method not only solves the problems of difficult deployment, high computing power requirements, and strong data dependence of deep learning solutions, but also breaks through the limitations of traditional template matching methods in terms of waveform type, frequency parameters, DC bias adaptability, and resource consumption. It realizes high-speed, high-precision, and highly adaptable waveform recognition on miniaturized devices, thereby improving the practical value and scenario coverage of the system.

[0012] Combination Figures 1 to 4 This application provides a waveform recognition implementation method based on FPGA waveform template matching, including: S100, Input an analog signal, perform ADC processing on the analog signal to obtain an unsigned digital signal, and perform preprocessing on the unsigned digital signal to obtain preprocessed data; S200, The preprocessed data is dynamically zero-point adjusted and the whole cycle is extracted to obtain the original number of sampling points for the whole cycle; This step includes a zero-point calibration stage and a full-cycle extraction stage. After each S600 matching is completed, you need to return to this step to re-perform the zero-point calibration in order to cope with the dynamic changes in the ADC DC offset.

[0013] S300, the original number of sampling points in the whole cycle is standardized by 100 points to obtain 100 data points, which are then stored in the dual-port RAM; The FPGA core executes a pipelined operation of "real-time ADC data reception → zero-crossing detection and extraction of the entire cycle → 100-point standardization processing → full-template parallel matching." Based on a hardware parallel architecture, it overcomes real-time bottlenecks and achieves accurate identification of sine, triangle, and square waves within the 1kHz~5MHz range. The entire cycle data and the standardized data are stored in DDR4, a double-data-rate fourth-generation synchronous dynamic random access memory that meets high-speed data caching requirements.

[0014] In this embodiment, since the input signal may have noise interference and frequency fluctuations, the original sampling data may have problems such as insufficient periodic integrity and inconsistent amplitude. The subsequent processing flow compensates for these signal changes through operations such as zero-crossing detection, standardization and normalization to ensure the accuracy of waveform feature extraction and provide a reliable data foundation for template matching.

[0015] S400, traverse the 100 data points in the dual-port RAM, normalize them, and then store the normalized data in the dual-port RAM; S500 loads the COE file and uses a pipelined reading architecture to read three standard waveforms from the COE file; This application requires the prior generation of a COE file, the generation process of which will be detailed later. Based on the FPGA-based hardware implementation, the number of parallel processing paths can be designed as a dynamically configurable structure, rather than a fixed three-path structure. Specifically, the system can dynamically adjust the number of matching units for each waveform type through configuration registers, based on available logic resources, power budget, or real-time requirements. For example, on high-end FPGA devices, one path for sine wave template matching can be split into two parallel processing units, responsible for the low-frequency band (1–2.5 MHz) and the high-frequency band (2.5–5 MHz) respectively, thereby reducing the single-round matching time by nearly half. On resource-constrained low-end devices, some waveform paths can be merged, retaining only one general matching engine, such as merging the paths for sine waves and square waves, sacrificing some speed for functional integrity. This dynamic reconfigurable mechanism significantly improves the platform adaptability and engineering practicality of the solution.

[0016] S600, the normalized data is matched with the three standard waveforms to obtain the SAD of the three channels. If one of the three SADs is less than the threshold, fast matching is triggered and the corresponding waveform type is locked. If all three SADs are less than the threshold, the historical minimum SAD and the corresponding group number of each channel are updated, and the next group judgment is entered until the normalized data of all groups are traversed. S700: If the normalized data of all groups has been judged, the global minimum value of SAD and the corresponding waveform are selected from all SADs, and a calibration trigger signal is generated to return to S200.

[0017] In one specific embodiment of this application, reference is made to Figure 3 The COE file is obtained through the following steps: a. Set initial parameters; wherein, the initial parameters include sampling frequency, frequency range, frequency interval, number of points per cycle, data bit width, normalized maximum value, and waveform core function; b. Based on the initialization parameters, traverse the frequency sequence to generate waveform sequences with multiple frequencies for each type; c. Normalize each frequency waveform sequence using the normalized maximum value, and then splice all waveform sequences in a predetermined order to obtain a standard waveform template. d. Use the standard waveform template to generate a COE file that meets the FPGA BRAM initialization requirements.

[0018] The discrete sequence of a standard waveform can be represented as (1) in The waveform amplitude, Waveform frequency (F) min= 1khz~F max =5MHz, interval ΔF=1kHz), The sampling frequency is 20MHz, and n is the sampling point index (1~N) (N=100). The initial phase is set to 0 for sine waves, triangle waves, and square waves respectively. DC offset (default 0). The core function for the waveform (sine / triangular / square wave).

[0019] Assuming a standard waveform template of a single frequency is generated, it is used as the reference unit for FPGA matching, i.e. For a fixed frequency value (e.g., 1 kHz), a standard waveform discrete sequence of a single frequency can be represented as follows: (2) Normalizing the discrete points generated by formula (2), the normalized amplitude mapping relationship is as follows: (3)

[0020] Clearly, the sequence characteristics of a standard waveform are determined by the core function. and frequency It was determined that waveforms of the same type exhibit consistent amplitude variation patterns. Based on this characteristic, multi-frequency, multi-type waveform templates were generated in batches. Batch generation was achieved using a parameterized traversal method, defined as follows:

[0021] (4) In the formula, =F min The starting frequency, =ΔF is the frequency interval. =F max To terminate the frequency, generate A sequence of frequency points; It is the minimum value of the k-th waveform sequence. It is its maximum value.

[0022] After the generated waveform sequence is normalized, its amplitude range is mapped to 0~NormMAX (NormMAX=255, 8-bit unsigned integer), which can be regarded as a standard template that can be recognized by FPGA. Given that practical applications require coverage of multiple waveform types, this design forms a complete template library by traversing the frequency sequences of sine waves, triangle waves, and square waves respectively, thereby achieving comprehensive recognition of multiple waveform types during FPGA matching.

[0023] The k-th (k=1,2,3…5000) frequency templates of the m-th waveform type (m=1,2,3 correspond to sine wave, triangle wave, and square wave respectively) are combined sequentially, where " "" represents sequence splicing.

[0024] (5) The memory address mapping in the COE file is determined based on the waveform type and frequency order. Let... Let be the starting address of the k-th frequency template of the m-th type, and N=100 be the number of points in a single template. Then the address mapping relationship is: (6) The batch-generated template data is encapsulated into a COE file using a formatted write function, as shown in equation (5): (7) Calculate and export the complete contents of the COE file: (8) Equation (8) is used to write all the standardized 8-bit waveform sequences into the COE file to complete the preparation of FPGA BRAM initialization data.

[0025] (9) Please refer to the following import process for details.

[0026] In one specific embodiment of this application, S100 includes: S110, Input an analog signal and use an ADC to quantize the analog signal into an 8-bit unsigned digital signal; S120, the unsigned digital signal is input to the FPGA through the IO interface, and the FPGA writes it into the deep asynchronous FIFO in real time; S130, the unsigned digital signal in the FIFO is processed by a 3-level register synchronous dejitting process to obtain preprocessed data.

[0027] The input analog signal is quantized into an 8-bit unsigned digital signal (amplitude range 0~255) by an ADC (8-bit resolution, 20MHz sampling rate), and then input to the FPGA through a high-speed I / O interface. Timing consistency is ensured by synchronous latching with a 20MHz sampling clock. Data is written in real-time to a 2K-depth asynchronous FIFO, with the write clock being the 20MHz sampling clock and the read clock being the 20MHz FPGA system clock. When the amount of data in the FIFO reaches a preset threshold of 512 points, subsequent modules are triggered to start. Simultaneously, the buffered data undergoes synchronous debouncing processing via a 3-level register to filter out high-frequency noise interference, outputting stable pre-processed data.

[0028] In one specific embodiment of this application, S200 includes: S210, the preprocessed data output in real time by the FIFO is acquired in real time through the parallel comparator array, and the extreme values ​​in the preprocessed data are extracted simultaneously. The dynamic zero point is calculated based on the extreme values, and the preprocessed data is calibrated based on the dynamic zero point to obtain calibration data; the dynamic zero point is stored in the calibration register. After this step is started, the first entry time is [duration]. Signal detection phase Configurable (typically 1ms, corresponding to 20,000 sampling points), it acquires preprocessed data output from the FIFO in real time through a parallel comparator array, and synchronously extracts the maximum sampling value within this stage. and minimum value Calculate the dynamic zero point based on the collected extreme values. The calculation formula is: Eliminate ADC inherent offset Influenced by the DC bias of the signal, latching is performed after calculation. The value is sent to the dedicated calibration register.

[0029] S220: The calibration data cycle start point is located by a combination of candidate point detection and multi-sampling point verification, and the cycle start point pulse is output to trigger the 32-bit counter to start accumulating. Simultaneously, the data between valid zero crossings is written to DDR4 to obtain the original number of sampling points for the entire cycle.

[0030] This step employs a two-stage hardware logic approach—candidate point detection and multi-sampling point verification—to locate the cycle start point. All level comparisons are based on the calibrated dynamic zero point. .

[0031] This step S220 includes: S221 compares continuous sampling points in real time using two parallel comparators. and and The relationship, when satisfied and Time stamp Select candidate points; then select three consecutive sampling points after the candidate points. Verification, if all conditions are met Then the candidate point is confirmed as a valid zero-crossing point, and the starting pulse of the output period is activated. ; S222, Periodic Start Pulse Trigger the 32-bit counter to start accumulating, and simultaneously begin loading data into DDR4 (address from 0 to 1). The system writes data from the previous valid zero-crossing point to the current valid zero-crossing point until the next valid zero-crossing point is detected, at which point the counting stops and writing stops, thus obtaining the original number of sampling points for the entire cycle. (4~20000 points, calculated by dividing the sampling rate of 20MHz by the signal frequency).

[0032] In one specific embodiment of this application, reference is made to Figure 4 The S300 includes: S310, when the number of original sampling points in the entire cycle At that time, the step size is calculated and extracted using a hardware divider. According to the formula Generate 100 truncation indices, and read data according to the indexes and store it into the on-chip dual-port RAM; S320, when At that time, Point data is written to a 1K-depth FIFO and configured for loop output mode, then processed by a hardware interpolator according to the formula. Generate 100 data points, synchronize them, and store them in the on-chip dual-port RAM.

[0033] This step is based on the number of original sampling points for the entire cycle. In low-frequency signal scenarios, the step size is calculated using a hardware divider. According to the formula Generate 100 truncation indices, and read data according to the indexes and store it into the on-chip dual-port RAM; when When (in a high-frequency signal scenario), Point data is written to a 1K-depth FIFO and configured for loop output mode, then processed by a hardware interpolator according to the formula. (in , ) Generate 100 data points, synchronize them, and store them in the on-chip dual-port RAM.

[0034] In addition to the currently used "zero-crossing detection + multi-point verification" strategy, this application can also introduce a period estimation module based on the autocorrelation function as a supplementary scheme. This module uses a sliding window to perform real-time autocorrelation calculations on the buffered data, and determines the signal period length by locating the maximum correlation peak. It is particularly suitable for complex scenarios with strong noise, DC offset, or waveform asymmetry. Since autocorrelation is insensitive to phase and has strong anti-interference ability, its robustness under non-ideal signal conditions is better than the traditional zero-crossing method. To control resource consumption, the original sampled data can be downsampled using a filter before performing autocorrelation, thereby achieving a balance between accuracy and efficiency.

[0035] In one specific embodiment of this application, reference is made to Figure 4 The S400 includes: S410 uses a parallel comparator to traverse 100 data points in the dual-port RAM, and extracts the maximum and minimum values ​​within 10 clock cycles through two levels of logic: group comparison and global comparison. S420: Based on whether the maximum value and the minimum value are equal, normalize the 100 data points to obtain normalized data, store it in the matching data register group, or output an amplitude abnormality flag to trigger a return to S100.

[0036] A parallel comparator array is used to traverse 100 data points in the on-chip RAM, and the maximum value is extracted within 10 clock cycles through a two-stage logic of "group comparison → global comparison". and minimum value .when At that time, the hardware divider calculates the scaling factor. ;like The output amplitude anomaly flag triggers resampling. Each data point is processed according to the formula. After normalization, rounding, and clipping, the data is stored in the matching data register group; if Output an amplitude abnormality flag, triggering the re-execution of S100.

[0037] In one specific embodiment of this application, reference is made to Figure 4 The S500 includes: S510, Load the COE file, wherein the COE file includes three waveform types, each waveform type corresponds to multiple sets of 100-point standard template libraries, each waveform type is independently partitioned and stored in the on-chip BRAM array, and each set of 100-point standard module libraries corresponds to one frequency point. Three waveform types (sine wave, triangle wave, and square wave) each correspond to 5000 sets of 100-point standard template libraries, stored in three independent partitions on the on-chip BRAM array (single partition capacity = 5000 sets × 100 points = 500,000 points, total capacity 1,500,000 points). Each set of templates corresponds to one frequency point (frequency coverage 1kHz~5MHz, groups 1 to 5000 are sorted in ascending order of frequency). Address mapping adopts a dual indexing rule of "group number + point number": for waveform type m (m=1 / 2 / 3, corresponding to sine wave / triangle wave / square wave), the g-th group ( Point i ( Its BRAM address is " ".

[0038] The S520 uses a pipelined read architecture to synchronously read standard waveforms from the BRAM array and distributes them to three computing units via three independent buses until all 100 points in all groups have been traversed.

[0039] This step employs a pipelined read architecture, indexed by a global synchronization point. (0~99) and group number iterative index (1~5000) Joint drive: Every 10ns clock cycle, the three BRAM partitions synchronously output the "current group number". "The next Point data is distributed to three computing units via three independent buses; when After iterating through 0 to 99 (100 points), The algorithm automatically increments by 1 to move on to the next group, until all 5000 groups have been traversed. A single pipeline read takes 50μs, which perfectly matches the pipeline rhythm of the computing unit.

[0040] In one specific embodiment of this application, reference is made to Figure 4 The S600 includes: S610 uses three computing units to simultaneously calculate the difference between normalized data and the corresponding standard waveform, and converts the difference into an 8-bit unsigned value to obtain the absolute difference value through an absolute value circuit; S620 uses the absolute difference of the current group to continuously accumulate the three-way SAD by each calculation unit; S630: For the current group, determine whether any of the three SAD values ​​of the current group are less than a preset threshold. If so, generate a fast matching signal and lock the corresponding waveform type, and pause pipeline reading. If not, compare the three SAD values ​​of the current group with the minimum SAD value of each waveform stored in the historical minimum SAD register, and update the historical minimum SAD and corresponding group number of each waveform using the comparison result.

[0041] This application adopts an architecture of "3 calculation units + pipelined accumulation + inter-group comparison", which is fully synchronized with the S500 pipelined reading. The core consists of 3 independent SAD (Sum of Absolute Differences) calculation units (corresponding to 3 waveforms respectively), with no redundant calculation units: ① Pipeline difference calculation: S500 outputs the current group The When processing point data, the three computing units simultaneously calculate the input normalized data. The difference between the data and the corresponding waveform template point data is converted into an 8-bit unsigned value by an absolute value circuit; ② Real-time accumulation within the group: Each calculation unit has a built-in 32-bit accumulator to accumulate data for the current group. The 100-point absolute difference is continuously accumulated ( (Synchronous accumulation during iterations from 0 to 99); ③ Intra-group threshold judgment and inter-group temporary storage: When the accumulation of 100 points is completed (i.e., the current group...) Upon completion of processing, immediately determine if any of the accumulated results of the three units (denoted as SAD_g1, SAD_g2, and SAD_g3) are ≤ a preset threshold λ (typically 500). If so, trigger the "fast match" signal, lock the corresponding waveform type, and pause the pipeline. If not, do not trigger fast match, compare the three SAD values ​​of the current group with the "historical minimum SAD register" (initialized to the maximum value), update and save the historical minimum SAD value and corresponding group number for each waveform, and then... Add 1 to move on to the next group, and repeat the above process until 5000 groups have been processed.

[0042] The current core criterion for template matching is the sum of absolute differences (SAD) method. While computationally efficient, it is sensitive to amplitude scaling. This application can alternatively employ normalized cross-correlation (NCC) as the similarity criterion. By removing the mean and normalizing the energy, it is naturally immune to amplitude variations and DC offsets. Although NCC involves division and square root operations, it can be efficiently implemented in an FPGA using lookup tables, the CORDIC algorithm, or approximate reciprocal units. The system can also be designed with a SAD / NCC dual-mode switching mechanism: using SAD for speed when the signal-to-noise ratio is high, and automatically switching to NCC to ensure robustness when the signal-to-noise ratio is low, thus achieving an adaptive balance between performance and accuracy.

[0043] In one specific embodiment of this application, S700 includes: S710, if the normalized data of all groups have been judged, then the global minimum value of SAD and the corresponding waveform are selected from all SADs. The S720 outputs the corresponding waveform type and valid flag based on the historical minimum SAD and the corresponding group number, and generates a calibration trigger signal. S730, based on the calibration trigger signal, drives the FPGA to return to S200 and enter the next batch process.

[0044] This step connects with the S600 pipeline and includes two scenarios: fast matching and full pipeline matching. The core is the comparison of three results. If all 5000 groups have been processed without triggering fast matching, the minimum SAD value (denoted as SAD_min1, SAD_min2, and SAD_min3) and the corresponding group number for each waveform are stored in three historical minimum SAD registers. A two-stage comparator compares these three values ​​to select the globally minimum value. And the corresponding waveform number: output the corresponding waveform type and valid flag; in both scenarios, a calibration trigger signal is generated immediately after the result is output, driving the system to return to step 2 to perform zero-point calibration, and then enter the next round of pipeline process. The total delay of the whole process is ≤52μs, which fully meets the requirements of real-time performance and pipeline architecture.

[0045] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0046] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A waveform recognition method based on FPGA waveform template matching, characterized in that, include: S100, Input an analog signal, perform ADC processing on the analog signal to obtain an unsigned digital signal, and perform preprocessing on the unsigned digital signal to obtain preprocessed data; S200, The preprocessed data is dynamically zero-point adjusted and the whole cycle is extracted to obtain the original number of sampling points for the whole cycle; S300, the original number of sampling points in the whole cycle is standardized by 100 points to obtain 100 data points, which are then stored in the dual-port RAM; S400, traverse the 100 data points in the dual-port RAM, normalize them, and then store the normalized data in the dual-port RAM; S500 loads the COE file and uses a pipelined reading architecture to read three standard waveforms from the COE file; S600, the normalized data is matched with the three standard waveforms to obtain the SAD of the three channels. If one of the three SADs is less than the threshold, fast matching is triggered and the corresponding waveform type is locked. If all three SADs are less than the threshold, the historical minimum SAD and the corresponding group number of each channel are updated, and the next group judgment is entered until the normalized data of all groups are traversed. S700: If the normalized data of all groups has been judged, the global minimum value of SAD and the corresponding waveform are selected from all SADs, and a calibration trigger signal is generated to return to S200.

2. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, The COE file is obtained through the following steps: a. Set initial parameters; wherein, the initial parameters include sampling frequency, frequency range, frequency interval, number of points per cycle, data bit width, normalized maximum value, and waveform core function; b. Based on the initialization parameters, traverse the frequency sequence to generate waveform sequences with multiple frequencies for each type; c. Normalize each frequency waveform sequence using the normalized maximum value, and then splice all waveform sequences in a predetermined order to obtain a standard waveform template. d. Use the standard waveform template to generate a COE file that meets the FPGA BRAM initialization requirements.

3. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, S100 includes: S110, Input an analog signal and use an ADC to quantize the analog signal into an 8-bit unsigned digital signal; S120, the unsigned digital signal is input to the FPGA through the IO interface, and the FPGA writes it into the deep asynchronous FIFO in real time; S130, the unsigned digital signal in the FIFO is processed by a 3-level register synchronous dejitting process to obtain preprocessed data.

4. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, S200 includes: S210, the preprocessed data output in real time by the FIFO is acquired in real time through the parallel comparator array, and the extreme values ​​in the preprocessed data are extracted simultaneously. The dynamic zero point is calculated based on the extreme values, and the preprocessed data is calibrated based on the dynamic zero point to obtain calibration data; the dynamic zero point is stored in the calibration register. S220: The calibration data cycle start point is located by a combination of candidate point detection and multi-sampling point verification, and the cycle start point pulse is output to trigger the 32-bit counter to start accumulating. Simultaneously, the data between valid zero crossings is written to DDR4 to obtain the original number of sampling points for the entire cycle.

5. The waveform recognition method based on FPGA waveform template matching according to claim 4, characterized in that, In S210, the extreme values ​​include the maximum and minimum sampled values. The dynamic zero-point calculation formula is expressed as follows: In the formula, For dynamic zero point, The maximum value sampled. The minimum value sampled; S220 includes: S221 compares continuous sampling points in real time using two parallel comparators. and and The relationship, when satisfied and Time stamp Select candidate points; then select three consecutive sampling points after the candidate points. Verification, if all conditions are met Then the candidate point is confirmed as a valid zero-crossing point, and the starting pulse of the output period is activated. ; S222, Periodic Start Pulse A 32-bit counter is triggered to start accumulating, and data from the previous valid zero-crossing point to the current valid zero-crossing point is written to the DDR4. Counting stops when the next valid zero-crossing point is detected, and writing also stops, thus obtaining the raw number of sampling points for the entire cycle. .

6. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, The S300 includes: S310, when the number of original sampling points in the entire cycle At that time, the step size is calculated and extracted using a hardware divider. According to the formula Generate 100 truncation indices, and read data according to the indexes and store it into the on-chip dual-port RAM; S320, when At that time, Point data is written to a 1K-depth FIFO and configured for loop output mode, then processed by a hardware interpolator according to the formula. Generate 100 data points, synchronize them, and store them in the on-chip dual-port RAM.

7. The waveform recognition method based on FPGA waveform template matching according to claim 6, characterized in that, The S400 includes: S410 uses a parallel comparator to traverse 100 data points in the dual-port RAM, and extracts the maximum and minimum values ​​within 10 clock cycles through two levels of logic: group comparison and global comparison. S420: Based on whether the maximum value and the minimum value are equal, normalize the 100 data points to obtain normalized data, store it in the matching data register group, or output an amplitude abnormality flag to trigger a return to S100.

8. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, The S500 includes: S510, Load the COE file, wherein the COE file includes three waveform types, each waveform type corresponds to multiple sets of 100-point standard template libraries, each waveform type is independently partitioned and stored in the on-chip BRAM array, and each set of 100-point standard module libraries corresponds to one frequency point. The S520 uses a pipelined read architecture to synchronously read standard waveforms from the BRAM array and distributes them to three computing units via three independent buses until all 100 points in all groups have been traversed.

9. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, The S600 includes: S610 uses three computing units to simultaneously calculate the difference between normalized data and the corresponding standard waveform, and converts the difference into an 8-bit unsigned value to obtain the absolute difference value through an absolute value circuit; S620 uses the absolute difference of the current group to continuously accumulate the three-way SAD by each calculation unit; S630: For the current group, determine whether any of the three SAD values ​​of the current group are less than a preset threshold. If so, generate a fast matching signal and lock the corresponding waveform type, and pause pipeline reading. If not, compare the three SAD values ​​of the current group with the minimum SAD value of each waveform stored in the historical minimum SAD register, and update the historical minimum SAD and corresponding group number of each waveform using the comparison result.

10. The waveform recognition method based on FPGA waveform template matching according to claim 1, characterized in that, The S700 includes: S710, if the normalized data of all groups have been judged, then the global minimum value of SAD and the corresponding waveform are selected from all SADs. The S720 outputs the corresponding waveform type and valid flag based on the historical minimum SAD and the corresponding group number, and generates a calibration trigger signal. S730, based on the calibration trigger signal, drives the FPGA to return to S200 and enter the next batch process.

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