Wafer defect detection method and device, medium and product

Abstract

The invention discloses a wafer defect detection method and device, a medium and a product, and relates to the technical field of semiconductor integrated circuits. The wafer defect detection method comprises the following steps: performing defect scanning on a wafer to obtain a to-be-detected defect image of at least one to-be-detected defect position of the wafer; aligning the to-be-detected defect image with the chip design layout of the wafer so as to determine the pattern characteristics of the design layout pattern of the to-be-detected defect position; based on the graphic feature conditions corresponding to the multiple reference image generation models, the reference image generation models matched with the graphic features of the design layout graph are selected, and different reference image generation models correspond to different graphic feature conditions; converting the design layout graph into a reference image based on a reference image generation model adaptive to the design layout graph; and comparing the to-be-detected defect image of the to-be-detected defect position with the reference image to obtain a defect detection result.

Description

Technical Field

[0001] This application belongs to the field of semiconductor integrated circuit technology, and in particular relates to a wafer defect detection method, equipment, medium and product. Background Technology

[0002] In integrated circuit manufacturing, as process nodes continue to evolve, pattern sizes are approaching physical limits, making defect detection crucial. Scanning electron microscopes, such as the Defect Review Scanning Electron Microscope (DRSEM), can be used to scan wafers to identify defects, making them important wafer defect detection tools. The accuracy and efficiency of their detection results directly affect production yield and the localization of process problems. However, with the changes in patterns brought about by process evolution, there are still some false defect detections and missed defects in wafer defect detection.

[0003] Therefore, how to improve the accuracy of wafer defect detection and avoid false defect misjudgment and missed defect detection has become an important problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a wafer defect detection method, device, medium, and product that can improve the accuracy of defect detection.

[0005] A first aspect of this application provides a wafer defect detection method, comprising: performing defect scanning on a wafer to obtain a defect image of at least one defect location to be detected; aligning the defect image to be detected with a chip design layout of the wafer to determine the graphic features of the design layout at the defect location; selecting a reference image generation model that matches the graphic features of the design layout based on graphic feature conditions corresponding to multiple reference image generation models, wherein different reference image generation models correspond to different graphic feature conditions; converting the design layout into a reference image based on the reference image generation model that matches the design layout; and comparing the defect image of the defect location to be detected with the reference image to obtain a defect detection result.

[0006] A second aspect of this application provides a wafer defect detection apparatus, comprising: a scanning module for scanning a wafer to obtain a defect image at at least one location of a defect to be detected; an alignment module for aligning the defect image with a chip design layout of the wafer to determine the graphic features of the design layout at the location of the defect to be detected; a selection module for selecting a reference image generation model that matches the graphic features of the design layout based on graphic feature conditions corresponding to multiple reference image generation models, wherein different reference image generation models correspond to different graphic feature conditions; a conversion module for converting the design layout into a reference image based on the reference image generation model that matches the design layout; and a comparison module for comparing the defect image at the location of the defect to be detected with the reference image to obtain a defect detection result.

[0007] A third aspect of the embodiments of this application provides an electronic device, the device comprising: a memory and a program or instructions stored in the memory and executable on a processor, wherein when the program or instructions are executed by the processor, they implement the wafer defect detection method provided by any aspect of the embodiments of this application described above.

[0008] A fourth aspect of the embodiments of this application provides a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, they implement the wafer defect detection method provided by any aspect of the embodiments of this application described above.

[0009] A fifth aspect of the embodiments of this application provides a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a wafer defect detection method as provided in any aspect of the embodiments of this application described above.

[0010] The wafer defect detection method provided in this application aligns the image of the defect to be detected with the chip design layout of the wafer to determine the graphic features of the design layout at the location of the defect. Then, based on the graphic feature conditions corresponding to multiple reference image generation models, a reference image generation model that matches the graphic features of the design layout is selected. Based on this model, the design layout is converted into a reference image, making the generated reference image closer to the actual morphology of the design layout on the wafer under actual process conditions. Furthermore, by comparing the image of the defect to be detected at the location of the defect with the reference image, the defect detection result is obtained, which can more accurately distinguish between actual defects and graphic differences caused by process variations, thus improving the accuracy of defect detection. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a wafer defect detection method provided in one embodiment of this application; Figure 2 This is a schematic diagram of a first reference image generation model provided in one embodiment of this application generating a reference image based on a design layout graphic; Figure 3 This is a schematic diagram of a second reference image generation model provided in one embodiment of this application generating a reference image based on a design layout graphic; Figure 4 This is a schematic flowchart of a wafer defect detection method provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of a wafer defect detection device provided in one embodiment of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0016] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0017] A scanning electron microscope (SEM) is a microscopic analytical instrument that uses a focused high-energy electron beam to scan the surface of a sample and to image it by detecting the various physical signals generated by the interaction between the electron beam and the sample.

[0018] The Defect Review Scanning Electron Microscope (DRSEM) is a specialized SEM instrument used for high-resolution, high-magnification imaging review of potential defect locations on wafers.

[0019] Die-to-Die (D2D) is a defect detection algorithm that identifies defects by comparing the image differences between the chip under test and an adjacent or known qualified reference chip at the same location on the same wafer.

[0020] Die-to-Database (D2DB) is a defect detection algorithm that identifies defects by comparing an actual image of the chip under test with an ideal reference image generated by simulating the chip design layout using a process model.

[0021] In the integrated circuit manufacturing process, as process nodes continue to evolve, pattern sizes are approaching physical limits, making defect detection crucial. Scanning electron microscopes, such as DRSEM, are important tools for wafer defect detection, and the accuracy and efficiency of their detection results directly affect the improvement of production yield and the localization of process problems.

[0022] DRSEM defect detection employs two methods: chip-to-chip (D2D) and chip-to-database (D2DB). The D2DB method identifies defects by comparing the DRSEM image with an ideal reference image generated from the chip design layout data using an optical proximity correction model. For simple, sparse graphic regions, the optical proximity correction model generates a reference image that closely approximates the real image. However, for complex, dense graphic regions, discrepancies arise between the generated reference image and the DRSEM image. If strict comparison is applied during inspection, systematic biases caused by the inaccuracy of the reference image in complex regions can lead to numerous false defects being misidentified. Conversely, relaxing the comparison criteria to avoid false defects can result in the missed detection of genuine random defects in complex regions.

[0023] In view of this, this application provides a wafer defect detection method, apparatus, medium, and product. The wafer defect detection method provided in this application aligns the image of the defect to be detected with the chip design layout of the wafer to determine the graphic features of the design layout at the location of the defect. Then, based on the graphic feature conditions corresponding to multiple reference image generation models, a reference image generation model that matches the graphic features of the design layout is selected. Based on this model, the design layout is converted into a reference image, making the generated reference image closer to the actual morphology of the design layout on the wafer under actual process conditions. Furthermore, by comparing the image of the defect to be detected at the location of the defect with the reference image, the defect detection result is obtained, which can more accurately distinguish between actual defects and graphic differences caused by process variations, thus improving the accuracy of defect detection.

[0024] In some application scenarios, the wafer defect detection method provided in this application embodiment can perform defect detection and classification based on DRSEM. In practical applications, the DRSEM is placed at the inspection station on the production line to perform defect detection on the produced wafers. The acquired DRSEM images are transmitted to a computer, which performs defect detection on the DRSEM images according to the wafer defect detection method provided in this application embodiment and stores the defect detection results in a data storage device. Operators can view the defect detection results through a display device and perform corresponding processing on defective chips based on the defect detection results, such as screening, repair, or scrapping.

[0025] It should be noted that the application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems. The wafer defect detection method provided by the embodiments of this application can be applied to various application scenarios that require defect detection of wafer scan images.

[0026] The wafer defect detection method provided in the embodiments of this application is described below. In practical applications, the wafer defect detection method of the embodiments of this application can be executed by an electronic device. The electronic device can have a display screen, so that the defect detection results can be displayed on the display screen.

[0027] The following describes specific embodiments of the wafer defect detection method, apparatus, equipment, medium, and product provided in this application. First, the wafer defect detection method will be introduced.

[0028] Figure 1 This is a schematic flowchart of a wafer defect detection method provided in one embodiment of this application. Figure 1 As shown, the method includes steps S101 to S105.

[0029] S101, perform defect scanning on the wafer to obtain an image of at least one defect location to be detected on the wafer.

[0030] S102, Align the image of the defect to be detected with the chip design layout of the wafer to determine the graphic features of the design layout graphic at the location of the defect to be detected.

[0031] S103, based on the graphic feature conditions corresponding to multiple reference image generation models, select the reference image generation model that matches the graphic features of the design layout graphic, with different reference image generation models corresponding to different graphic feature conditions.

[0032] S104, a reference image generation model based on design layout graphic adaptation, transforms the design layout graphic into a reference image.

[0033] S105, compare the image of the defect to be detected at the location of the defect with the reference image to obtain the defect detection result.

[0034] The wafer defect detection method provided in this application aligns the image of the defect to be detected with the chip design layout of the wafer to determine the graphic features of the design layout at the location of the defect. Then, based on the graphic feature conditions corresponding to multiple reference image generation models, a reference image generation model that matches the graphic features of the design layout is selected. Based on this model, the design layout is converted into a reference image, ensuring that the generated reference image closely approximates the actual morphology of the design layout on the wafer under actual process conditions. Furthermore, by comparing the image of the defect to be detected at the location of the defect with the reference image, the defect detection result is obtained, enabling a more accurate distinction between actual defects and graphic differences caused by process variations, thus improving the accuracy of defect detection.

[0035] In step S101, to improve chip manufacturing accuracy and yield, a DRSEM can be used to scan the locations on the wafer that have been marked as potential defects, obtaining an image of at least one defect location to be detected. The location of the potential defect is the defect location to be detected, which can be characterized by absolute or relative coordinates. The defect location to be detected can be determined and marked in advance using various possible detection methods. For example, it can be detected by a rapid optical inspection device based on light scattering or light intensity contrast; such a rapid optical inspection device could be, for example, a bright-field or dark-field optical scanner.

[0036] One defect location can be scanned to obtain one defect image or multiple defect images, depending on the defect analysis requirements and detection accuracy requirements. This application does not impose any limitations on this.

[0037] In step S102, to accurately select the appropriate reference image generation model based on graphic features in subsequent steps, the image of the defect to be detected is aligned with the chip design layout. This allows for precise determination of the design layout graphic corresponding to the location of the defect to be detected, and extraction of the graphic features of the design layout graphic. The chip design layout refers to the design graphic data required for integrated circuit manufacturing, typically described in formats such as Graphical Database System (GDS) to depict the geometric layout of the circuit. Graphic features refer to the geometric attributes of the graphics in the chip design layout, such as the shape, density, linewidth, and number of edges and corners.

[0038] In some implementations, the process of aligning the image of the defect to be detected with the chip design layout of the wafer may include: first extracting the image outline of the image of the defect to be detected, then converting the image outline into an image outline with the same data format as the design layout, and performing feature point matching and alignment between the image outline after data format conversion and the design layout.

[0039] In step S103, the reference image generation model is an algorithm model used to simulate the design layout based on process parameters and generate a wafer image that conforms to the actual wafer morphology. The graphic feature conditions refer to the judgment criteria for graphic features applicable to each reference image generation model, which can be expressed as numerical thresholds, qualitative descriptions, etc., used to constrain graphic features.

[0040] In some embodiments, in order to accurately select a reference image generation model for adapting the graphic features of the selected design layout graphic, the processing procedure of step S103 may include: Based on the graphic features of the design layout graphic, the graphic complexity of the design layout graphic is determined, and the graphic complexity is matched with the graphic complexity conditions corresponding to multiple reference image generation models respectively, and the reference image generation model with suitable graphic complexity is selected. Alternatively, based on the graphic characteristics of the design layout graphic, determine the design check rules triggered by the design layout graphic, match the design check rules with the design check rule conditions corresponding to multiple reference image generation models, and select the reference image generation model that is compatible with the design check rules.

[0041] Graphic complexity refers to the geometric complexity of a design layout graphic. It can be evaluated using parameters such as graphic type, edge morphology, topological relationships, graphic density, number of corners, and line width variations. It can be qualitatively described as high or low graphic complexity, or numerically classified into complexity levels. Graphic types can include single basic geometric shapes and combinations of multiple basic geometric shapes. Topological relationships can include array distribution, multi-layered nesting, and heterogeneous arrays. Edge morphology can include right angles, arcs, and acute angles. For example, graphic complexity can be calculated by determining the number of corner points per unit area or the graphic density of the design layout graphic. For instance, if the number of corner points per unit area exceeds a preset threshold, the graphic complexity is considered high; otherwise, it is low. Graphic complexity conditions are the criteria for judging graphic complexity applicable to the reference image generation model. For example, high graphic complexity can be used as the graphic complexity condition, and low graphic complexity as the graphic complexity condition.

[0042] The number of corner points per unit area refers to the total number of all corner vertices in a design layout within a unit area. A higher number of corner points per unit area generally indicates more turns and a more complex structure.

[0043] Graphic density refers to the proportion of area occupied by graphic elements within a unit area of ​​graphic design. Higher graphic density means denser graphic elements, narrower process windows, and correspondingly higher complexity.

[0044] Minimum linewidth refers to the narrowest line width within a graphic region. At advanced process nodes, the closer the linewidth is to the physical limit, the greater the manufacturing variability and the higher the graphic complexity of that region.

[0045] In one implementation, the graphics complexity can be determined by setting a preset corner density threshold. For example, if the number of corners per unit area is greater than the preset corner density threshold, the graphics complexity is high; if the number of corners per unit area is less than the preset corner density threshold, the graphics complexity is low.

[0046] In one implementation, the graphics complexity can be determined by a preset density threshold. For example, if the graphics density is greater than the preset density threshold, the graphics complexity is high; if the graphics density is less than the preset density threshold, the graphics complexity is low.

[0047] In one implementation, the graphics complexity can be determined by a preset line width threshold. For example, if the minimum line width is greater than the preset line width threshold, the graphics complexity is determined to be high; if the minimum line width is less than the preset line width threshold, the graphics complexity is determined to be low.

[0048] In one implementation, the graphic complexity can be determined based on the number of corner points per unit area, graphic density, and minimum line width. For example, the number of corner points per unit area, graphic density, and minimum line width are normalized and then weighted and summed. The weighted sum is then compared with a preset threshold. If it is greater than the preset threshold, the graphic complexity is determined to be high; if it is less than the preset threshold, the complexity is determined to be low.

[0049] Design check rules refer to the set of rules used in the chip design verification phase to check whether the design layout conforms to the geometric constraints of the manufacturing process, such as minimum linewidth rules and minimum spacing rules. Design check rule conditions are the triggered design check rules applicable to the reference image generation model. For example, the design layout graphic corresponding to the defect image to be detected in the chip design layout can be run with design check rules to identify whether the graphic triggers any design check rule. Triggering a design check rule can also be understood as violating a design check rule. For example, if the linewidth of the graphic is less than the minimum value specified in the design check rule, then the minimum linewidth rule is triggered. Multiple reference image generation models can include reference image generation models that use triggering the minimum linewidth rule as a design check rule condition.

[0050] The wafer defect detection method provided in this application determines the graphic complexity of the design layout graphic or the design inspection rules triggered by the graphic features based on the graphic features of the design layout graphic. It can quantify the graphic features into graphic complexity or associate them with the design inspection rules, and then match the graphic complexity or design inspection rules with the graphic feature conditions or design inspection rule conditions corresponding to multiple reference image generation models respectively, so as to accurately select the reference image generation model that matches the graphic features of the design layout graphic.

[0051] In some embodiments, the plurality of reference image generation models include a first reference image generation model that generates reference images based on optical proximity correction and a second reference image generation model that generates reference images based on hotspot simulation; wherein the graphics complexity requirement of the first reference image generation model is lower than the graphics complexity requirement of the second reference image generation model.

[0052] The first reference image generation model is based on optical proximity correction (OPC). Optical proximity correction (OPC) is a technique used to compensate for the optical proximity effect (OPE) during photolithography. In photolithography, when the size of the design pattern is close to or smaller than the resolution limit of the photolithography system, phenomena such as light diffraction and interference can cause deviations between the actual pattern transferred to the wafer and the original design pattern, such as changes in linewidth, rough edges, rounded corners, and uneven spacing. OPC pre-adjusts and modifies the pattern on the photolithography mask by adding auxiliary patterns or changing the shape, size, and position of the original patterns to counteract the influence of the optical proximity effect, thereby making the final pattern formed on the wafer as close as possible to the ideal design pattern. The first reference image generation model based on OPC is used to generate a reference image that matches the morphology of the wafer after photolithography through morphology simulation based on optical proximity correction.

[0053] The second reference image generation model is a model based on hotspot simulation to generate reference images. Hotspots, also known as hotspots, are areas in the chip design layout that are prone to defects during lithography and etching processes, and are subject to high-precision process simulation. In some embodiments, the model based on hotspot simulation can generate a reference image that matches the actual morphology of the hotspot area after lithography, based on high-precision process simulation of the hotspot area. In other embodiments, the model based on hotspot simulation can be a model constructed by adding a multilayer perceptron to a lithography model. This model is used to simulate the lithography process based on the lithography model to predict the wafer morphology, and the multilayer perceptron learns the mapping relationship between process parameters and wafer morphology.

[0054] In some implementations, for design layout graphics with low graphic complexity, a first reference image generation model can be selected to generate a reference image, while for design layout graphics with high graphic complexity, a second reference image generation model can be selected to generate a reference image.

[0055] The wafer defect detection method provided in this application embodiment has a lower graphic complexity requirement for the first reference image generation model than for the second reference image generation model. This allows for the accurate selection of either the first reference image generation model based on optical proximity correction or the second reference image generation model based on hotspot simulation, depending on the graphic complexity of the design layout. This results in the generation of more accurate reference images and improved defect detection accuracy.

[0056] In some embodiments, in order to generate an accurate reference image and improve the accuracy of defect detection, when the design layout graphics are adapted to the first reference image generation model, the processing in step S104 may include: Optical proximity correction is performed on the design layout graphic to obtain the corrected mask graphic; The light intensity distribution corresponding to the corrected mask pattern is calculated based on the optical model. The photoresist pattern is predicted based on the photoresist model and light intensity distribution; Based on the etching compensation rule, the photoresist pattern is etched to obtain the etch-compensated pattern. Etching simulation is performed based on the etch-compensated image to obtain a reference image generated by the etch simulation.

[0057] In this embodiment, the first reference image generation model takes the design layout graphic as input and outputs the reference image through optical proximity correction, optical simulation, photoresist development simulation, etching compensation and etching simulation.

[0058] The optical model can simulate the light intensity distribution formed on the wafer surface after light passes through a mask and projection lens. By setting parameters such as the shape of the light source, numerical aperture, and aberrations, the optical model generates a light intensity distribution that describes the intensity of light irradiation energy received at various points on the wafer surface.

[0059] A photoresist model is a mathematical model that simulates the chemical and physical changes of photoresist materials during exposure, post-baking, and development, and is used to predict the three-dimensional profile formed by the photoresist after development.

[0060] Etching compensation rules are a set of adjustment parameters based on process experience, used to pre-correct the pattern size changes that may be caused by the etching process at the design data level, so as to obtain the pattern after etching compensation.

[0061] Etching simulation is a process that uses mathematical models to predict the etching process and transfer photoresist patterns to semiconductor materials or metal layers on a wafer to form the wafer's morphology.

[0062] In some implementations, firstly, an optical proximity correction model is used to perform optical proximity correction on the design layout graphic. Then, the edges of the input graphic are fine-tuned according to a preset rule library, such as by adding auxiliary graphics or adjusting the edge position, to obtain the corrected mask graphic.

[0063] Then, the light intensity distribution corresponding to the corrected mask pattern is calculated based on the optical model. Specifically, the corrected mask pattern data and the set lithography machine optical parameters can be input into the optical model together, and the optical model is used to calculate the light intensity distribution formed on the wafer surface after the light passes through the corrected mask pattern and the projection lens.

[0064] Next, the photoresist pattern is predicted based on the photoresist model and light intensity distribution. Specifically, the light intensity distribution can be input into the photoresist model, and the photoresist model can be used to simulate a series of processes such as exposure, post-baking, and development. Finally, the predicted three-dimensional morphology of the photoresist, i.e., the photoresist pattern, is output.

[0065] Then, based on the etching compensation rules, the photoresist pattern is etched to obtain the etch-compensated pattern. Specifically, the edges of the photoresist pattern can be adjusted in reverse according to the etching compensation table for the current process to generate an etch-compensated pattern to compensate for deviations in subsequent etching processes.

[0066] Finally, based on the etch-compensated pattern, an etch simulation is performed to obtain a reference image generated by the etch simulation. Specifically, an etch process model can be used to simulate the process of transferring the etch-compensated pattern onto the wafer substrate and output the final predicted wafer morphology. The final predicted wafer morphology is the reference image for the transformation of the design layout pattern.

[0067] Figure 2This is a schematic diagram of a first reference image generation model provided in one embodiment of this application generating a reference image based on a design layout graphic. For example... Figure 2 As shown, the design layout graphic 21 corresponding to the location of the defect to be detected is a simple graphic with low graphic complexity. A reference image is generated using the first reference image generation model to obtain reference image 22.

[0068] The wafer defect detection method provided in this application simulates key process steps from mask preparation to final wafer morphology formation through optical proximity correction, optical simulation, photolithography simulation, etching compensation rules, and etching simulation. This enables the generated reference image to more realistically reflect the morphology that simple patterns should have in actual manufacturing, thereby reducing systematic errors caused by process deviations, and further reducing the possibility of false alarms and missed alarms in simple pattern areas, thus improving the accuracy of defect detection.

[0069] In some embodiments, in order to generate an accurate reference image and improve the accuracy of defect detection, when the design layout graphics are adapted to the second reference image generation model, the processing in step S104 may include: Optical proximity correction is performed on the design layout graphic to obtain the corrected mask graphic; The light intensity distribution corresponding to the corrected mask pattern is calculated based on the hotspot model, and the light intensity distribution includes the light intensity distribution of the hotspot region. The photoresist pattern is predicted based on the photoresist model and light intensity distribution; The etching of photoresist patterns is simulated based on a hotspot etching model to obtain a reference image generated by the etching simulation.

[0070] In this embodiment, the second reference image generation model takes the design layout graphic as input and outputs the reference image through optical proximity correction, optical simulation of hotspot model, photoresist development simulation, and etching simulation of hotspot etching model.

[0071] Among them, the hotspot model is a model specifically designed to identify and simulate complex graphic regions in chip design layouts that are prone to manufacturing problems. Compared to ordinary optical models, the hotspot model can more accurately predict optical and process effects at dense graphics and special topologies.

[0072] The light intensity distribution in hotspot areas is the light energy distribution corresponding to the local graphics that are prone to defects, as identified by the hotspot model. The light intensity distribution in hotspot areas usually has special distribution characteristics.

[0073] The hotspot etching model is a specialized model for simulating etching processes in the aforementioned complex graphic regions.

[0074] In some embodiments, since the hotspot model needs to handle complex graphics, it can employ a more rigorous full-vector diffraction theory algorithm. For example, it can treat light waves as vector fields, fully consider the polarization state of light, such as TE mode (Transverse Electric Mode) and TM mode (Transverse Magnetic Mode), as well as the interaction and coupling of light when passing through masks and projection systems. For instance, in dense lines and contact hole arrays, the interference effect of polarized light can greatly affect the imaging contrast, and the full-vector model can accurately simulate this phenomenon.

[0075] In some embodiments, the hotspot model can employ more rigorous electromagnetic field simulation algorithms, such as the finite-difference time-domain method or rigorous coupled-wave analysis. These methods take into account the three-dimensional topology of the mask, such as the indentation of the phase-shifting mask and the thickness of the absorption layer, to calculate the interaction between the light field and the three-dimensional structure of the mask. For example, for dense patterns using phase-shifting masks, it is possible to accurately calculate the phase change and intensity attenuation caused by light passing through phase layers of different thicknesses.

[0076] In some embodiments, the hotspot model not only considers the optical proximity effect caused by light diffraction between patterns, but can also specifically simulate the standing wave effect within the photoresist and the chemical diffusion effect during the development process. For example, when calculating the light intensity distribution, the hotspot model can superimpose the standing wave pattern caused by reflection from the photoresist substrate onto the incident light intensity distribution, thereby significantly changing the local exposure dose in dense patterns.

[0077] In some embodiments, the hotspot model may also include advanced optimization and modeling of the light source shape. Compared to the simple circular or ring light source that may be used in ordinary optical models, the hotspot model can use more complex pixelated light sources or freeform light sources, optimizing the imaging quality of specific complex patterns by adjusting the intensity of each point on the light source, and simulating the imaging results under such optimized light sources.

[0078] In some embodiments, the hotspot model can identify regions susceptible to process variations, such as shortened line ends, rounded corners, or excessive line edge roughness, using predefined rules or machine learning algorithms, such as convolutional neural networks. The hotspot model can also be based on random effects analysis, simulating variations in light intensity distribution, such as increases or decreases in brightness, to generate probability distribution profiles, thereby defining hotspot boundaries and identifying hotspot regions.

[0079] Understandably, for simple, sparse patterns, the degree of diffraction and interference of light after passing through a mask is relatively limited. However, in hotspot regions, due to the presence of dense lines, complex corners, adjacent patterns, or subwavelength dimensional structures, light undergoes strong diffraction and complex interference. Secondly, for simple, sparse patterns, the light intensity distribution typically exhibits a regular, predictable pattern, such as a uniform bright field or a dark field with smooth edges. In contrast, the light intensity distribution in hotspot regions contains unique, anomalous local features. Furthermore, the light intensity distribution in ordinary regions is relatively insensitive to minute changes in lithography process parameters, such as focal length and dose. However, the light intensity distribution in hotspot regions is extremely sensitive to minute fluctuations in process parameters, making its morphology unstable and difficult to predict. In summary, this application employs a high-precision hotspot model to accurately capture its relationship with process parameters.

[0080] After calculating the light intensity distribution using the hotspot model, the photoresist pattern is predicted based on the photoresist model and the light intensity distribution. Specifically, the light intensity distribution generated by the hotspot model can be input into the photoresist model. Since the light intensity distribution includes the light intensity distribution of the hotspot region, the photoresist model can simulate a photoresist pattern that is closer to the actual situation based on the light intensity distribution of the hotspot region.

[0081] In some embodiments, the photoresist pattern is etched based on a hotspot etching model. Specifically, the photoresist pattern can be input into a hotspot etching model that is specifically designed for etching simulation of complex pattern areas. The model simulates the selective differences of the etching process in special locations such as dense pattern areas and corners, and outputs a reference image generated by the etching simulation, so that the reference image can better reflect the true shape of the complex pattern area.

[0082] Among them, the hot spot etching model simulates the etching process based on the physicochemical equations describing the etching process.

[0083] The parameters of the hotspot etching model can be flexibly set according to the required graphic complexity. In some embodiments, the hotspot etching model can employ more complete and complex physical effects than a general etching model, and use higher resolution and more dimensional parameters to improve the accuracy of the etching simulation. For example, in addition to the global bias, the parameters of the hotspot etching model can also include variable parameters related to the local density of the graphic, the orientation of the graphic, and even the topology of neighboring graphics.

[0084] Figure 3 This is a schematic diagram of a second reference image generation model provided in one embodiment of this application, which generates a reference image based on a design layout graphic. Figure 3 As shown, the design layout graphic 31 corresponding to the location of the defect to be detected is a complex graphic with high graphic complexity. A reference image is generated using the second reference image generation model to obtain reference image 32.

[0085] The wafer defect detection method provided in this application simulates key process steps from mask preparation to final silicon wafer pattern formation through optical proximity correction, optical simulation based on hotspot model, photolithography simulation, and etching simulation based on hotspot etching model. This enables the generated reference image to more realistically reflect the ideal morphology of complex patterns in actual manufacturing, avoiding false alarms and missed alarms caused by the inability to distinguish between process effects and defects in complex pattern areas, thereby improving the accuracy of defect detection.

[0086] In some embodiments, in order to determine accurate defect detection results, the processing procedure of step S105 includes: Calculate the difference between the graphic contour in the defect image to be detected and the graphic contour in the reference image; Based on the graphic complexity corresponding to the graphic features, the threshold for comparison of the graphic features is determined. The graphic complexity and the threshold for comparison of the graphic features are negatively correlated. Determine whether the difference exceeds the comparison threshold corresponding to the graphic feature; If so, it confirms that a defect exists at the location of the defect to be detected; If not, it is determined that there is no defect at the location of the defect to be detected.

[0087] In some implementations, firstly, image processing can be performed on the image of the defect to be detected to extract the graphic contours. Then, image processing can be performed on the reference image generation model to extract the graphic contours from the reference image. Next, the geometric deviation between the graphic contours in the defect image and the reference image can be calculated, and this geometric deviation can be defined as the degree of difference between the graphic contours in the defect image and the reference image. The geometric deviation can be the average Euclidean distance between corresponding points on the contour, the maximum deviation value, or the root mean square error, etc.

[0088] Then, for each defect image to be detected, the threshold for comparison can be determined based on the graphic complexity corresponding to the graphic features. The higher the graphic complexity, the smaller the threshold for comparison; the lower the graphic complexity, the larger the threshold for comparison.

[0089] Next, it is determined whether the difference between the graphic contour in the defect image to be detected and the graphic contour in the reference image exceeds the comparison difference threshold corresponding to the graphic feature. If it exceeds the threshold, it is determined that there is a defect at the location of the defect to be detected. If it does not exceed the threshold, it is determined that there is no defect at the location of the defect to be detected.

[0090] Because simple graphic regions have a high signal-to-noise ratio, small deviations are likely noise, so larger deviations can be allowed and identified as defects. However, complex graphic regions have a low signal-to-noise ratio, so even small anomalies may represent real defects, and therefore smaller deviations need to be identified as defects.

[0091] For example, for two different defect locations A and B to be detected, hereinafter referred to as location A and location B, location A is determined to be a simple graphic region based on graphic features, with a comparison difference threshold of 10 nanometers. If the difference between the graphic contour in the defect image of location A and the graphic contour in the reference image is 8 nanometers, then since 8 nanometers does not exceed the 10 nanometer threshold, it can be determined that location A has no defect. Location B is determined to be a complex graphic region based on graphic features, with a comparison difference threshold of 3 nanometers. If the difference between the graphic contour in the defect image of location B and the graphic contour in the reference image is 5 nanometers, then since 5 nanometers exceeds the 3 nanometer threshold, it can be determined that location B has a defect.

[0092] The wafer defect detection method provided in this application determines the comparison difference threshold corresponding to the graphic features based on the graphic complexity of the graphic features. It can determine different comparison difference thresholds for defect images with different graphic features, dynamically adjust the comparison difference thresholds, avoid false alarms and missed detections caused by different signal-to-noise ratios in different regions, and improve the detection accuracy.

[0093] In some embodiments, in order to determine accurate defect detection results, the processing procedure of step S105 includes: Images of multiple defects to be detected at different locations are stitched together to obtain a stitched defect image. Multiple reference images of the locations of defects to be detected are stitched together to obtain a stitched reference image; By comparing the stitched defect image with the stitched reference image, defect detection results are obtained for multiple defect locations to be detected.

[0094] In some implementations, the images of multiple defect locations to be detected can be stitched together based on their physical coordinates on the wafer to obtain a stitched reference image. Then, the reference images corresponding to the images of multiple defect locations to be detected can be stitched together to obtain another stitched reference image. The stitched defect image is then compared with the stitched reference image to obtain the defect detection results for multiple defect locations. Specific comparison methods and methods for determining whether a defect is detected can be found in the descriptions in the above embodiments, and will not be repeated here.

[0095] In some implementations, when it is necessary to detect and analyze multiple defect locations from the same process layer or process area, the stitched defect image is compared with a stitched reference image to determine the defect detection result for each defect location. This facilitates the identification of whether multiple defect locations exhibit spatial distribution patterns, common characteristics, or systemic process problems. For example, it can determine whether defects are arranged along a certain direction or whether defects are concentrated near specific graphic patterns, in order to determine whether there are equipment malfunctions or process defects, and to distinguish between random defects and systemic defects with repeating patterns.

[0096] The wafer defect detection method provided in this application compares the stitched defect image with the stitched reference image to obtain defect detection results for multiple defect locations to be detected. This not only reduces the computational resource consumption of image loading, alignment and other processes, saves computational resources and improves detection efficiency, but also enables global analysis of wafer defects to accurately determine whether the defects are random or systematic.

[0097] Figure 4 This is a schematic flowchart of a wafer defect detection method provided in one embodiment of this application. Figure 4 As shown, the method includes steps S401 to S410.

[0098] S401, Perform defect scanning on the wafer to obtain an image of at least one defect location to be detected on the wafer.

[0099] S402 aligns the image of the defect to be detected with the chip design layout of the wafer to determine the graphic features of the design layout graphic at the location of the defect to be detected.

[0100] S403, based on the graphic features of the design layout graphics, determines the graphic complexity of the design layout graphics or the design check rules triggered by the graphic features.

[0101] S404, based on the graphic features of the design layout graphic, determine the graphic complexity of the design layout graphic, and match the graphic complexity with the graphic complexity conditions corresponding to multiple reference image generation models respectively, and select the reference image generation model with suitable graphic complexity; or, based on the graphic features of the design layout graphic, determine the design check rules triggered by the design layout graphic, match the design check rules with the design check rule conditions corresponding to multiple reference image generation models respectively, and select the reference image generation model with suitable design check rules.

[0102] S405 is a reference image generation model based on design layout graphics adaptation, which transforms design layout graphics into reference images.

[0103] S406, calculate the difference between the graphic contour in the defect image to be detected and the graphic contour in the reference image.

[0104] S407, Based on the graphic complexity corresponding to the graphic feature, determine the comparison threshold corresponding to the graphic feature, wherein the graphic complexity and the comparison threshold are negatively correlated.

[0105] S408, determine whether the difference exceeds the comparison threshold corresponding to the graphic feature.

[0106] S409, if so, confirm that a defect exists at the location of the defect to be detected.

[0107] S410, if not, determine that there is no defect at the location of the defect to be detected.

[0108] The specific implementation methods of steps S401 to S410 can be found in the description of the above embodiments, and will not be repeated here.

[0109] As can be seen from the above one or more embodiments, the wafer defect detection method provided in this application can improve the accuracy of defect detection.

[0110] Based on wafer defect detection methods, this application also provides specific embodiments of wafer defect detection apparatus.

[0111] Figure 5 This is a schematic diagram of the structure of a wafer defect detection device provided in one embodiment of this application. Figure 5 As shown, the wafer defect detection device 50 provided in this application embodiment includes a scanning module 51, an alignment module 52, a selection module 53, a conversion module 54, and a comparison module 55.

[0112] Scanning module 51 is used to perform defect scanning on the wafer to obtain an image of the defect to be detected at least one location of the defect to be detected on the wafer. Alignment module 52 is used to align the image of the defect to be detected with the chip design layout of the wafer in order to determine the graphic features of the design layout graphic at the location of the defect to be detected. The selection module 53 is used to select the reference image generation model that matches the graphic features of the design layout graphic based on the graphic feature conditions corresponding to the multiple reference image generation models. Different reference image generation models correspond to different graphic feature conditions. The conversion module 54 is used to generate a reference image based on the design layout graphic adaptation model, and convert the design layout graphic into a reference image. The comparison module 55 is used to compare the image of the defect to be detected at the location of the defect with a reference image to obtain the defect detection result.

[0113] As an optional embodiment, the selection module 53 is specifically used to determine the graphic complexity of the design layout graphic based on the graphic features of the design layout graphic, and match the graphic complexity with the graphic complexity conditions corresponding to multiple reference image generation models respectively, and select the reference image generation model with suitable graphic complexity; or, based on the graphic features of the design layout graphic, determine the design check rules triggered by the design layout graphic, match the design check rules with the design check rule conditions corresponding to multiple reference image generation models respectively, and select the reference image generation model with suitable design check rules.

[0114] As an optional embodiment, the plurality of reference image generation models include a first reference image generation model that generates reference images based on optical proximity correction and a second reference image generation model that generates reference images based on hotspot simulation; wherein, the complexity of the graphics complexity requirement of the first reference image generation model is lower than the complexity of the graphics complexity requirement of the second reference image generation model.

[0115] As an optional embodiment, when the design layout graphic is adapted to the first reference image generation model, the conversion module 54 is specifically used to perform optical proximity correction on the design layout graphic to obtain a corrected mask graphic; calculate the light intensity distribution corresponding to the corrected mask graphic based on the optical model; predict the photoresist graphic based on the photoresist model and the light intensity distribution; perform etch compensation on the photoresist graphic based on the etch compensation rule to obtain an etch-compensated graphic; and perform etch simulation based on the etch-compensated graphic to obtain a reference image generated by the etch simulation.

[0116] As an optional embodiment, when the design layout graphic is adapted to the second reference image generation model, the conversion module 54 is specifically used to perform optical proximity correction on the design layout graphic to obtain a corrected mask graphic; calculate the light intensity distribution corresponding to the corrected mask graphic based on the hotspot model, the light intensity distribution including the light intensity distribution of the hotspot region; predict the photoresist pattern based on the photoresist model and the light intensity distribution; and perform etching simulation on the photoresist pattern based on the hotspot etching model to obtain a reference image generated by the etching simulation.

[0117] As an optional embodiment, the comparison module 55 is specifically used to calculate the difference between the graphic contour in the image of the defect to be detected and the graphic contour in the reference image; based on the graphic complexity corresponding to the graphic feature, determine the comparison difference threshold corresponding to the graphic feature, wherein the graphic complexity and the comparison difference threshold are negatively correlated; determine whether the difference exceeds the comparison difference threshold corresponding to the graphic feature; if yes, determine that there is a defect at the location of the defect to be detected; if no, determine that there is no defect at the location of the defect to be detected.

[0118] As an optional embodiment, the comparison module 55 is specifically used to stitch together images of multiple defect locations to be detected to obtain a stitched defect image; to stitch together reference images of multiple defect locations to be detected to obtain a stitched reference image; and to compare the stitched defect image with the stitched reference image to obtain defect detection results for multiple defect locations to be detected.

[0119] Based on the wafer defect detection method, this application also provides a specific embodiment of an electronic device.

[0120] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. For example... Figure 6 As shown, the electronic device may include a processor 61 and a memory 62 storing computer program instructions.

[0121] Specifically, the processor 61 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0122] Memory 62 may include mass storage for data or instructions. For example, and not limitingly, memory 62 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 62 may include removable or non-removable (or fixed) media. Where appropriate, memory 62 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 62 is non-volatile solid-state memory.

[0123] The processor 61 implements any of the wafer defect detection methods described in the above embodiments by reading and executing computer program instructions stored in the memory 62.

[0124] In one example, the electronic device may also include a communication interface 63 and a bus 64. Wherein, for example... Figure 6 As shown, the processor 61, memory 62, and communication interface 63 are connected via bus 64 and communicate with each other.

[0125] Communication interface 63 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0126] Bus 64 includes hardware, software, or both, that couples the components of the electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 64 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0127] Furthermore, in conjunction with the wafer defect detection methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the wafer defect detection methods in the above embodiments.

[0128] In addition, in conjunction with the wafer defect detection method in the above embodiments, this application embodiment can provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device performs the wafer defect detection method provided by any aspect of the above embodiments of this application.

[0129] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0130] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0131] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0132] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0133] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for detecting wafer defects, characterized in that, include: Defect scanning is performed on the wafer to obtain an image of at least one defect location to be detected on the wafer; Align the image of the defect to be detected with the chip design layout of the wafer to determine the graphic features of the design layout graphic at the location of the defect to be detected; Based on the graphic feature conditions corresponding to multiple reference image generation models, the reference image generation model that matches the graphic features of the design layout graphic is selected, and different reference image generation models correspond to different graphic feature conditions. Based on the reference image generation model adapted to the design layout graphic, the design layout graphic is transformed into a reference image; The defect image at the location of the defect to be detected is compared with the reference image to obtain the defect detection result.

2. The wafer defect detection method according to claim 1, characterized in that, The step of selecting the reference image generation model that best matches the graphic features of the design layout graphic based on the graphic feature conditions corresponding to multiple reference image generation models includes: Based on the graphic features of the design layout graphic, the graphic complexity of the design layout graphic is determined, and the graphic complexity is matched with the graphic complexity conditions corresponding to multiple reference image generation models respectively, and the reference image generation model that is suitable for the graphic complexity is selected. or, Based on the graphic features of the design layout graphic, the design check rules triggered by the design layout graphic are determined, and the design check rules are matched with the design check rule conditions corresponding to the multiple reference image generation models respectively, and the reference image generation model that is compatible with the design check rules is selected.

3. The wafer defect detection method according to claim 2, characterized in that, The plurality of reference image generation models include a first reference image generation model based on optical proximity correction and a second reference image generation model based on hotspot simulation; wherein, the graphics complexity required by the graphics complexity condition corresponding to the first reference image generation model is lower than the graphics complexity required by the graphics complexity condition corresponding to the second reference image generation model.

4. The wafer defect detection method according to claim 3, characterized in that, When the design layout graphic is adapted to the first reference image generation model, the design layout graphic is converted into a reference image based on the reference image generation model adapted to the design layout graphic, including: The design layout graphic is subjected to optical proximity correction to obtain the corrected mask graphic; The light intensity distribution corresponding to the corrected mask pattern is calculated based on the optical model. The photoresist pattern is predicted based on the photoresist model and the light intensity distribution. The photoresist pattern is etched and compensated according to the etch compensation rule to obtain the etch-compensated pattern. Based on the etch-compensated pattern, an etch simulation is performed to obtain a reference image generated by the etch simulation.

5. The wafer defect detection method according to claim 3, characterized in that, When the design layout graphic is adapted to the second reference image generation model, the design layout graphic is converted into a reference image based on the reference image generation model adapted to the design layout graphic, including: The design layout graphic is subjected to optical proximity correction to obtain the corrected mask graphic; The light intensity distribution corresponding to the corrected mask pattern is calculated based on the hotspot model, and the light intensity distribution includes the light intensity distribution of the hotspot region. The photoresist pattern is predicted based on the photoresist model and the light intensity distribution. The photoresist pattern is etched using a hotspot etching model to obtain a reference image generated by the etching simulation.

6. The wafer defect detection method according to any one of claims 1-5, characterized in that, The step of comparing the image of the defect to be detected at the location of the defect to be detected with the reference image to obtain the defect detection result includes: Calculate the difference between the graphic contour in the defect image to be detected and the graphic contour in the reference image; Based on the graphic complexity corresponding to the graphic feature, the comparison difference threshold corresponding to the graphic feature is determined, wherein the graphic complexity and the comparison difference threshold are negatively correlated. Determine whether the degree of difference exceeds the comparison threshold corresponding to the graphic feature; If so, it is determined that a defect exists at the location of the defect to be detected; If not, it is determined that there is no defect at the location of the defect to be detected.

7. The wafer defect detection method according to any one of claims 1-5, characterized in that, The defect image at the location of the defect to be detected is compared with the reference image to obtain the defect detection result, including: The images of the defects to be detected at multiple locations are stitched together to obtain a stitched defect image. The reference images of multiple locations of the defects to be detected are stitched together to obtain a stitched reference image; The stitched defect image is compared with the stitched reference image to obtain defect detection results for multiple defect locations to be detected.

8. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the wafer defect detection method as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the wafer defect detection method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the wafer defect detection method as described in any one of claims 1-7.

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