Dual-bus self-switching display interface and non-inductive backlight adjusting method and system

Abstract

The invention discloses a dual-bus self-switching display interface and a non-inductive backlight adjusting method and system, which integrate automatic identification of dual-bus MIPI DSI and LVDS, IOVDD level self-adaptive configuration, level self-switching matching and an integral non-inductive backlight adjusting method based on image acquisition, and realize plug and play and automatic compatibility of the display interface. The display module with different power supply levels and communication protocols can be adapted without manual intervention, electrical compatibility of reset, IC, interrupt and other signals under different IOVDD is ensured through the level self-switching circuit, the system robustness is improved, the ambient brightness is analyzed by using a camera image, real non-inductive backlight adjustment is realized, and the display quality is improved. The problem that a traditional photoresistor is prone to being affected by shielding or aging is avoided, the hardware cost and BOM complexity are reduced through the overall scheme, and meanwhile user experience and product universality are improved.

Description

Technical Field

[0001] This invention relates to the field of image processing, and in particular to a dual-bus self-switching display interface and a method and system for seamless backlight adjustment. Background Technology

[0002] The existing core board display interface circuit only supports specific display buses, such as LVDS or MIPI bus output. When the core board needs to support two types of screen modules, its display circuit (such as backlight circuit and control signal) and interface circuit cannot be merged and are incompatible. Moreover, the existing screen backlight adjustment relies on sensors.

[0003] Existing core board display interface circuits cannot support two or more types of display modules with a single interface, nor can they achieve compatibility with multiple display modules on a single interface. Furthermore, current technology requires a light distance sensor for screen backlight brightness adjustment, necessitating additional component costs.

[0004] In summary, a dual-bus self-switching display interface and a seamless backlight adjustment method and system are needed to address the shortcomings of existing technologies. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a dual-bus self-switching display interface and a seamless backlight adjustment method and system, aiming to solve the aforementioned problems.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a dual-bus self-switching display interface and a seamless backlight adjustment method, comprising the following steps:

[0007] Step S1: Power on and initialize the system. Configure the general purpose input / output (GPIO) of the core board to high impedance input mode, disable the internal pull-up / pull-down resistors, and initialize the MIPI DSI controller and LVDS physical layer PHY to high impedance mode.

[0008] Step S2: Control at least three GPIO pins to output different level combinations in sequence to drive the adjustable low dropout linear regulator ADJ LDO to poll and output multiple preset IOVDD level levels;

[0009] Step S3: At each IOVDD level, attempt to read the device address response and register ID of the external display module via the I²C bus; if a valid response is successfully obtained, lock the current IOVDD level and proceed to the next step, performing display bus type identification based on the locked IOVDD level;

[0010] Step S4: Using the IOVDD level output by ADJ LDO, the logic levels of the reset signal RST, I²C signal and touch interrupt signal INT output by the core board are automatically matched to the IOVDD level required by the external display module through the MOS transistor level self-switching circuit.

[0011] Step S5: After the display module is working normally, periodically start the camera module, collect the current environmental image through the MIPI CSI interface, perform brightness analysis on the collected image, and obtain the environmental brightness value;

[0012] Step S6: Compare the ambient brightness value M with the preset target brightness threshold K, and dynamically adjust the duty cycle of the backlight PWM signal in conjunction with the hysteresis mechanism.

[0013] Optionally, step S2 is implemented in the following manner:

[0014] Step A1: Construct the circuit. Select an adjustable LDO chip and connect a fixed resistor R1 between its OUT and ADJ pins to build a feedback network. Connect the three GPIOs SET1, SET2, and SET3 to the ADJ pin through current-limiting resistors. Connect each GPIO to ground with a pull-down resistor.

[0015] Step A2: System initialization. Initialize SET1, SET2, and SET3 as push-pull outputs and set them high. At the same time, establish a truth table in the program to map the combination of each GPIO in Hi-Z or Low state to the four-level IOVDD output voltage.

[0016] Step A3: Perform polling and level switching. The program polls the level level in sequence according to the four IOVDD output voltages increasing one by one. The target GPIO is set low and the other GPIOs are set to high impedance to configure the current voltage. After delaying and waiting for the LDO to stabilize, I²C detection is initiated. If the communication is successful, the level is locked and the loop is exited. Otherwise, the GPIO state is restored and the polling of the next level continues.

[0017] Optionally, step S3 is implemented in the following manner:

[0018] Step B1: Initialize the I²C controller. Under the configured IOVDD level, the MOS transistor level self-switching circuit automatically matches the electrical properties of the I²C master controller SCL / SDA pins and initializes the I²C bus to standard mode or fast mode, enabling the seven-bit address addressing and response mechanism.

[0019] Step B2: Perform I²C device address scanning. The host broadcasts the preset common display module I²C slave addresses in sequence. After each address, it checks whether an ACK signal is received from the slave pulling SDA low. If no ACK is received after traversing all candidate addresses, it is determined that there is no valid display module under the current IOVDD level and the detection of that level is terminated.

[0020] Step B3: Read the register ID to verify the module's validity. After receiving the ACK, the host immediately writes the manufacturer-defined ID register address to the slave address, then issues a repeat start condition and re-addresses in read mode, receives the ID value returned by the slave, sends NACK after the last byte and ends the transmission, and finally compares the read ID with the pre-stored valid list. If they match, it is confirmed as a valid display module.

[0021] Step B4: Lock IOVDD and enter the bus type identification stage. After the system initializes the MIPI DSI PHY and configures the clock and data channels, it sends the DSI Generic Read command to read the DCS ID of the module. If a response packet that conforms to the MIPI specification and has correct ECC / CRC verification is received, it is determined to be a MIPI display module.

[0022] Step B5: Perform bus type identification based on the lockout voltage. After locking the IOVDD level, the system performs MIPI DSI identification and LVDS identification respectively. Based on the identification results, it controls the analog switch SEL signal to select the corresponding channel and shuts down the drive of the other interface.

[0023] Optionally, the MIPI DSI identification is performed in the following ways:

[0024] After the system initializes the MIPI DSI PHY and configures the DSI_CLK and DSI_D0–D3 channels, it sends the DSI GenericRead command to read the DCS ID of the module. If a response packet conforming to the MIPI specification and with correct ECC / CRC verification is received, it is determined to be a MIPI display module.

[0025] Optionally, the LVDS identification is performed in the following ways:

[0026] The system enables LVDS PHY output, sends DE, HS, VS synchronization timing signals and test pixel data, and reads the module's internal status register via I²C. If the data is successfully obtained and its contents match the characteristics of LVDS, it is determined to be an LVDS display module.

[0027] Optionally, step S4 is implemented in the following manner:

[0028] Step C1: Build the hardware circuit, determine the high and low voltage domains, and build a level conversion unit composed of N-channel MOS transistors and pull-up / pull-down resistors for the RST, I²C, and INT signals respectively.

[0029] Step C2: When the core board outputs high and low levels, the MOS transistors turn off or on accordingly, automatically converting the low-side signals into high-side levels that match the IOVDD. When the interrupt signal is transmitted in reverse, through the combined action of the body diode and the channel conduction, the high-to-low level drops and is released.

[0030] Step C3: Once the ADJ LDO locks onto the target IOVDD, it provides the high-side pull-up power supply for all MOS level conversion units, automatically and seamlessly adapting the logic levels of the RST, I²C, and INT signals to the current IOVDD.

[0031] Optionally, the step S5 is implemented in the following manner:

[0032] Step D1: Periodically collect images. By creating a timer thread or a kernel work queue, wake up the camera periodically, and then successively open the device node, configure the YUYV format, apply for and map the DMA buffer, start the video stream, capture one frame of image, and then stop the collection and close the camera.

[0033] Step D2: Automatically select the brightness extraction strategy according to the image format - directly take the Y component for YUV images, calculate according to the formula for RGB images, and directly use the pixel values for RAW or grayscale images, and calculate the average ambient brightness value of the entire frame of image based on this.

[0034] Step D3: Output the result, and transfer the calculated ambient brightness value to the backlight control module.

[0035] Optionally, the step S6 is implemented in the following manner:

[0036] After successfully obtaining the ambient brightness value M, perform the following actions:

[0037] Compare the ambient brightness with the target threshold, compare the current ambient brightness value M with the preset target brightness threshold K, and determine the adjustment direction in combination with the hysteresis interval width ΔH.

[0038] Judge whether it is necessary to increase the backlight. If M < K - ΔH, it is determined that the current environment is too dark, and the backlight PWM duty cycle D is increased by a fixed step ΔD.

[0039] Judge whether it is necessary to decrease the backlight. If M > K + ΔH, it is determined that the current environment is too bright, and the backlight PWM duty cycle D is decreased by a fixed step ΔD.

[0040] If |MK|≤ΔH, meaning the ambient brightness is within the allowable fluctuation range near the target value, then keep the current PWM duty cycle D unchanged.

[0041] A dual-bus self-switching display interface and a seamless backlight adjustment system, employing the dual-bus self-switching display interface and seamless backlight adjustment method, includes a system initialization module, a power management and IOVDD configuration module, a display module automatic identification and bus type discrimination module, a level adaptive conversion module, an ambient brightness sensing and image acquisition module, and a seamless backlight dynamic adjustment module.

[0042] The system initialization module is used to configure the general-purpose input / output (GPIO) of the core board to high-impedance input mode, disable the internal pull-up / pull-down resistors, and initialize the MIPI DSI controller and LVDS physical layer PHY to high-impedance state.

[0043] The power management and IOVDD configuration module is used to generate multiple preset IOVDD voltages through an adjustable low-dropout linear regulator and multiple GPIO pin combinations. It polls different IOVDD levels to provide a suitable power supply level for subsequent I²C communication. Once a valid display module is detected, the current IOVDD level is locked.

[0044] The display module automatic identification and bus type discrimination module is used to scan common device addresses and read register IDs through the I²C bus under the current IOVDD level to verify the authenticity of the display module. It attempts to perform communication tests on both MIPI DSI and LVDS interface protocols. Based on the identification results, it controls the analog switch to select the corresponding bus channel and shuts down the other interface driver.

[0045] The level adaptive conversion module is used to form a level conversion unit using an N-channel MOSFET and pull-up / pull-down resistors to automatically match the logic level of the reset, I²C, and INT touch interrupt signals output by the core board to the high voltage domain corresponding to the current IOVDD.

[0046] The ambient brightness perception and image acquisition module is used to periodically wake up the camera module, acquire a frame of ambient image through the MIPI CSI interface, automatically select a brightness extraction strategy according to the image format, and calculate the average brightness value M of the whole frame image as the basis for backlight adjustment.

[0047] The seamless backlight dynamic adjustment module compares the ambient brightness value M with the preset target brightness threshold K, introduces a hysteresis interval ΔH to prevent frequent jitter, and dynamically adjusts the duty cycle D of the backlight PWM signal to achieve seamless and smooth adjustment.

[0048] The beneficial effects of this invention are:

[0049] 1. This invention integrates a method for automatic identification of dual-bus MIPI DSI and LVDS, adaptive configuration of IOVDD level, self-switching matching of level, and seamless backlight adjustment based on image acquisition. It achieves plug-and-play and automatic compatibility of the display interface, adapting to display modules with different power supply levels and communication protocols without manual intervention. Through the self-switching circuit of level, it ensures electrical compatibility of signals such as reset, I²C, and interrupt under different IOVDD, improving system robustness. It uses camera images to analyze ambient brightness, achieving truly seamless backlight adjustment and avoiding the problems of traditional photoresistors being easily affected by obstruction or aging. The overall solution reduces hardware costs and BOM complexity, while improving user experience and product versatility.

[0050] 2. In this invention, a core board circuit system with a single interface compatible with both LVDS and MIPI dual display buses is used. This display interface supports level adaptation, module identification, protocol determination, signal switching, and IO level matching. The control interface adaptively adjusts the level to match the external screen module. A camera module is used to acquire environmental image data, sense ambient brightness, and control the backlight in a closed loop. Self-adjusting backlight brightness is achieved without the need for a distance sensor.

[0051] 3. In this invention, the feedback network of the adjustable LDO is controlled by three GPIOs, generating multiple IOVDD levels with high-impedance / low-level combinations. Four voltage output levels can be achieved using only three GPIOs, saving MCU pin resources. The pull-down resistor + high-impedance state design avoids GPIO conflicts and improves the reliability of level switching. The polling mechanism combined with delay stabilization ensures that the LDO output is stable before I²C detection, improving the recognition success rate. The modular design facilitates software porting and maintenance, and the clear responsibilities of each module are conducive to hardware and software co-optimization. It provides a complete adaptive display and intelligent backlight solution for products, with high integration and mass production capability, and can be widely used in scenarios requiring highly compatible display terminals such as automotive, industrial control, medical, and consumer electronics. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of a method flow of the present invention.

[0053] Figure 2 This is a schematic diagram of a logic recognition process according to the present invention.

[0054] Figure 3 This is a schematic diagram of a brightness value calculation and judgment process according to the present invention.

[0055] Figure 4 This is a schematic diagram of the overall system structure of the present invention.

[0056] Figure 5 This is a schematic diagram of a power switching circuit according to the present invention.

[0057] Figure 6 This is a backlight control and adjustment structure diagram of the present invention. Detailed Implementation

[0058] To more clearly illustrate the technical solutions in the embodiments of the invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] like Figures 1 to 3 As shown, a dual-bus self-switching display interface and a seamless backlight adjustment method include the following:

[0060] Step S1: Power on and initialize the system. Configure the general purpose input / output (GPIO) of the core board to high impedance input mode, disable the internal pull-up / pull-down resistors, and initialize the MIPI DSI controller and LVDS physical layer PHY to high impedance mode.

[0061] Step S2: Control at least three GPIO pins to output different level combinations in sequence to drive the adjustable low dropout linear regulator ADJ LDO to poll and output multiple preset IOVDD level levels;

[0062] Implemented in the following ways:

[0063] Step A1: Construct the circuit. Select an adjustable LDO chip and connect a fixed resistor R1 between its OUT and ADJ pins to build a feedback network. Connect the three GPIOs SET1, SET2, and SET3 to the ADJ pin through current-limiting resistors. Connect each GPIO to ground with a pull-down resistor.

[0064] Step A2: System initialization. Initialize SET1, SET2, and SET3 as push-pull outputs and set them high. At the same time, establish a truth table in the program to map the combination of each GPIO in Hi-Z or Low state to the four-level IOVDD output voltage.

[0065] Step A3: Perform polling and level switching. The program polls the level level in sequence according to the four IOVDD output voltages increasing one by one. The target GPIO is set low and the other GPIOs are set to high impedance to configure the current voltage. After delaying and waiting for the LDO to stabilize, I²C detection is initiated. If the communication is successful, the level is locked and the loop is exited. Otherwise, the GPIO state is restored and the polling of the next level continues.

[0066] Step S3: At each IOVDD level, attempt to read the device address response and register ID of the external display module via the I²C bus; if a valid response is successfully obtained, lock the current IOVDD level and proceed to the next step, performing display bus type identification based on the locked IOVDD level;

[0067] Implemented in the following ways:

[0068] Step B1: Initialize the I²C controller. Under the configured IOVDD level, the MOS transistor level self-switching circuit automatically matches the electrical properties of the I²C master controller SCL / SDA pins and initializes the I²C bus to standard mode or fast mode, enabling the seven-bit address addressing and response mechanism.

[0069] Step B2: Perform I²C device address scanning. The host broadcasts the preset common display module I²C slave addresses in sequence. After each address, it checks whether an ACK signal is received from the slave pulling SDA low. If no ACK is received after traversing all candidate addresses, it is determined that there is no valid display module under the current IOVDD level and the detection of that level is terminated.

[0070] Step B3: Read the register ID to verify the module's validity. After receiving the ACK, the host immediately writes the manufacturer-defined ID register address to the slave address, then issues a repeat start condition and re-addresses in read mode, receives the ID value returned by the slave, sends NACK after the last byte and ends the transmission, and finally compares the read ID with the pre-stored valid list. If they match, it is confirmed as a valid display module.

[0071] Step B4: Lock IOVDD and enter the bus type identification stage. After the system initializes the MIPI DSI PHY and configures the clock and data channels, it sends the DSI Generic Read command to read the DCS ID of the module. If a response packet that conforms to the MIPI specification and has correct ECC / CRC verification is received, it is determined to be a MIPI display module.

[0072] Step B5: Perform bus type identification based on the lockout voltage. After locking the IOVDD level, the system performs MIPI DSI identification and LVDS identification respectively. Based on the identification results, it controls the analog switch SEL signal to select the corresponding channel and shuts down the drive of the other interface.

[0073] Perform MIPI DSI identification in the following ways:

[0074] After the system initializes the MIPI DSI PHY and configures the DSI_CLK and DSI_D0–D3 channels, it sends the DSI GenericRead command to read the DCS ID of the module. If a response packet conforming to the MIPI specification and with correct ECC / CRC verification is received, it is determined to be a MIPI display module.

[0075] LVDS identification is performed in the following ways:

[0076] The system enables LVDS PHY output, sends DE, HS, VS synchronization timing signals and test pixel data, and reads the module's internal status register via I²C. If the data is successfully obtained and its contents match the characteristics of LVDS, it is determined to be an LVDS display module.

[0077] Step S4: Using the IOVDD level output by ADJ LDO, the logic levels of the reset signal RST, I²C signal and touch interrupt signal INT output by the core board are automatically matched to the IOVDD level required by the external display module through the MOS transistor level self-switching circuit.

[0078] Implemented in the following ways:

[0079] Step C1: Build the hardware circuit, determine the high and low voltage domains, and build level conversion units consisting of N-channel MOSFETs and pull-up / pull-down resistors for the RST, I²C, and INT signals respectively;

[0080] Step C2: When the core board outputs a high or low level, the MOSFET is turned off or turned on, automatically converting the low-voltage side signal to the high-voltage side level that matches IOVDD. When the interrupt signal is transmitted in reverse, the body diode and the channel conduction work together to make the high-voltage to low-voltage level fall back and be released.

[0081] Step C3: Once the ADJ LDO locks onto the target IOVDD, it provides high-voltage pull-up power to all MOS level conversion units and automatically and seamlessly adapts the logic levels of the RST, I²C, and INT signals to the current IOVDD.

[0082] Step S5: After the display module is working normally, periodically start the camera module, collect the current environmental image through the MIPI CSI interface, perform brightness analysis on the collected image, and obtain the environmental brightness value;

[0083] Implemented in the following ways:

[0084] Step D1: Periodically acquire images. By creating a timer thread or kernel work queue, periodically wake up the camera, and sequentially open the device node, configure the YUYV format, request and map the DMA buffer, start the video stream, capture a frame of image, stop acquiring and turn off the camera.

[0085] Step D2: Automatically select the brightness extraction strategy according to the image format - directly take the Y component for YUV images, calculate according to the formula for RGB images, and directly use the pixel values for RAW or grayscale images, and calculate the average ambient brightness value of the entire frame of the image accordingly;

[0086] Step D3: Output the result, and transfer the calculated ambient brightness value to the backlight control module.

[0087] Step S6: Compare the ambient brightness value M with the preset target brightness threshold K, and dynamically adjust the duty cycle of the backlight PWM signal in combination with the hysteresis zone mechanism.

[0088] S6 is implemented in the following manner:

[0089] After successfully obtaining the ambient brightness value M, perform the following actions:

[0090] Compare the ambient brightness with the target threshold, compare the current ambient brightness value M with the preset target brightness threshold K, and determine the adjustment direction in combination with the hysteresis zone width ΔH;

[0091] Determine whether it is necessary to increase the backlight. If M < K - ΔH, it is determined that the current environment is too dark, and increase the backlight PWM duty cycle D by a fixed step ΔD;

[0092] Determine whether it is necessary to decrease the backlight. If M > K + ΔH, it is determined that the current environment is too bright, and decrease the backlight PWM duty cycle D by a fixed step ΔD;

[0093] Maintain the current brightness. If |M - K| ≤ ΔH, that is, the ambient brightness is within the allowable fluctuation range near the target value, keep the current PWM duty cycle D unchanged.

[0094] Such as Figures 4 to 6 , a dual-bus self-switching display interface and a non-sensing backlight adjustment system, adopting the dual-bus self-switching display interface and the non-sensing backlight adjustment method, including a system initialization module, a power management and IOVDD configuration module, a display module automatic identification and bus type discrimination module, a level adaptive conversion module, an ambient brightness perception and image acquisition module, and a non-sensing backlight dynamic adjustment module;

[0095] The system initialization module is used to configure the general-purpose input / output GPIO of the core board as a high-impedance input mode, turn off the internal pull-up / pull-down resistors, and initialize the MIPI DSI controller and the LVDS physical layer PHY to a high-impedance state;

[0096] The power management and IOVDD configuration module is used to generate multiple preset IOVDD voltages through an adjustable low-dropout linear regulator and multiple GPIO pin combinations. It polls different IOVDD levels to provide a suitable power supply level for subsequent I²C communication. Once a valid display module is detected, the current IOVDD level is locked.

[0097] The display module automatic identification and bus type discrimination module is used to scan common device addresses and read register IDs through the I²C bus under the current IOVDD level to verify the authenticity of the display module. It attempts to perform communication tests on both MIPI DSI and LVDS interface protocols. Based on the identification results, it controls the analog switch to select the corresponding bus channel and shuts down the other interface driver.

[0098] The level adaptive conversion module is used to form a level conversion unit using an N-channel MOSFET and pull-up / pull-down resistors to automatically match the logic level of the reset, I²C, and INT touch interrupt signals output by the core board to the high voltage domain corresponding to the current IOVDD.

[0099] The ambient brightness perception and image acquisition module is used to periodically wake up the camera module, acquire a frame of ambient image through the MIPI CSI interface, automatically select a brightness extraction strategy according to the image format, and calculate the average brightness value M of the whole frame image as the basis for backlight adjustment.

[0100] The seamless backlight dynamic adjustment module compares the ambient brightness value M with the preset target brightness threshold K, introduces a hysteresis interval ΔH to prevent frequent jitter, and dynamically adjusts the duty cycle D of the backlight PWM signal to achieve seamless and smooth adjustment.

[0101] The core board is compatible with LVDS / MIPI dual buses, featuring a self-switching display interface and a sensorless backlight adjustment system. Its overall circuitry includes the core board, analog switches, backlight control circuitry, display interface, and level self-switching circuitry, as follows: Figure 4 As shown.

[0102] Core board: Outputs LVDS / MIPI / IIC / RST and other signal lines.

[0103] Analog switch: By controlling the logic high / low output of the SEL pin, it switches the LVDS or MIPI signal to the display interface. Signal lines include: DSI_CLK / D0-D3, LVDS_CLK / D0-D3.

[0104] Backlight control circuit: The core board outputs a PWM signal to control the screen backlight brightness.

[0105] Display interface: Connects to external display modules, such as LVDS or MIPI screens.

[0106] Camera module: mainly collects the current environment image input. The core board adjusts the PWM signal to achieve screen brightness self-adjustment by collecting the brightness of the current environment image.

[0107] Level switching circuit: Used to switch the GPIO level of the core board's output / input to the communication level defined by the external screen module.

[0108] The specific steps of the system collaborative control process are as follows:

[0109] 1.1 System power-on initialization: After the core board powers on, it executes the initialization process, including:

[0110] Initialize GPIO direction (Input) and default state (Hi-Z), initialize Output Driver Disable, disable internal Pull-up / Pull-down, configure MIPI DSI and LVDS controller PHY to high impedance, set SET1 / SET2 / SET3 GPIO to high impedance input mode, initialize backlight PWM output to default duty cycle (50%), and keep the Camera module (MIPI DSI PHY) off after power-on initialization.

[0111] 1.2 The system displays the module's level adaptation and recognition. The core board controls SET1 / SET2 / SET3 GPIOs to perform multi-level polling configuration on the IOVDD output of the ADJ LDO:

[0112] Initially, IOVDD is configured to 1.8V, 2.5V, 3.3V, and 5.0V in sequence. At each voltage level, the display module is read via the IIC bus to check if the device address responds and the module register ID. If a valid device response and ID are successfully read at a certain voltage level, the IOVDD voltage level configuration is locked.

[0113] As shown in Table 1 below, the adaptive multi-level polling of the IOVDD level is achieved by controlling the levels of SET1-SET3 through initial configuration.

[0114] Table 1 Truth Table for Controlling ADJ LDO Output

[0115]

[0116] The parameters of the required supported screens can be written into the core board. External display module detection logic is then implemented through the SET level control and level self-switching circuit in Table 1. The identification process is as follows: Figure 2 As shown.

[0117] 1.3 Display bus type automatic switching steps

[0118] After the IOVDD level configuration is locked, the core board performs a display interface type determination:

[0119] If a MIPI DSI protocol response characteristic is detected (such as the host sending a DCS Read command to read the ManufacturerID), the analog switch SEL signal is switched to the MIPI channel, the DSI_CLK / D0-D3 signals are enabled, and the LVDS PHY TX output is disabled. If the LVDS device ID is read correctly (such as the host reading the ManufacturerID), the analog switch SEL signal is switched to the LVDS channel, the LVDS_CLK / D0-D3 signals are enabled, and the MIPI DSI PHY output is disabled.

[0120] 1.4 Control signal level self-switching steps

[0121] After the IOVDD level is locked, the RST / IIC / INT signals are automatically switched to match the amplitude of the display module's IOVDD level through the ADJ LDO + MOS transistor level self-switching circuit. This process does not require reconfiguration of the IO level within the SoC.

[0122] SoC internal control signal configuration logic:

[0123] The IIC is configured in Open-Drain Fast Mode, disabling internal pull-ups and relying on external IOVDD domains for pull-ups.

[0124] SoC internal control signal configuration logic:

[0125] RST: Output mode, GPIO Output Speed ​​is set to High Speed ​​(10)

[0126] INT: Input mode, GPIO mode is set to General-purpose input mode (00).

[0127] like Figure 5 This is a schematic diagram of a level-shifting circuit. The power input PVIN powers the ADJ, LDO, and core board. The core board outputs power to the screen interface. Simultaneously, the core board's GPIO SET1 / SET2 / SET3 controls the ADJ and LDO to output IOVDD. The IOVDD level can be adaptively adjusted according to the external screen module. Q3 / Q4 / Q5 are MOS devices capable of level shifting. Automatic level switching of RST_OUT1 / INT_IN / RST_OUT2 can be achieved by using Q3 / Q4 / Q5 in conjunction with the ADJ and LDO circuit.

[0128] 1.5 Camera Periodic Sampling Steps

[0129] After the display module is working normally, the core board periodically enables the camera module to acquire images via CSI data and process them internally on the core board.

[0130] Image resolution: 1280*800

[0131] Frame rate: 2 fps, sampling non-continuous video; software configurable to 1 fps / 2 fps / 5 fps.

[0132] Sampling period: T=10s, software can be configured for 5s / 10s / 15s / 20s.

[0133] like Figure 6 This describes the backlight control circuit. The core board enables the Camera module to capture images of the current environment. Through image brightness calculation, brightness thresholding, and PWM mapping, it adjusts the PWM signal input to the backlight control circuit. The specific implementation logic and scheme are as follows: Figure 6 As shown.

[0134] 1.6 Steps for calculating the brightness of the sampled image

[0135] The core board performs brightness analysis on the acquired images and calculates the ambient brightness value M.

[0136] If the image format is YUV, then the Y component is directly extracted as the luminance value M.

[0137] If the image format is RGB, the brightness value is calculated using the following formula:

[0138]

[0139] in The average brightness M of the current environment is obtained by averaging the pixels of the entire frame image.

[0140] If the image is in another format, the image brightness is calculated as the brightness value M using a weighted method that conforms to the characteristics of human visual perception.

[0141] 1.7 Brightness Threshold and PWM Mapping Steps

[0142] The system presets a target display brightness threshold K (the ambient brightness value corresponding to 400 nits). After the core board is powered on, the Camera module periodically powers on and operates (T=10s), and the module acquires image data to perform image brightness analysis.

[0143] The image format is analyzed for brightness, and the overall brightness value of the image is output. The default value of the PWM duty cycle in the backlight control circuit is 50%. The current image brightness value M is obtained. When M ≥ K, it means that the current ambient light intensity is normal or strong. In this case, the PWM duty cycle is reduced, thereby reducing the output current of the backlight control circuit and thus lowering the backlight brightness. When M < K, it means that the current ambient light intensity is weak. In this case, the PWM duty cycle is increased, thereby increasing the output current of the backlight control circuit and thus increasing the backlight brightness.

[0144] The adjustment strategy for the PWM duty cycle D is as follows:

[0145] Initial duty cycle of the core board to the screen Default state

[0146]

[0147] in The PWM adjustment coefficient is 0.05.

[0148] and The duty cycle adjustment range is as follows: .

[0149] To avoid frequent backlight adjustments caused by fluctuations in ambient brightness around a threshold, a hysteresis region is introduced during the brightness comparison process. ( ).

[0150] Definition of hysteresis region: That is, when At this time, the PWM is not adjusted, and the duty cycle remains unchanged.

[0151] The adaptive adjustment process is as follows: Figure 1 As shown, during the adjustment process, the PWM duty cycle is adjusted according to the previous adjustment result. Incremental adjustments are made based on a baseline, rather than repeatedly using the initial duty cycle. When the difference between the current ambient brightness value M and the target brightness threshold K is within the hysteresis range, the PWM duty cycle remains unchanged. Only when the difference exceeds the hysteresis range will the PWM adjustment operation be performed.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dual-bus self-switching display interface and a seamless backlight adjustment method, characterized in that, Includes the following steps: Step S1: Power on and initialize the system. Configure the general purpose input / output (GPIO) of the core board to high impedance input mode, disable the internal pull-up / pull-down resistors, and initialize the MIPI DSI controller and LVDS physical layer PHY to high impedance mode. Step S2: Control at least three GPIO pins to output different level combinations in sequence to drive the adjustable low dropout linear regulator ADJ LDO to poll and output multiple preset IOVDD level levels; Step S3: At each IOVDD level, attempt to read the device address response and register ID of the external display module via the I²C bus; If a valid response is successfully obtained, the current IOVDD level is locked, and the process proceeds to the next step, where the display bus type identification is performed based on the locked IOVDD level. Step S4: Using the IOVDD level output by ADJ LDO, the logic levels of the reset signal RST, I²C signal and touch interrupt signal INT output by the core board are automatically matched to the IOVDD level required by the external display module through the MOS transistor level self-switching circuit. Step S5: After the display module is working normally, periodically start the camera module, collect the current environmental image through the MIPI CSI interface, perform brightness analysis on the collected image, and obtain the environmental brightness value; Step S6: Compare the ambient brightness value M with the preset target brightness threshold K, and dynamically adjust the duty cycle of the backlight PWM signal in conjunction with the hysteresis mechanism.

2. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 1, characterized in that, Step S2 is implemented in the following manner: Step A1: Construct the circuit. Select an adjustable LDO chip and connect a fixed resistor R1 between its OUT and ADJ pins to build a feedback network. Connect the three GPIOs SET1, SET2, and SET3 to the ADJ pin through current-limiting resistors. Connect each GPIO to ground with a pull-down resistor. Step A2: System initialization. Initialize SET1, SET2, and SET3 as push-pull outputs and set them high. At the same time, establish a truth table in the program to map the combination of each GPIO in Hi-Z or Low state to the four-level IOVDD output voltage. Step A3: Perform polling and level switching. The program polls the level level in sequence according to the four IOVDD output voltages increasing one by one. The target GPIO is set low and the other GPIOs are set to high impedance to configure the current voltage. After delaying and waiting for the LDO to stabilize, I²C detection is initiated. If the communication is successful, the level is locked and the loop is exited. Otherwise, the GPIO state is restored and the polling of the next level continues.

3. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 1, characterized in that, Step S3 is implemented in the following manner: Step B1: Initialize the I²C controller. Under the configured IOVDD level, the MOS transistor level self-switching circuit automatically matches the electrical properties of the I²C master controller SCL / SDA pins and initializes the I²C bus to standard mode or fast mode, enabling the seven-bit address addressing and response mechanism. Step B2: Perform I²C device address scanning. The host broadcasts the preset common display module I²C slave addresses in sequence. After each address, it checks whether an ACK signal is received from the slave pulling SDA low. If no ACK is received after traversing all candidate addresses, it is determined that there is no valid display module under the current IOVDD level and the detection of that level is terminated. Step B3: Read the register ID to verify the module's validity. After receiving the ACK, the host immediately writes the manufacturer-defined ID register address to the slave address, then issues a repeat start condition and re-addresses in read mode, receives the ID value returned by the slave, sends NACK after the last byte and ends the transmission, and finally compares the read ID with the pre-stored valid list. If they match, it is confirmed as a valid display module. Step B4: Lock IOVDD and enter the bus type identification stage. After the system initializes the MIPI DSI PHY and configures the clock and data channels, it sends the DSI Generic Read command to read the DCS ID of the module. If a response packet that conforms to the MIPI specification and has correct ECC / CRC verification is received, it is determined to be a MIPI display module. Step B5: Perform bus type identification based on the lockout voltage. After locking the IOVDD level, the system performs MIPIDSI identification and LVDS identification respectively. Based on the identification results, the analog switch SEL signal is controlled to select the corresponding channel and the drive of the other interface is turned off.

4. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 3, characterized in that, The MIPI DSI identification is performed in the following ways: After the system initializes the MIPI DSI PHY and configures the DSI_CLK and DSI_D0–D3 channels, it sends the DSI Generic Read command to read the DCS ID of the module. If a response packet conforming to the MIPI specification and with correct ECC / CRC verification is received, it is determined to be a MIPI display module.

5. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 3, characterized in that, The LVDS identification is performed in the following way: The system enables LVDS PHY output, sends DE, HS, VS synchronization timing signals and test pixel data, and reads the module's internal status register via I²C. If the data is successfully obtained and its contents match the characteristics of LVDS, it is determined to be an LVDS display module.

6. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 1, characterized in that, Step S4 is implemented in the following manner: Step C1: Build the hardware circuit, determine the high and low voltage domains, and build level conversion units consisting of N-channel MOSFETs and pull-up / pull-down resistors for the RST, I²C, and INT signals respectively; Step C2: When the core board outputs a high or low level, the MOSFET is turned off or turned on, automatically converting the low-voltage side signal to the high-voltage side level that matches IOVDD. When the interrupt signal is transmitted in reverse, the body diode and the channel conduction work together to make the high-voltage to low-voltage level fall back and be released. Step C3: Once the ADJ LDO locks onto the target IOVDD, it provides high-voltage pull-up power to all MOS level conversion units and automatically and seamlessly adapts the logic levels of the RST, I²C, and INT signals to the current IOVDD.

7. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 1, characterized in that, Step S5 is implemented in the following manner: Step D1: Periodically collect images. By creating a timer thread or a kernel work queue, wake up the camera periodically, and then successively open the device node, configure the YUYV format, apply for and map the DMA buffer, start the video stream. After capturing a frame of image, stop the collection and close the camera. Step D2: Automatically select the brightness extraction strategy according to the image format - directly take the Y component for YUV images, calculate according to the formula for RGB images, and directly use the pixel values for RAW or grayscale images, and calculate the average ambient brightness value of the entire frame of image accordingly. Step D3: Output the result, and transfer the calculated ambient brightness value to the backlight control module.

8. The dual-bus self-switching display interface and the seamless backlight adjustment method according to claim 1, characterized in that, The step S6 is implemented in the following manner: After successfully obtaining the ambient brightness value M, perform the following actions: Compare the ambient brightness with the target threshold, compare the current ambient brightness value M with the preset target brightness threshold K, and determine the adjustment direction in combination with the hysteresis interval width ΔH. Judge whether it is necessary to increase the backlight. If M < K - ΔH, it is determined that the current environment is too dark, and the backlight PWM duty cycle D is increased by a fixed step ΔD. Judge whether it is necessary to decrease the backlight. If M > K + ΔH, it is determined that the current environment is too bright, and the backlight PWM duty cycle D is decreased by a fixed step ΔD. Maintain the current brightness. If |M - K| ≤ ΔH, that is, the ambient brightness is within the allowable fluctuation range near the target value, the current PWM duty cycle D remains unchanged.

9. A dual-bus self-switching display interface and a seamless backlight adjustment system, employing the dual-bus self-switching display interface and seamless backlight adjustment method as described in any one of claims 1-8, characterized in that, It includes a system initialization module, a power management and IOVDD configuration module, a display module automatic identification and bus type discrimination module, a level adaptive conversion module, an ambient brightness perception and image acquisition module, and a touchless backlight dynamic adjustment module. The system initialization module is used to configure the general-purpose input / output GPIO of the core board as a high-impedance input mode, turn off the internal pull-up / pull-down resistors, and initialize the MIPI DSI controller and the LVDS physical layer PHY to a high-impedance state. The power management and IOVDD configuration module is used to generate multiple preset IOVDD voltages through the combination control of an adjustable low-dropout linear regulator and multiple GPIO pins, poll different IOVDD levels, provide a suitable power supply level for subsequent I²C communication, and once a valid display module is detected, lock the current IOVDD level. The display module automatic identification and bus type discrimination module is used to scan the common device addresses through the I²C bus and read the register ID at the current IOVDD level to verify the legality of the display module. Try to communicate and test using the MIPI DSI and LVDS interface protocols respectively. According to the identification result, control the analog switch to select the corresponding bus channel and turn off the other interface driver. The level adaptive conversion module is used to use an N-channel MOS transistor and pull-up / pull-down resistors to form a level conversion unit, and automatically match the logic levels of the reset, I²C, and INT touch interrupt signals output by the core board to the high-voltage domain corresponding to the current IOVDD. The ambient brightness perception and image acquisition module is used to periodically wake up the camera module, acquire a frame of ambient image through the MIPI CSI interface, automatically select a brightness extraction strategy according to the image format, and calculate the average brightness value M of the whole frame image as the basis for backlight adjustment. The seamless backlight dynamic adjustment module compares the ambient brightness value M with the preset target brightness threshold K, introduces a hysteresis interval ΔH to prevent frequent jitter, and dynamically adjusts the duty cycle D of the backlight PWM signal to achieve seamless and smooth adjustment.

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