Dual polysilicon non-volatile memory bit cell

Abstract

The invention relates to a dual polysilicon non-volatile memory bit cell. A non-volatile memory (NVM) bit cell is disclosed. The NVM bit cell includes a control gate, a state transistor, and an access transistor coupled in series with the state transistor. The control gate includes a floating terminal formed of a first polysilicon layer, a control terminal formed of a second polysilicon layer, and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-K dielectric layer. The state transistor includes a floating gate terminal formed of the first polysilicon layer and coupled to a floating terminal of the control gate. The state transistor also includes a tunnel oxide layer formed between the first polysilicon layer and the active region of the state transistor.

Description

Technical Field

[0001] This disclosure relates generally to integrated circuit technology, and more particularly to the design and methods for manufacturing non-volatile memory devices. Background Technology

[0002] Integrated circuits can be fabricated to include both data processing units (such as central processing units or graphics processing units) and memory blocks that can be used to store data for the data processing units. In some configurations, the memory blocks may include non-volatile memory (NVM), such as electrically erasable programmable read-only memory (EEPROM).

[0003] Conventional techniques for incorporating non-volatile memory on the same complementary metal-oxide-semiconductor (CMOS) integrated circuit as the data processing unit have utilized the gate oxide of CMOS processes to instantiate logic-based mono-polysilicon floating-gate EEPROMs. The inventors of embodiments of this disclosure have recognized that such embedded mono-polysilicon EEPROM cells typically require separate control gate and floating-gate transistors from access and state transistors, and their isolation. Relatedly, the inventors of embodiments of this disclosure have also recognized that such embedded mono-polysilicon EEPROM cells typically have a large footprint, thus consuming a considerable area of ​​the semiconductor die. Other NVM technologies using multiple polysilicon layers have been designed to have a smaller footprint than mono-polysilicon EEPROM cells. However, the inventors of embodiments of this disclosure have recognized that such other NVM technologies have higher processing costs and lower reliability. Embodiments of this disclosure address one or more of these challenges. Summary of the Invention

[0004] According to one aspect of this disclosure, a non-volatile memory (NVM) bit cell is provided, the NVM bit cell comprising: a control gate, the control gate including: a floating terminal formed of a first polysilicon layer; a control terminal formed of a second polysilicon layer; and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-k dielectric layer; a state transistor including: a floating gate terminal formed of the first polysilicon layer and coupled to the floating terminal of the control gate; and a tunnel oxide layer formed between the first polysilicon layer and an active region of the state transistor; and an access transistor connected in series with the state transistor.

[0005] According to another aspect of this disclosure, an integrated circuit is provided, the integrated circuit comprising: a logic block; and a non-volatile memory (NVM) bit cell array coupled to the logic block, the NVM bit cell array comprising a plurality of NVM bit cells arranged in multiple rows and columns, each NVM bit cell comprising: a control gate, the control gate comprising: a floating terminal formed of a first polysilicon layer; a control terminal formed of a second polysilicon layer; and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer comprises a high-k dielectric layer; a state transistor comprising: a floating gate terminal formed of the first polysilicon layer and coupled to the floating terminal of the control gate; and a tunnel oxide layer formed between the first polysilicon layer and an active region of the state transistor; and an access transistor connected in series with the state transistor.

[0006] According to another aspect of this disclosure, a method is provided, the method comprising: forming a well region; forming an access transistor in the well region; forming a state transistor in the well region, the state transistor having a floating gate terminal formed by a first polysilicon layer; forming a control gate having a floating terminal formed by the first polysilicon layer, a control terminal formed by a second polysilicon layer, and a control gate dielectric layer disposed between the first polysilicon layer and the second polysilicon layer and including a high-k dielectric layer. Attached Figure Description

[0007] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0008] Figure 1 A block diagram of an integrated circuit according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A schematic diagram of a non-volatile memory bit cell according to an embodiment of the present disclosure is shown.

[0010] Figure 3 This is a diagram illustrating the operating conditions of a non-volatile memory bit cell according to an embodiment of the present disclosure.

[0011] Figure 4 A top view of a semiconductor process region for a non-volatile memory bit cell array according to an embodiment of the present disclosure is shown.

[0012] Figure 5AA cross-sectional view of an array of non-volatile memory bit cells according to an embodiment of the present disclosure is shown.

[0013] Figure 5B A cross-sectional view of an array of non-volatile memory bit cells according to an embodiment of the present disclosure is shown.

[0014] Figure 5C A cross-sectional view of an array of non-volatile memory bit cells according to an embodiment of the present disclosure is shown.

[0015] Figure 6 This is a diagram illustrating the operating conditions of a non-volatile memory bit cell according to an embodiment of the present disclosure.

[0016] Figure 7 A method for manufacturing a non-volatile memory bit cell according to an embodiment of the present disclosure is shown. Detailed Implementation

[0017] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims.

[0018] Figure 1 A block diagram of an integrated circuit 100 according to an embodiment of the present disclosure is shown. The integrated circuit 100 may include a logic block 101, a non-volatile memory (NVM) bit cell array 102, a programming unit 104, an erasing unit 106, and a reading unit 108. The logic block 101 may include a data processing unit, such as a central processing unit or a graphics processing unit. The NVM bit cell array 102 may include a plurality of NVM bit cells arranged in multiple rows and columns. The logic block 101 may be coupled to the NVM bit cell array 102, and the NVM bit cell array 102 may be used to store information that can be used in one or more data processing functions.

[0019] Programming unit 104, erasing unit 106, and reading unit 108 can be configured to provide corresponding voltages to the NVM bit cell array 102 for programming, erasing, and reading bit cells within the NVM bit cell array 102. Figure 1 As shown, the programming unit 104, erasing unit 106, and reading unit 108 may be implemented as separate units in some embodiments. In other embodiments, the programming unit 104, erasing unit 106, and reading unit 108 may be implemented together in a single circuit having, for example, a charge pump and one or more voltage dividers, which may be used together to generate different corresponding voltages for programming, erasing, and reading one or more bit cells of the NVM bit cell array 102.

[0020] Figure 2A schematic diagram of a non-volatile memory (NVM) bit cell 200 according to an embodiment of the present disclosure is shown. The NVM bit cell 200 may include a control gate 210, a state transistor 220, and an access transistor 230. The NVM bit cell 200 may also be connected to various input and output lines for programming, erasing, and reading the state of the NVM bit cell 200. For example, as described in further detail below, various terminals of the NVM bit cell 200 may be coupled to access line AL, control line CL, source line SL, bit line BL, and p-well line PW. Also referenced below... Figures 4 to 6 The NVM bit cell 200 can represent a bit cell in a multi-row and multi-column bit cell array formed by different instances of the NVM bit cell 200. Therefore, as described in further detail below, one instance of the NVM bit cell 200 can share connections with other instances of the NVM bit cell 200 to one or more of the access line AL, control line CL, source line SL, bit line BL, and p-well line PW.

[0021] The control gate 210 may include a floating terminal 213 and a control terminal 214. The control terminal 214 may be coupled to a control line CL. The floating terminal 213 may be coupled to the floating gate terminal 223 of the state transistor 220. See below for reference. Figure 5A In a further detailed description, the control gate 210 may include a capacitor extending from a first polysilicon layer forming the floating terminal 213 across the control gate dielectric layer and to a second polysilicon layer forming the control terminal 214. For the purposes of this disclosure, the term "polysilicon layer" or "layer of polysilicon" may also be referred to as "poly layer" or "layer of poly". The first polysilicon layer may be a shared polysilicon layer for both the floating terminal 213 of the control gate 210 and the floating gate terminal 223 of the state transistor 220. Thus, by means of two terminals formed from a shared first polysilicon layer, the floating terminal 213 of the control gate 210 may be coupled to the floating gate terminal 223 of the state transistor 220.

[0022] See below for reference. Figure 5A As described in further detail, the control gate dielectric layer may include a high-k dielectric layer. The high-k dielectric layer may have a higher dielectric constant than, for example, silicon dioxide. The high-k dielectric layer can thus increase the capacitance on the control gate 210 and improve the capacitive coupling between the control terminal 214 and the floating terminal 213. This improved capacitive coupling between the control terminal 214 and the floating terminal 213 can thus reduce the impact on write and erase operations (such as those described in the reference below). Figure 3The voltage required to induce Fowler-Nordheim tunneling on the control gate 210 during the operations described. This reduced voltage further reduces the stress on the control gate 210 and state transistor 220 during write and erase operations, thereby improving the reliability of the NVM bit cell 200. Additionally, reducing the voltage required to induce Fowler-Nordheim tunneling provides the further advantage of reducing the size and complexity of the supply circuitry (such as charge pumps and / or high-voltage logic circuitry) needed to generate the necessary voltage levels.

[0023] State transistor 220 may include a source terminal 221 coupled to the source line SL and a drain terminal 222 coupled to the intermediate node 250. State transistor 220 may also include a floating gate terminal 223 coupled to a floating terminal 213 of the control gate 210. The gate of state transistor 220 may be implemented using a state transistor tunnel oxide layer located beneath a shared polysilicon layer forming both the floating terminal 213 of the control gate 210 and the floating gate terminal 223 of state transistor 220. As described further in detail below, state transistor 220 may be formed in a well region (e.g., a p-well region). In embodiments where the well region is a p-well region, state transistor 220 may be an n-type metal-oxide-semiconductor field-effect transistor (“N-type MOSFET” or “NMOS transistor”) and may therefore be referred to as an NMOS state transistor. Furthermore, in such embodiments, state transistor 220 may include a body terminal 224 coupled to the p-well line PW.

[0024] Access transistor 230 may be coupled in series with state transistor 220. For example, access transistor 230 may include a source terminal 231 coupled to the drain terminal 222 of state transistor 220 at intermediate node 250. Access transistor 230 may also include a drain terminal 232 coupled to bit line BL and a gate terminal 233 coupled to access line AL. Similar to state transistor 220, the gate of access transistor 230 may be implemented using a tunnel oxide layer located beneath the polysilicon layer forming gate terminal 233. As described further in detail below, access transistor 230 may be formed together with state transistor 220 in a well region (e.g., a p-well region). In embodiments where the well region is a p-well region, access transistor 230 may be an NMOS transistor and may therefore be referred to as an NMOS access transistor. Furthermore, in such embodiments, access transistor 230 may include a body terminal 234 coupled to p-well line PW.

[0025] Figure 3 This is a diagram illustrating the operating conditions of the NVM bit cell 200 according to an embodiment of this disclosure. (See diagram for example.) Figure 2 As shown, the p-well line PW of the NVM bit cell 200 can be coupled to the source line SL. Therefore, in Figure 3The diagram does not include the p-well line PW separately. As described directly below, the state transistor 220 and the control gate 210 can be jointly configured to perform erase and write operations using Fowler-Nordheim tunneling.

[0026] To perform the erase operation, the bit line BL can be set to high impedance, such as... Figure 3 The "Z" in the figure represents this. For example, any other external connection to the bit line BL can be disconnected, resulting in an open-circuit high-impedance condition on the bit line BL. A programming voltage VPP can be applied to the access line AL and the source line SL. See the reference above. Figure 2 As described, the p-well line PW can be coupled to the source line SL. Therefore, by applying, for example, a 10-volt VPP to the source line SL, the same programming voltage VPP can be applied to the p-well line PW. Furthermore, a nominal voltage, for example, 0 volts, can be applied to the control line CL. The programming voltage VPP can be, for example, 10 volts, or any other voltage higher than that applied to the control line CL suitable for inducing Fowler-Nordheim tunneling, as described directly below.

[0027] When a nominal voltage of 0 volts is applied to the p-well line PW, for example, 10 volts (VPP), and the control line CL, a large voltage drop can cause electron tunneling across the state transistor tunnel oxide layer of state transistor 220 and the control gate dielectric layer of control gate 210. See below for reference. Figures 5A to 5C As described, the first gate capacitance on the control gate dielectric layer of control gate 210 may be greater than the second gate capacitance on the state transistor tunnel oxide layer of state transistor 220. Therefore, during an erase operation, the first gate capacitance of control gate 210 may have a greater influence than the second gate capacitance of state transistor 220 on the amount of charge stored on the shared polysilicon layer forming the floating terminal 213 of control gate 210 and the floating gate terminal 223 of state transistor 220. Consequently, due to the erase operation, the first gate capacitance of control gate 210 may also have a greater influence than the second gate capacitance of state transistor 220 on the resulting voltages at the floating terminal 213 of control gate 210 and the floating gate terminal 223 of state transistor 220. For example, in an embodiment where the first gate capacitance of the control gate 210 is four times larger than the second gate capacitance of the state transistor 220, applying a nominal voltage of 10 volts VPP to the source line SL (and therefore to the p-well line PW) and 0 volts to the control line CL can provide charge accumulation at the shared polysilicon layer forming the floating terminal 213 and the floating gate terminal 223, thereby generating an erase state voltage of approximately 2 volts. When the erase operation voltage is removed from the p-well line PW and the control line CL, the charge accumulated at the shared polysilicon layer forming the floating terminal 213 and the floating gate terminal 223 can be retained and therefore used to detect the erase state during subsequent read operations.

[0028] As described above, a programming voltage VPP can also be applied to the access line AL during the erase operation. When VPP is also applied to the source line SL and the p-well line PW, applying VPP to the access line AL during the erase operation prevents unwanted stress from being applied to the gate of the access transistor 230 during the erase operation.

[0029] To perform a write operation, the bit line BL can be set to high impedance, such as... Figure 3 The "Z" in the figure represents this. For example, any other external connection to the bit line BL can be disconnected, resulting in an open-circuit high-impedance condition on the bit line BL. A nominal voltage, such as 0V, can be applied to the access line AL and the source line SL. (See above reference.) Figure 2 As described, the p-well line PW can be coupled to the source line SL. Therefore, by applying a nominal voltage, such as 0V, to the source line SL, the same nominal voltage can be applied to the p-well line PW. Furthermore, a programming voltage VPP can be applied to the control line CL. The programming voltage VPP can be, for example, 10 volts, or any other voltage higher than that applied to the p-well line PW suitable for inducing Fowler-Nordheim tunneling, as directly described below.

[0030] For example, when a nominal voltage of 0 volts is applied to the p-well line PW and a 10-volt VPP is applied to the control line CL, a large voltage drop can cause electron tunneling on the control gate dielectric layer of the control gate 210 and the state transistor tunnel oxide layer of the state transistor 220. See below for reference. Figures 5A to 5CAs described, the first gate capacitance on the control gate dielectric layer of control gate 210 may be greater than the second gate capacitance on the state transistor tunnel oxide layer of state transistor 220. Therefore, during a write operation, the first gate capacitance of control gate 210 may have a greater influence than the second gate capacitance of state transistor 220 on the amount of charge stored on the shared polysilicon layer forming the floating terminal 213 of control gate 210 and the floating gate terminal 223 of state transistor 220. Consequently, due to the write operation, the first gate capacitance of control gate 210 may also have a greater influence than the second gate capacitance of state transistor 220 on the resulting voltage at the floating terminal 213 of control gate 210 and the floating gate terminal 223 of state transistor 220. For example, in an embodiment where the first gate capacitance of the control gate 210 is four times larger than the second gate capacitance of the state transistor 220, applying a nominal voltage of 10 volts VPP to the control line CL and 0 volts to the p-well line PW can provide charge accumulation at the shared polysilicon layer forming the floating terminal 213 of the control gate 210 and the floating gate terminal 223 of the state transistor 220, thereby generating a write state voltage of approximately 8 volts. When the write operation voltage is removed from the p-well line PW and the control line CL, the charge accumulated at the shared polysilicon layer forming the floating terminal 213 and the floating gate terminal 223 can be retained and therefore used to detect the write state during subsequent read operations.

[0031] As described above, a nominal voltage, such as 0V, can also be applied to the access line AL during a write operation. When the nominal voltage is also applied to the source line SL and the p-well line PW, applying the nominal voltage to the access line AL during an erase operation prevents unwanted stress from being applied to the gate of the access transistor 230 during a write operation.

[0032] After an erase or write operation, a read operation can be performed by turning on the access transistor 230, applying a drain-to-source voltage to the state transistor 220, and monitoring the current conducted by the state transistor 220. For a given drain-to-source voltage, the current conducted by the state transistor 220 can depend on the remaining charge accumulation at the shared polysilicon layer forming the floating terminal 213 and the floating gate terminal 223, and thus can indicate whether the NVM bit cell 200 is in an erase or write state.

[0033] For example, during a read operation, a nominal voltage of zero volts can be applied to the source line SL. A supply voltage VDD can be applied to the access line AL. In some embodiments, VDD can be, for example, 1.8 volts, or any other voltage suitable for turning on access transistor 230 and driving it to saturation. Additionally, a gate read voltage VGR can be applied to the control line. The gate read voltage VGR can be combined with the charge accumulated on the shared polysilicon layer forming floating terminals 213 and 223 to provide a bias voltage to the floating gate terminal 223 of the state transistor 220. For example, the gate read voltage VGR can be set to any suitable baseline voltage such that if the NVM bit cell 200 is in a write state before a read operation, the state transistor 220 can be biased to an on state, and if the NVM bit cell 200 is in an erase state before a read operation, the state transistor 220 can be biased to an off state. Furthermore, a drive voltage (VDR) can be applied to the bit line BL. The drive voltage VDR can be used to apply a drain-to-source voltage to the state transistor 220. In some embodiments, VDR may be equal to, for example, the VDD voltage of 1.8V. With VDR applied to the bit line BL, a nominal voltage of, for example, 0V applied to the source line SL, and the access transistor 230 driven in the on state, the amount of current conducted at the bit line BL can depend on the bias at the floating gate terminal 223 of the state transistor 220. Therefore, the amount of current conducted at the bit line BL can indicate whether the NVM bit cell 200 was last placed in an erase state or a write state before a read operation.

[0034] although Figure 3 The example voltage values ​​for the read operation shown list a nominal voltage of 0V for the source line SL and p-well line, and a positive voltage for the bit line BL and access line AL, but the same read operation can be achieved using alternative voltage values ​​with the same relative difference. For example, the bit line BL and access line AL can be placed at a nominal voltage of zero volts, while the source line SL and p-well line PW are placed at a negative voltage of, for example, -1.8 volts. In such embodiments, the gate read voltage VGR can be similarly adjusted such that if the NVM bit cell 200 is placed in a write state before the read operation, the state transistor 220 can be biased in an on state, and if the NVM bit cell 200 is placed in an erase state before the read operation, the state transistor 220 can be biased in an off state.

[0035] Furthermore, although the above embodiments involve tunneling during erase and write operations, allowing the state transistor 220 to be turned on during a read operation following a write operation and turned off during a read operation following an erase operation, the designation of "write" and "erase" can be toggled. For example, in an alternative embodiment, Figure 3The "erase" and "write" operations can be toggled on and off, allowing the state transistor 220 to be turned on during a read operation following an erase operation and turned off during a read operation following a write operation.

[0036] Figure 4 A top view of a semiconductor process region for a non-volatile memory (NVM) bit cell array according to an embodiment of the present disclosure is shown. Certain semiconductor process regions are referenced. Figure 4 The top view is described, and it can be used to manufacture elements of NVM bit cell 401. NVM bit cell 401 can represent the above reference. Figure 2 The described embodiment of the NVM bit cell 200 includes a control gate 210, a state transistor 220, and an access transistor 230. For example... Figure 4 As shown, a single instance of NVM bit cell 401 can be repeated in the array. Rows of the array can be formed by instances of NVM bit cells with similar orientations repeating from one side to the other, and columns of the array can be formed by instances of NVM bit cells with vertical orientation in a mirror manner.

[0037] like Figure 4 As shown, the semiconductor process region may include an active region 402, a contact region 404, a polysilicon region 410, an exclusion region 412, a first metal layer region 420, a via region 425, and a second metal layer region 430.

[0038] Active region 402 can be used to form a well in which access transistors and state transistors for each NVM bit cell can be formed. Active region 402 can also be used to form silicide on the active region of each bit cell, which can improve the conductivity from the contact to the underlying region. Furthermore, active region 402 can be used to delineate a channel isolation region. For example, in some embodiments, any region outside active region 402 may include a channel region.

[0039] Contact region 404 can be used to form contacts from the underlying active region or polysilicon region to the upper metal layer. For example, contact region 404a can be combined with first metal layer region 420 and via region 425a to couple the drain terminal of the access transistor of NVM bit cell 401 to a second metal layer region 430, which forms the bit line (BL-2) of the column where the NVM bit cell is located. As another example, contact region 404b can be used to couple the source terminal of the state transistor of NVM bit cell 401 to the first metal layer region 420, which forms the source line (SL-2) of the column where the NVM bit cell 401 is located.

[0040] Polysilicon region 410 can be used to pattern the first and second polysilicon layers. See below for reference. Figures 5A to 5C In further detail, the first polysilicon layer can be used to form the floating gate terminal of the state transistor of the NVM bit cell 401. Furthermore, the first and second polysilicon layers can be used to form the floating terminal and control terminal of the control gate of the NVM bit cell 401, respectively. The exclusion region 412 can also be used to pattern the first polysilicon layer. Specifically, the first polysilicon layer can be omitted from the region outside the exclusion region 412.

[0041] The first metal layer region 420 can be used to pattern a region of the first metal layer capable of coupling the NVM bit cell 401 to various lines. Similarly, the second metal layer region 430 can be used to pattern a region of the second metal layer that is located above the first metal layer and can also be used to couple the NVM bit cell 401 to various lines. The via region 425 can be used to form a via between the different patterned regions of the first and second metal layers.

[0042] like Figure 4 As shown, a single instance of NVM bit cell 401 can be repeated in an array with multiple rows and columns. Instances of NVM bit cells in the same row or column can share various lines. For example, NVM bit cells in the first column can share the first bit line BL-1 and the first source line SL-1. Similarly, NVM bit cells in the second column can share the second bit line BL-2 and the second source line SL-2. Furthermore, NVM bit cells in the third column can share the third bit line BL-3 and the third source line SL-3. As another example, NVM bit cells in the first row can share the first access line AL-1 and the first control line CL-1. Similarly, NVM bit cells in the second row can share the second access line AL-2 and the second control line CL-2. Furthermore, NVM bit cells in the third row can share the third access line AL-3 and the third control line CL-3. Additionally, NVM bit cells in the fourth row can share the fourth access line AL-4 and the fourth control line CL-4.

[0043] Although Figure 4 An NVM bit cell array with three columns and four rows is shown, but an NVM bit cell array can be formed with any suitable number of NVM bit cells. For example, instances of NVM bit cells 401 can be repeated to form any number of rows and columns, thereby forming an NVM bit cell array of any size suitable for the application of integrated circuit 100, such as NVM bit cell array 102. See below for reference. Figure 5CAs described in further detail, certain portions of the active region can be used to couple the wells of the body terminals of the state transistors and access transistors to the source line SL. For example, active region 402a can be used to form a highly doped region adapted to couple the wells of the state transistors and access transistors therein to the source line SL. When instances of NVM bit cells are repeated vertically to form a column, active region 402a can be repeated at regular intervals within that column to ensure adequate contact between the wells of the body terminals of the state transistors and access transistors for a given row and the source line SL.

[0044] Figures 5A to 5C A cross-sectional view of an array of non-volatile memory bit cells according to an embodiment of the present disclosure is shown.

[0045] Figure 5A It shows the corresponding Figure 4 The section line 5A is shown in the cross-sectional view, specifically along the control line (CL-2) for the second row of NVM bit cells. Therefore, Figure 5A Cross-sections of the control gate and state transistors of NVM bit cell 401 and other NVM bit cells in the same row are shown.

[0046] like Figure 5A As shown, the NVM bit cell 401 can be formed on a semiconductor substrate including an epitaxial layer. For example, the epitaxial layer 502 can be disposed on the semiconductor substrate or can be grown separately on the semiconductor substrate. In some embodiments, the semiconductor substrate can be a p-type semiconductor substrate, and the epitaxial layer 502 can be a p-type epitaxial layer. A deep well 504 can be formed in the epitaxial layer 502. The deep well 504 can have a conductivity type opposite to that of the epitaxial layer 502. For example, in an embodiment where the epitaxial layer 502 is a p-type epitaxial layer, the deep well 504 can be an n-type deep well. And in an embodiment where the epitaxial layer 502 is an n-type epitaxial layer, the deep well 504 can be a p-type deep well.

[0047] NVM bit cell 401 may include a well region in which state transistors and access transistors may be formed. For example, NVM bit cell 401 may include well region 506. Figure 5A As shown, the well region 506 can be located within the deep well 504. Similarly, as... Figure 5A As shown, deep well 504 may have a deeper well than the well depth of well region 506. Well region 506 may have a conductivity type opposite to that of deep well 504. For example, in an embodiment where deep well 504 is an n-type deep well, well region 506 may be a p-well region. In such embodiments, the state transistor may be an NMOS transistor and the access transistor may be an NMOS transistor. In other embodiments where deep well 504 is a p-type deep well, well region 506 may be an n-well region. In such embodiments, the state transistor may be a PMOS transistor and the access transistor may be a PMOS transistor.

[0048] NVM bit cell 401 may further include one or more channel regions 508. In some embodiments, channel region 508 may have a channel depth greater than or equal to the well depth of well region 506. Thus, the well region of a first NVM bit cell (such as well region 506 of NVM bit cell 401) may be isolated from the well regions 506n of adjacent NVM bit cells in the same row of the NVM bit cell array via channel region 508. In some embodiments, and depending on the lateral distance between well region 506 and adjacent well region 506n, the channel depth of channel region 508 may be nominally less than the well depth of well region 506 to such an extent that the channel depth and lateral distance between well region 506 and adjacent well region 506n are sufficient to electrically isolate well region 506 and adjacent well region 506n.

[0049] like Figure 5A As shown, the NVM bit cell 401 may include a tunnel oxide layer 520. In some embodiments, the tunnel oxide layer 520 may be grown on an exposed region of the well region 506. The tunnel oxide layer 520 may thus form the dielectric for the gate of the state transistor of the NVM bit cell 401. Furthermore, for the purposes of this disclosure, the portion of the tunnel oxide layer 520 forming the gate of the state transistor may also be referred to as the state transistor tunnel oxide layer. Additionally, a first polysilicon layer 530 may be formed on the tunnel oxide layer 520. Figure 5A As shown, the first polysilicon layer 530 can be patterned such that the portion of the first polysilicon layer 530 located within the NVM bit cell 401 can be isolated from the portion of the first polysilicon layer 530 located within the adjacent NVM bit cell.

[0050] A control gate dielectric layer 540 may be formed on the first polysilicon layer 530. For example... Figure 5A As shown, the control gate dielectric layer 540 can be formed continuously, spanning NVM bit cells 401 and adjacent NVM bit cells, from spacer 532 at one end of the row to spacer 532 at the other end of the row. The control gate dielectric layer 540 may include a high-k dielectric layer 541. The high-k dielectric layer 541 can be formed using any suitable dielectric material with a dielectric constant greater than that of silicon dioxide. For example, the high-k dielectric layer can be formed using one or more layers of any one or more of hafnium oxide, aluminum oxide, and / or tantalum oxide. In some embodiments, the control gate dielectric layer 540 may also include at least one silicon dioxide layer. For example, as Figure 5A As shown, the control gate dielectric layer 540 may include a first silicon dioxide layer 542a on the first side of the high-K dielectric layer 541 and a second silicon dioxide layer 542b on the second side of the high-K dielectric layer 541.

[0051] The second polysilicon layer 550 may be formed on the control gate dielectric layer 540. The second polysilicon layer 550 can be formed continuously, spanning NVM bit cells 401 and adjacent NVM bit cells, from the spacer 532 at one end of the row to the spacer 532 at the other end of the row. And as... Figure 5A As shown, silicide 552 can be formed on top of the second polysilicon layer 550. As described above, silicide 552 can improve the contact between the second polysilicon layer 550 and the metal layer included above for signal routing (in... Figure 5A Conductivity (not shown in the cross-sectional slice).

[0052] The various layers described above can be added to the semiconductor substrate to form the state transistor and control gate of the NVM bit cell 401. For example, the state transistor may include a floating gate terminal formed by the first polysilicon layer 530 and coupled to a floating terminal of the control gate. The state transistor may also include a tunnel oxide layer 520 formed between the first polysilicon layer 530 and the active region of the state transistor in the well region 506.

[0053] The control gate may include a floating terminal formed by a first polysilicon layer 530. The first polysilicon layer 530 may be a shared polysilicon layer that forms both the floating terminal of the control gate and the floating gate terminal of the state transistor. Therefore, by means of two terminals formed from the same shared portion of the first polysilicon layer 530, the floating terminal of the control gate can be coupled to the floating gate terminal of the state transistor. The control gate may also include a control terminal formed by a second polysilicon layer 550.

[0054] Additionally, the control gate may include a control gate dielectric layer 540 formed between the first polysilicon layer 530 and the second polysilicon layer 550. As described above, the control gate dielectric layer 540 may include a high-k dielectric layer 541. The high-k dielectric layer may have a higher dielectric constant than, for example, silicon dioxide. The high-k dielectric layer can thus increase the capacitance on the control gate and improve the capacitive coupling between the control terminal formed by the second polysilicon layer 550 and the floating terminal formed by the first polysilicon layer 530.

[0055] Improved capacitive coupling reduces the impact of write and erase operations (as mentioned in the reference above). Figure 3The voltage required to induce Fowler-Nordheim tunneling on the control gate during the operations described. The reduced voltage, in turn, reduces the stress induced by the control gate and state transistors during write and erase operations, thereby improving the reliability of the NVM bit cell 401. Specifically, the reduced stress induced by the control gate and state transistors during write and erase operations allows the NVM bit cell 401 to operate reliably through numerous write or erase cycles and under harsh environmental conditions. For example, the NVM bit cell 401 can maintain operation for more than one million write and / or erase cycles at temperatures, for example, 175 degrees Celsius. Furthermore, compared to, for example, monocrystalline or polycrystalline NVM bit cells, improved reliability can be achieved with smaller area consumption and therefore lower manufacturing costs.

[0056] like Figure 5A As shown, the NVM bit cell 401 may further include an oxide 560, a first metal layer 561, and a second metal layer 562. The first metal layer 561 may be as described above. Figure 4 The first metal layer region 420 is patterned as described above. Similarly, the second metal layer 562 can be patterned according to the same reference above. Figure 4 The second metal layer region 430 is described as patterned. The first metal layer 561 and the second metal layer 562 can be used to route various signals associated with the NVM bit cell 401 and adjacent NVM bit cells. For example, as... Figure 5A As shown, the first metal layer 561 can be used to route the source line (SL-2) of the second column where the NVM bit cell 401 is located. Furthermore, the second metal layer 562 can be used to route the bit line (BL-2) of the second column where the NVM bit cell 401 is located. Other patterned portions of the first metal layer 561 and the second metal layer 562 corresponding to adjacent NVM bit cells can similarly be used to route the source lines (SL-1 and SL-3) and bit lines (BL-1 and BL-3) of adjacent NVM bit cells in adjacent first and third columns.

[0057] Figure 5B It shows the corresponding Figure 4 The section line 5B is shown in the cross-sectional view, specifically along the access line (AL-2) for the second row of NVM bit cells. Therefore, Figure 5B The cross-section of the access transistor for NVM bit cell 401 and other NVM bit cells in the same row is shown.

[0058] like Figure 5B As shown, the access transistor can be formed in the reference above. Figure 5A The described state transistor is located in the same well region 506. Furthermore, as referenced above... Figure 5AAs described, the tunnel oxide layer 520 can be grown on the exposed region of the well region 506. The tunnel oxide layer 520 can thus form the dielectric of the gate of the access transistor for the NVM bit cell 401. Furthermore, for the purposes of this disclosure, the portion of the tunnel oxide layer 520 forming the gate of the access transistor can also be referred to as the access transistor tunnel oxide layer.

[0059] A first polysilicon layer 530 may be formed on the tunnel oxide layer 520. Therefore, the first polysilicon layer 530 may form the gate terminal of the access transistor of the NVM bit cell 401. For example... Figure 5B As shown, the first polysilicon layer 530 can be formed continuously, spanning NVM bit cells 401 and adjacent NVM bit cells, from spacer 532 at one end of the row to spacer 532 at the other end of the row. The first polysilicon layer 530 can be used to route access lines (AL-2) of NVM bit cells 401 and other NVM bit cells located in the same second row as NVM bit cells 401. For example, contact 534 can couple the first polysilicon layer 530 to a patterned portion of the first metal layer 561 forming the access line (AL-2).

[0060] Figure 5C It shows the corresponding Figure 4 The section line 5C is shown in the cross-sectional view, specifically along the bit line (BL-2) of the second column for NVM bit cells. Therefore, Figure 5C Cross-sections of the control gate and access gate of NVM bit cell 401 and other NVM bit cells in the same column are shown.

[0061] like Figure 5C As shown, well region 506 can be shared by a first NVM bit cell (such as NVM bit cell 401) and one or more adjacent NVM bit cells in the same column. Furthermore, different doping methods can be used to form the active regions of the state transistor and access transistor. For example, heavily doped region 505 can be formed using heavy doping of the same conductivity type as the well region. For example, in an embodiment where well region 506 is a p-type well region, heavily doped region 505 can also be a p-type well region with heavier doping than well region 506. Heavily doped region 505 can therefore help provide a low-resistance contact between well region 506 (which forms the body terminals of the state transistor and access transistor of NVM bit cell 401) and the source line (SL-2) of the second column where NVM bit cell 401 is located.

[0062] Additional doping of opposite conductivity types can be added to form the source and drain terminals of the state transistor and access transistor. For example, a low doping level can be applied to form a low-doped region 507 by using one or both of the first polysilicon layer 530 and the second polysilicon layer 550 as a mask. After the subsequent formation of the spacer 532, a heavy doping level can be applied to form a heavily doped region 509. The low-doped region 507 and the heavily doped region 509 may have a conductivity type opposite to that of the well region 506. For example, in an embodiment where the well region 506 is a p-type well region, the low-doped region and the heavily doped region 509 may be n-type doped regions. In such embodiments, the state transistor and access transistor may be NMOS transistors, and the n-type low-doped region 507 and the heavily doped region 509 may form the source and drain terminals of the NMOS access transistor and the NMOS state transistor. For example, the heavily doped region 509a and the low-doped region 507a may together form the source terminal of the access transistor of the NVM bit cell 401. Furthermore, the heavily doped region 509b and the lightly doped region 507b can together form the drain terminal of the access transistor of the NVM bit cell 401. Additionally, the lightly doped region 507c can form both the drain terminal of the state transistor and the source terminal of the access transistor of the NVM bit cell 401. In some embodiments, Figure 5C Another heavily doped region 509, not shown, can be combined with the lightly doped region 507c to jointly form the drain terminal of the state transistor and the source terminal of the access transistor. For example, spacer 532 can act as a mask for the heavy doping of the heavily doped region 509. Therefore, in an embodiment where the gates of the state transistor and the access transistor are further dispersed such that the spacers between the state transistor and the access transistor do not overlap, an additional heavily doped region 509 can be formed centered within the lightly doped region 507c.

[0063] Silicide 552 may be formed on top of the second polysilicon layer 550 and on top of the heavily doped region 509. Silicide 552 may improve the conductivity of the features below the contact 534 to the NVM bit cell 401 (such as the source and drain terminals of the state transistor and access transistor, which are partially formed by the heavily doped region 509).

[0064] like Figure 5C As shown, contact 534a can couple a portion of the first metal layer 561 forming the source lines (SL-2) of the second column to a heavily doped region 509a, which partially forms the source terminal of the state transistor of the NVM bit cell 401. Another contact 534b can couple a portion of a portion of the first metal layer 561 forming the bit lines (BL-2) of the second column to a heavily doped region 509b, which partially forms the drain terminal of the access transistor of the NVM bit cell 401. Similarly... Figure 5CAs shown, the via 563 can be used to couple a portion of the first metal layer 561 to a portion of the second metal layer 562. For example, as Figure 5C As shown in the cross-sectional slice, via 563a can couple a portion of the first metal layer 561 to a portion of the second metal layer 562, which is designated for routing bit lines (BL-2) of the second column of the NVM bit cell array.

[0065] Given a mirrored and repeated arrangement, different instances of an NVM bit cell (such as NVM bit cell 401) can share a common well region 506. For example, as referenced above. Figures 5A to 5C As described, the well region 506 of NVM bit cell 401 can be isolated from the well regions 506n of adjacent NVM bit cells in the same row but different columns via channel region 508. However, the well region 506 of NVM bit cell 401 can be shared with other adjacent NVM bit cells in different rows located in the same column. Furthermore, certain lines (such as access lines AL, control lines CL, source lines SL, and bit lines BL) can be shared by multiple instances of NVM bit cells (such as NVM bit cell 401) located in the same row or column. Therefore, refer to the following... Figure 6 The various controls described herein can be applied to an instance of NVM bit cell 401, not only erasing, writing, and reading that particular instance of NVM bit cell 401, but also preventing that instance from changing state when other bit cells in the same row or column may undergo erasure or write operations.

[0066] Figure 6 This is a diagram illustrating the operating conditions of an NVM bit cell according to an embodiment of the present disclosure. Figure 6 The above reference is shown as an example. Figures 5A to 5C The operation of the described NVM bit cell (such as NVM bit cell 401) when included in an array having other instances of NVM bit cells that repeat in rows and columns. See above reference. Figure 2 As described, the p-well line PW of the NVM bit cell can be coupled to the source line SL. Therefore, in Figure 6 The diagram does not include the p-well line PW separately. Furthermore, the text refers to the single bit line BL, source line SL, control line CL, and access line AL, rather than specifying such lines for each row and column in different rows and columns.

[0067] For an erase operation, when both the row and column of the NVM bit cell are selected, the erase operation can be performed by applying a high impedance to the bit line BL, a programming voltage VPP to the access line AL and the source line SL, and a nominal voltage, such as 0 volts, to the control line CL. The programming voltage VPP can be, for example, 10 volts, or any other voltage higher than that applied to the control line CL suitable for inducing Fowler-Nordheim tunneling, as referenced above. Figure 2 As described.

[0068] When a row is selected instead of a column for an erase operation, a high impedance can be applied to the bit line BL, a programming voltage VPP can be applied to the access line AL, and a nominal voltage, such as 0 volts, can be applied to the control line CL. Furthermore, to prevent unwanted interference to the NVM bit cells, a suppressor voltage Vinh can be applied to the source line SL. In some embodiments, the suppressor voltage Vinh applied to the source line SL can be set to ensure that the difference between the source line SL and the access line AL does not exceed the voltage capability of the gate dielectric of the access transistor 230. The suppressor voltage also ensures that the difference between the source line SL and the control line CL does not exceed, for example, 5 volts, thereby ensuring prevention or reduction of unwanted tunneling. Conversely, when a column is selected instead of a row for an erase operation, a high impedance can be applied to the bit line BL, and a programming voltage VPP can be applied to each of the access line AL, the control line CL, and the source line SL. Finally, when neither column nor row is selected for the erase operation, a high impedance can be applied to the bit line BL, a programming voltage VPP can be applied to the access line AL and the control line CL, and a suppressor voltage Vinh can be applied to the source line to prevent interference with other NVM bit cells in the same column. In some embodiments, the suppressor voltage Vinh applied to the source line SL can be set to ensure that the difference between the source line SL and the access line AL does not exceed the voltage capability of the gate dielectric of the access transistor 230. The suppressor voltage Vinh also ensures that the difference between the control line CL and the source line SL does not exceed, for example, 5 volts, thereby ensuring prevention or reduction of unwanted tunneling.

[0069] For a write operation, when both the row and column of the NVM bit cell are selected, the write operation can be performed by applying a high impedance to the bit line BL, a programming voltage VPP to the control line, and a nominal voltage, such as 0 volts, to the access and source lines. The programming voltage VPP can be, for example, 10 volts, or any other voltage higher than the voltage applied to the source line SL suitable for inducing Fowler-Nordheim tunneling, as referenced above. Figure 2 As described.

[0070] When a row is selected instead of a column for a write operation, a high impedance can be applied to the bit line BL, a programming voltage VPP can be applied to the control line CL, and a nominal voltage, such as 0 volts, can be applied to the access line AL. Furthermore, to prevent unwanted interference to the NVM bit cells, a suppressor voltage Vinh can be applied to the source line SL. In some embodiments, the suppressor voltage Vinh applied to the source line SL can be set to ensure that the difference between the source line SL and the access line AL does not exceed the voltage capability of the gate dielectric of the access transistor 230. The suppressor voltage Vinh also ensures that the difference between the control line CL and the source line SL does not exceed, for example, 5 volts, thereby ensuring prevention or reduction of unwanted tunneling. Conversely, when a column is selected instead of a row for a write operation, a high impedance can be applied to the bit line BL, and a nominal voltage, such as 0 volts, can be applied to each of the access line AL, the control line CL, and the source line SL. Finally, when neither column nor row is selected for a write operation, a high impedance can be applied to the bit line BL, a nominal voltage of, for example, 0 volts can be applied to the access line AL and the control line CL, and a suppressor voltage Vinh can be applied to the source line to prevent interference with other NVM bit cells in the same column. In some embodiments, the suppressor voltage Vinh applied to the source line SL can be set to ensure that the difference between the source line SL and the access line AL does not exceed the voltage capability of the gate dielectric of the access transistor 230. The suppressor voltage Vinh also ensures that the difference between the source line SL and the control line CL does not exceed, for example, 5 volts, thereby ensuring prevention or reduction of unwanted tunneling.

[0071] For a read operation, the operation can be performed by turning on the access transistor, applying a drain-to-source voltage to the status transistor, and monitoring the current conducted by the status transistor. For example, when selecting both the row and column of an NVM bit cell for a read operation, a drive voltage VDR can be applied to the bit line BL, a nominal voltage such as 0 volts can be applied to the source line, a supply voltage VDD can be applied to the access line, and a gate read voltage VGR can be applied to the control line. The current conducted by the status transistor for a given drain-to-source voltage indicates whether the NVM bit cell is in an erase or write state.

[0072] When a row is selected instead of a column for a read operation, a supply voltage VDD can be applied to the access line, a gate read voltage VGR can be applied to the control line, and a nominal voltage of, for example, 0 volts can be applied to both the bit line BL and the source line SL. Conversely, when a column is selected instead of a row for a read operation, a drive voltage VDR can be applied to the bit line BL, but a nominal voltage of, for example, 0 volts can be applied to each of the access line AL, the control line CL, and the source line SL. Finally, when neither a row nor a column is selected for a read operation, a nominal voltage of, for example, 0 volts can be applied to each of the bit line BL, the access line AL, the control line CL, and the source line SL.

[0073] Figure 7 A method 700 for manufacturing non-volatile memory (NVM) bit cells according to an embodiment of this disclosure is shown. Method 700 can be performed by any suitable mechanism. Method 700 is available in... Figure 7 The method can be executed in fewer or more steps. Furthermore, steps in method 700 can be omitted, repeated, executed in parallel, or combined with... Figure 7 The steps of method 700, though shown in order, may be executed in a different order or recursively. One or more steps of method 700, although shown in order, may be executed simultaneously or in a reordered manner. As a result, in contrast to... Figure 7 As an example of sequentially executing steps with different orders, step 704 may be executed before step 702. And as an example of parallel execution steps, steps 706 and 708 may be executed at least partially in parallel with each other during the same semiconductor process steps.

[0074] Step 702 may include forming a well region. For example, such as... Figures 5A to 5C As shown, the well region 506 can be formed in the deep well 504.

[0075] Step 704 may include forming a channel region that is adjacent to the well region on at least one side and has a channel depth greater than or equal to the well depth. For example, as Figure 5A and Figure 5B As shown, the channel region 508 may be formed in the deep well 504 and may be adjacent to the well region 506 on at least one side. In addition, the channel region 508 may be formed with a channel depth greater than or equal to the well depth of the well region 506.

[0076] Step 706 may include forming an access transistor in the well region. For example, as referenced above. Figure 5B As described, the access transistor of the NVM bit cell 401 may be formed in the same well region 506 as the state transistor of the NVM bit cell 401.

[0077] Step 708 may include forming a state transistor in the well region, the state transistor having a floating gate terminal formed of a first polysilicon layer. For example, as Figure 5A As shown, the state transistor of the NVM bit cell 401 may be formed in the well region 506. Furthermore, the state transistor may have a floating gate terminal formed from a first polysilicon layer 530.

[0078] Step 710 may include forming a control gate having a floating terminal formed of a first polysilicon layer, a control terminal formed of a second polysilicon layer, and a control gate dielectric disposed between the first and second polysilicon layers and including a high-k dielectric layer. For example, as referenced above. Figure 5AAs described, the floating terminal of the control gate may be formed by a first polysilicon layer 530. Furthermore, the control terminal of the control gate may be formed by a second polysilicon layer 550. The control gate may include a control gate dielectric layer 540 disposed between the first polysilicon layer 530 and the second polysilicon layer 550. The control gate dielectric layer 540 may include a high-k dielectric layer 541. In some embodiments, the control gate dielectric layer 540 may have a first silicon dioxide layer 542a on a first side of the high-k dielectric layer 541 and a second silicon dioxide layer 542b on a second side of the high-k dielectric layer 541.

[0079] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A non-volatile memory NVM bit cell, the NVM bit cell comprising: Control gate, the control gate comprising: A floating terminal, wherein the floating terminal is formed of a first polysilicon layer; Control terminals, the control terminals being formed of a second polysilicon layer; and A control gate dielectric layer is formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-k dielectric layer; State transistor, the state transistor comprising: A floating gate terminal, the floating gate terminal being formed of the first polysilicon layer and coupled to the floating terminal of the control gate; and A tunnel oxide layer, the tunnel oxide layer being formed between the first polysilicon layer and the active region of the state transistor; and An access transistor, wherein the access transistor is connected in series with the state transistor.

2. The NVM bit unit according to claim 1, wherein the NVM bit unit further comprises: A well region, wherein the state transistor and the access transistor are formed; and A channel region having a channel depth greater than or equal to the well depth of the well region.

3. The NVM bit cell according to claim 2, wherein: The well region is a p-well region; and The state transistor and the access transistor are NMOS transistors.

4. The NVM bit cell according to claim 2, wherein: The well region is located in a deep well; and The well region has the opposite conductivity type to the deep well.

5. The NVM bit cell of claim 1, wherein the state transistor and the control gate are configured to perform erase and write operations using Fowler-Nordheim tunneling.

6. The NVM bit cell according to claim 1, wherein the control gate dielectric layer further comprises at least one silicon dioxide layer.

7. The NVM bit cell according to claim 1, wherein the control gate dielectric layer further comprises a first silicon dioxide layer on a first side of the high-k dielectric layer and a second silicon dioxide layer on a second side of the high-k dielectric layer.

8. An integrated circuit, the integrated circuit comprising: Logic blocks; and A non-volatile memory (NVM) bit cell array, coupled to the logic block, the NVM bit cell array comprising multiple NVM bit cells arranged in multiple rows and columns, each NVM bit cell comprising: Control gate, the control gate comprising: A floating terminal, wherein the floating terminal is formed of a first polysilicon layer; Control terminals, the control terminals being formed of a second polysilicon layer; and A control gate dielectric layer is formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-k dielectric layer; State transistor, the state transistor comprising: A floating gate terminal, the floating gate terminal being formed of the first polysilicon layer and coupled to the floating terminal of the control gate; and A tunnel oxide layer, the tunnel oxide layer being formed between the first polysilicon layer and the active region of the state transistor; and An access transistor, wherein the access transistor is connected in series with the state transistor.

9. The integrated circuit of claim 8, wherein each NVM bit cell further comprises: A well region, wherein the state transistor and the access transistor are formed; and A channel region having a channel depth greater than or equal to the well depth of the well region.

10. The integrated circuit according to claim 9, wherein: The well region is a p-well region; and The state transistor and the access transistor are NMOS transistors.

11. The integrated circuit according to claim 9, wherein: The well region is located in a deep well; and The well region has the opposite conductivity type to the deep well.

12. The integrated circuit of claim 9, wherein the well region is shared by a first NVM bit cell and one or more adjacent NVM bit cells located in the same column.

13. The integrated circuit of claim 9, wherein the well region of the first NVM bit cell is isolated from the well regions of adjacent NVM bit cells located in the same row via the channel region.

14. The integrated circuit of claim 8, wherein the state transistor and the control gate are configured together to perform erase and write operations using Fowler-Nordheim tunneling.

15. The integrated circuit of claim 8, wherein the control gate dielectric layer further comprises at least one silicon dioxide layer.

16. The integrated circuit of claim 8, wherein the control gate dielectric layer further comprises a first silicon dioxide layer on a first side of the high-k dielectric layer and a second silicon dioxide layer on a second side of the high-k dielectric layer.

17. A method, the method comprising: Formation of a trap region; An access transistor is formed in the well region; A state transistor is formed in the well region, the state transistor having a floating gate terminal formed of a first polysilicon layer; A control gate is formed, the control gate having a floating terminal formed by a first polysilicon layer, a control terminal formed by a second polysilicon layer, and a control gate dielectric layer disposed between the first polysilicon layer and the second polysilicon layer and including a high-k dielectric layer.

18. The method of claim 17, further comprising forming a channel region adjacent to the well region on at least one side and having a channel depth greater than or equal to the well depth of the well region.

19. The method of claim 17, wherein the control gate dielectric layer is formed with a first silicon dioxide layer on a first side of the high-k dielectric layer and a second silicon dioxide layer on a second side of the high-k dielectric layer.

20. The method of claim 17, wherein the state transistor and the control gate are configured together to perform erase and write operations using Fowler-Nordheim tunneling.

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