Bandgap reference source circuit

Abstract

This invention relates to the field of wireless communication technology and provides a bandgap reference source circuit. The bandgap reference source circuit includes a first gain enhancement circuit, a second gain enhancement circuit, a third gain enhancement circuit, an operational amplifier, a first voltage sampling circuit, a second voltage sampling circuit, a third voltage sampling circuit, and a buffer circuit. The first voltage sampling circuit controls the output gain of the first gain enhancement circuit based on a bias voltage. The second voltage sampling circuit controls the output gain of the second gain enhancement circuit based on a bias voltage. The third voltage sampling circuit controls the output gain of the third gain enhancement circuit based on a bias voltage. The operational amplifier receives the gain output from the second gain enhancement circuit through its non-inverting input and amplifies it in-phase before outputting an enhanced gain signal. The operational amplifier also receives the gain output from the first gain enhancement circuit through its inverting input. This bandgap reference source circuit can improve the voltage rejection ratio of high-frequency power supplies.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a bandgap reference source circuit. Background Technology

[0002] Bandgap reference sources are core foundational modules in analog integrated circuits and mixed-signal systems. Their key performance indicators, such as output voltage temperature stability, power supply rejection ratio (PSRR), and accuracy, directly determine the overall performance of electronic systems including digital-to-analog converters (DACs), analog-to-digital converters (ADCs), low-dropout regulators (LDOs), and RF transceivers. With the evolution of semiconductor processes and the expansion of electronic device applications, portable, low-power, and high-precision electronic devices place higher demands on the performance of bandgap reference sources. In particular, the voltage rejection ratio (PSRR), as a core parameter for measuring a reference source's ability to suppress power supply noise, directly affects the system's anti-interference capability and output accuracy, making it an important direction for bandgap reference source technology research and development.

[0003] Traditional bandgap reference sources rely on the temperature compensation principle of the bandgap voltage to achieve the reference voltage output. However, in their classic structure, the core amplifier transistor and load transistor use a single-stage MOSFET architecture, making it easy for power supply noise to be directly transmitted to the output through the MOSFET's channel coupling, thus limiting PSRR performance. To overcome this bottleneck, the industry has proposed upgrading the single-stage transistor structure to a cascode structure, increasing the power supply noise suppression path by adding device stacking, which has become the mainstream improvement approach for improving the PSRR of bandgap reference sources. This invention focuses on optimizing and improving the PSRR of bandgap reference sources, proposing a more practical technical solution to address the shortcomings of traditional structures and existing cascode improvements.

[0004] In related technologies, such as Figure 1As shown, a traditional bandgap reference source employs a classic bandgap core architecture, primarily composed of an operational amplifier (OP), MOSFETs (M1 / M2 / M3), bipolar junction transistors (BJTs) (Q1 / Q2 / Q3), and resistors R1 / R2. M1 and M2 are differential pairs, and M3 is the output reference voltage transistor. Q1 and Q2 are temperature compensation core devices, utilizing BJTs with different emitter areas to generate a temperature-dependent voltage difference. Combined with the temperature-independent bandgap voltage, temperature compensation is achieved through a resistor network, outputting a zero-temperature coefficient reference voltage VREF. The operational amplifier operates in a negative feedback closed-loop state, forcing the collector voltages of Q1 and Q2 to be equal, ensuring consistent gate-source voltages of M1 and M2, thereby achieving precise current mirror matching. However, this traditional bandgap reference source architecture relies solely on a single-stage MOSFET for current mirroring and signal transmission. Power supply noise can be directly coupled to the output terminal through the gate-source / drain capacitance of the MOSFET, resulting in extremely poor voltage rejection ratio performance.

[0005] To improve the voltage rejection ratio of traditional structures, such as Figure 2 As shown, the existing technology upgrades the single-stage MOSFET architecture to a common-source, common-gate structure by adding common-source, common-gate transistors M4 / M5 / M6 to the source / drain paths of MOSFETs M1, M2, and M3, forming a three-stage stacked architecture of M1-M4, M2-M5, and M3-M6. M4 introduces a fixed bias voltage VB and, together with M1, M2, and M3, forms a common-source, common-gate current mirror, replacing the traditional single-stage current mirror structure. The feedback node of the operational amplifier is separated from the gate bias node of the common-source, common-gate transistors, retaining the temperature compensation core logic of the traditional bandgap reference source, and only upgrading the architecture of the core amplifier and load transistors.

[0006] However, the existing cascode structure adds M4 / M5 / M6 cascode transistors, requiring an independent bias voltage VB, which increases the design complexity and power consumption of the bias circuit. The additional bias module not only increases chip area and power consumption costs but also necessitates the design of an additional bias stability mechanism. If the bias voltage VB itself has temperature drift or noise, it can negatively impact the overall accuracy and stability of the reference source. While the cascode structure improves power supply noise suppression in the low-frequency range, in the high-frequency range, the parasitic capacitance of the cascode transistors and the bandwidth limitations of the operational amplifiers introduce new noise coupling paths, resulting in a negligible improvement in high-frequency PSRR performance. This fails to meet the high-frequency anti-interference requirements of high-frequency communication and high-speed data conversion systems. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, this invention proposes a bandgap reference source circuit to solve the problem of poor high-frequency voltage suppression in existing bandgap reference source circuits.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] This invention provides a bandgap reference source circuit, which includes a first gain enhancement circuit, a second gain enhancement circuit, a third gain enhancement circuit, an operational amplifier, a first voltage sampling circuit, a second voltage sampling circuit, a third voltage sampling circuit, and a buffer circuit.

[0010] The first terminal of the first gain enhancement circuit is connected to the first terminal of the second gain enhancement circuit, the first terminal of the third gain enhancement circuit, and the first terminal of the buffer circuit, and together they are used to connect to the power supply. The second terminal of the first gain enhancement circuit is connected to the second terminal of the second gain enhancement circuit, the second terminal of the third gain enhancement circuit, the second terminal of the buffer circuit, and the output terminal of the operational amplifier. The third terminal of the first gain enhancement circuit is connected to the first terminal of the first voltage sampling circuit. The second terminal of the first voltage sampling circuit is connected to the second terminal of the second voltage sampling circuit, the second terminal of the third voltage sampling circuit, and the third terminal of the buffer circuit. The third terminal of the first voltage sampling circuit is connected to the second voltage sampling circuit. The third terminal of the circuit, the third terminal of the third voltage sampling circuit, and the fourth terminal of the buffer circuit are connected and grounded; the fourth terminal of the first voltage sampling circuit is connected to the fourth terminal of the first gain enhancement circuit and the inverting input terminal of the operational amplifier, the fourth terminal of the second voltage sampling circuit is connected to the fourth terminal of the second gain enhancement circuit and the non-inverting input terminal of the operational amplifier, and the fourth terminal of the third gain enhancement circuit is connected to the fourth terminal of the third voltage sampling circuit and used to output a reference voltage; the fourth terminal of the buffer circuit is also used to connect to an external logic control circuit, which is used to provide bias voltages for the first voltage sampling circuit, the second voltage sampling circuit, the third voltage sampling circuit, and the buffer circuit.

[0011] The first voltage sampling circuit controls the output gain of the first gain enhancement circuit according to the bias voltage; the second voltage sampling circuit controls the output gain of the second gain enhancement circuit according to the bias voltage; the third voltage sampling circuit controls the output gain of the third gain enhancement circuit according to the bias voltage; the operational amplifier receives the gain output by the second gain enhancement circuit through its non-inverting input terminal and amplifies it in the same phase before outputting an enhanced gain signal; the operational amplifier receives the gain output by the first gain enhancement circuit through its inverting input terminal and amplifies it in reverse before outputting a reduced gain signal; the buffer circuit is used to buffer the voltage of the third voltage sampling circuit.

[0012] Preferably, the first gain enhancement circuit includes a first MOSFET, a second MOSFET, and a third MOSFET;

[0013] The source of the first MOS transistor is connected to the source of the third MOS transistor and serves as the first terminal of the first gain enhancement circuit. The gate of the first MOS transistor serves as the second terminal of the first gain enhancement circuit. The drain of the first MOS transistor is connected to the source of the second MOS transistor and the gate of the third MOS transistor. The gate of the second MOS transistor is connected to the drain of the third MOS transistor and serves as the third terminal of the first gain enhancement circuit. The drain of the second MOS transistor serves as the fourth terminal of the first gain enhancement circuit.

[0014] Preferably, the second gain enhancement circuit includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET;

[0015] The source of the fourth MOS transistor is connected to the source of the sixth MOS transistor and serves as the first terminal of the second gain enhancement circuit. The gate of the fourth MOS transistor serves as the second terminal of the second gain enhancement circuit. The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor and the gate of the sixth MOS transistor. The gate of the fifth MOS transistor is connected to the drain of the sixth MOS transistor and serves as the third terminal of the second gain enhancement circuit. The drain of the fifth MOS transistor serves as the fourth terminal of the second gain enhancement circuit.

[0016] Preferably, the third gain enhancement circuit includes a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor;

[0017] The source of the seventh MOS transistor is connected to the source of the ninth MOS transistor and serves as the first terminal of the third gain enhancement circuit. The gate of the seventh MOS transistor serves as the second terminal of the third gain enhancement circuit. The drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor and the gate of the ninth MOS transistor. The gate of the eighth MOS transistor is connected to the drain of the ninth MOS transistor and serves as the third terminal of the third gain enhancement circuit. The drain of the eighth MOS transistor serves as the fourth terminal of the third gain enhancement circuit.

[0018] Preferably, the first MOS transistor to the ninth MOS transistor are all PMOS transistors.

[0019] Preferably, the buffer circuit includes a tenth MOS transistor and an eleventh MOS transistor;

[0020] The source of the tenth MOS transistor serves as the first terminal of the buffer circuit, the gate of the tenth MOS transistor serves as the second terminal of the tenth MOS transistor, the drain of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor, the source of the eleventh MOS transistor serves as the fourth terminal of the buffer circuit and is grounded, and the drain of the eleventh MOS transistor is connected to the gate of the eleventh MOS transistor and serves as the third terminal of the buffer circuit.

[0021] Preferably, the first voltage sampling circuit includes a twelfth MOSFET and a first transistor;

[0022] The drain of the twelfth MOS transistor serves as the first terminal of the first voltage sampling circuit, the gate of the twelfth MOS transistor serves as the second terminal of the first voltage sampling circuit, the source of the twelfth MOS transistor is connected to the base and collector of the first transistor respectively and serves as the third terminal of the first voltage sampling circuit, and the emitter of the first transistor serves as the fourth terminal of the first voltage sampling circuit.

[0023] Preferably, the second voltage sampling circuit includes a thirteenth MOSFET, a second transistor, and a first resistor;

[0024] The drain of the thirteenth MOS transistor serves as the first terminal of the second voltage sampling circuit, the gate of the thirteenth MOS transistor serves as the second terminal of the second voltage sampling circuit, the source of the thirteenth MOS transistor is connected to the base and collector of the second transistor respectively and serves as the third terminal of the second voltage sampling circuit, the emitter of the second transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor serves as the fourth terminal of the second voltage sampling circuit.

[0025] Preferably, the third voltage sampling circuit includes a fourteenth MOS transistor, a third transistor, and a second resistor;

[0026] The drain of the fourteenth MOS transistor serves as the first terminal of the third voltage sampling circuit, the gate of the fourteenth MOS transistor serves as the second terminal of the third voltage sampling circuit, the source of the fourteenth MOS transistor is connected to the base and collector of the third transistor respectively and serves as the third terminal of the third voltage sampling circuit, the emitter of the third transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor serves as the fourth terminal of the third voltage sampling circuit.

[0027] Preferably, the twelfth MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor are all NMOS transistors.

[0028] Compared with related technologies, in the embodiments of the present invention, external logic control circuits are used to provide bias voltages for the first voltage sampling circuit, the second voltage sampling circuit, the third voltage sampling circuit, and the buffer circuit, respectively; the first voltage sampling circuit controls the output gain of the first gain enhancement circuit according to the bias voltage; the second voltage sampling circuit controls the output gain of the second gain enhancement circuit according to the bias voltage; the third voltage sampling circuit controls the output gain of the third gain enhancement circuit according to the bias voltage; the operational amplifier receives the gain output by the second gain enhancement circuit through its non-inverting input terminal and amplifies it in the same phase to output an enhanced gain signal; the operational amplifier receives the gain output by the first gain enhancement circuit through its inverting input terminal and amplifies it in reverse to output a reduced gain signal; the buffer circuit is used to buffer the voltage of the third voltage sampling circuit; multiple gain enhancement circuits are used to increase the output impedance of the constant current source load, thereby significantly improving the high-frequency power supply voltage rejection ratio (PSRR) of the reference voltage. Attached Figure Description

[0029] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0030] Figure 1 The circuit diagram is for a traditional bandgap reference structure.

[0031] Figure 2 This refers to the conventional bandgap reference structure that uses a common source and common gate structure in existing technologies.

[0032] Figure 3 A circuit diagram of a bandgap reference source circuit provided in an embodiment of the present invention;

[0033] Figure 4 for Figure 2 The basic principle diagram of the cascode structure to improve voltage rejection ratio;

[0034] Figure 5 A basic schematic diagram of the boost voltage rejection ratio of the bandgap reference source circuit provided in this embodiment of the invention;

[0035] Figure 6 A comparison of simulation curves of the voltage rejection ratio of the bandgap reference source circuit provided in the embodiments of the present invention and the prior art.

[0036] In the figure, 100 is the bandgap reference source circuit, 1 is the first gain enhancement circuit, 2 is the second gain enhancement circuit, 3 is the third gain enhancement circuit, 4 is the first voltage sampling circuit, 5 is the second voltage sampling circuit, 6 is the third voltage sampling circuit, 7 is the buffer circuit, and 8 is the operational amplifier. Detailed Implementation

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0038] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Please see Figures 1-6 As shown, an embodiment of the present invention provides a bandgap reference source circuit 100, which includes a first gain enhancement circuit 1, a second gain enhancement circuit 2, a third gain enhancement circuit 3, an operational amplifier 8, a first voltage sampling circuit 4, a second voltage sampling circuit 5, a third voltage sampling circuit 6, and a buffer circuit 7.

[0041] The first terminal of the first gain enhancement circuit 1 is connected to the first terminals of the second gain enhancement circuit 2, the third gain enhancement circuit 3, and the buffer circuit 7, respectively, and is used to connect to the power supply VDD. The second terminal of the first gain enhancement circuit 1 is connected to the second terminals of the second gain enhancement circuit 2, the third gain enhancement circuit 3, the buffer circuit 7, and the output terminal of the operational amplifier 8. The third terminal of the first gain enhancement circuit 1 is connected to the first terminal of the first voltage sampling circuit 4. The second terminal of the first voltage sampling circuit 4 is connected to the second terminals of the second voltage sampling circuit 5, the third voltage sampling circuit 6, and the buffer circuit 7, respectively. The third terminal of the first voltage sampling circuit 4 is connected to the second voltage sampling circuit... The third terminal of the first voltage sampling circuit 4, the third terminal of the third voltage sampling circuit 6, and the fourth terminal of the buffer circuit 7 are connected and grounded; the fourth terminal of the first voltage sampling circuit 4 is connected to the fourth terminal of the first gain enhancement circuit 1 and the inverting input terminal of the operational amplifier 8, respectively; the fourth terminal of the second voltage sampling circuit 5 is connected to the fourth terminal of the second gain enhancement circuit 2 and the non-inverting input terminal of the operational amplifier 8, respectively; the fourth terminal of the third gain enhancement circuit 3 is connected to the fourth terminal of the third voltage sampling circuit 6 and is used to output the reference voltage VREF; the fourth terminal of the buffer circuit 7 is also used to connect to an external logic control circuit, which is used to provide a bias voltage VBN for the first voltage sampling circuit 4, the second voltage sampling circuit 5, the third voltage sampling circuit 6, and the buffer circuit 7, respectively.

[0042] The first voltage sampling circuit 4 controls the output gain of the first gain enhancement circuit 1 according to the bias voltage VBN; the second voltage sampling circuit 5 controls the output gain of the second gain enhancement circuit 2 according to the bias voltage VBN; the third voltage sampling circuit 6 controls the output gain of the third gain enhancement circuit 3 according to the bias voltage VBN; the operational amplifier 8 receives the output gain of the second gain enhancement circuit 2 through its non-inverting input and synchronously outputs an enhanced gain signal; the operational amplifier 8 receives the output gain of the first gain enhancement circuit 1 through its inverting input and amplifies it in reverse to output a reduced gain signal; the buffer circuit 7 buffers the voltage of the third voltage sampling circuit 6. By using multiple gain enhancement circuits to increase the output impedance of the constant current source load, the high-frequency power supply voltage rejection ratio of the reference voltage VREF can be significantly improved.

[0043] In this embodiment, the first gain enhancement circuit 1 includes a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3. The source of the first MOSFET M1 is connected to the source of the third MOSFET M3 and serves as the first terminal of the first gain enhancement circuit 1. The gate of the first MOSFET M1 serves as the second terminal of the first gain enhancement circuit 1. The drain of the first MOSFET M1 is connected to the source of the second MOSFET M2 and the gate of the third MOSFET M3. The gate of the second MOSFET M2 is connected to the drain of the third MOSFET M3 and serves as the third terminal of the first gain enhancement circuit 1. The drain of the second MOSFET M2 serves as the fourth terminal of the first gain enhancement circuit 1. Specifically, the first terminal of the first gain enhancement circuit 1 is connected to the power supply VDD to provide source bias for the first MOSFET M1 and the third MOSFET M3. The gate of the first MOSFET M1 is connected to the inverting input terminal of the operational amplifier 8 as the input control terminal of the circuit, driving the first MOSFET M1 to enter the saturation region and realize the bias voltage VBN input and the initial circuit conduction. The drain of the first MOSFET M1 is simultaneously connected to the source of the second MOSFET M2 and the gate of the third MOSFET M3. The gate of the second MOSFET M2 and the drain of the third MOSFET M3 are cross-coupled, forming a positive feedback loop. After the first MOSFET M1 is turned on, its drain current drives the gate potential of the second MOSFET M2 to change, thereby regulating the gate voltage of the third MOSFET M3. The gate voltage of the third MOSFET M3, in turn, affects the current distribution at the drain of the first MOSFET M1. The second MOSFET M2 and the third MOSFET M3 form a two-stage cascaded amplification path through cross-coupling. Utilizing the gain enhancement effect of positive feedback, the voltage gain of the single-stage amplifier circuit is improved. The drain of the second MOSFET M2, as the fourth terminal, outputs the amplified signal to the inverting input of the operational amplifier 8 of the bandgap reference source. Working in conjunction with the negative feedback closed loop of the operational amplifier 8, it stabilizes the potential of the core node. At the same time, it utilizes the gain enhancement characteristic to improve the open-loop gain of the entire bandgap reference source loop, providing support for the stability of the reference voltage VREF. A high-gain amplification unit is constructed through the cross-coupling positive feedback of the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3, increasing the voltage gain several times. The high open-loop gain makes it easier for the negative feedback closed loop of operational amplifier 8 to achieve precise potential clamping, reducing the potential mismatch between the first voltage sampling circuit 4 and the second voltage sampling circuit 5, lowering the output voltage error of the bandgap reference, and improving the absolute accuracy of the reference voltage VREF. Thus, the cascaded common-source and common-gate characteristics of the first gain enhancement circuit 1, combined with the high output impedance of the MOSFETs, block the path of noise from the power supply VDD directly coupled to the output terminal through the amplification branch. This positive feedback further increases the impedance of the amplification branch, reduces the noise coupling path, and significantly improves the voltage rejection ratio performance of the bandgap reference.The positive feedback architecture of the first gain enhancement circuit 1 can optimize the distribution of parasitic capacitance by adjusting the width-to-length ratio of the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3, thereby weakening the coupling path of high-frequency signals and effectively improving the voltage rejection ratio performance in the high-frequency band. In high-speed data conversion and high-frequency communication systems, this circuit can suppress the interference of high-frequency power supply noise on the reference voltage VREF, ensuring the operational stability of high-speed circuits.

[0044] In this embodiment, the second gain enhancement circuit 2 includes a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6. The source of the fourth MOSFET M4 is connected to the source of the sixth MOSFET M6 and serves as the first terminal of the second gain enhancement circuit 2. The gate of the fourth MOSFET M4 serves as the second terminal of the second gain enhancement circuit 2. The drain of the fourth MOSFET M4 is connected to the source of the fifth MOSFET M5 and the gate of the sixth MOSFET M6. The gate of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6 and serves as the third terminal of the second gain enhancement circuit 2. The drain of the fifth MOSFET M5 serves as the fourth terminal of the second gain enhancement circuit 2. The positive feedback architecture of the second gain enhancement circuit 2 can optimize the distribution of parasitic capacitance and weaken the coupling path of high-frequency signals by adjusting the width-to-length ratio of the fourth MOSFET M4, the fifth MOSFET M5, and the sixth MOSFET M6, effectively improving the voltage rejection ratio performance in the high-frequency band. In high-speed data conversion and high-frequency communication systems, this circuit can suppress the interference of high-frequency power supply noise on the reference voltage VREF, ensuring the working stability of high-speed circuits.

[0045] In this embodiment, the third gain enhancement circuit 3 includes a seventh MOSFET M7, an eighth MOSFET M8, and a ninth MOSFET M9. The source of the seventh MOSFET M7 is connected to the source of the ninth MOSFET M9 and serves as the first terminal of the third gain enhancement circuit 3. The gate of the seventh MOSFET M7 serves as the second terminal of the third gain enhancement circuit 3. The drain of the seventh MOSFET M7 is connected to the source of the eighth MOSFET M8 and the gate of the ninth MOSFET M9. The gate of the eighth MOSFET M8 is connected to the drain of the ninth MOSFET M9 and serves as the third terminal of the third gain enhancement circuit 3. The drain of the eighth MOSFET M8 serves as the fourth terminal of the third gain enhancement circuit 3. The positive feedback architecture of the third gain enhancement circuit 3 can optimize the distribution of parasitic capacitance and weaken the coupling path of high-frequency signals by adjusting the width-to-length ratio of the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9, thereby effectively improving the voltage rejection ratio performance in the high-frequency band. In high-speed data conversion and high-frequency communication systems, this circuit can suppress the interference of high-frequency power supply noise on the reference voltage VREF, ensuring the working stability of high-speed circuits.

[0046] In this embodiment, all of the first MOS transistors M1 to M9 are PMOS transistors. Since all of them are PMOS transistors, the power supply VDD can be used uniformly as the source bias, eliminating the need to design different bias networks for different types of MOS transistors, thus simplifying the topology and debugging difficulty of the bias circuit. Simultaneously, the gate control logic (low-level conduction) of the PMOS transistors is more easily matched with the closed-loop of the operational amplifier 8 of the bandgap reference source and the potential clamping logic of the BJT transistor in the bandgap core, reducing crosstalk and drift risks of the bias signal and improving the overall reliability of the circuit.

[0047] In this embodiment, the buffer circuit 7 includes a tenth MOSFET M10 and an eleventh MOSFET M11. The source of the tenth MOSFET M10 serves as the first terminal of the buffer circuit 7, the gate of the tenth MOSFET M10 serves as the second terminal of the tenth MOSFET M10, the drain of the tenth MOSFET M10 is connected to the drain of the eleventh MOSFET M11, the source of the eleventh MOSFET M11 serves as the fourth terminal of the buffer circuit 7 and is grounded, and the drain of the eleventh MOSFET M11 is connected to the gate of the eleventh MOSFET M11 and serves as the third terminal of the buffer circuit 7. The source of the tenth MOSFET M10 is connected to the power supply VDD of the bandgap reference source through the buffer circuit 7, providing an input signal for the tenth MOSFET M10; the source of the eleventh MOSFET M11 is grounded, and the gate and drain are shorted to form a fixed bias, establishing a stable drain potential through its own conduction characteristics, providing load impedance for the tenth MOSFET M10. Based on the conduction characteristics of PMOS transistors, when the gate potential of the tenth MOS transistor M10 matches its source potential, M10 conducts. Current flows from the drain of M10 to the drain of the eleventh MOS transistor M11, and then through the source of M11 to ground, forming a stable DC bias path to ensure that the buffer circuit 7 operates within its normal operating range. When the source potential of the tenth MOS transistor M10 changes, the buffer circuit 7 achieves accurate signal transmission through a source follower and negative feedback mechanism. During the operation of the buffer circuit 7, the diode-connected structure of the eleventh MOS transistor M11 provides a constant active load impedance, effectively suppressing fluctuations in the input signal. This buffer circuit 7 requires no additional complex biasing; it only needs to rely on the self-biasing of the eleventh MOS transistor M11 and the input signal of the tenth MOS transistor M10 to operate. It is structurally compatible with the third gain enhancement circuit 3, further simplifying the overall circuit design complexity while improving the output stability and driving capability of the reference source.

[0048] In this embodiment, the first voltage sampling circuit 4 includes a twelfth MOSFET M12 and a first transistor Q1. The drain of the twelfth MOSFET M12 serves as the first terminal of the first voltage sampling circuit 4, the gate of the twelfth MOSFET M12 serves as the second terminal of the first voltage sampling circuit 4, the source of the twelfth MOSFET M12 is connected to the base and collector of the first transistor Q1 and serves as the third terminal of the first voltage sampling circuit 4, and the emitter of the first transistor Q1 serves as the fourth terminal of the first voltage sampling circuit 4. A bias voltage VBN is input to the gate of the twelfth MOSFET M12. When the potential of the bias voltage VBN is lower than the source potential of the twelfth MOSFET M12 (the potential of the node to be sampled), the twelfth MOSFET M12 enters the conducting state, providing a current path for the sampling circuit. The first transistor Q1 is connected in a diode configuration (base-collector short-circuited), operates in the amplification region, and its base-emitter voltage is a fixed transistor bandgap reference voltage VREF, establishing a stable potential reference for the sampling circuit. The first voltage sampling circuit 4 addresses the core requirements of the bandgap reference source, achieving key technical effects such as improved sampling accuracy, enhanced anti-interference capability, and optimized circuit compatibility.

[0049] In this embodiment, the second voltage sampling circuit 5 includes a thirteenth MOSFET M13, a second transistor Q2, and a first resistor R1. The drain of the thirteenth MOSFET M13 serves as the first terminal of the second voltage sampling circuit 5, the gate of the thirteenth MOSFET M13 serves as the second terminal of the second voltage sampling circuit 5, the source of the thirteenth MOSFET M13 is connected to the base and collector of the second transistor Q2 respectively, and serves as the third terminal of the second voltage sampling circuit 5. The emitter of the second transistor Q2 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 serves as the fourth terminal of the second voltage sampling circuit 5. The drain of the thirteenth MOSFET M13 is connected to the core bias node of the bandgap reference source to provide an input potential for the second voltage sampling circuit 5. The connection between the second transistor Q2 and the thirteenth MOSFET M13 enables temperature compensation. By connecting the first resistor R1 to the emitter of the second transistor Q2, current-to-voltage conversion is achieved, and the voltage is superimposed with the bias voltage VBN of the second transistor Q2 to generate a sampling voltage with temperature compensation characteristics.

[0050] Specifically, operational amplifier 8 forces the collector potentials of the first transistor Q1 and the second transistor Q2 to be consistent through a feedback mechanism. The bias voltage VBN acquired by the first voltage sampling circuit 4 is fed back to the inverting input of operational amplifier 8, forming a closed-loop regulation. The constant current characteristic of the twelfth MOSFET M12 can isolate the load effect between the preceding node and the first transistor Q1, preventing the current change of the first transistor Q1 from affecting the potential of the node to be sampled in reverse, thus ensuring sampling accuracy and closed-loop stability. When changes in power supply voltage and temperature cause the potential of the node to be sampled to drift, the twelfth MOSFET M12 automatically adjusts the drain-source current to maintain the bias voltage VBN of the first transistor Q1 stable, providing an accurate and interference-resistant sampling signal for temperature compensation of the bandgap reference source.

[0051] In this embodiment, the third voltage sampling circuit 6 includes a fourteenth MOSFET M14, a third transistor Q3, and a second resistor R2. The drain of the fourteenth MOSFET M14 serves as the first terminal of the third voltage sampling circuit 6, the gate of the fourteenth MOSFET M14 serves as the second terminal of the third voltage sampling circuit 6, the source of the fourteenth MOSFET M14 is connected to the base and collector of the third transistor Q3 and serves as the third terminal of the third voltage sampling circuit 6, the emitter of the third transistor Q3 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 serves as the fourth terminal of the third voltage sampling circuit 6. A bias voltage VBN is input to the gate of the fourteenth MOSFET M14. When the potential of the bias voltage VBN is lower than the source potential of the fourteenth MOSFET M14, the fourteenth MOSFET M14 enters the conducting state, providing a current path for the sampling circuit. The third transistor Q3 adopts a diode connection and operates in the amplification region. Its base-emitter voltage is a fixed transistor bandgap reference voltage VREF, establishing a stable potential reference for the sampling circuit. This third voltage sampling circuit 6 addresses the core requirements of the bandgap reference source, achieving key technical effects such as improved sampling accuracy, enhanced anti-interference capability, and optimized circuit compatibility.

[0052] In this embodiment, the twelfth MOSFET M12, the thirteenth MOSFET M13, and the fourteenth MOSFET M14 are all NMOS transistors. They are perfectly matched with the core current path and operational amplifier drive logic of the bandgap reference source, simplifying the topology and reducing design and layout costs. Leveraging high mobility and strong constant current characteristics, precise temperature compensation is achieved, significantly reducing the reference voltage VREF and improving accuracy. Ground noise and high-frequency coupling can be suppressed, improving voltage rejection ratio and closed-loop stability.

[0053] In this embodiment, the basic principle of improving PSRR using a gain-enhanced cascode structure is as follows; Figure 4 For the existing cascode structure, the gain of this existing structure is Av=(gm rDS)1(gm rDS)2; gm represents transconductance, rDS represents the internal resistance between the drain and source of the MOS transistor, and 1 and 2 represent M1 and M2, respectively. In this invention, as... Figure 5 As shown, by increasing the feedback of M3, the gain is increased to AV = (gm rDS)1(gm rDS)2(gm rDS)3; where 3 represents M3.

[0054] Through the above feedback, the output impedance increases by a multiple of the feedback gain, and the total gain also increases by a multiple of the feedback gain. Furthermore, adding the first MOSFET M1 does not significantly increase the power supply voltage. Figure 5 and Figure 4 The applicable minimum operating voltage is the same, in other words, Figure 5 The gain effect of a three-layer cascode structure can be achieved without increasing the power supply voltage; therefore, compared with existing technologies... Figure 2 In this invention, the impedance from the reference voltage VREF to the power supply is significantly increased, while the impedance from the reference voltage VREF to ground remains unchanged. Through the principle of impedance division, more of the jitter on the power supply is distributed to the gain enhancement structure, and the jitter received by the reference voltage VREF itself becomes smaller, that is, it is less affected by the fluctuation of the power supply VDD, thus improving the voltage rejection ratio (PSRR). Figure 6 It is known that the low-frequency PSRR of this invention can be improved from -75dB to -100dB, and the PSRR at the worst frequency point can be improved from -32dB to -40dB. All of this invention can significantly improve the PSRR of the reference voltage VREF; at the minimum operating voltage without affecting the original basic cascode structure.

[0055] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A bandgap reference source circuit, characterized in that, The bandgap reference source circuit includes a first gain enhancement circuit, a second gain enhancement circuit, a third gain enhancement circuit, an operational amplifier, a first voltage sampling circuit, a second voltage sampling circuit, a third voltage sampling circuit, and a buffer circuit. The first terminal of the first gain enhancement circuit is connected to the first terminal of the second gain enhancement circuit, the first terminal of the third gain enhancement circuit, and the first terminal of the buffer circuit, and together they are used to connect to the power supply. The second terminal of the first gain enhancement circuit is connected to the second terminal of the second gain enhancement circuit, the second terminal of the third gain enhancement circuit, the second terminal of the buffer circuit, and the output terminal of the operational amplifier. The third terminal of the first gain enhancement circuit is connected to the first terminal of the first voltage sampling circuit. The second terminal of the first voltage sampling circuit is connected to the second terminal of the second voltage sampling circuit, the second terminal of the third voltage sampling circuit, and the third terminal of the buffer circuit. The third terminal of the first voltage sampling circuit is connected to the second voltage sampling circuit. The third terminal of the circuit, the third terminal of the third voltage sampling circuit, and the fourth terminal of the buffer circuit are connected and grounded; the fourth terminal of the first voltage sampling circuit is connected to the fourth terminal of the first gain enhancement circuit and the inverting input terminal of the operational amplifier, the fourth terminal of the second voltage sampling circuit is connected to the fourth terminal of the second gain enhancement circuit and the non-inverting input terminal of the operational amplifier, and the fourth terminal of the third gain enhancement circuit is connected to the fourth terminal of the third voltage sampling circuit and used to output a reference voltage; the fourth terminal of the buffer circuit is also used to connect to an external logic control circuit, which is used to provide bias voltages for the first voltage sampling circuit, the second voltage sampling circuit, the third voltage sampling circuit, and the buffer circuit. The first voltage sampling circuit controls the output gain of the first gain enhancement circuit according to the bias voltage; the second voltage sampling circuit controls the output gain of the second gain enhancement circuit according to the bias voltage; the third voltage sampling circuit controls the output gain of the third gain enhancement circuit according to the bias voltage; the operational amplifier receives the gain output by the second gain enhancement circuit through its non-inverting input terminal, amplifies it in the same phase, and outputs an enhanced gain signal; the operational amplifier receives the gain output by the first gain enhancement circuit through its inverting input terminal, amplifies it in the opposite phase, and outputs a reduced gain signal; the buffer circuit is used to buffer the voltage of the third voltage sampling circuit.

2. The bandgap reference source circuit as described in claim 1, characterized in that, The first gain enhancement circuit includes a first MOSFET, a second MOSFET, and a third MOSFET; The source of the first MOS transistor is connected to the source of the third MOS transistor and serves as the first terminal of the first gain enhancement circuit. The gate of the first MOS transistor serves as the second terminal of the first gain enhancement circuit. The drain of the first MOS transistor is connected to the source of the second MOS transistor and the gate of the third MOS transistor. The gate of the second MOS transistor is connected to the drain of the third MOS transistor and serves as the third terminal of the first gain enhancement circuit. The drain of the second MOS transistor serves as the fourth terminal of the first gain enhancement circuit.

3. The bandgap reference source circuit as described in claim 2, characterized in that, The second gain enhancement circuit includes a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; The source of the fourth MOS transistor is connected to the source of the sixth MOS transistor and serves as the first terminal of the second gain enhancement circuit. The gate of the fourth MOS transistor serves as the second terminal of the second gain enhancement circuit. The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor and the gate of the sixth MOS transistor. The gate of the fifth MOS transistor is connected to the drain of the sixth MOS transistor and serves as the third terminal of the second gain enhancement circuit. The drain of the fifth MOS transistor serves as the fourth terminal of the second gain enhancement circuit.

4. The bandgap reference source circuit as described in claim 3, characterized in that, The third gain enhancement circuit includes a seventh MOSFET, an eighth MOSFET, and a ninth MOSFET; The source of the seventh MOS transistor is connected to the source of the ninth MOS transistor and serves as the first terminal of the third gain enhancement circuit. The gate of the seventh MOS transistor serves as the second terminal of the third gain enhancement circuit. The drain of the seventh MOS transistor is connected to the source of the eighth MOS transistor and the gate of the ninth MOS transistor. The gate of the eighth MOS transistor is connected to the drain of the ninth MOS transistor and serves as the third terminal of the third gain enhancement circuit. The drain of the eighth MOS transistor serves as the fourth terminal of the third gain enhancement circuit.

5. The bandgap reference source circuit as described in claim 4, characterized in that, All of the first to the ninth MOS transistors are PMOS transistors.

6. The bandgap reference source circuit as described in claim 1, characterized in that, The buffer circuit includes a tenth MOSFET and an eleventh MOSFET; The source of the tenth MOS transistor serves as the first terminal of the buffer circuit, the gate of the tenth MOS transistor serves as the second terminal of the buffer circuit, the drain of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor, the source of the eleventh MOS transistor serves as the fourth terminal of the buffer circuit and is grounded, and the drain of the eleventh MOS transistor is connected to the gate of the eleventh MOS transistor and serves as the third terminal of the buffer circuit.

7. The bandgap reference source circuit as described in claim 1, characterized in that, The first voltage sampling circuit includes a twelfth MOSFET and a first transistor; The drain of the twelfth MOS transistor serves as the first terminal of the first voltage sampling circuit, the gate of the twelfth MOS transistor serves as the second terminal of the first voltage sampling circuit, the source of the twelfth MOS transistor is connected to the base and collector of the first transistor respectively and serves as the third terminal of the first voltage sampling circuit, and the emitter of the first transistor serves as the fourth terminal of the first voltage sampling circuit.

8. The bandgap reference source circuit as described in claim 7, characterized in that, The second voltage sampling circuit includes a thirteenth MOSFET, a second transistor, and a first resistor; The drain of the thirteenth MOS transistor serves as the first terminal of the second voltage sampling circuit, the gate of the thirteenth MOS transistor serves as the second terminal of the second voltage sampling circuit, the source of the thirteenth MOS transistor is connected to the base and collector of the second transistor respectively and serves as the third terminal of the second voltage sampling circuit, the emitter of the second transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor serves as the fourth terminal of the second voltage sampling circuit.

9. The bandgap reference source circuit as described in claim 8, characterized in that, The third voltage sampling circuit includes a fourteenth MOSFET, a third transistor, and a second resistor; The drain of the fourteenth MOS transistor serves as the first terminal of the third voltage sampling circuit, the gate of the fourteenth MOS transistor serves as the second terminal of the third voltage sampling circuit, the source of the fourteenth MOS transistor is connected to the base and collector of the third transistor respectively and serves as the third terminal of the third voltage sampling circuit, the emitter of the third transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor serves as the fourth terminal of the third voltage sampling circuit.

10. The bandgap reference source circuit as described in claim 9, characterized in that, The twelfth, thirteenth, and fourteenth MOS transistors are all NMOS transistors.

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