Unilateral current detection amplifier circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of circuits, in particular to a single-side current detection amplifier circuit, a chip and electronic equipment, and the single-side current detection amplifier circuit comprises an operational amplifier op, an enhanced PMOS (P-channel Metal Oxide Semiconductor) transistor MPF1, an enhanced PMOS transistor MPL1, an enhanced PMOS transistor MPF2, an enhanced PMOS transistor MPL2, a resistor Rla, a resistor R1b, a resistor Rda, a resistor Rdb, a resistor RS, a buffer BUF1 and a buffer BUF2. According to the single-side current detection amplifier circuit in the technical scheme provided by the embodiment of the invention, switching between a high-side circuit and a low-side circuit is not needed, and bidirectional current sampling can be realized through one circuit, so that the circuit scale is reduced, a large chip area does not need to be occupied when the circuit is integrated, and the cost is reduced. Therefore, the design and manufacturing cost is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, specifically to a single-sided current detection amplifier circuit, chip, and electronic device. Background Technology

[0002] Accurate current measurement is a fundamental requirement of modern electronic systems, widely used in power management, battery monitoring, motor control, and industrial automation. Current sense amplifiers (CSAs), as key components in these systems, enable high-precision current monitoring by converting the small voltage drop across a shunt resistor into an amplified, noise-resistant voltage signal.

[0003] In related technologies, current sensing amplifier circuits, in order to achieve bidirectional current sampling, need to handle common-mode voltages that vary over a wide range. Therefore, current sensing amplifier circuits typically include complementary circuit structures on both sides, namely, a high-side circuit and a low-side circuit. When the common-mode voltage is high, the high-side circuit is off, and the low-side circuit operates normally; when the common-mode voltage is low, the high-side circuit operates normally, and the low-side circuit is off. However, such a design results in a large size for the current sensing amplifier circuit. Integrating this circuit would occupy more chip area, leading to higher design and manufacturing costs. Summary of the Invention

[0004] To address the problems in the related technologies, this disclosure provides a single-sided current detection amplifier circuit, chip, and electronic device.

[0005] In a first aspect, this disclosure provides a single-sided current detection amplifier circuit, including: an operational amplifier op, an enhancement-mode PMOS transistor MPF1, an enhancement-mode PMOS transistor MPL1, an enhancement-mode PMOS transistor MPF2, an enhancement-mode PMOS transistor MPL2, and a resistor R. la Resistance R lb Resistance R da Resistance R db Resistance R S Buffer BUF1, Buffer BUF2; Wherein, resistance R S One end is connected to resistor R da One end and the common-mode voltage terminal V cm1 Connection, resistor R S The other end is connected to resistor R db One end and the common-mode voltage terminal V cm2 Connection, resistor R da The other end is connected to the non-inverting input V+ of the operational amplifier op and the drain of the enhancement-mode PMOS transistor MPF1, with resistor R dbThe other end is connected to the inverting input terminal V- of operational amplifier op and the drain of enhancement-mode PMOS transistor MPF2, and the non-inverting output terminal V of operational amplifier op. O+ The gates of enhancement-mode PMOS transistors MPF1 and MPL1 are connected, and the inverting output terminal V of operational amplifier op is... O- The gates of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are connected to each other. The sources of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are all connected to the input voltage terminal V. DD Connections between the drain of enhancement-mode PMOS transistor MPL1 and resistor R la One end of the resistor is connected to the non-inverting input of buffer BUF1, and resistor R is connected to the non-inverting input of buffer BUF1. la The other end is grounded to GND, and the drain of the enhancement-mode PMOS transistor MPL2 is connected to resistor R. lb One end of the resistor is connected to the non-inverting input of buffer BUF2, and resistor R is connected to the non-inverting input of buffer BUF2. lb The other end is grounded to GND, and the inverting input of buffer BUF1 is connected to the output B of buffer BUF1. out1 Connect the power supply terminal of buffer BUF1 to the input voltage terminal V. DD Connect the inverting input of buffer BUF2 to the output B of buffer BUF2. out2 Connect the power supply terminal of buffer BUF2 to the input voltage terminal V. DD connect.

[0006] In one embodiment of this disclosure, the operational amplifier op includes a current amplification unit, a bias unit, a main circuit unit, and a common-mode feedback circuit unit. Among them, the first terminal of the current amplification unit is connected to the non-inverting input terminal V+ of the operational amplifier op, the second terminal of the current amplification unit is connected to the inverting input terminal V- of the operational amplifier op, the third terminal of the current amplification unit is connected to the first terminal of the main circuit unit, and the fourth terminal of the current amplification unit is connected to the second terminal of the main circuit unit. The first terminal of the bias unit is connected to the third terminal of the main circuit unit; The fourth terminal of the main circuit unit is connected to the first terminal of the common-mode feedback circuit unit, the fifth terminal of the main circuit unit is connected to the second terminal of the common-mode feedback circuit unit, and the sixth terminal of the main circuit unit is connected to the third terminal of the common-mode feedback circuit unit. The fourth terminal of the common-mode feedback circuit unit is connected to the non-inverting output terminal V of the operational amplifier op. O+ Connect the fifth terminal of the common-mode feedback circuit unit to the inverting output terminal V of the operational amplifier op. O- connect.

[0007] In one embodiment of this disclosure, the current amplification unit includes an NPN transistor Q. N1 NPN transistor Q N2 NPN transistor Q N3 NPN transistor Q N4 Enhanced PMOS transistor M P1 Enhanced PMOS transistor M P2 Resistance R 2a and resistance R 2b ; Among them, the first terminal of the current amplification unit is connected to the NPN transistor Q. N1 The emitter and the NPN transistor Q N2 The emitter is connected, and the second terminal of the current amplification unit is connected to the NPN transistor Q. N3 The emitter and the NPN transistor Q N4 The emitter connection of the NPN transistor Q is... N1 The base of the NPN transistor Q N2 The base of the NPN transistor Q N2 collector, NPN transistor Q N3 The base of the NPN transistor Q N3 The collector and NPN transistor Q N4 The base of both is the same as that of the enhancement-mode PMOS transistor M P2 The drain connection of the NPN transistor Q N1 collector and resistor R 2a One end is connected to the fourth end of the current amplification unit, and the NPN transistor Q is connected. N4 collector and resistor R 2b One end of the transistor is connected to the third end of the current amplification unit, and the enhancement-mode PMOS transistor M is connected to it. P2 The source and enhancement-mode PMOS transistor M P1 The drain connection of the enhancement PMOS transistor M P2 The gate and the external bias voltage terminal V B4 Connection, enhancement-mode PMOS transistor M P1 The gate and the external bias voltage terminal V B3 Connection, resistor R 2a The other end, resistor R 2b The other end and the enhancement-type PMOS transistor M P1 The source terminals are all connected to the input voltage terminal V. DD connect.

[0008] In one embodiment of this disclosure, the biasing unit includes an enhancement-mode NMOS transistor M. N1 Enhanced NMOS transistor M N2 Enhanced PMOS transistor MP11 PNP transistor Q3, resistor R 2c Resistance R 3a and resistance R 3b ; Among them, the enhancement-mode NMOS transistor M N1 The source and resistor R 3a One end is grounded to GND, and the resistor R 3a The other end is connected to the enhancement PMOS transistor M. P11 The drain connection of the enhancement NMOS transistor M N1 The gate and the external bias voltage terminal V B1 Connection, enhancement NMOS transistor M N1 The drain and enhancement-mode NMOS transistor M N2 The source connection of the enhancement NMOS transistor M N2 The gate and the external bias voltage terminal V B2 Connection, enhancement NMOS transistor M N2 The drain of the enhancement-mode PMOS transistor M P11 The gate of the PNP transistor Q3 and the collector of the enhancement-mode PMOS transistor M are connected. P11 The source of the PNP transistor Q3 is connected to the base of the PNP transistor, and the resistor R is connected to the base of the PNP transistor Q3. 3b One end of the PNP transistor Q3 is connected to the first end of the bias unit, and the emitter of the PNP transistor Q3 is connected to the resistor R. 2c One end is connected to resistor R 3b The other end is connected to resistor R 2c The other end is connected to the input voltage terminal V DD connect.

[0009] In one embodiment of this disclosure, resistor R 2a The resistance value and resistance R 2b The resistance values ​​are the same, and the resistance R 2a The resistance value and resistance R 2b The resistance value is resistor R 2c Half of the resistance value.

[0010] In one embodiment of this disclosure, the main circuit unit includes a PNP transistor Q1, a PNP transistor Q2, and an enhancement-mode NMOS transistor M. N3 Enhanced NMOS transistor M N4 Enhanced NMOS transistor M N5 Enhanced NMOS transistor M N6 Enhanced NMOS transistor M N7 Enhanced NMOS transistor M N8 Enhanced PMOS transistor M P3 Enhanced PMOS transistor M P4 Enhanced PMOS transistor MP5 Enhanced PMOS transistor M P6 Enhanced PMOS transistor M P7 Enhanced PMOS transistor M P8 Capacitor C M1 and capacitor C M2 ; Among them, the enhancement-mode NMOS transistor M N3 The source of the enhancement-mode NMOS transistor M N4 The source of the enhancement-mode NMOS transistor M N7 The source and enhancement-mode NMOS transistor M N8 The source is grounded to GND, and the enhancement-mode NMOS transistor M... N3 The gate and enhancement NMOS transistor M N4 The gate of the NMOS transistor is connected to the sixth terminal of the main circuit unit. N3 The drain of the PNP transistor Q1 and the collector of the enhancement-mode NMOS transistor M N5 The source connection of the enhancement NMOS transistor M N4 The drain of the PNP transistor Q2 and the collector of the enhancement-mode NMOS transistor M N6 The source of PNP transistor Q1 and the base of PNP transistor Q2 are connected to the third terminal of the main circuit unit. The emitter of PNP transistor Q1 is connected to the first terminal of the main circuit unit, and the emitter of PNP transistor Q2 is connected to the second terminal of the main circuit unit. The enhancement-mode NMOS transistor M... N5 The gate and enhancement NMOS transistor M N6 The gate and the external bias voltage terminal V B2 Connection, enhancement NMOS transistor M N5 The drain of the enhancement-mode PMOS transistor M P5 The drain of the enhancement-mode PMOS transistor M P8 The gate and capacitor C M2 One end is connected to the enhancement-mode NMOS transistor M. N6 The drain of the enhancement-mode PMOS transistor M P6 The drain of the enhancement-mode PMOS transistor M P7 The gate and capacitor C M1 One end is connected to the enhancement-mode PMOS transistor M. P5 The gate and enhancement PMOS transistor M P6 The gate and the external bias voltage terminal V B4 Connection, enhancement-mode PMOS transistor M P5 The source and enhancement-mode PMOS transistor M P3 The drain connection of the enhancement PMOS transistor M P6 The source and enhancement-mode PMOS transistor M P4The drain connection of the enhancement PMOS transistor M P3 The gate and enhancement PMOS transistor M P4 The gate and the external bias voltage terminal V B3 Connection, enhancement NMOS transistor M N7 The gate and enhancement NMOS transistor M N8 The gate and the external bias voltage terminal V B1 Connection, enhancement NMOS transistor M N7 The drain and capacitor C M1 At the other end, the enhancement-mode PMOS transistor M P7 The drain of the transistor is connected to the fourth terminal of the main circuit unit, and the enhancement-mode NMOS transistor M is connected. N8 The drain and capacitor C M2 At the other end, the enhancement-mode PMOS transistor M P8 The drain of the transistor is connected to the fifth terminal of the main circuit unit, and the enhancement-mode PMOS transistor M... P3 The source of the enhancement-mode PMOS transistor M P4 The source of the enhancement-mode PMOS transistor M P7 The source and enhancement-mode PMOS transistor M P8 The source and input voltage terminal V DD connect.

[0011] In one embodiment of this disclosure, the common-mode feedback circuit unit includes an enhancement-mode NMOS transistor M. N9 Enhanced PMOS transistor M P9 and enhancement-mode PMOS transistor M P10 ; Among them, the enhancement-mode NMOS transistor M N9 The source is grounded to GND, and the enhancement-mode NMOS transistor M... N9 The drain of the enhancement-mode NMOS transistor M N9 Gate, enhancement-mode PMOS transistor M P9 The drain and enhancement PMOS transistor M P10 The drains of both transistors are connected to the third terminal of the common-mode feedback circuit unit, and the enhancement-mode PMOS transistor M... P9 The gate of the enhancement-mode PMOS transistor M is connected to the first terminal of the common-mode feedback circuit unit and the fourth terminal of the common-mode feedback circuit unit. P10 The gate of the enhancement-mode PMOS transistor M is connected to the second terminal of the common-mode feedback circuit unit and the fifth terminal of the common-mode feedback circuit unit. P9 The source and enhancement-mode PMOS transistor M P10 The source terminals are all connected to the input voltage terminal V. DD connect.

[0012] In one embodiment of this disclosure, the external bias voltage terminal V B1Used to output the first gate bias voltage, the first gate bias voltage is used to enable the enhancement-mode NMOS transistor M N1 Enhanced NMOS transistor M N7 and enhancement-mode NMOS transistor M N8 All are operating in the saturation region; External bias voltage terminal V B2 Used to output the second gate bias voltage, the second gate bias voltage is used to enable the enhancement-mode NMOS transistor M N2 Enhanced NMOS transistor M N5 and enhancement-mode NMOS transistor M N6 All are operating in the saturation region; External bias voltage terminal V B3 Used to output the third gate bias voltage, the third gate bias voltage is used to enable the enhancement-mode PMOS transistor M P1 Enhanced PMOS transistor M P3 and enhancement-mode PMOS transistor M P4 All are operating in the saturation region; External bias voltage terminal V B4 This is used to output the fourth gate bias voltage, which is used to enable the enhancement-mode PMOS transistor M... P2 Enhanced PMOS transistor M P5 and enhancement-mode PMOS transistor M P6 All are operating in the saturation region.

[0013] Secondly, this disclosure provides a chip that includes a single-sided current detection amplifier circuit according to any one of the first aspects.

[0014] Thirdly, this disclosure provides an electronic device, which includes the chip described in the second aspect.

[0015] According to the technical solution provided in this disclosure, a single-sided current detection amplifier circuit includes an operational amplifier op, an enhancement-mode PMOS transistor MPF1, an enhancement-mode PMOS transistor MPL1, an enhancement-mode PMOS transistor MPF2, an enhancement-mode PMOS transistor MPL2, and a resistor R. la Resistance R lb Resistance R da Resistance R db Resistance R S Buffers BUF1 and BUF2; wherein, the non-inverting input V+ of operational amplifier op is connected through resistor R. da Connect the common-mode voltage terminal V cm1 With resistance R S At one end, the inverting input V- of the operational amplifier op is connected to R. db Connect the common-mode voltage terminal V cm2 With resistance RS At the other end, this allows the operational amplifier op to detect the resistor R in real time. S The above is due to the common-mode voltage terminal V cm1 and common-mode voltage terminal V cm2 The voltage difference generated by the input current; the drain of the enhancement-mode PMOS transistor MPF1 is connected to the non-inverting input terminal V+ of the operational amplifier op, and the gate of the enhancement-mode PMOS transistor MPF1 is connected to the non-inverting output terminal V+ of the operational amplifier op. O+ The drain of enhancement-mode PMOS transistor MPF2 is connected to the inverting input V- of operational amplifier op, and the gate of enhancement-mode PMOS transistor MPF2 is connected to the inverting output V- of operational amplifier op. O- The operational amplifier op is connected through the non-inverting output terminal V. O+ and the inverting output terminal V O- The output is a control voltage used to control the conduction state of enhancement-mode PMOS transistors MPF1 and MPF2. MPF1 and MPF2 then feed back their respective drain currents to the non-inverting input V+ and inverting input V- of operational amplifier op, respectively, thus forming a negative feedback loop. This stabilizes the single-sided current sensing amplifier circuit at the feedback current and resistance R. S The voltage matching state is as follows. Enhancement-mode PMOS transistors MPL1 and MPF1 form a current mirror, and enhancement-mode PMOS transistors MPL2 and MPF2 also form a current mirror. MPL1 replicates the current flowing from the source to the drain of MPF1, and MPL2 replicates the current flowing from the source to the drain of MPF2. These currents are reflected at resistor R. la and resistance R lb The corresponding voltage drop is generated, and then it passes through the output terminal B of buffer BUF1. out1 With the output terminal B of BUF2 out2 Each outputs a corresponding detection voltage, based on output terminal B. out1 and output terminal B out2 The voltage difference of the output detection voltage can determine the resistance R. S The voltage across the resistor R is used to determine the voltage across the resistor R. S The direction and value of the current are measured to achieve bidirectional current sampling.

[0016] In the above scheme, the sources of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are all directly connected to the input voltage terminal V. DDThe turn-on condition for the aforementioned enhancement-mode PMOS transistors is that the voltage difference between the gate and source voltages is less than or equal to the threshold voltage. Since the operating state of an enhancement-mode PMOS transistor is determined solely by the voltage difference between the gate and source voltages, and is not affected by the voltage across the common-mode voltage terminal V... cm1 With common-mode voltage terminal V cm2 The input common-mode voltage has an impact, therefore regardless of whether the common-mode voltage is close to the input voltage terminal V. DD Whether in the high range or the low range close to ground (GND), the operational amplifier op can be adjusted through the non-inverting output terminal V. O+ and the inverting output terminal V O- The output voltage ensures that the gate voltages of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are always lower than their source voltages, and satisfies the condition that the voltage difference between the gate and source voltages is less than or equal to the threshold voltage. This keeps all the enhancement-mode PMOS transistors in the conducting state, ensuring the single-sided current-sensing amplifier circuit operates stably. In summary, the single-sided current-sensing amplifier circuit provided in this embodiment eliminates the need to switch between high-side and low-side circuits, achieving bidirectional current sampling with a single circuit. This reduces the circuit size and minimizes chip area required for circuit integration, thereby lowering design and manufacturing costs.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0018] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings: Figure 1 A structural diagram of a current detection amplifier circuit according to one embodiment is shown.

[0019] Figure 2 A structural diagram of a single-sided current-sensing amplifier circuit according to the present disclosure is shown. Figure 3 A structural diagram of another single-sided current-sensing amplifier circuit according to this disclosure is shown.

[0020] Figure 4 A structural diagram of another single-sided current-sensing amplifier circuit according to the present disclosure is shown. Detailed Implementation

[0021] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0022] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0023] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] In this disclosure, any operation involving the acquisition of user information or user data, or the display of user information or user data to others, is an operation authorized or confirmed by the user, or actively selected by the user.

[0025] In related technologies, current sensing amplifier circuits, in order to achieve bidirectional current sampling, need to handle common-mode voltages that vary over a wide range. Therefore, current sensing amplifier circuits typically include complementary circuit structures on both sides, namely, a high-side circuit and a low-side circuit. When the common-mode voltage is high, the high-side circuit is off, and the low-side circuit operates normally; when the common-mode voltage is low, the high-side circuit operates normally, and the low-side circuit is off. However, such a design results in a large size for the current sensing amplifier circuit. Integrating this circuit would occupy more chip area, leading to higher design and manufacturing costs.

[0026] In one implementation, Figure 1 A structural diagram of a current detection amplifier circuit according to one embodiment is shown. Figure 1 As shown, the current detection amplifier circuit includes operational amplifier A1, operational amplifier A2, and NPN transistor Q. 11 PNP transistor Q 12 PNP transistor Q 13 Resistors R1, R2, R3, R4, and R S1 Resistance R L And a buffer.

[0027] Among them, the PNP transistor Q 12 The emitter and the PNP transistor Q 13 emitter and power supply V DD1 Connection, PNP transistor Q 12 The base of the PNP transistor and the Q-type transistor13 The base of the transistor is connected to the output of operational amplifier A1, and the PNP transistor Q... 12 The collector of the transistor is connected to the positive input terminal of operational amplifier A1 and one end of resistor R2. The PNP transistor Q... 13 collector and resistor R L One end of the NPN transistor Q 11 The emitter and input of the buffer are connected, and the resistor R is... L The other end is grounded to GND, the inverting input of operational amplifier A1 is connected to one end of resistor R1, and the common-mode voltage terminal V... CM11 With resistance R S1 One end of resistor R1, the other end of resistor R1, and one end of resistor R3 are connected together. S1 The other end connects to the other end of resistor R2, one end of resistor R4, and the common-mode voltage terminal V. CM12 The other end of resistor R3 is connected to the positive input terminal of operational amplifier A2 and NPN transistor Q. 11 The collector of the transistor is connected, and the other end of resistor R4 is connected to the inverting input of operational amplifier A2. The output of operational amplifier A2 is connected to NPN transistor Q. 11 The base connection.

[0028] exist Figure 1 In the current detection amplifier circuit shown, the high-side circuit consists of operational amplifier A1 and PNP transistor Q. 12 PNP transistor Q 13 The circuit consists of resistors R1 and R2. The low-side circuit comprises operational amplifier A2 and NPN transistor Q. 11 It consists of resistors R3 and R4. Among them, when the common-mode voltage terminal V is applied... CM11 and common-mode voltage terminal V CM12 The input common-mode voltage is relatively high (close to the power supply voltage V). DD1 When the voltage is ( ), the PNP transistor Q in the high-side circuit 12 PNP transistor Q 13 The voltage at the emitter is close to the power supply V. DD1 The voltage, but the PNP transistor Q 12 PNP transistor Q 13 The voltage on the collector and base will rise synchronously with the common-mode voltage to near the power supply voltage V. DD1 The voltage causes the PNP transistor Q to... 12 PNP transistor Q 13 The emitter junction forward bias voltage approaches 0, resulting in insufficient bias, which causes the PNP transistor Q to... 12 PNP transistor Q 13 When the transistor Q is cut off, the high-side circuit cannot function; while in the low-side circuit, the NPN transistor Q...11 The collector of the transistor is connected to the common-mode voltage through resistor R3, and the operational amplifier A2 can adjust the NPN transistor Q. 11 The base voltage of the NPN transistor Q... 11 The base voltage is higher than that of the NPN transistor Q. 11 The emitter voltage satisfies the forward bias condition of the NPN transistor's emitter junction, enabling the NPN transistor Q... 11 When the circuit is turned on, the low-side circuit will conduct through resistor R. S1 The sampling current is directed to the load resistor R L This enables normal sampling.

[0029] When the common-mode voltage is low (close to the voltage of ground GND), the PNP transistor Q in the high-side circuit... 12 PNP transistor Q 13 The emitter voltage is close to the power supply V. DD1 The voltage, but the PNP transistor Q 12 PNP transistor Q 13 The collector and base voltages of the PNP transistor will drop synchronously with the common-mode voltage to near ground (GND), satisfying the forward bias condition of the PNP transistor. The PNP transistor Q... 12 PNP transistor Q 13 When the circuit is turned on, the high-side circuit can stably drive the sampling current; while in the low-side circuit, the NPN transistor Q... 11 As the common-mode voltage approaches ground (GND), the base voltage of the NPN transistor Q also decreases synchronously, failing to meet the forward bias requirement that the base voltage be greater than the emitter voltage. 11 When the transistor is switched off, the low-side circuit stops working. This circuit switching design based on the transistor bias characteristics achieves coverage of a large common-mode voltage range, but it results in a large current sensing amplifier circuit. If this circuit is integrated, it will occupy more chip area, leading to higher design and manufacturing costs.

[0030] To address the aforementioned issues, this disclosure provides a single-sided current sensing amplifier circuit, chip, and electronic device.

[0031] According to the technical solution provided in this disclosure, a single-sided current detection amplifier circuit includes an operational amplifier op, an enhancement-mode PMOS transistor MPF1, an enhancement-mode PMOS transistor MPL1, an enhancement-mode PMOS transistor MPF2, an enhancement-mode PMOS transistor MPL2, and a resistor R. la Resistance R lb Resistance R da Resistance R db Resistance R S Buffers BUF1 and BUF2; wherein, the non-inverting input V+ of operational amplifier op is connected through resistor R.da Connect the common-mode voltage terminal V cm1 With resistance R S At one end, the inverting input V- of the operational amplifier op is connected to R. db Connect the common-mode voltage terminal V cm2 With resistance R S At the other end, this allows the operational amplifier op to detect the resistor R in real time. S The above is due to the common-mode voltage terminal V cm1 and common-mode voltage terminal V cm2 The voltage difference generated by the input current; the drain of the enhancement-mode PMOS transistor MPF1 is connected to the non-inverting input terminal V+ of the operational amplifier op, and the gate of the enhancement-mode PMOS transistor MPF1 is connected to the non-inverting output terminal V+ of the operational amplifier op. O+ The drain of enhancement-mode PMOS transistor MPF2 is connected to the inverting input V- of operational amplifier op, and the gate of enhancement-mode PMOS transistor MPF2 is connected to the inverting output V- of operational amplifier op. O- The operational amplifier op is connected through the non-inverting output terminal V. O+ and the inverting output terminal V O- The output is a control voltage used to control the conduction state of enhancement-mode PMOS transistors MPF1 and MPF2. MPF1 and MPF2 then feed back their respective drain currents to the non-inverting input V+ and inverting input V- of operational amplifier op, respectively, thus forming a negative feedback loop. This stabilizes the single-sided current sensing amplifier circuit at the feedback current and resistance R. S The voltage matching state is as follows. Enhancement-mode PMOS transistors MPL1 and MPF1 form a current mirror, and enhancement-mode PMOS transistors MPL2 and MPF2 also form a current mirror. MPL1 replicates the current flowing from the source to the drain of MPF1, and MPL2 replicates the current flowing from the source to the drain of MPF2. These currents are reflected at resistor R. la and resistance R lb The corresponding voltage drop is generated, and then it passes through the output terminal B of buffer BUF1. out1 With the output terminal B of BUF2 out2 Each outputs a corresponding detection voltage, based on output terminal B. out1 and output terminal B out2 The voltage difference of the output detection voltage can determine the resistance R. S The voltage across the resistor R is used to determine the voltage across the resistor R. S The direction and value of the current are measured to achieve bidirectional current sampling.

[0032] In the above scheme, the sources of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are all directly connected to the input voltage terminal V. DD The turn-on condition for the aforementioned enhancement-mode PMOS transistors is that the voltage difference between the gate and source voltages is less than or equal to the threshold voltage. Since the operating state of an enhancement-mode PMOS transistor is determined solely by the voltage difference between the gate and source voltages, and is not affected by the voltage across the common-mode voltage terminal V... cm1 With common-mode voltage terminal V cm2 The input common-mode voltage has an impact, therefore regardless of whether the common-mode voltage is close to the input voltage terminal V. DD Whether in the high range or the low range close to ground (GND), the operational amplifier op can be adjusted through the non-inverting output terminal V. O+ and the inverting output terminal V O- The output voltage ensures that the gate voltages of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are always lower than their source voltages, and satisfies the condition that the voltage difference between the gate and source voltages is less than or equal to the threshold voltage. This keeps all the enhancement-mode PMOS transistors in the conducting state, ensuring the single-sided current-sensing amplifier circuit operates stably. In summary, the single-sided current-sensing amplifier circuit provided in this embodiment eliminates the need to switch between high-side and low-side circuits, achieving bidirectional current sampling with a single circuit. This reduces the circuit size and minimizes chip area required for circuit integration, thereby lowering design and manufacturing costs.

[0033] Figure 2 A structural diagram of a single-sided current-sensing amplifier circuit according to this disclosure is shown. Figure 2 As shown, the single-sided current sensing amplifier circuit includes: operational amplifier op, enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2, and resistor R. la Resistance R lb Resistance R da Resistance R db Resistance R S Buffer BUF1, Buffer BUF2; Wherein, resistance R S One end is connected to resistor R da One end and the common-mode voltage terminal V cm1 Connection, resistor R S The other end is connected to resistor R db One end and the common-mode voltage terminal V cm2 Connection, resistor R daThe other end is connected to the non-inverting input V+ of the operational amplifier op and the drain of the enhancement-mode PMOS transistor MPF1, with resistor R db The other end is connected to the inverting input terminal V- of operational amplifier op and the drain of enhancement-mode PMOS transistor MPF2, and the non-inverting output terminal V of operational amplifier op. O+ The gates of enhancement-mode PMOS transistors MPF1 and MPL1 are connected, and the inverting output terminal V of operational amplifier op is... O- The gates of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are connected to each other. The sources of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are all connected to the input voltage terminal V. DD Connections between the drain of enhancement-mode PMOS transistor MPL1 and resistor R la One end of the resistor is connected to the non-inverting input of buffer BUF1, and resistor R is connected to the non-inverting input of buffer BUF1. la The other end is grounded to GND, and the drain of the enhancement-mode PMOS transistor MPL2 is connected to resistor R. lb One end of the resistor is connected to the non-inverting input of buffer BUF2, and resistor R is connected to the non-inverting input of buffer BUF2. lb The other end is grounded to GND, and the inverting input of buffer BUF1 is connected to the output B of buffer BUF1. out1 Connect the power supply terminal of buffer BUF1 to the input voltage terminal V. DD Connect the inverting input of buffer BUF2 to the output B of buffer BUF2. out2 Connect the power supply terminal of buffer BUF2 to the input voltage terminal V. DD connect.

[0034] According to the technical solution provided in this disclosure, a single-sided current detection amplifier circuit includes an operational amplifier op, an enhancement-mode PMOS transistor MPF1, an enhancement-mode PMOS transistor MPL1, an enhancement-mode PMOS transistor MPF2, an enhancement-mode PMOS transistor MPL2, and a resistor R. la Resistance R lb Resistance R da Resistance R db Resistance R S Buffers BUF1 and BUF2; wherein, the non-inverting input V+ of operational amplifier op is connected through resistor R. da Connect the common-mode voltage terminal V cm1 With resistance R S At one end, the inverting input V- of the operational amplifier op is connected to R. db Connect the common-mode voltage terminal V cm2 With resistance R SAt the other end, this allows the operational amplifier op to detect the resistor R in real time. S The above is due to the common-mode voltage terminal V cm1 and common-mode voltage terminal V cm2 The voltage difference generated by the input current; the drain of the enhancement-mode PMOS transistor MPF1 is connected to the non-inverting input terminal V+ of the operational amplifier op, and the gate of the enhancement-mode PMOS transistor MPF1 is connected to the non-inverting output terminal V+ of the operational amplifier op. O+ The drain of enhancement-mode PMOS transistor MPF2 is connected to the inverting input V- of operational amplifier op, and the gate of enhancement-mode PMOS transistor MPF2 is connected to the inverting output V- of operational amplifier op. O- The operational amplifier op is connected through the non-inverting output terminal V. O+ and the inverting output terminal V O- The output is a control voltage used to control the conduction state of enhancement-mode PMOS transistors MPF1 and MPF2. MPF1 and MPF2 then feed back their respective drain currents to the non-inverting input V+ and inverting input V- of operational amplifier op, respectively, thus forming a negative feedback loop. This stabilizes the single-sided current sensing amplifier circuit at the feedback current and resistance R. S The voltage matching state is as follows. Enhancement-mode PMOS transistors MPL1 and MPF1 form a current mirror, and enhancement-mode PMOS transistors MPL2 and MPF2 also form a current mirror. MPL1 replicates the current flowing from the source to the drain of MPF1, and MPL2 replicates the current flowing from the source to the drain of MPF2. These currents are reflected at resistor R. la and resistance R lb The corresponding voltage drop is generated, and then it passes through the output terminal B of buffer BUF1. out1 With the output terminal B of BUF2 out2 Each outputs a corresponding detection voltage, based on output terminal B. out1 and output terminal B out2 The voltage difference of the output detection voltage can determine the resistance R. S The voltage across the resistor R is used to determine the voltage across the resistor R. S The direction and value of the current are measured to achieve bidirectional current sampling.

[0035] In the above scheme, the sources of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are all directly connected to the input voltage terminal V. DDThe turn-on condition for the aforementioned enhancement-mode PMOS transistors is that the voltage difference between the gate and source voltages is less than or equal to the threshold voltage. Since the operating state of an enhancement-mode PMOS transistor is determined solely by the voltage difference between the gate and source voltages, and is not affected by the voltage across the common-mode voltage terminal V... cm1 With common-mode voltage terminal V cm2 The input common-mode voltage has an impact, therefore regardless of whether the common-mode voltage is close to the input voltage terminal V. DD Whether in the high range or the low range close to ground (GND), the operational amplifier op can be adjusted through the non-inverting output terminal V. O+ and the inverting output terminal V O- The output voltage ensures that the gate voltages of enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are always lower than their source voltages, and satisfies the condition that the voltage difference between the gate and source voltages is less than or equal to the threshold voltage. This keeps all the enhancement-mode PMOS transistors in the conducting state, ensuring the single-sided current-sensing amplifier circuit operates stably. In summary, the single-sided current-sensing amplifier circuit provided in this embodiment eliminates the need to switch between high-side and low-side circuits, achieving bidirectional current sampling with a single circuit. This reduces the circuit size and minimizes chip area required for circuit integration, thereby lowering design and manufacturing costs.

[0036] In one embodiment of this disclosure, Figure 3 A structural diagram of another single-sided current-sensing amplifier circuit according to this disclosure is shown. Figure 3 As shown, the operational amplifier op includes a current amplification unit 110, a bias unit 120, a main circuit unit 130, and a common-mode feedback circuit unit 140. Among them, the first terminal 111 of the current amplification unit 110 is connected to the non-inverting input terminal V+ of the operational amplifier op, the second terminal 112 of the current amplification unit 110 is connected to the inverting input terminal V- of the operational amplifier op, the third terminal 113 of the current amplification unit 110 is connected to the first terminal 131 of the main circuit unit 130, and the fourth terminal 114 of the current amplification unit 110 is connected to the second terminal 132 of the main circuit unit 130. The first terminal 121 of the bias unit 120 is connected to the third terminal 133 of the main circuit unit 130; The fourth terminal 134 of the main circuit unit 130 is connected to the first terminal 141 of the common-mode feedback circuit unit 140, the fifth terminal 135 of the main circuit unit 130 is connected to the second terminal 142 of the common-mode feedback circuit unit 140, and the sixth terminal 136 of the main circuit unit 130 is connected to the third terminal 143 of the common-mode feedback circuit unit 140. The fourth terminal 144 of the common-mode feedback circuit unit 140 is connected to the non-inverting output terminal V of the operational amplifier op. O+ The fifth terminal 145 of the common-mode feedback circuit unit 140 is connected to the inverting output terminal V of the operational amplifier op. O- connect.

[0037] In the above scheme, the current amplification unit is used to receive the differential current signals input from the non-inverting input terminal V+ and the inverting input terminal V- of the operational amplifier op, and then, in conjunction with resistor R... 2a Resistance R 2b The current amplification unit converts the differential current signal into a differential voltage signal, and then transmits the converted differential voltage signal to the corresponding input terminal of the main circuit unit through its third and fourth terminals, providing the basic input for subsequent signal amplification. The bias unit generates an initial bias voltage based on the circuit's power supply, calibrates this voltage to reduce fluctuations, and then transmits the calibrated base bias voltage to the third terminal of the main circuit unit through its first terminal, providing a suitable static operating point bias for the common-base amplifier transistor inside the main circuit unit, ensuring stable operation of the common-base amplifier transistor. The main circuit unit receives the differential voltage signal from the current amplification unit through its first and second terminals, and simultaneously receives the base bias voltage provided by the bias unit through its third terminal. It then amplifies the differential voltage signal under the control of the base bias voltage, and simultaneously receives the control signal from the common-mode feedback unit through its sixth terminal, stabilizing the common-mode voltage based on the control signal. Finally, it transmits the amplified differential voltage to the common-mode feedback circuit unit through its fourth and fifth terminals. The common-mode feedback circuit unit receives the differential voltage signal output by the main circuit unit through its first and second terminals, converts it into a differential current, and then summarizes it to obtain the common-mode current reflecting the common-mode voltage. The common-mode current information is then converted into a control signal through an internal current mirror and transmitted to the sixth terminal of the main circuit unit through its fourth terminal to stabilize the common-mode voltage. At the same time, the differential voltage output by the main circuit is level-adapted and sent to the gates of enhancement-mode PMOS transistors MPF1 and MPF2 through its fourth and fifth terminals to drive these two devices to generate feedback current that is fed back to the amplifier input terminal, forming a closed-loop feedback to improve detection accuracy.

[0038] In one embodiment of this disclosure, Figure 4 A structural diagram of another single-sided current-sensing amplifier circuit according to this disclosure is shown. Figure 4 As shown, the current amplification unit includes an NPN transistor Q. N1 NPN transistor Q N2 NPN transistor Q N3 NPN transistor Q N4Enhancement-mode PMOS transistor MP1, enhancement-mode PMOS transistor MP2, resistor R 2a and resistance R 2b ; Among them, the first terminal of the current amplification unit is connected to the NPN transistor Q. N1 The emitter and the NPN transistor Q N2 The emitter is connected, and the second terminal of the current amplification unit is connected to the NPN transistor Q. N3 The emitter and the NPN transistor Q N4 The emitter connection of the NPN transistor Q is... N1 The base of the NPN transistor Q N2 The base of the NPN transistor Q N2 collector, NPN transistor Q N3 The base of the NPN transistor Q N3 The collector and NPN transistor Q N4 The base of both is the same as that of the enhancement-mode PMOS transistor M P2 The drain connection of the NPN transistor Q N1 collector and resistor R 2a One end is connected to the fourth end of the current amplification unit, and the NPN transistor Q is connected. N4 collector and resistor R 2b One end of the transistor is connected to the third end of the current amplification unit, and the enhancement-mode PMOS transistor M is connected to it. P2 The source and enhancement-mode PMOS transistor M P1 The drain connection of the enhancement PMOS transistor M P2 The gate and the external bias voltage terminal V B4 Connection, enhancement-mode PMOS transistor M P1 The gate and the external bias voltage terminal V B3 Connection, resistor R 2a The other end, resistor R 2b The other end and the enhancement-type PMOS transistor M P1 The source terminals are all connected to the input voltage terminal V. DD connect.

[0039] In the above scheme, the differential current signal is first input from the first terminal of the current amplification unit to the NPN transistor Q. N1 NPN transistor Q N2 The emitter of the transistor is input from the second terminal of the current amplification unit to the NPN transistor Q. N3 NPN transistor Q N4 The emitter; simultaneously, the external bias voltage terminal V B3 For enhancement-mode PMOS transistor M P1 Provides gate bias voltage and external bias voltage terminal V B4For enhancement-mode PMOS transistor M P2 Provides gate bias voltage to enable the enhancement-mode PMOS transistor M P1 Enhanced PMOS transistor M P2 Turn on, and turn on the input voltage terminal V DD The voltage is transferred to the enhancement-mode PMOS transistor M P2 The drain of the transistor becomes the drain of the NPN transistor Q. N1 NPN transistor Q N2 NPN transistor Q N3 NPN transistor Q N4 Provides a stable base voltage; the differential current input from the first and second terminals of the current amplification unit drives the NPN transistor Q. N1 NPN transistor Q N2 NPN transistor Q N3 NPN transistor Q N4 When the base current changes synchronously, it causes a corresponding amplified current to be generated at the collector; among them, the NPN transistor Q... N1 The collector current flows through resistor R 2a NPN transistor Q N4 The collector current flows through resistor R 2b The differential current signal is converted into a differential voltage signal; resistor R 2a The corresponding voltage signal is output from the fourth terminal of the current amplification unit, with resistor R. 2b The corresponding voltage signal is output from the third terminal of the current amplification unit, completing the conversion from current signal to voltage signal in the input stage, and transmitting the processed differential voltage signal to the main circuit unit.

[0040] In one embodiment of this disclosure, such as Figure 4 As shown, the bias unit includes an enhancement-mode NMOS transistor M. N1 Enhanced NMOS transistor M N2 Enhanced PMOS transistor M P11 PNP transistor Q3, resistor R 2c Resistance R 3a and resistance R 3b ; Among them, the enhancement-mode NMOS transistor M N1 The source and resistor R 3a One end is grounded to GND, and the resistor R 3a The other end is connected to the enhancement PMOS transistor M. P11 The drain connection of the enhancement NMOS transistor M N1 The gate and the external bias voltage terminal V B1 Connection, enhancement NMOS transistor M N1 The drain and enhancement-mode NMOS transistor MN2 The source connection of the enhancement NMOS transistor M N2 The gate and the external bias voltage terminal V B2 Connection, enhancement NMOS transistor M N2 The drain of the enhancement-mode PMOS transistor M P11 The gate of the PNP transistor Q3 and the collector of the enhancement-mode PMOS transistor M are connected. P11 The source of the PNP transistor Q3 is connected to the base of the PNP transistor, and the resistor R is connected to the base of the PNP transistor Q3. 3b One end of the PNP transistor Q3 is connected to the first end of the bias unit, and the emitter of the PNP transistor Q3 is connected to the resistor R. 2c One end is connected to resistor R 3b The other end is connected to resistor R 2c The other end is connected to the input voltage terminal V DD connect.

[0041] In the above scheme, the external bias voltage terminal V B1 For enhancement-mode NMOS transistor M N1 Provide a gate bias voltage to turn it on, enhancement-mode NMOS transistor M N1 The source and resistor R 3a One end of each transistor is grounded to GND, and the enhancement-mode NMOS transistor M... N1 The drain current will flow through the external bias voltage terminal V B2 Enhancement NMOS transistor M driven to conduct N2 The current is transferred to the enhancement-mode PMOS transistor M. P11 The gate of the transistor is connected to the collector of the PNP transistor Q3; simultaneously, the input voltage terminal V... DD Through resistor R 2c To provide a high potential to the emitter of PNP transistor Q3, the input voltage terminal V... DD Also through resistor R 3b For enhancement-mode PMOS transistor M P11 The source and base of the PNP transistor Q3 are provided with potential, but due to the enhancement-mode NMOS transistor M... N1 Enhanced NMOS transistor M N2 External bias voltage V has been applied B1 V B2 Turning on, thereby pulling down the enhancement-mode PMOS transistor M P11 The gate potential of the enhancement-mode PMOS transistor M P11 Entering the conduction state; Enhancement PMOS transistor M P11 After conduction, the resistor R3a connected to its drain is grounded to GND, so the current will flow from the base of the PNP transistor Q3 through the enhancement-mode PMOS transistor M. P11 Flow resistance R 3aThen, the current path to ground (GND) pulls down the base potential of PNP transistor Q3, thus allowing Q3 to meet the forward bias condition that the emitter voltage is greater than the base voltage and enter the conduction state; enhancement-mode PMOS transistor M... P11 Drain and resistor R 3a The other end is connected to the enhancement-mode PMOS transistor M. P11 The gate of the enhanced NMOS transistor M N2 The drain potential is controlled to turn on the transistor, forming a stable current path; the enhancement-mode PMOS transistor M... P11 The source, base of PNP transistor Q3, and resistor R 3b The node connected at one end generates a stable bias voltage, which is transmitted to the main circuit unit through the first end of the bias unit to provide bias voltage for the common-base amplifier in the main circuit unit.

[0042] In one embodiment of this disclosure, resistor R 2a The resistance value and resistance R 2b The resistance values ​​are the same, and the resistance R 2a The resistance value and resistance R 2b The resistance value is resistor R 2c Half of the resistance value.

[0043] In one embodiment of this disclosure, such as Figure 4 As shown, the main circuit unit includes PNP transistor Q1, PNP transistor Q2, and enhancement-mode NMOS transistor M. N3 Enhanced NMOS transistor M N4 Enhanced NMOS transistor M N5 Enhanced NMOS transistor M N6 Enhanced NMOS transistor M N7 Enhanced NMOS transistor M N8 Enhanced PMOS transistor M P3 Enhanced PMOS transistor M P4 Enhanced PMOS transistor M P5 Enhanced PMOS transistor M P6 Enhanced PMOS transistor M P7 Enhanced PMOS transistor M P8 Capacitor C M1 and capacitor C M2 ; Among them, the enhancement-mode NMOS transistor M N3 The source of the enhancement-mode NMOS transistor M N4 The source of the enhancement-mode NMOS transistor M N7 The source and enhancement-mode NMOS transistor M N8 The source is grounded to GND, and the enhancement-mode NMOS transistor M... N3The gate and enhancement NMOS transistor M N4 The gate of the NMOS transistor is connected to the sixth terminal of the main circuit unit. N3 The drain of the PNP transistor Q1 and the collector of the enhancement-mode NMOS transistor M N5 The source connection of the enhancement NMOS transistor M N4 The drain of the PNP transistor Q2 and the collector of the enhancement-mode NMOS transistor M N6 The source of PNP transistor Q1 and the base of PNP transistor Q2 are connected to the third terminal of the main circuit unit. The emitter of PNP transistor Q1 is connected to the first terminal of the main circuit unit, and the emitter of PNP transistor Q2 is connected to the second terminal of the main circuit unit. The enhancement-mode NMOS transistor M... N5 The gate and enhancement NMOS transistor M N6 The gate and the external bias voltage terminal V B2 Connection, enhancement NMOS transistor M N5 The drain of the enhancement-mode PMOS transistor M P5 The drain of the enhancement-mode PMOS transistor M P8 The gate and capacitor C M2 One end is connected to the enhancement-mode NMOS transistor M. N6 The drain of the enhancement-mode PMOS transistor M P6 The drain of the enhancement-mode PMOS transistor M P7 The gate and capacitor C M1 One end is connected to the enhancement-mode PMOS transistor M. P5 The gate and enhancement PMOS transistor M P6 The gate and the external bias voltage terminal V B4 Connection, enhancement-mode PMOS transistor M P5 The source and enhancement-mode PMOS transistor M P3 The drain connection of the enhancement PMOS transistor M P6 The source and enhancement-mode PMOS transistor M P4 The drain connection of the enhancement PMOS transistor M P3 The gate and enhancement PMOS transistor M P4 The gate and the external bias voltage terminal V B3 Connection, enhancement NMOS transistor M N7 The gate and enhancement NMOS transistor M N8 The gate and the external bias voltage terminal V B1 Connection, enhancement NMOS transistor M N7 The drain and capacitor C M1 At the other end, the enhancement-mode PMOS transistor M P7 The drain of the transistor is connected to the fourth terminal of the main circuit unit, and the enhancement-mode NMOS transistor M is connected. N8The drain and capacitor C M2 At the other end, the enhancement-mode PMOS transistor M P8 The drain of the transistor is connected to the fifth terminal of the main circuit unit, and the enhancement-mode PMOS transistor M... P3 The source of the enhancement-mode PMOS transistor M P4 The source of the enhancement-mode PMOS transistor M P7 The source and enhancement-mode PMOS transistor M P8 The source and input voltage terminal V DD connect.

[0044] In one embodiment of this disclosure, such as Figure 4 As shown, the common-mode feedback circuit unit includes an enhancement-mode NMOS transistor M. N9 Enhanced PMOS transistor M P9 and enhancement-mode PMOS transistor M P10 ; Among them, the enhancement-mode NMOS transistor M N9 The source is grounded to GND, and the enhancement-mode NMOS transistor M... N9 The drain of the enhancement-mode NMOS transistor M N9 Gate, enhancement-mode PMOS transistor M P9 The drain and enhancement PMOS transistor M P10 The drains of both transistors are connected to the third terminal of the common-mode feedback circuit unit, and the enhancement-mode PMOS transistor M... P9 The gate of the enhancement-mode PMOS transistor M is connected to the first terminal of the common-mode feedback circuit unit and the fourth terminal of the common-mode feedback circuit unit. P10 The gate of the enhancement-mode PMOS transistor M is connected to the second terminal of the common-mode feedback circuit unit and the fifth terminal of the common-mode feedback circuit unit. P9 The source and enhancement-mode PMOS transistor M P10 The source terminals are all connected to the input voltage terminal V. DD connect.

[0045] In the above scheme, the input voltage terminal V DD First, let's look at the enhancement-grade PMOS transistor M. P9 The source of the enhancement-mode PMOS transistor M P10 The source of the transistor is provided with a high potential; the first terminal of the common-mode feedback circuit unit receives a differential voltage output from the main circuit unit and transmits it to the enhancement-mode PMOS transistor M. P9 The gate of the common-mode feedback circuit unit is connected to the fourth terminal of the common-mode feedback circuit unit. The second terminal of the common-mode feedback circuit unit receives another differential voltage output from the main circuit unit and transmits it to the enhancement-mode PMOS transistor M. P10 The gate and the fifth terminal of the common-mode feedback circuit unit; these two differential voltages will synchronously regulate the enhancement-mode PMOS transistor M. P9 Enhanced PMOS transistor M P10The conduction level (the lower the gate voltage of the PMOS transistor, the stronger its conduction capability) enables the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 The drain current from the output is collected and flows to the enhancement-mode NMOS transistor M. N9 Enhanced NMOS transistor M N9 The source of the NMOS transistor is grounded to GND, and the enhancement-mode NMOS transistor M... N9 The gate and drain of the transistor are shorted, thereby clamping and converting the collected current, transforming the current signal into a corresponding potential signal; the enhancement-mode PMOS transistor M... P9 The drain of the enhancement-mode PMOS transistor M P10 The drain and enhancement-mode NMOS transistor M N9 The drain of the enhancement-mode NMOS transistor M N9 The gates of the two transistors are connected to the same node. When the common-mode component of the differential voltage output by the main circuit unit increases, the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 The gate voltage of the PMOS transistor increases synchronously, causing the gate voltage of the PMOS transistor to rise. P9 Enhanced PMOS transistor M P10 The conduction capability of the enhanced PMOS transistor M is weakened. P9 Enhanced PMOS transistor M P10 The sum of the drain output currents decreases; due to the enhancement-mode NMOS transistor M N9 With the gate and drain shorted and the source grounded (GND), the drain current and drain-source voltage follow the saturation current characteristics. A decrease in the total current lowers the potential of the same node, generating a low-level modulation signal corresponding to an increase in the common-mode voltage. Conversely, when the common-mode component of the differential voltage decreases, the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 With enhanced conduction capability and increased total drain current, the potential of the same node rises, forming a high-level control signal corresponding to the decrease in common-mode voltage. This potential signal of the same node, reflecting the change in common-mode voltage, is directly output to the main circuit unit through the third terminal of the common-mode feedback circuit unit. After receiving it, the main circuit unit adjusts the tail current of the folded common-source common-gate amplifier. When the common-mode voltage is too high, the tail current is reduced; when it is too low, the tail current is increased. This stabilizes the differential output common-mode voltage of the main circuit within the target range, achieving closed-loop common-mode feedback control.

[0046] In one embodiment of this disclosure, the external bias voltage terminal V B1 Used to output the first gate bias voltage, the first gate bias voltage is used to enable the enhancement-mode NMOS transistor M N1 Enhanced NMOS transistor M N7 and enhancement-mode NMOS transistor M N8 All are operating in the saturation region; External bias voltage terminal V B2 Used to output the second gate bias voltage, the second gate bias voltage is used to enable the enhancement-mode NMOS transistor M N2 Enhanced NMOS transistor M N5 and enhancement-mode NMOS transistor M N6 All are operating in the saturation region; External bias voltage terminal V B3 Used to output the third gate bias voltage, the third gate bias voltage is used to enable the enhancement-mode PMOS transistor M P1 Enhanced PMOS transistor M P3 and enhancement-mode PMOS transistor M P4 All are operating in the saturation region; External bias voltage terminal V B4 This is used to output the fourth gate bias voltage, which is used to enable the enhancement-mode PMOS transistor M... P2 Enhanced PMOS transistor M P5 and enhancement-mode PMOS transistor M P6 All are operating in the saturation region.

[0047] exist Figure 3 In the single-sided current-sensing amplifier circuit shown, the enhancement-type PMOS transistor M P9 Enhanced PMOS transistor M P10 The source terminals are all connected to the input voltage terminal V. DD Connection, enhancement-mode PMOS transistor M P9 Enhanced PMOS transistor M P10 The gates of the two terminals are directly connected to the non-inverting output terminal V of the operational amplifier op. O+ Inverting output terminal V O- These two output terminals are also enhancement-mode PMOS transistors M P7 Enhanced PMOS transistor M P8 The drain output terminal of the enhancement-mode PMOS transistor M... P9 With enhancement-mode PMOS transistor M P7 Enhanced PMOS transistor M P10 With enhancement-mode PMOS transistor M P8 Forming a precise parallel structure, it can synchronize the output terminals V in the same direction in real time. O+ Inverting output terminal V O- The potential change. When common-mode voltage fluctuations occur, the non-inverting output terminal V... O+ Inverting output terminal V O- The potential will rise or fall synchronously: due to the enhancement-mode PMOS transistor M P9 Enhanced PMOS transistor M P10 For PMOS transistors, the gate-source voltage is positively correlated with the conduction capability. When the common-mode voltage increases, the enhancement-mode PMOS transistor M...P9 Enhanced PMOS transistor M P10 The gate potential rises synchronously, the gate-source voltage decreases synchronously, and the drain current decreases synchronously; when the common-mode voltage decreases, the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 The gate potential decreases synchronously, the gate-source voltage increases synchronously, and the drain current increases synchronously; however, if a differential-mode component exists, the non-inverting output terminal V... O+ The potential of the output increases, and the inverting output terminal V O- The potential decreases, through the enhancement-mode PMOS transistor M P9 The current decreases and passes through the enhancement-mode PMOS transistor M. P10 The current increases, passing through the enhancement-mode PMOS transistor M P9 The current and the current through the enhancement PMOS transistor M P10 The reverse current changes cancel each other out, ultimately enabling precise extraction of the common-mode current reflecting the common-mode voltage change, thus achieving effective separation of the common-mode and differential-mode signals. The summarized common-mode current flows to the enhancement-mode NMOS transistor M. N9 Enhanced NMOS transistor M N9 The source is grounded to GND, and the enhancement-mode NMOS transistor M... N9 The gate of the enhancement-mode NMOS transistor M N9 The drain is directly shorted, and the external bias voltage V is applied. B1 The provided bias voltage enables the enhancement-mode NMOS transistor M N9 It operates in the saturation region. Based on the saturation current characteristics of an NMOS transistor, changes in the common-mode current directly translate into changes in the enhancement-mode NMOS transistor's M... N9 The potential changes at the drain and gate of the transistor can be converted from common-mode current to a control potential without the need for an additional intermediate conversion module, and the conversion process has low signal loss and extremely low delay. This control potential is directly supplied to the enhancement-mode NMOS transistor M. N3 Enhanced NMOS transistor M N4 The gate of the enhancement-mode NMOS transistor M N3 Enhanced NMOS transistor M N4 The source of the NMOS transistor is grounded to GND. N3 Enhanced NMOS transistor M N4 The drains of the transistors are connected to the collectors of PNP transistors Q1 and Q2, and the enhancement-mode NMOS transistor M, respectively. N5 Enhanced NMOS transistor M N6 The source of the transistor is the tail current transistor of the folded cascode amplifier, and the enhancement-mode NMOS transistor M. N3 Enhanced NMOS transistor M N4 The on-current of the enhancement-mode NMOS transistor M directly determines the on-state current. N5 Enhanced NMOS transistor M N6The current, thereby regulating the non-inverting output terminal V O+ Inverting output terminal V O- The common-mode voltage. When the common-mode voltage is too high, the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 The sum of drain currents decreases, and the enhancement-mode NMOS transistor M... N9 The gate-source voltage decreases, and the enhancement-mode NMOS transistor M... N9 The drain potential of the enhancement-mode NMOS transistor M decreases, leading to a decrease in the drain potential of the NMOS transistor M. N3 Enhanced NMOS transistor M N4 As the gate potential decreases, the conduction capability weakens, the tail current decreases, and the enhancement-mode NMOS transistor M... N5 Enhanced NMOS transistor M N6 The reduced current causes the enhancement-mode PMOS transistor M... P7 Enhanced PMOS transistor M P8 As the gate voltage increases, the non-inverting output terminal V... O+ Inverting output terminal V O- The common-mode voltage is pulled down to the equilibrium value; when the common-mode voltage is too low, the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 The sum of currents increases, and the enhancement-mode NMOS transistor M... N9 The drain potential of the enhancement-mode NMOS transistor M increases. N3 Enhanced NMOS transistor M N4 The tail current increases, and the enhancement-mode NMOS transistor M N5 Enhanced NMOS transistor M N6 The increased drain current of the enhancement-mode PMOS transistor M... P7 Enhanced PMOS transistor M P8 The gate voltage drops, and the non-inverting output terminal V... O+ Inverting output terminal V O- The common-mode voltage is raised to an equilibrium value, forming a closed-loop control. The stable point of the common-mode voltage is determined by the enhancement-mode PMOS transistor M. P9 Enhanced PMOS transistor M P10 The gate-source voltage is self-consistently determined. Specifically, when the circuit is balanced, the non-inverting output voltage V... O+ Inverting output terminal V O- The common-mode voltage, and the input voltage terminal V DD The voltage minus the enhancement-mode PMOS transistor M P9 The voltage difference obtained from the gate-source voltage, and the input voltage V DD The voltage minus the enhancement-mode PMOS transistor M P10 The voltage difference obtained from the gate-source voltage is equal. This is achieved by making the enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10Enhanced PMOS transistor M P7 Enhanced PMOS transistor M P8 Employing a matching design with the same process and dimensions, and featuring an enhanced PMOS transistor M... P7 Enhanced PMOS transistor M P8 The gates are respectively connected to capacitor C M1 C M2 Connecting the enhancement-type NMOS transistor M N6 Enhanced NMOS transistor M N5 The drain of the enhancement-mode PMOS transistor M can form a stable amplification path. P9 Enhanced PMOS transistor M P10 The gate-source voltage is consistent, requiring no external reference voltage source for calibration, and can operate over a wide range of input current variations and voltage terminal V. DD Under different operating scenarios, such as voltage fluctuations, the common-mode voltage is stabilized within a preset range. Compared to related technologies that require the additional integration of redundant devices such as a bandgap reference source, a high-gain error operational amplifier, and a voltage divider resistor network, the above solution only requires an enhancement-mode PMOS transistor M... P9 Enhanced PMOS transistor M P10 Enhanced NMOS transistor M N9 Three core components, combined with an enhancement-mode NMOS transistor M as the tail current transistor. N3 Enhanced NMOS transistor M N4 The PNP transistors Q1 and Q2, which act as amplifiers, complete the entire feedback loop from common-mode current sampling to tail current regulation, thereby simplifying the circuit size and reducing the chip area occupied.

[0048] This disclosure provides a chip that includes any of the single-sided current detection amplifier circuits provided in the embodiments of this disclosure.

[0049] This disclosure provides an electronic device, which includes a chip provided in the embodiments of this disclosure.

[0050] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A single-sided current detection amplifier circuit, characterized in that, include: Operational amplifier op, enhancement-mode PMOS transistor MPF1, enhancement-mode PMOS transistor MPL1, enhancement-mode PMOS transistor MPF2, enhancement-mode PMOS transistor MPL2, resistor R la Resistance R lb Resistance R da Resistance R db Resistance R S Buffer BUF1, Buffer BUF2; Wherein, the resistor R S One end is connected to the resistor R da One end and the common-mode voltage terminal V cm1 Connection, the resistor R S The other end is connected to the resistor R db One end and the common-mode voltage terminal V cm2 Connection, the resistor R da The other end is connected to the non-inverting input terminal V+ of the operational amplifier op and the drain of the enhancement-mode PMOS transistor MPF1, and the resistor R db The other end is connected to the inverting input terminal V- of the operational amplifier op and the drain of the enhancement-mode PMOS transistor MPF2, and the non-inverting output terminal V of the operational amplifier op. O+ The inverting output terminal V of the operational amplifier op is connected to the gates of the enhancement-mode PMOS transistor MPF1 and the enhancement-mode PMOS transistor MPL1. O- The gates of the enhancement-mode PMOS transistors MPF1 and MPL2 are connected, and the sources of the enhancement-mode PMOS transistors MPF1, MPL1, MPF2, and MPL2 are all connected to the input voltage terminal V. DD The connection is made between the drain of the enhancement-type PMOS transistor MPL1 and the resistor R. la One end of the resistor R is connected to the non-inverting input of the buffer BUF1. la The other end is grounded to GND, and the drain of the enhancement-mode PMOS transistor MPL2 is connected to the resistor R. lb One end of the resistor R is connected to the non-inverting input of the buffer BUF2. lb The other end is grounded to GND, and the inverting input of the buffer BUF1 is connected to the output B of the buffer BUF1. out1 The power supply terminal of the buffer BUF1 is connected to the input voltage terminal V. DD The connection is made between the inverting input terminal of the buffer BUF2 and the output terminal B of the buffer BUF2. out2 The power supply terminal of the buffer BUF2 is connected to the input voltage terminal V. DD connect.

2. The single-sided current detection amplifier circuit according to claim 1, characterized in that, The operational amplifier op includes a current amplification unit, a bias unit, a main circuit unit, and a common-mode feedback circuit unit; Wherein, the first terminal of the current amplification unit is connected to the non-inverting input terminal V+ of the operational amplifier op, the second terminal of the current amplification unit is connected to the inverting input terminal V- of the operational amplifier op, the third terminal of the current amplification unit is connected to the first terminal of the main circuit unit, and the fourth terminal of the current amplification unit is connected to the second terminal of the main circuit unit. The first terminal of the bias unit is connected to the third terminal of the main circuit unit; The fourth terminal of the main circuit unit is connected to the first terminal of the common-mode feedback circuit unit, the fifth terminal of the main circuit unit is connected to the second terminal of the common-mode feedback circuit unit, and the sixth terminal of the main circuit unit is connected to the third terminal of the common-mode feedback circuit unit. The fourth terminal of the common-mode feedback circuit unit is connected to the non-inverting output terminal V of the operational amplifier op. O+ The fifth terminal of the common-mode feedback circuit unit is connected to the inverting output terminal V of the operational amplifier op. O- connect.

3. The single-sided current detection amplifier circuit according to claim 2, characterized in that, The current amplification unit includes an NPN transistor Q. N1 NPN transistor Q N2 NPN transistor Q N3 NPN transistor Q N4 Enhanced PMOS transistor M P1 Enhanced PMOS transistor M P2 Resistance R 2a and resistance R 2b ; The first terminal of the current amplification unit is connected to the NPN transistor Q. N1 The emitter and the NPN transistor Q N2 The emitter of the current amplifier unit is connected to the emitter of the NPN transistor Q. N3 The emitter and the NPN transistor Q N4 The emitter connection of the NPN transistor Q is... N1 The base of the NPN transistor Q N2 The base of the NPN transistor Q N2 The collector of the NPN transistor Q N3 The base of the NPN transistor Q N3 The collector and the NPN transistor Q N4 The base of each is connected to the enhanced PMOS transistor M. P2 The drain connection of the NPN transistor Q N1 collector and resistor R 2a One end of the transistor is connected to the fourth end of the current amplification unit, and the NPN transistor Q is connected to the fourth end of the current amplification unit. N4 The collector and the resistor R 2b One end of the transistor is connected to the third end of the current amplification unit, and the enhancement-mode PMOS transistor M is connected to the third end of the current amplification unit. P2 The source of the enhanced PMOS transistor M P1 The drain connection of the enhancement PMOS transistor M P2 The gate and the external bias voltage terminal V B4 Connection, the enhanced PMOS transistor M P1 The gate and the external bias voltage terminal V B3 Connection, the resistor R 2a The other end, the resistor R 2b The other end and the enhanced PMOS transistor M P1 The sources of all are connected to the input voltage terminal V. DD connect.

4. The single-sided current detection amplifier circuit according to claim 3, characterized in that, The bias unit includes an enhancement-mode NMOS transistor M. N1 Enhanced NMOS transistor M N2 Enhanced PMOS transistor M P11 PNP transistor Q3, resistor R 2c Resistance R 3a and resistance R 3b ; Among them, the enhanced NMOS transistor M N1 The source and the resistor R 3a One end of the resistor is grounded to GND, and the resistor R 3a The other end is connected to the enhanced PMOS transistor M P11 The drain connection of the enhancement NMOS transistor M N1 The gate and the external bias voltage terminal V B1 Connection, the enhanced NMOS transistor M N1 The drain of the enhanced NMOS transistor M N2 The source connection of the enhancement NMOS transistor M N2 The gate and the external bias voltage terminal V B2 Connection, the enhanced NMOS transistor M N2 The drain of the enhanced PMOS transistor M P11 The gate of the PNP transistor Q3 is connected to the collector of the PNP transistor M. P11 The source of the PNP transistor Q3 and the base of the PNP transistor Q3, and the resistor R 3b One end of the transistor Q3 is connected to the first end of the bias unit, and the emitter of the PNP transistor Q3 is connected to the resistor R. 2c One end is connected, the resistor R 3b The other end is connected to the resistor R 2c The other end is connected to the input voltage terminal V DD connect.

5. The single-sided current detection amplifier circuit according to claim 4, characterized in that, The resistor R 2a The resistance value and the resistance R 2b The resistance values ​​are the same, and the resistor R 2a The resistance value and the resistance R 2b The resistance value is the resistor R. 2c Half of the resistance value.

6. The single-sided current detection amplifier circuit according to claim 4, characterized in that, The main circuit unit includes a PNP transistor Q1, a PNP transistor Q2, and an enhancement-mode NMOS transistor M. N3 Enhanced NMOS transistor M N4 Enhanced NMOS transistor M N5 Enhanced NMOS transistor M N6 Enhanced NMOS transistor M N7 Enhanced NMOS transistor M N8 Enhanced PMOS transistor M P3 Enhanced PMOS transistor M P4 Enhanced PMOS transistor M P5 Enhanced PMOS transistor M P6 Enhanced PMOS transistor M P7 Enhanced PMOS transistor M P8 Capacitor C M1 and capacitor C M2 ; Among them, the enhanced NMOS transistor M N3 The source of the enhanced NMOS transistor M N4 The source of the enhanced NMOS transistor M N7 The source and the enhancement NMOS transistor M N8 The source of the enhanced NMOS transistor is grounded to GND. N3 The gate of the enhanced NMOS transistor M N4 The gate of the transistor is connected to the sixth terminal of the main circuit unit, and the enhancement-mode NMOS transistor M... N3 The drain of the PNP transistor Q1 and the collector of the enhancement-mode NMOS transistor M N5 The source connection of the enhancement NMOS transistor M N4 The drain of the PNP transistor Q2 and the collector of the enhancement-mode NMOS transistor M N6 The source of the PNP transistor Q1 is connected to the source of the main circuit unit. The bases of the PNP transistor Q1 and Q2 are connected to the third terminal of the main circuit unit. The emitter of the PNP transistor Q1 is connected to the first terminal of the main circuit unit. The emitter of the PNP transistor Q2 is connected to the second terminal of the main circuit unit. The enhancement-mode NMOS transistor M... N5 The gate of the enhanced NMOS transistor M N6 The gate and the external bias voltage terminal V B2 Connection, the enhanced NMOS transistor M N5 The drain of the enhancement-mode PMOS transistor M P5 The drain of the enhancement-mode PMOS transistor M P8 The gate and capacitor C M2 One end is connected to the enhanced NMOS transistor M. N6 The drain of the enhancement-mode PMOS transistor M P6 The drain of the enhancement-mode PMOS transistor M P7 The gate and capacitor C M1 One end is connected to the enhanced PMOS transistor M. P5 The gate of the enhanced PMOS transistor M P6 The gate and the external bias voltage terminal V B4 Connection, the enhanced PMOS transistor M P5 The source of the enhanced PMOS transistor M P3 The drain connection of the enhancement PMOS transistor M P6 The source of the enhanced PMOS transistor M P4 The drain connection of the enhancement PMOS transistor M P3 The gate of the enhanced PMOS transistor M P4 The gate and the external bias voltage terminal V B3 Connection, the enhanced NMOS transistor M N7 The gate of the enhanced NMOS transistor M N8 The gate and the external bias voltage terminal V B1 Connection, the enhanced NMOS transistor M N7 The drain and capacitor C M1 At the other end, the enhanced PMOS transistor M P7 The drain of the transistor is connected to the fourth terminal of the main circuit unit, and the enhancement-mode NMOS transistor M... N8 The drain and capacitor C M2 At the other end, the enhanced PMOS transistor M P8 The drain of the transistor is connected to the fifth terminal of the main circuit unit, and the enhancement-type PMOS transistor M... P3 The source of the enhanced PMOS transistor M P4 The source of the enhanced PMOS transistor M P7 The source and the enhancement PMOS transistor M P8 The source and the input voltage terminal V DD connect.

7. The single-sided current detection amplifier circuit according to claim 6, characterized in that, The common-mode feedback circuit unit includes an enhancement-mode NMOS transistor M. N9 Enhanced PMOS transistor M P9 and enhancement-mode PMOS transistor M P10 ; Among them, the enhanced NMOS transistor M N9 The source of the enhanced NMOS transistor is grounded to GND. N9 The drain of the enhanced NMOS transistor M N9 The gate of the enhanced PMOS transistor M P9 The drain of the enhanced PMOS transistor M P10 The drains of all transistors are connected to the third terminal of the common-mode feedback circuit unit, and the enhancement-mode PMOS transistor M... P9 The gate of the enhancement-mode PMOS transistor M is connected to the first terminal and the fourth terminal of the common-mode feedback circuit unit. P10 The gate of the enhancement-mode PMOS transistor M is connected to the second terminal and the fifth terminal of the common-mode feedback circuit unit. P9 The source and the enhancement PMOS transistor M P10 The sources of all are connected to the input voltage terminal VDD.

8. The single-sided current detection amplifier circuit according to claim 7, characterized in that, The external bias voltage terminal V B1 This is used to output a first gate bias voltage, which is used to enable the enhancement-mode NMOS transistor M... N1 The enhanced NMOS transistor M N7 and the enhanced NMOS transistor M N8 All are operating in the saturation region; The external bias voltage terminal V B2 This is used to output a second gate bias voltage, which is used to enable the enhancement-mode NMOS transistor M... N2 The enhanced NMOS transistor M N5 and the enhanced NMOS transistor M N6 All are operating in the saturation region; The external bias voltage terminal V B3 This is used to output a third gate bias voltage, which is used to enable the enhancement-mode PMOS transistor M... P1 The enhanced PMOS transistor M P3 and the enhanced PMOS transistor M P4 All are operating in the saturation region; The external bias voltage terminal V B4 This is used to output a fourth gate bias voltage, which is used to enable the enhancement-mode PMOS transistor M... P2 The enhanced PMOS transistor M P5 and the enhanced PMOS transistor M P6 All are operating in the saturation region.

9. A chip, characterized in that, The chip includes the single-sided current sensing amplifier circuit according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the chip of claim 9.

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