Delta-sigma modulator with downsampled digital integrator

Abstract

Systems and methods for a delta-sigma modulator having a downsampled digital integrator. In various embodiments, a delta-sigma modulator may include a comparator configured to receive an analog input and provide a digital output at a sampling frequency, where the digital output is applied to an integrator path and a feed-forward path; a digital integrator in the integrator path, wherein the digital integrator is configured to operate at a clock frequency less than the sampling frequency; and a summator configured to add an output of the integrator path to an output of the feed-forward path to produce a bitstream.

Description

Technical Field

[0001] This disclosure generally relates to electronic circuits, and more specifically to a Δ-Σ modulator having an undersampled digital integrator. Background Technology

[0002] Within a range of analog-to-digital converters (ADCs), there exists a category that employs oversampling techniques to achieve high-resolution digital output. Traditionally, in such ADCs, the analog / digital domain (e.g., quantizer) crossover and the digital / analog domain (e.g., feedback circuitry) use the same number of levels or bits, while multi-level approaches increase complexity. Alternatively, there are methods where the number of quantizer levels is less than the number of feedback levels; however, this has proven difficult to implement due to stability issues.

[0003] As the inventors have recognized, ADCs with more feedback levels than the quantization level face challenges in maintaining stability, especially when their digital components operate at the same clock frequency. Conventional solutions, such as analog compensation or digital feedforward, require significant hardware resources and lead to increased noise. Summary of the Invention

[0004] In an illustrative, non-limiting embodiment, a Δ-Σ modulator may include: a comparator configured to receive an analog input and provide a digital output at a sampling frequency, wherein the digital output is applied to an integrator path and a feedforward path; a digital integrator in the integrator path, wherein the digital integrator is configured to operate at a clock frequency less than the sampling frequency; and a summer configured to add the output of the integrator path to the output of the feedforward path to generate a bit stream.

[0005] The Δ-Σ modulator may include a downsampler in the integrator path, wherein the downsampler is configured to provide a downsampled digital signal to the digital integrator at a clock frequency. Alternatively, the Δ-Σ modulator may include an accumulator in the integrator path, wherein the accumulator is configured to receive the digital output and provide the running sum of the digital output. Alternatively, the Δ-Σ modulator may include a digital amplifier in the integrator path, wherein the digital amplifier is configured to normalize the running average of the digital output of the accumulator.

[0006] In some cases, a Δ-Σ modulator may include an accumulator implemented as an FIR filter. The accumulator can output the average of n values ​​after receiving the nth value, and the digital amplifier can be configured to divide the output by n.

[0007] A Δ-Σ modulator may include a cutoff coupled between an accumulator and a digital integrator, wherein the cutoff is configured to reduce the bit width of the accumulator's output. Alternatively, a Δ-Σ modulator may include a cutoff coupled between a digital integrator and a summer, wherein the cutoff is configured to reduce the bit width of the digital integrator's output. A Δ-Σ modulator may also include a digital amplifier in a feedforward path.

[0008] In operation, the integrator path can add poles to the transfer function of the Δ-Σ modulator, and the feedforward path can add zeros configured to compensate for the poles. Furthermore, the comparator can be configured to receive analog inputs via a loop filter.

[0009] In another illustrative, non-limiting embodiment, a Δ-Σ modulator may include: a comparator configured to receive an analog input; an integrator path configured to receive the digital output of the comparator, wherein the integrator path includes a digital integrator configured to operate at a clock frequency less than the sampling frequency of the comparator, and wherein the digital integrator adds poles to the transfer function of the Δ-Σ modulator; and a feedforward path configured to receive the digital output of the comparator and compensate for the poles.

[0010] The integrator path may include an accumulator configured to receive a digital signal and generate a running sum of the digital signal; followed by a normalizer configured to generate an average of the accumulator's output. The integrator path may also include a downsampling unit configured to: receive at least one of: (a) a running average of the digital signal, or (b) a normalized running sum of the digital signal; and provide a downsampled signal to the digital integrator.

[0011] In another illustrative, non-limiting embodiment, in an ADC, a method may include: generating a digital output using a comparator operating at a sampling frequency; providing the digital output to an integration path and a feedforward path; downsampling data from the integration path to a frequency lower than the sampling frequency; integrating the data from the integration path using a digital integrator after the downsampling; and combining the integrated, downsampled data from the integration path with the digital output to generate a bit stream.

[0012] The method may further include the comparator receiving an analog input via a loop filter and generating a digital output at a sampling frequency based on the analog input. In some cases, downsampling the digital output may include downsampling the running average of the digital output.

[0013] Downsampling the running average of the digital output may further include: truncating the running average of the digital output; and downsampling the truncated running average of the digital output. In some cases, the method may include truncating the integrated downsampled data of the integration path after integration. Alternatively, the method may include truncated integrated downsampled data of the integration path. Attached Figure Description

[0014] This disclosure is by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0015] Figure 1 This is a high-level block diagram of an example of a Δ-Σ modulator according to some embodiments.

[0016] Figure 2 This is a detailed block diagram of an example of a Δ-Σ modulator according to some embodiments.

[0017] Figure 3 This is a flowchart of an example of a method for operating a Δ-Σ modulator according to some embodiments.

[0018] Figure 4 This is a circuit diagram of an example implementation of a Δ-Σ modulator according to some embodiments.

[0019] Figure 5 This is a circuit diagram of another example implementation of a Δ-Σ modulator according to some embodiments. Detailed Implementation

[0020] Analog-to-digital converters (ADCs) are essential components in modern electronics, converting analog signals into digital data for processing and analysis. Among various types of ADCs, delta-sigma modulators are often favored for their ability to achieve high resolution and accuracy through oversampling and noise shaping. These modulators are widely used in applications such as audio processing, telecommunications, and instrumentation, where accuracy and dynamic range are important and data rates are typically low.

[0021] Conventional delta-sigma modulators utilize a unit comparator or quantizer and a feedback digital-to-analog converter (DAC) to digitize analog signals via oversampling. While multi-bit comparators can sometimes achieve the same quantization accuracy with a lower oversampling ratio, they also introduce nonlinearity due to mismatches between levels within the comparator and between levels within the feedback DAC. Digital integrators allow the use of unit comparators, which are inherently linear, but still require potentially nonlinear multi-bit feedback DACs.

[0022] To linearize domain crossover (analog / digital or digital / analog), mismatch shaping techniques, such as Dynamic Element Matching (DEM) algorithms, can be employed for this purpose. In many cases, linearizing digital / analog crossover in the form of a feedback DAC is simpler than linearizing it in the form of a comparator. DEM techniques can improve the linearity of the DAC by dynamically selecting the use of DAC elements over time and averaging the use of DAC elements to reduce or minimize the effects of component mismatch, thereby effectively distributing mismatch errors across the Nyquist bandwidth.

[0023] One advantage of a multi-bit feedback DAC in a delta-sigma modulator is its ability to coarsely track the analog input, allowing oversampling without covering the entire input range. However, in current systems, the multi-bit comparator significantly increases the design complexity of the delta-sigma modulator. Alternatively, current systems use a digital integrator that operates at the same frequency as the comparator, which makes the entire delta-sigma loop difficult to stabilize because the integrator introduces poles in the feedback loop.

[0024] The transfer function of a Δ-Σ modulator, represented in the discrete and continuous time domains (for z and s, respectively), characterizes how the input signal and quantization noise propagate through the system, and it is shaped by strategically placing poles and zeros within the transfer function. Poles are typically placed (positions in the z or s domain where the transfer function approaches infinity) to enhance the shape of the quantization noise. On the other hand, zeros are chosen (positions in the z or s domain where the transfer function approaches zero) to control the system's stability and impulse response.

[0025] When a pole is introduced by the digital integrator of a Δ-Σ modulator, this pole can be compensated by adding a zero in the digital domain via feedforward on the digital integrator. To address this and other issues, embodiments of the systems and methods described herein can provide an ADC with stable digital integration and reduced hardware complexity, thereby reducing or eliminating the need for pole compensation for analog components.

[0026] In some embodiments, these systems and methods can introduce an undersampled digital integrator within the feedback loop of the Δ-Σ modulator. The digital integrator can be sampled at a lower frequency than the comparator of the Δ-Σ modulator. By adding a digital feedforward path that samples at the same frequency as the comparator, these systems and methods can compensate for the added poles of the digital integrator, thereby allowing fine quantization without the need for analog zeros. In some cases, truncation of the digital integrator's output can also reduce the need for an overly large feedback DAC.

[0027] In many embodiments, these features improve the flexibility and stability of the Δ-Σ modulator, making it particularly suitable for high-resolution applications such as audio codecs and sensor interfaces. The resulting architecture is robust to loop delay and suitable for high sampling frequencies, thus providing significant performance improvements, especially for high-resolution applications.

[0028] In some cases, the use of DEM can further mitigate mismatches in the feedback element, thereby enhancing linearity and accuracy. By downsampling the digital integrator and employing a feedforward path, these systems and methods can provide a more efficient and stable solution for the ADC, thereby reducing hardware complexity and improving overall performance.

[0029] Figure 1 This is a block diagram of an example of a Δ-Σ modulator 100. In this embodiment, the Δ-Σ modulator 100 receives an analog input 101 and generates a digital bit stream 109. Specifically, the analog input 101 is coupled to a loop filter 102, which in turn is coupled to a comparator 103. The output of the comparator 103 includes an integrator path 104 and a feedforward path 105.

[0030] Integrator path 104 includes a downsampler 106 and a digital integrator 107. Summer 108 adds the output of feedforward path 105 to the output of digital integrator 107 to produce bit stream 109. Bit stream 109 is also provided to DAC 110, which tracks analog input 101.

[0031] Analog input 101 provides an initial signal to loop filter 102. Loop filter 102 may include, for example, an integrator or a low-pass filter, which provides poles at DC or low frequencies. Loop filter 102 may be implemented in continuous or discrete time. Furthermore, loop filter 102 may include a second-order (or higher-order) filter. It may also include passive or active configurations. Thus, loop filter 102 processes analog input 101 and sends the resulting filtered analog signal to comparator 103.

[0032] Comparator 103 converts the filtered analog signal into a digital output signal, which is then simultaneously sent to integrator path 104 and feedforward path 105. In different implementations, comparator 103 may be a single-bit or multi-bit comparator.

[0033] Downsampler 106 downsamples the integrator path 104 data at a lower clock frequency, thereby reducing the bit width of the comparator 103 signal output to, for example, reduce hardware cost (possibly at the cost of data loss). However, in some embodiments, the bit width may remain the same after downsampling. Digital integrator 107 operates at the same clock frequency as downsampler 106.

[0034] Digital integrator 107 receives the downsampled digital output from downsampler 106 and increments, maintains, or decrements its internal state accordingly. Summer 108 adds the results of digital integrator 107 and feedforward path 105 to produce bit stream 109, which represents the digital output of Δ-Σ modulator 100.

[0035] DAC 110 also receives bitstream 109 and converts it into an analog signal. In some cases, DAC 110 can include current-mode, resistive, or capacitive types. Furthermore, there are at least two ways to scale DAC 110 (where "scaling" refers to how the DAC's digital input values ​​are mapped to a specific analog output level): binary or thermometric, where the former gives a small coverage area and large element mismatch, while the latter does the opposite. Binary scaling assigns a power-of-2 weight to each digital bit, making it compact and efficient for a high-resolution DAC. In contrast, thermometric scaling uses equal weighting units for each bit, which enhances linearity and minimizes glitches. A hybrid version can also be implemented, where the most significant bit (MSB) is thermometrically scaled, while the least significant bit (LSB) is binary. Moreover, this scaling applies to current-mode, resistive, and capacitive DACs. Its analog output can then be fed back into loop filter 102 to complete the feedback loop.

[0036] In the Δ-Σ modulator 100, the loop filter 102 operates in the analog domain. The comparator 103 and DAC 110 convert signals between the analog / digital and digital / analog domains, respectively. Importantly, both the integrator path 104 and the feedforward path 105 operate in the digital domain: the comparator 103 operates at a frequency equal to the sampling frequency. The clock operation is performed by the digital integrator 107 at a lower frequency. operate.

[0037] In some cases, the operation of the downsampler 106 can be limited by the downsampling factor "n", such that .

[0038] Digital integrator 107 can be a simple non-delayed integrator. Alternatively, digital integrator 107 can be a delayed integrator. Alternatively, digital integrator 107 can be sized with DAC 110 to ensure that its output word, after being summed by summer 108 and feedforward path 105, does not exceed the bit capacity of the DAC.

[0039] The digital integrator 107 allows the DAC 110 to output a DC feedback signal to compensate for analog input offset, thereby enabling fine quantization and reducing quantization noise while maintaining a large dynamic range. This allows for ripple reduction on the digital integrator 107, as well as the benefits of the analog loop filter 102 design, whether passively or actively configured.

[0040] Figure 2 This is a detailed block diagram of an example of a Δ-Σ modulator 200. In this embodiment, modulator 200 includes a digital amplifier (Afb) 201 in feedforward path 105, and integrator path 104 includes an accumulator 202 coupled to digital amplifier (A) 203—both positioned between comparator 103 and downsampler 106. Digital integrator 107 is implemented by summer 204 and flip-flop 205. In various embodiments, accumulator 202 may be implemented as... Finite Input Response (FIR) filters, etc.

[0041] Comparator 103 provides its digital output to accumulator 202 in integrator path 104 and digital amplifier 201 in feedforward path 105. In some cases, digital amplifier 201 can add stability to modulator 200, especially when using a feedback DAC. Digital amplifier 201 can also provide its output to summer 108.

[0042] Simultaneously, accumulator 202 can generate a running average of the input values ​​as its output (e.g., the average of the last four samples), thereby effectively filtering the output of comparator 103 so that only selected frequency components are present. Digital amplifier 203 can normalize the output of accumulator 202 and compensate for filtering losses before the signal is received by downsampler 106, thereby generating a running average of the values ​​received by accumulator 202.

[0043] by The operating digital integrator 107 receives the downsampled digital output from the downsampler 106 and increments, holds, or decrements its internal state accordingly. The summer 108 adds the outputs of the integrator path 104 and the feedforward path 105 to produce a bit stream 109.

[0044] In operation, accumulator 202 provides information to digital amplifier 203 from samples not timed by digital integrator 107. Specifically, accumulator 202 can sum the previous n samples of the comparator's digital output, expressed as:

[0045]

[0046] The output of accumulator 202 can be normalized by digital amplifier 203. It can then be truncated to prevent sub-LSB output, such as... Figure 5 The modulator 500 is shown. Alternatively, truncation can be performed after the digital integrator, as shown. Figure 4 The modulator 400 is shown.

[0047] Figure 3This is a flowchart illustrating an example of a method 300 for operating digital components of a Δ-Σ modulator 200. In various embodiments, method 300 may be performed by the Δ-Σ modulator 200.

[0048] Specifically, method 300 begins at 301. At 302, method 300 begins with... Operate comparator 103. This ensures that comparator 103 receives analog input 101 and produces digital output at a selected sampling frequency.

[0049] At 303, method 300 averages and normalizes the output of comparator 103. For this purpose, the output of accumulator 202 can present a value (-1, 0, or 1) based on the accumulation (including truncation) of n samples. For example, if n=4, accumulator 202 can output the average of four values ​​(after receiving the fourth value). In this case, the first three samples are delayed, except for the last sample. Digital amplifier 203 then normalizes the average signal output of accumulator 202 (e.g., by dividing the output by 4).

[0050] At 304, method 300 operates at a lower frequency. Operating integrator 107 reduces circuit complexity and improves stability, but it increases or shifts the poles added by digital integrator 107. In some cases, the circuit can be operated by shifting the clock phase between different blocks. At 305, method 300 uses the sampling frequency... Provide a feedforward path 105 for the comparator output.

[0051] At 306, the output of digital integrator 107 and the output of feedforward path 105 are added by summer 108, such that the former generates a pole compensated by the latter through summation. This stabilizes the feedback loop by canceling out the effect of the pole introduced by digital integrator 107 via the zeros from feedforward path 105. Method 300 ends at 307.

[0052] To illustrate the implementation scheme of the Δ-Σ modulator as described in this article, Figure 4 A Δ-Σ modulator 400 is depicted. As shown, the Δ-Σ modulator 400 receives an analog input 101 and generates a bit stream 109. It includes a loop filter 102, a comparator 103, an accumulator (FIR filter) 202, digital amplifiers 201 and 203, flip-flops, latches or clock digital units 106, 205 and 401, and summers 108 and 204. 111、 112. The cutoff circuit (“cutoff”) 402, DAC controller 403, and feedback DAC 404 are coupled as shown in the figure. In this embodiment, comparator 103 and flip-flop 401 are based on Operation 111, while triggers 106 and 205 are based on Operation 112.

[0053] In operation, analog input 101 provides an initial signal to loop filter 102. Loop filter 102 processes analog input 101 and sends the filtered signal to comparator 103. Comparator 103 converts the filtered analog signal into a digital output and then sends it to flip-flop 401. Flip-flop 401 also... 111 operates and provides its output to digital amplifier 201, which passes the adjusted output (with digital gain) to summer 108 along feedforward path 105.

[0054] In integrator path 104, FIR filter 206 provides a filtered signal (e.g., the running sum of "n" values) to digital amplifier 203, which applies a selected gain to normalize the output of FIR filter 206 (to produce a running average). Flip-flop 106, operating at 112, receives the output of digital amplifier 203, downsamples it, and provides the downsampled output to summer 204. Flip-flop 205 is coupled to one of the outputs and one of the inputs of summer 204, thus also acting as a... 107 is a digital integrator operating on 112.

[0055] Cutoff 402 reduces the bit width of the signal to reduce the number of components required in the feedback DAC 404. Summer 108 combines the output signal from integrator path 104 with the output signal from feedforward path 105 to provide bit stream 109 as a digital representation of analog input 101.

[0056] DAC controller 403 receives the digital output from summer 108 and modulates the signal before providing it to feedback DAC 404. Modulation may include, for example, DEM and conversion from binary to thermometer encoding. Feedback DAC 404 applies a compensation analog signal to loop filter 102 to complete the feedback loop.

[0057] For example, comparator 103 can be a 1-bit quantizer, to... It generates a 1-bit bitstream of 0 or 1. The digital integrator 107 can be configured to operate at a reduced frequency. Run, which is selected as the better in this example. 4 times lower. Accumulator 202 can be implemented as an averaging filter and is given a length of 4 equal to the downsampling ratio.

[0058] Use and Figure 4In the same implementation, truncation can be applied after integration, so the normalized output of accumulator 101 in 203 is [-1, -0.5, 0, 0.5, 1]. The number of levels in digital integrator 107 can be selected based on DAC 110, since the number of levels after summation in 108 should not exceed the number of levels in DAC 110. In this example, DAC 110 can be selected as 4-bit, which allows 16 levels. Therefore, digital integrator 107 can have 29 levels, such that after LSB truncation in 402, 15 levels are retained.

[0059] Figure 5 An alternative approach is presented, where truncation is performed before downsampling in 106, resulting in the normalized accumulator output at 203 being [-1, 0, 1]. In this case, the digital integrator 107 can have 15 levels, so that after summing in 108, it can then have 16 levels, which are presented to the DAC 110. In this case, no effective data loss occurs because the feedforward path 105 is not truncated.

[0060] To illustrate another implementation of the Δ-Σ modulator as described in this article Figure 5 A Δ-Σ modulator 500 is depicted. As shown, the Δ-Σ modulator 500 receives an analog input 101 and generates a bit stream 109. The following components are included: loop filter 102, comparator 103, accumulator (FIR filter) 202, comparator 501, digital amplifiers 201 and 203, flip-flops, latches or clock digital units 106, 205 and 401, summers 108 and 204. 111、 112. The DAC controller 403 and the feedback DAC 404 are coupled as shown in the figure. In this embodiment, the comparator 103 and the flip-flop 401 are based on... Operation 111, while triggers 106 and 205 are based on Operation 112.

[0061] and Figure 4 Compared to the Δ-Σ modulator 400, modulator 500 includes comparator 501, which truncates the output of FIR filter 202 before being downsampled by trigger 106, such that the output of summer 204 is added to the output of digital amplifier 201 and then matched with the number of bits of bit stream 109 / DAC controller 403.

[0062] Typically, truncation of digital integrators ( Figure 4 ) can provide more than truncated FIR ( Figure 5Better performance is possible, but it might require a larger digital integrator, which is feasible for small n. Furthermore, in some cases, truncation can be optional, but omitting truncation might increase the number of components in DAC 210. Thus, modulator 400 can be considered suitable for processing high-frequency analog input signals 101 because truncation after digital integrator 107 allows for efficient processing of rapidly changing inputs (e.g., audio processing). Conversely, modulator 500 can be considered suitable for processing DC-type analog input signals 101 because truncation before downsampling 106 enhances the performance of signals with slower changes (e.g., sensor data acquisition, where the focus is on capturing steady-state or slowly changing signals).

[0063] In speed-priority scenarios, the order of the accumulator and digital integrator can be reversed. In this architecture, the digital integrator can operate at full speed, receiving additional gain to manage the increased number of samples compared to other configurations. This gain compensates for the additional samples processed by the digital integrator, ensuring the output remains consistent with the desired signal characteristics. The integrator output can be truncated after the integration process. Alternatively, the accumulator output can also be truncated.

[0064] In various embodiments, implementing a downsampled digital integrator within the feedback loop of the Δ-Σ modulator enhances stability without requiring analog compensation. Downsampling the digital integrator shifts the added poles to a lower frequency, where they can be canceled out by corresponding digital zeros. This design improves the flexibility of the loop filter and enhances stability and robustness, making it suitable for high-resolution applications with reduced hardware complexity. Operating the digital integrator at a lower frequency than the comparator reduces hardware and power consumption, making the circuit more efficient.

[0065] In many implementations, the systems and methods described herein can be incorporated into a wide range of electronic devices, including, for example, computer systems or information technology (IT) products; consumer devices or appliances; scientific instruments; industrial robots; medical or laboratory electronic devices; transportation vehicles such as automobiles, buses, trucks, trains, ships, and airplanes; military equipment, etc.

[0066] For the sake of brevity, conventional techniques are not described in detail herein. Furthermore, the connecting lines shown in the figures contained herein are intended to illustrate relationships (e.g., logical relationships) or physical couplings (e.g., electrical couplings) between the various elements. However, it should be noted that alternative relationships and connections may be used in other embodiments. Additionally, the circuit system described herein may be implemented in silicon or another semiconductor material, or alternatively, it may be formed using discrete components on a printed circuit board.

[0067] Although various systems and methods have been described herein with reference to specific embodiments, modifications and changes may be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included. It is not intended that any benefit, advantage, or solution to a problem described herein with reference to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0068] This document refers to a device as "configured" or a device "configured to" perform certain operations. This may include selecting predefined logic blocks and logically associating them. It may also include programming and modifying the computer software-based logic of the control device, wiring discrete hardware components, or a combination thereof. A device thus configured is physically designed to perform the specified operations.

[0069] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate a temporal or other priority ordering of such elements. The term “coupled” or “operably coupled” is defined as a connection, but not necessarily a direct connection or a mechanical connection. Unless otherwise stated, the term “a / an / a kind” is defined as one (kind) or more (kinds). The terms “comprise” (and any form of inclusion, such as “comprises” and “comprising”), “have” (and any form of having, such as “has” and “having”), “include” (and any form of including, such as “includes” and “including”), and “contain” (and any form of containing, such as “contains” and “containing”) are open-ended linking verbs. Therefore, a system, apparatus, or device that “comprises,” “has,” “includes,” or “contains” one or more elements possesses, but is not limited to, only possessing, the one or more elements. Similarly, a method or process that "includes," "has," "contains," or "comprises" one or more operations has, but is not limited to, having only one or more operations.

Claims

1. A Δ-Σ modulator, characterized in that, include: A comparator configured to receive an analog input and provide a digital output at a sampling frequency, wherein the digital output is applied to an integrator path and a feedforward path; The digital integrator in the integrator path, wherein the digital integrator is configured to operate at a clock frequency less than the sampling frequency. as well as A summer is configured to add the output of the integrator path to the output of the feedforward path to produce a bit stream.

2. The Δ-Σ modulator according to claim 1, characterized in that, Additionally, a downsampler is included in the integrator path, wherein the downsampler is configured to provide a downsampled digital signal at the clock frequency to the digital integrator.

3. The Δ-Σ modulator according to claim 1, characterized in that, Additionally, it includes an accumulator in the integrator path, wherein the accumulator is configured to receive the digital output and provide a running sum of the digital output.

4. The Δ-Σ modulator according to claim 3, characterized in that, The accumulator includes a finite impulse response (FIR) filter.

5. The Δ-Σ modulator according to claim 3, characterized in that, The accumulator outputs the average of n values ​​after receiving the nth value, and the digital amplifier is configured to divide the output by n.

6. The Δ-Σ modulator according to claim 3, characterized in that, Additionally, a digital amplifier is included, coupled to the accumulator in the integrator path, wherein the digital amplifier is configured to normalize the running sum of the digital output and provide a running average of the digital output.

7. The Δ-Σ modulator according to claim 6, characterized in that, Additionally, a truncation is included, coupled between the accumulator and the digital integrator, wherein the truncation is configured to reduce the bit width of the accumulator's output.

8. The Δ-Σ modulator according to claim 1, characterized in that, Additionally, a truncation is included, coupled between the digital integrator and the summer, wherein the truncation is configured to reduce the bit width of the output of the digital integrator.

9. A Δ-Σ modulator, characterized in that, include: A comparator configured to receive analog input; An integrator path configured to receive the digital output of the comparator, wherein the integrator path includes a digital integrator configured to operate at a clock frequency less than the sampling frequency of the comparator, and wherein the digital integrator adds poles to the transfer function of the Δ-Σ modulator. as well as A feedforward path is configured to receive the digital output of the comparator and compensate for the poles.

10. A method in an analog-to-digital converter (ADC), characterized in that, The method includes: A comparator that operates at the sampling frequency is used to generate a digital output; The digital output is provided to the integration path and the feedforward path; The data in the integration path is downsampled to a frequency lower than the sampling frequency; After the downsampling, the data in the integration path is integrated using a digital integrator; and The integrated downsampled data from the integration path is combined with the digital output to generate a bit stream.

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