On-chip capacitor structure and preparation method thereof

Abstract

The invention discloses an on-chip capacitor structure and a preparation method thereof, and the structure comprises a substrate, a first metal layer which is located at the center of a first surface of the substrate; the second metal layer is divided into a first area and a second area, the first area is located on the first surface of the substrate, and the second area is located above the first metal layer; wherein the second region is higher than the first region, so that a vertical distance is formed between the first metal layer and the second metal layer; the overlapped parts of the second metal layer and the first metal layer in the second region have relative areas; and the vertical distance and the relative area are used for regulating and controlling the capacitance.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum chip technology, specifically to an on-chip capacitor structure and its fabrication method. Background Technology

[0002] The on-chip capacitor of a superconducting quantum chip is its core passive component, and its performance (such as low loss and high stability) directly determines the coherence time and computational reliability of the qubits. To improve chip integration and performance, current research is moving from traditional planar designs to more compact and efficient structures.

[0003] Currently, capacitive devices on superconducting quantum chips are all two-dimensional capacitors. For example, coupling capacitors and bit capacitors are implemented using closely spaced metal films, with the electric field distributed between the films. The capacitance is approximately proportional to the length of the opposing edges of the two metal films. In some cases, if a larger capacitance is required, longer opposing edges of the metal films need to be designed, potentially occupying more chip area and resulting in lower integration density. Summary of the Invention

[0004] To address the aforementioned deficiencies in this field, this application aims to provide an on-chip capacitor structure and its fabrication method.

[0005] According to one aspect of this application, an on-chip capacitor structure is provided, comprising: Substrate, The first metal layer is located in the central region of the first surface of the substrate; The second metal layer is divided into a first region and a second region. The first region is located on the first surface of the substrate, and the second region is located above the first metal layer. The second region is higher than the first region, so that there is a vertical spacing between the first metal layer and the second metal layer. The overlapping portion between the second metal layer and the first metal layer in the second region has a relative area; The vertical spacing and relative area are used to regulate the capacitance.

[0006] According to some embodiments of this application, a cavity or silicon oxide layer is provided between the first metal layer and the second metal layer.

[0007] According to some embodiments of this application, the substrate thickness is 300-500 nm; the thickness of the first metal layer is 100-400 nm; and the thickness of the second metal layer is 400-600 nm.

[0008] According to some embodiments of this application, the thickness of the silicon oxide layer is 200-3000 nm.

[0009] According to some embodiments of this application, the vertical spacing is 200-3000 nm.

[0010] According to some embodiments of this application, the relative area is 2500-250000 μm. 2 .

[0011] According to some embodiments of this application, the substrate is a sapphire substrate or a silicon substrate; the material of the first metal layer is aluminum, tantalum or niobium; and the material of the second metal layer is aluminum.

[0012] According to another aspect of this application, a method for fabricating the above-described on-chip capacitor structure is also provided, comprising: A first metal thin film is deposited on the first surface of the substrate; A first photoresist is spin-coated onto the surface of a first metal thin film to prepare a first photoresist pattern; The first photoresist pattern is etched to obtain the first metal layer, thus forming the bottom circuit. A second photoresist is spin-coated onto the surface of the bottom circuit to prepare a second photoresist pattern; The second photoresist pattern is subjected to thermal reflow treatment to obtain a second photoresist pattern with arc-shaped edges. A second metal thin film is deposited on the first surface of the substrate and on the surface of a second photoresist pattern with arc-shaped edges; A third photoresist is spin-coated onto the surface of the second metal thin film to prepare a third photoresist pattern. The third photoresist pattern is etched, and the remaining first, second, and third photoresists are removed to obtain the second metal layer, thus obtaining the on-chip capacitor structure.

[0013] According to some embodiments of this application, the thermal reflow process includes: placing the substrate on a hot plate, heating it from 110-120°C to a target temperature of 140-160°C, and placing it for 6-10 minutes to make the edge of the second photoresist pattern arc-shaped.

[0014] According to one aspect of this application, another method for fabricating the above-described on-chip capacitor structure is provided, comprising: A first metal thin film is deposited on the first surface of the substrate; A first photoresist is spin-coated onto the surface of a first metal thin film to prepare a first photoresist pattern; The first photoresist pattern is etched to obtain the first metal layer, thus forming the bottom circuit. A second photoresist and a third photoresist are spin-coated onto the surface of the bottom circuit to prepare a second photoresist pattern. Silicon oxide is deposited on the surface of the first metal layer by a second photoresist pattern, and the second and third photoresists are stripped to obtain a silicon oxide layer covering the surface of the first metal layer. A second metal thin film is deposited on the first surface of the substrate and the surface of the silicon oxide layer; A fourth photoresist is spin-coated onto the surface of the second metal film to prepare a third photoresist pattern; The third photoresist pattern is etched, and the residual fourth photoresist is removed to obtain the second metal layer, thus obtaining the on-chip capacitor structure. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the on-chip capacitor structure in an example embodiment of this application; Figure 2 This is a schematic diagram of an on-chip capacitor structure according to another embodiment of this application; Figure 3 This is a flowchart of an example embodiment of the on-chip capacitor structure of this application; Figure 4 A flowchart illustrating an on-chip capacitor structure according to another embodiment of this application; Figure 5 This is a schematic diagram of the structure of the first metal layer in an example embodiment of this application; Figure 6 This is a three-dimensional flowchart of the fabrication method of the on-chip capacitor structure in the example embodiment of this application; Figure 7 This is a three-dimensional structural diagram of an on-chip capacitor in an example embodiment of this application; Figure 8 To compare the simulation results of the two-dimensional capacitor and the capacitor structure in this application. Detailed Implementation

[0016] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0018] Unless otherwise specified, this application is conducted under standard conditions or conditions recommended by the manufacturer. The raw materials or excipients used, as well as the reagents or instruments used, whose manufacturers are not specified, are all conventional products that can be obtained commercially.

[0019] The following is a detailed description of this application.

[0020] With the development of quantum measurement and control and quantum algorithms, larger-scale and more-qubit chips will become increasingly in demand. If such two-dimensional capacitor devices are used, very large-area chips will be required, which will not only increase the cost and difficulty of processing, but also occupy more valuable space in the refrigerator, resulting in a sharp drop in overall cost-effectiveness.

[0021] This application provides an on-chip capacitor structure that occupies a small chip area while having a large capacitance, thereby saving chip space and making the design more flexible.

[0022] In some examples, the on-chip capacitor structure of this application, such as Figure 1 or Figure 2 As shown, it includes: a substrate Z, a first metal layer B, and a second metal layer C.

[0023] The first metal layer B is located in the central region of the first surface of the substrate Z; The second metal layer C (C') is divided into a first region C1 and a second region C2. The first region is located on the first surface of the substrate, and the second region covers the first metal layer. In this region, the second region C2 is higher than the first region C1, thus creating a vertical spacing d between the first metal layer B and the second metal layer C. The overlapping portion between the second metal layer and the first metal layer in the second region has a relative area A; The vertical spacing D and the relative area A are used to regulate the capacitance.

[0024] Optionally, such as Figure 5 The diagram shown is a schematic representation of the structure of the substrate Z and the first metal layer B.

[0025] Optionally, a silicon oxide layer G is provided between the first metal layer B and the second metal layer C (C').

[0026] Optionally, the substrate Z has a thickness of 300-500 nm; the first metal layer B has a thickness of 100-400 nm; and the second metal layer C (C') has a thickness of 400-600 nm. Optionally, the thickness of the silicon oxide layer G is 200-3000 nm.

[0027] Optionally, the vertical spacing d is 200-3000 nm. The relative area A is 2500-250000 μm 2 Optionally, the substrate Z is a sapphire substrate or a silicon substrate; the material of the first metal layer B is aluminum, tantalum or niobium; and the material of the second metal layer C (C') is aluminum.

[0028] In some examples, the fabrication method of the on-chip capacitor structure described above in this application, such as... Figure 3 As shown or Figure 6 As shown, it includes: Step I: Deposit a first metal thin film 1 on the first surface of substrate Z; Steps II-III: Spin-coat the surface of the first metal thin film 1 with the first photoresist 2 to prepare the first photoresist pattern 3; Steps IV-V: Etch the first photoresist pattern 3 to obtain the first metal layer B and fabricate the bottom circuit; Steps VI-VII: Spin-coat the second photoresist 4 onto the surface of the bottom circuit to prepare the second photoresist pattern 5; Step VIII: Perform thermal reflow treatment on the second photoresist pattern 5 to obtain a second photoresist pattern 6 with arc-shaped edges; Step IX: Deposit a second metal thin film 7 on the first surface of substrate Z and the surface of the second photoresist pattern 6 with arc-shaped edges; Steps X-XI: Spin-coat the surface of the second metal thin film 7 with a third photoresist (not shown in the figure) to prepare a third photoresist pattern; etch the third photoresist pattern and remove the residual first, second and third photoresist to obtain the second metal layer C.

[0029] Optionally, the thermal reflow process includes: placing the substrate on a hot plate and heating it from 110-120°C to 140-160°C for 6-10 minutes to make the edge of the second photoresist pattern arc-shaped.

[0030] In some examples, the fabrication method of the on-chip capacitor structure described above in this application, such as... Figure 4 As shown, it includes: Step I: Deposit a first metal thin film 1 on the first surface of substrate Z; Steps II-III: Spin-coat the surface of the first metal thin film 1 with the first photoresist 2 to prepare the first photoresist pattern 3; Steps IV-V: Etch the first photoresist pattern 3 to obtain the first metal layer B and fabricate the bottom circuit; Steps VI-VII: Spin-coat the second photoresist 8 and the third photoresist 9 on the surface of the bottom circuit to prepare the second photoresist pattern 10; Steps VIII-IX: Deposit silicon oxide 11 on the surface of the first metal layer B through the second photoresist pattern 10, and strip the second and third photoresists to obtain a silicon oxide layer G covering the surface of the first metal layer; Step X: Deposit a second metal thin film 12 on the first surface of substrate Z and the surface of silicon oxide layer G; Step XI: Spin-coat a fourth photoresist (not shown in the figure) onto the surface of the second metal thin film 12 to prepare a third photoresist pattern; etch the third photoresist pattern and remove the residual fourth photoresist to obtain the second metal layer C'.

[0031] In some examples, the silicon oxide layer may be retained or removed, which creates a difference in the dielectric constant of the materials between the metal film layers and can also adjust the capacitance value of the on-chip capacitor structure of this application.

[0032] The on-chip capacitor structure of this application, or the on-chip capacitor structure prepared by the method of this application, has a wide range of capacitance values ​​that can be designed. The capacitance can be adjusted over a large range by adjusting the relative area and spacing of the two metal films within a small range. This capacitor occupies less space, improving integration density. The capacitor of this application can be used as a coupling capacitor and a bit capacitor in superconducting quantum chip circuits; it offers high design flexibility, can be used as various capacitors involved in superconducting quantum chips, and can achieve coupling of multiple lines, improving the flexibility of quantum chip circuit design.

[0033] The technical solution of this application will be further described below with reference to specific embodiments.

[0034] Example 1 Niobium films of 100-400 nm were deposited on polished sapphire substrates using sputtering. S1813 photoresist was spin-coated onto the niobium film surface at 3000 rpm for 1 minute, and then baked on a hot plate at 115℃ for 2 minutes. According to the circuit layout, ultraviolet exposure is performed in the laser direct writing system. MF319 developer is used to develop the photoresist in the exposed area for 1 minute to completely dissolve the photoresist and make the photoresist layer present the first photoresist pattern.

[0035] Reactive ion etching was used to dry etch areas not covered by photoresist to remove the exposed niobium film. CF4 was used as the etching gas with a flow rate of 30 sccm, a reaction power of 100 W, and a reaction pressure of 2 Pa.

[0036] Soak in acetone solution and place in an ultrasonic cleaner for 5 minutes, then soak in isopropanol solution and place in an ultrasonic cleaner for 1 minute to remove residual photoresist and obtain the bottom circuit.

[0037] Spin-coat the bottom circuit surface with SPR220 photoresist at a speed of 2000-3000 rpm for 1 minute, and then bake on a hot plate at 115℃ for 2 minutes.

[0038] According to the circuit layout, perform ultraviolet exposure in the laser direct writing system, and use MF319 developer for 1-2 minutes to completely dissolve the photoresist in the exposed area, so that the photoresist layer presents the layout pattern.

[0039] The substrate is placed on a hot plate for reflow heating, starting at 115°C and increasing to 140°C for 7 minutes, so that the edges of the photoresist layer become curved.

[0040] In-situ ion beam etching was first performed on the surface of the substrate at a voltage of 300V and a beam current of 20mA for 3 minutes; then an aluminum film with a thickness of 500nm was deposited by vapor deposition.

[0041] The aluminum film is patterned, and the exposed aluminum film is then immersed in aluminum etching solution Type A for wet etching for 8-10 minutes.

[0042] The substrate was placed in a reactive ion etching apparatus and treated with oxygen plasma at an oxygen flow rate of 50 sccm, a power of 50 W, and a pressure of 20 Pa for 30 seconds. Then it was immersed in a methylpyrrolidone solution and the container was placed in a water bath at 80°C for 10 hours to remove the remaining photoresist on the bottom layer.

[0043] Example 2 A 100-400 nm tantalum film was deposited on a polished silicon substrate using sputtering. S1813 photoresist was spin-coated onto the tantalum film at 3000 rpm for 1 minute, and then baked on a hot plate at 115°C for 2 minutes. According to the circuit layout, ultraviolet exposure is performed in the laser direct writing system. MF319 developer is used to develop the photoresist in the exposed area for 1 minute to completely dissolve the photoresist and make the photoresist layer present the first photoresist pattern.

[0044] Reactive ion etching was used to dry etch areas not covered by photoresist to remove the exposed tantalum film. CF4 was used as the etching gas with a flow rate of 30 sccm, a reaction power of 100 W, and a reaction pressure of 2 Pa.

[0045] Soak in acetone solution and place in an ultrasonic cleaner for 5 minutes, then soak in isopropanol solution and place in an ultrasonic cleaner for 1 minute to remove residual photoresist and obtain the bottom circuit.

[0046] Spin-coat the first layer of photoresist LOR10B onto the bottom circuit at 3000 rpm for 1 minute, and then bake it on a hot plate at 200°C for 10 minutes; then spin-coat the second layer of photoresist S1813 at 3000 rpm for 1 minute, and then bake it on a hot plate at 115°C for 2 minutes.

[0047] According to the circuit layout, perform ultraviolet exposure in the laser direct writing system, and use MF319 developer for 1 minute to completely dissolve the photoresist in the exposed area, so that the photoresist layer presents the layout pattern.

[0048] Silicon oxide was deposited by sputtering with an oxygen flow rate of 10 sccm, an argon flow rate of 50 sccm, a power of 150 W, and a deposition thickness of 200-1000 nm.

[0049] The substrate was immersed in a methylpyrrolidone solution for 10 hours, leaving only the silicon oxide film on the desired area.

[0050] In-situ ion beam etching was first performed on the substrate surface at a voltage of 300V and a beam current of 20mA for 3 minutes; then an aluminum film with a thickness of 500nm was deposited by vapor deposition.

[0051] The aluminum film is patterned by developing it with MF319 developer for 1-2 minutes to completely dissolve the photoresist in the exposed areas, revealing the patterned photoresist layer. The exposed aluminum film is then wet-etched by immersing the substrate in Type A aluminum etching solution for 8-10 minutes.

[0052] The on-chip capacitor structure described in this application occupies a small chip area while having a large capacitance, thereby saving chip space and making the design more flexible. In this capacitor structure, the area of ​​the overlapping portion of the metal layers, also known as the relative area, is denoted as A. The distance between the first and second metal layers is d, then the capacitance of the capacitor is C = A / d, where Let be the dielectric constant of the material between the two metal layers. Based on this model, the dielectric constant can be adjusted in the design. With the three parameters A and d, the capacitance value of the capacitor can be flexibly designed.

[0053] Using a conventional two-dimensional capacitor as a comparative example, simulation tests were performed on the two-dimensional capacitor and the simplified capacitor structure described in this application, respectively, while occupying the same chip area. The test results are attached. Figure 8 As shown, the capacitance value of the capacitor structure of this application is significantly increased compared to that of a two-dimensional capacitor; furthermore, according to the above formula, changing the area (A) of the pattern in the figure can cause a wide range of changes in the capacitance value.

[0054] In the on-chip capacitor structure of this application, the relative area can be defined by the processing layout (i.e., the first photoresist pattern, the second photoresist pattern, etc.); at the same time, the mutual distance between the two metal films opposite each other on the upper and lower sides of the capacitor can also be flexibly designed, and the distance can be changed by changing the spin coating speed of the photoresist layer or changing the thickness of the deposited silicon oxide.

[0055] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An on-chip capacitor structure, characterized in that, include: Substrate, The first metal layer is located in the central region of the first surface of the substrate; The second metal layer is divided into a first region and a second region. The first region is located on the first surface of the substrate, and the second region is located above the first metal layer. The second region is higher than the first region, so that there is a vertical spacing between the first metal layer and the second metal layer. The overlapping portion between the second metal layer and the first metal layer in the second region has a relative area; The vertical spacing and the relative area are used to regulate the electrical capacity.

2. The on-chip capacitor structure according to claim 1, characterized in that, There is a cavity or silicon oxide layer between the first metal layer and the second metal layer.

3. The on-chip capacitor structure according to claim 1 or 2, characterized in that, The substrate thickness is 300-500 nm; The thickness of the first metal layer is 100-400 nm; The thickness of the second metal layer is 400-600 nm.

4. The on-chip capacitor structure according to claim 2, characterized in that, The thickness of the silicon oxide layer is 200-3000 nm.

5. The on-chip capacitor structure according to claim 1, characterized in that, The vertical spacing is 200-3000nm.

6. The on-chip capacitor structure according to claim 1 or 5, characterized in that, The relative area is 2500-250000μm 2 .

7. The on-chip capacitor structure according to claim 6, characterized in that, The substrate is a sapphire substrate or a silicon substrate; The material of the first metal layer is aluminum, tantalum, or niobium; The material of the second metal layer is aluminum.

8. A method for fabricating an on-chip capacitor structure according to any one of claims 1-7, characterized in that, include: A first metal thin film is deposited on the first surface of the substrate; A first photoresist is spin-coated onto the surface of the first metal thin film to prepare a first photoresist pattern; The first photoresist pattern is etched to obtain the first metal layer, thus forming the bottom circuit. A second photoresist is spin-coated onto the surface of the bottom circuit to prepare a second photoresist pattern; The second photoresist pattern is subjected to thermal reflow treatment to obtain a second photoresist pattern with arc-shaped edges. A second metal thin film is deposited on the first surface of the substrate and on the surface of the second photoresist pattern with arc-shaped edges; A third photoresist is spin-coated onto the surface of the second metal thin film to prepare a third photoresist pattern; The third photoresist pattern is etched, and the remaining first, second, and third photoresists are removed to obtain the second metal layer, thus obtaining the on-chip capacitor structure.

9. The method for fabricating an on-chip capacitor structure according to claim 8, characterized in that, The thermal reflow process includes: placing the substrate on a hot plate, heating it from 110-120°C to a target temperature of 140-160°C, and placing it for 6-10 minutes to make the edge of the second photoresist pattern arc-shaped.

10. A method for fabricating an on-chip capacitor structure according to any one of claims 1-7, characterized in that, include: A first metal thin film is deposited on the first surface of the substrate; A first photoresist is spin-coated onto the surface of the first metal thin film to prepare a first photoresist pattern; The first photoresist pattern is etched to obtain the first metal layer, thus forming the bottom circuit. A second photoresist and a third photoresist are spin-coated onto the surface of the bottom circuit to prepare a second photoresist pattern. Silicon oxide is deposited on the surface of the first metal layer by the second photoresist pattern, and the second photoresist and the third photoresist are stripped off to obtain a silicon oxide layer covering the surface of the first metal layer; A second metal thin film is deposited on the first surface of the substrate and the surface of the silicon oxide layer; A fourth photoresist is spin-coated onto the surface of the second metal thin film to prepare a third photoresist pattern; The third photoresist pattern is etched, and the residual fourth photoresist is removed to obtain the second metal layer, thus obtaining the on-chip capacitor structure.

Images