LED chip and preparation method thereof
By adjusting the position and area arrangement of the dielectric holes in the LED chip, the problem of uneven current distribution was solved, the current was extended to the edge of the chip, and the chip brightness was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-27
- Publication Date
- 2026-05-12
AI Technical Summary
Existing LED chips with an all-around reflector structure have uneven current distribution when powered on, with current concentrated near the bottom of the top electrode, resulting in current congestion and low chip brightness.
In an LED chip, the orthographic projection of the dielectric aperture is located around the second electrode, and its area gradually increases in the direction away from the electrode, forming a circumferential or radial arrangement to promote the current to extend to the chip edge. The distribution of the contact resistance between the metal and the semiconductor in the dielectric aperture gradually changes, achieving a uniform current distribution.
By adjusting the area and arrangement of the dielectric vias, the current distribution becomes more uniform, thus improving the chip brightness.
Smart Images
Figure CN122028561A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of light-emitting diode technology, and in particular to an LED chip and its fabrication method. Background Technology
[0002] Currently, many light-emitting diodes (LEDs) employ an omnidirectional reflector (ODR) structure to improve reflection efficiency, thereby enhancing light extraction efficiency. This ODR structure comprises a semiconductor layer, a dielectric layer, and a specular reflective layer. To ensure an ohmic contact between the semiconductor layer and the specular reflective layer, dielectric vias are created in the dielectric layer, allowing the specular reflective layer to fill these vias and form an ohmic contact with the semiconductor layer.
[0003] However, when LED chips using omnidirectional reflectors are powered on, the current distribution is mainly concentrated in the area near the bottom of the top electrode. The uneven current distribution is not conducive to the current spreading to the edge of the chip, which can easily cause current congestion and ultimately result in lower chip brightness. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides an LED chip and its fabrication method, which enables the current to extend to the edge of the chip, resulting in a more uniform current distribution and improved chip brightness.
[0005] To achieve the above objectives, this application provides the following technical solution:
[0006] In a first aspect, this application provides an LED chip, comprising:
[0007] Bonded substrate;
[0008] The bonding layer, the specular reflection layer, the dielectric layer, and the epitaxial stack are stacked on one side of the bonding substrate in a direction away from the bonding substrate; the epitaxial stack includes a window layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked in a direction away from the bonding substrate; the dielectric layer has a plurality of dielectric holes; the specular reflection layer fills the dielectric holes and forms an ohmic contact with the window layer.
[0009] A first electrode located on the side of the bonding substrate opposite to the bonding layer;
[0010] And a second electrode located on the side of the epitaxial stack opposite to the bonding substrate;
[0011] In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is located outside the orthographic projection of the second electrode, and the area of the orthographic projection of the dielectric hole gradually increases along the direction away from the orthographic projection of the second electrode.
[0012] Optionally, in a plane parallel to the plane where the bonding substrate is located, the orthographic projection of the dielectric aperture is arranged around the orthographic projection of the second electrode in at least two circles, and along the direction away from the orthographic projection of the second electrode, the area of the orthographic projection of the dielectric aperture in the (i+1)th circle is greater than the area of the orthographic projection of the dielectric aperture in the ith circle, i≥1, and i is an integer.
[0013] Optionally, in a plane parallel to the plane of the bonding substrate, the orthographic projections of the dielectric vias in each ring have the same arrangement pattern, or at least some rings of the dielectric vias have different orthographic projection arrangements.
[0014] Optionally, in a plane parallel to the plane where the bonding substrate is located, at least a portion of the orthographic projections of the dielectric holes are arranged in a circular or polygonal ring.
[0015] Optionally, in a plane parallel to the plane of the bonding substrate, the orthographic projections of the dielectric holes are arranged radially with respect to the center of the orthographic projection of the second electrode, and the area of the orthographic projections of the dielectric holes gradually increases along any arrangement direction away from the orthographic projection of the second electrode.
[0016] Optionally, in a plane parallel to the plane where the bonding substrate is located, the number of orthographic projections of the dielectric holes along the first arrangement direction is greater than the number of orthographic projections of the dielectric holes along the second arrangement direction, wherein the size of the LED chip along the first arrangement direction is greater than the size of the LED chip along the second arrangement direction.
[0017] Optionally, in a plane parallel to the plane where the bonding substrate is located, the orthographic projection of the dielectric hole is circular; along the direction away from the orthographic projection of the second electrode, the radius of the orthographic projection of the innermost dielectric hole is not less than 2 μm, the radius of the orthographic projection of the outermost dielectric hole is not greater than 5 μm, and the spacing between the orthographic projections of each dielectric hole is not less than 5 μm.
[0018] Optionally, in a plane parallel to the plane where the bonding substrate is located, the distance between the orthographic projection of each of the dielectric holes and the orthographic projection of the second electrode is not less than 15 μm, and the distance between the orthographic projection of each of the dielectric holes and the edge of the LED chip is not less than 15 μm.
[0019] Optionally, the dielectric layer includes a SiO2 layer or a MgF2 layer.
[0020] Secondly, this application provides a method for fabricating an LED chip, comprising:
[0021] Provide a growth substrate;
[0022] An epitaxial stack is formed on one side of the growth substrate, the epitaxial stack comprising a second type semiconductor layer, an active layer, a first type semiconductor layer and a window layer stacked along a direction away from the growth substrate;
[0023] A dielectric layer is formed on the side of the window layer opposite to the growth substrate, and a plurality of dielectric holes are formed in the dielectric layer;
[0024] A mirror reflection layer is formed on the side of the dielectric layer opposite to the growth substrate. The mirror reflection layer fills the dielectric holes and forms an ohmic contact with the window layer.
[0025] A first sub-bonding layer is formed on the side of the mirror-reflective layer opposite to the growth substrate;
[0026] A bonding substrate is provided, and a second sub-bonding layer is formed on one side of the bonding substrate;
[0027] The first sub-bonding layer and the second sub-bonding layer are bonded together to form a bonding layer;
[0028] Remove the growth substrate;
[0029] A first electrode is formed on the side of the bonding substrate away from the bonding layer, and a second electrode is formed on the side of the epitaxial stack away from the bonding substrate;
[0030] In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is located outside the orthographic projection of the second electrode, and the area of the orthographic projection of the dielectric hole gradually increases along the direction away from the orthographic projection of the second electrode.
[0031] Compared with existing technologies, the above technical solution has the following advantages:
[0032] The LED chip provided in this application includes a bonding substrate and a bonding layer, a mirror reflection layer, a dielectric layer, and an epitaxial stack stacked on one side of the bonding substrate in a direction away from the bonding substrate. A first electrode is disposed on the side of the bonding substrate away from the bonding layer, and a second electrode is disposed on the side of the epitaxial stack away from the bonding substrate. The epitaxial stack stack includes a window layer, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in a direction away from the bonding substrate. The dielectric layer has multiple dielectric holes, and the mirror reflection layer fills the dielectric holes, thereby forming an ohmic contact with the window layer. That is, the window layer, dielectric layer, and mirror reflection layer form an omnidirectional reflector structure, reflecting light emitted from the active layer towards the bonding substrate side towards the second electrode side, improving light extraction efficiency. Unlike existing omnidirectional reflector structures where the dielectric holes in the dielectric layer have uniform sizes, resulting in uneven current distribution, this chip... In this application, within a plane parallel to the bonding substrate, the orthographic projection of the dielectric via is located outside the orthographic projection of the second electrode. Furthermore, the area of the orthographic projection of the dielectric via gradually increases along the direction away from the orthographic projection of the second electrode. That is, in the region close to the orthographic projection of the second electrode, the area of the orthographic projection of the dielectric via is relatively small, resulting in a smaller contact area between the metal and semiconductor within the dielectric via and a larger contact resistance, thus reducing the current flow. Conversely, in the region further away from the orthographic projection of the second electrode, the area of the orthographic projection of the dielectric via is larger, resulting in a larger contact area between the metal and semiconductor within the dielectric via and a smaller contact resistance. This promotes the current to extend away from the orthographic projection of the second electrode, i.e., towards the edge of the chip, making the current distribution more uniform and thereby improving the chip brightness. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a cross-sectional structural diagram of an LED chip provided in an embodiment of this application;
[0035] Figure 2 This is a schematic diagram of a cross-sectional structure of an epitaxial laminate.
[0036] Figure 3 This is a schematic diagram showing the orthographic projection of the second electrode and the orthographic projection of the dielectric hole in the dielectric layer in a plane parallel to the plane of the bonding substrate.
[0037] Figure 4This is another schematic diagram showing the orthographic projection of the second electrode and the orthographic projection of the dielectric hole in the dielectric layer in a plane parallel to the plane of the bonding substrate.
[0038] Figure 5 This is another schematic diagram showing the orthographic projection of the second electrode and the orthographic projection of the dielectric hole in the dielectric layer in a plane parallel to the plane of the bonding substrate.
[0039] Figure 6 This is another schematic diagram showing the orthographic projection of the second electrode and the orthographic projection of the dielectric hole in the dielectric layer in a plane parallel to the plane of the bonding substrate.
[0040] Explanation of reference numerals in the attached figures:
[0041] Bonding substrate 10; growth substrate 11; bonding layer 20; mirror reflection layer 30; dielectric layer 40; epitaxial stack 50; first electrode T1; second electrode T2; second type semiconductor layer 51; active layer 52; first type semiconductor layer 53; window layer 54; buffer layer 501; etch stop layer 502; ohmic contact layer 503; electrode bonding layer 504; roughening layer 505; current spreading layer 506; orthogonal projection of the second electrode T2'; orthogonal projection of the dielectric hole K1'; first arrangement direction X1; second arrangement direction X2. Detailed Implementation
[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.
[0044] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the accompanying drawings illustrating the device structure may be partially enlarged, not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.
[0045] As described in the background section, when current LED chips using omnidirectional reflectors are powered on, the current distribution is mainly concentrated in the area near the bottom of the top electrode. The uneven current distribution is not conducive to the current spreading to the edge of the chip, which can easily cause current congestion and ultimately result in low chip brightness.
[0046] Research has found that this is primarily due to the uniform size of the dielectric apertures in the dielectric layer of existing omnidirectional reflector structures. In LED chips, current is injected from the top electrode. When flowing through the omnidirectional reflector structure, it first flows laterally through the semiconductor layer, then through the dielectric apertures in the dielectric layer to enter the mirror layer. For dielectric apertures near the top electrode, the current only needs to flow a short lateral distance to pass through, while for those farther away, the current needs to travel a longer lateral distance. The longer the path, the greater the accumulated lateral resistance. Therefore, the current distribution is inherently concentrated in the area near the top electrode. If the dielectric apertures in the dielectric layer are of uniform size, because the path resistance of the dielectric apertures closer to the top electrode is lower, a large amount of current will still accumulate in the dielectric apertures closer to the top electrode for injection. This results in the current distribution being mainly concentrated in the area below the top electrode, leading to uneven current distribution, current congestion, and ultimately lower chip brightness.
[0047] In view of this, embodiments of this application provide an LED chip, Figure 1 This illustration shows a cross-sectional structural diagram of an LED chip provided in an embodiment of this application, as shown below. Figure 1 As shown, the LED chip includes a bonding substrate 10 and a bonding layer 20, a mirror reflection layer 30, a dielectric layer 40, and an epitaxial stack 50 stacked on one side of the bonding substrate 10 in a direction away from the bonding substrate 10. A first electrode T1 is disposed on the side of the bonding substrate 10 away from the bonding layer 20, and a second electrode T2 is disposed on the side of the epitaxial stack 50 away from the bonding substrate 10.
[0048] Figure 2 A schematic cross-sectional view of an epitaxial laminate 50 is shown, as follows. Figure 2As shown, the epitaxial stack 50 is first epitaxially grown on a growth substrate 11. The epitaxial stack 50 includes a second type semiconductor layer 51, an active layer 52, a first type semiconductor layer 53, and a window layer 54 stacked along a direction away from the growth substrate 11. Optionally, the second type semiconductor layer 51 can be an N-type AlGaInP confinement layer, the first type semiconductor layer 53 can be a P-type AlGaInP confinement layer, and the window layer 54 can be a P-type GaP window layer. Then, combined with... Figure 1 As shown, a dielectric layer 40 and a specular reflection layer 30 are sequentially formed on the side of the window layer 54 away from the growth substrate 11; a first sub-bonding layer is then formed on the side of the specular reflection layer 30 away from the growth substrate 11, and a second sub-bonding layer is formed on the side of the bonding substrate 10. The first and second sub-bonding layers are bonded together to form a bonding layer 20, so that the epitaxial stack 50 is bonded to the bonding substrate 10 from the side of its specular reflection layer 30 through the bonding layer 20. Then, the growth substrate 11 is removed, and a first electrode T1 is formed on the side of the bonding substrate 10 away from the bonding layer 20, and a second electrode T2 is formed on the side of the epitaxial stack 50 away from the bonding substrate 10 to obtain the LED chip structure.
[0049] Combination Figure 1 and Figure 2 As shown, when forming the dielectric layer 40, multiple dielectric holes K1 are formed in the dielectric layer 40. After the mirror reflection layer 30 is formed on the side of the dielectric layer 40 away from the growth substrate 11, the mirror reflection layer 30 fills the dielectric holes K1 and forms an ohmic contact with the window layer 54.
[0050] It is understandable that the window layer 54, the dielectric layer 40 and the mirror reflection layer 30 form an all-around reflector structure, thereby reflecting the light emitted from the active layer toward the bonding substrate 10 side toward the second electrode T2 side, thus improving the light extraction efficiency.
[0051] Unlike existing omnidirectional reflector structures where the dielectric holes in the dielectric layer have uniform dimensions, leading to uneven current distribution, the LED chip provided in this application embodiment has a dielectric hole K1 whose orthogonal projection is located outside the orthogonal projection of the second electrode T2 in a plane parallel to the plane of the bonding substrate 10. That is, in the direction perpendicular to the plane of the bonding substrate 10, the dielectric hole K1 and the second electrode T2 do not overlap, allowing the current to be extended away from the second electrode T2 through the ohmic contact point at the dielectric hole K1, preventing current accumulation below the second electrode T2. Furthermore, along the direction away from the orthogonal projection of the second electrode T2, the area of the orthogonal projection of the dielectric hole K1 gradually increases. In other words, in the region near the orthogonal projection of the second electrode T2, the area of the orthogonal projection of the dielectric via K1 is relatively small, resulting in a smaller contact area between the metal and semiconductor within the dielectric via K1 and a larger contact resistance, thus reducing the current flow. Conversely, in the region further away from the orthogonal projection of the second electrode T2, the area of the orthogonal projection of the dielectric via K1 is larger, resulting in a larger contact area between the metal and semiconductor within the dielectric via K1 and a smaller contact resistance. This causes the current to extend further away from the orthogonal projection of the second electrode T2, i.e., towards the edge of the chip, making the current distribution more uniform and thereby improving the chip brightness.
[0052] In practical applications, such as Figure 2 As shown, the epitaxial stack 50 may further include a buffer layer 501 (specifically, an N-type GaAs buffer layer), an etching stop layer 502 (specifically, an N-type GaInP etching stop layer), an ohmic contact layer 503 (specifically, an N-type GaAs ohmic contact layer), an electrode bonding layer 504 (specifically, an N-type GaInP electrode bonding layer), a roughening layer 505 (specifically, an N-type AlGaInP roughening layer), and a current spreading layer 506 (specifically, an N-type AlGaInP current spreading layer) stacked between the growth substrate 11 and the second type semiconductor layer 51, in a direction away from the growth substrate 11. Furthermore, when the growth substrate 11 is removed, the buffer layer 501 (specifically, an N-type GaAs buffer layer) and the etching stop layer 502 (specifically, an N-type GaInP etching stop layer) are also removed together due to the high selectivity of the etchant.
[0053] Figures 3-5 Three schematic diagrams are shown, illustrating the orthographic projection T2' of the second electrode and the orthographic projection K1' of the dielectric hole in the dielectric layer, both within a plane parallel to the plane of the bonding substrate. Figures 3-5As shown, optionally, in some embodiments of this application, in a plane parallel to the plane where the bonding substrate is located, the orthographic projection K1' of the dielectric aperture is arranged around the orthographic projection T2' of the second electrode in at least two circles, and along the direction away from the orthographic projection T2' of the second electrode, the area of the orthographic projection K1' of the (i+1)th circle of dielectric aperture is greater than the area of the orthographic projection K1' of the i-th circle of dielectric aperture, i≥1, and i is an integer. In this way, the area of the orthographic projection K1' of the dielectric aperture gradually increases along the direction away from the orthographic projection T2' of the second electrode, causing the current to extend in the direction away from the orthographic projection of the second electrode T2, that is, the edge direction of the chip, so that the current distribution is more uniform.
[0054] For example, such as Figures 3-5 As shown, in a plane parallel to the plane where the bonding substrate is located, the orthographic projections K1' of the dielectric holes are arranged in three concentric rings around the orthographic projection T2' of the second electrode. In the direction away from the orthographic projection T2' of the second electrode, the area of the orthographic projections K1' of the second ring of dielectric holes is larger than the area of the orthographic projections K1' of the first ring of dielectric holes, and the area of the orthographic projections K1' of the third ring of dielectric holes is larger than the area of the orthographic projections K1' of the second ring of dielectric holes.
[0055] Alternatively, in a plane parallel to the plane where the bonding substrate is located, along the direction away from the orthogonal projection T2' of the second electrode, the area of the orthogonal projection K1' of the (i+1)th ring of dielectric holes can be increased by 1.1 to 1.5 times relative to the area of the orthogonal projection K1' of the i-th ring of dielectric holes, depending on the specific circumstances.
[0056] It is understandable that, in a plane parallel to the plane of the bonding substrate, the orthographic projection K1' of each ring of dielectric holes is arranged around the orthographic projection T2' of the second electrode, which is beneficial to the uniformity of current spread in all directions away from the orthographic projection T2' of the second electrode.
[0057] It is also understandable that, such as Figures 3-4 As shown, optionally, the arrangement of the orthographic projections K1' of each ring of dielectric vias is identical within a plane parallel to the plane of the bonding substrate; for example, as... Figure 3 As shown, the orthographic projections K1' of each ring of dielectric holes are arranged in a circular pattern; for example, as... Figure 4 As shown, the orthographic projections K1' of each ring of dielectric vias are arranged in a square annular pattern. Alternatively, in a plane parallel to the plane of the bonding substrate, the orthographic projections K1' of at least some rings of dielectric vias may have different arrangements; for example, as shown... Figure 5 As shown, along the direction away from the second electrode's orthogonal projection T2', the first ring of dielectric holes's orthogonal projection K1' is arranged in a circular ring, the second ring of dielectric holes's orthogonal projection K1' is arranged in an octagonal ring, and the third ring of dielectric holes's orthogonal projection K1' is arranged in a square ring.
[0058] In a plane parallel to the plane of the bonding substrate, at least a portion of the orthographic projections K1' of the dielectric vias are arranged in a circular pattern (e.g., Figure 3 and Figure 5 The first ring of medium holes is shown as an orthographic projection), or it is in the form of a polygonal ring (as shown in the image). Figure 4 and Figure 5 (As shown in the orthographic projection of the second and third rings of dielectric holes), it also contributes to the uniformity of current spread in all directions along the orthographic projection T2' away from the second electrode.
[0059] Furthermore, it can be understood that, within a plane parallel to the bonding substrate, for any ring of dielectric vias, the area of the orthographic projection K1' of each via can be set to be the same, meaning that each via uses the same size. Alternatively, depending on the size of the LED chip, the area of the orthographic projection K1' of the dielectric vias in certain specific directions can be appropriately larger. For example, if the LED chip is square, since the path for lateral current expansion is relatively longer along the diagonal of the LED chip, the area of the orthographic projection K1' of the dielectric vias along the diagonal of the LED chip can be appropriately larger, meaning that the size of the dielectric vias K1 along the diagonal of the LED chip can be appropriately larger. This strengthens the lateral current expansion along the diagonal of the LED chip, resulting in a more uniform current distribution.
[0060] Furthermore, in a plane parallel to the plane where the bonding substrate is located, for any ring of dielectric vias, the orthographic projection K1' of each adjacent dielectric via can be set to have the same spacing. Alternatively, depending on the actual situation, the spacing of some adjacent dielectric vias' orthographic projection K1' can be appropriately increased or decreased to make the current distribution more uniform.
[0061] Of course, in a plane parallel to the plane where the bonding substrate is located, the arrangement density of the orthographic projection K1' of different rings of dielectric holes can be the same or different; the spacing of the orthographic projection K1' of adjacent rings of dielectric holes can be the same or different, depending on the specific situation.
[0062] Figure 6 This diagram illustrates another schematic representation of the orthographic projection T2' of the second electrode and the orthographic projection K1' of the dielectric via in the dielectric layer, both within a plane parallel to the plane of the bonding substrate. Figure 6As shown, in another optional embodiment of this application, in a plane parallel to the plane where the bonding substrate is located, the orthographic projection K1' of the dielectric aperture is arranged radially with respect to the center of the orthographic projection T2' of the second electrode, and the area of the orthographic projection K1' of the dielectric aperture gradually increases along any arrangement direction away from the orthographic projection T2' of the second electrode. This achieves the effect that the area of the orthographic projection K1' of the dielectric aperture gradually increases along the direction away from the orthographic projection T2' of the second electrode, causing the current to extend in the direction away from the orthographic projection of the second electrode T2, that is, the edge direction of the chip, so that the current distribution is more uniform.
[0063] Alternatively, in a plane parallel to the plane of the bonding substrate, along any arrangement direction away from the orthogonal projection T2' of the second electrode, the area of the orthogonal projection K1' of the dielectric hole can be increased sequentially by an increase ratio of 1.1 to 1.5 times, depending on the specific situation.
[0064] Understandably, in a plane parallel to the bonding substrate, compared to arranging the orthographic projection K1' of the dielectric vias in at least two loops around the orthographic projection T2' of the second electrode, arranging the orthographic projection K1' of the dielectric vias radially around the center of the orthographic projection T2' of the second electrode allows for more flexible design of the dielectric via arrangement as needed. For example, along different arrangement directions away from the orthographic projection T2' of the second electrode, the area of the orthographic projection K1' of the dielectric vias and the number of dielectric vias can be set differently to achieve a more uniform current distribution.
[0065] Further optional, in some embodiments of this application, such as Figure 6 As shown, in a plane parallel to the plane where the bonding substrate is located, the number of orthographic projections K1' of dielectric vias along the first arrangement direction X1 is greater than the number of orthographic projections K1' of dielectric vias along the second arrangement direction X2. The size of the LED chip along the first arrangement direction X1 is greater than the size of the LED chip along the second arrangement direction X2.
[0066] It is understandable that if the size of the LED chip along the first arrangement direction X1 is larger than the size of the LED chip along the second arrangement direction X2, then the path for the current to spread laterally along the first arrangement direction X1 is relatively longer. Therefore, the number of dielectric vias with orthographic projections K1' along the first arrangement direction X1 can be increased in a plane parallel to the plane where the bonding substrate is located, thereby enhancing the lateral spread of the current along the first arrangement direction X1 and making the current distribution more uniform.
[0067] For example, such as Figure 6 As shown, the LED chip is square. The first arrangement direction X1 can be the direction of the diagonal of the LED chip, and the second arrangement direction X2 can be the direction parallel to the edge of the LED chip.
[0068] Based on any of the above embodiments, optionally, in some embodiments of this application, in a plane parallel to the plane where the bonding substrate is located, the orthographic projection K1' of the dielectric hole is circular; along the direction away from the orthographic projection T2' of the second electrode, the radius of the orthographic projection K1' of the innermost dielectric hole is not less than 2μm, the radius of the orthographic projection K1' of the outermost dielectric hole is not greater than 5μm, and the spacing between the orthographic projections K1' of each dielectric hole is not less than 5μm.
[0069] Understandably, in actual processes, photolithography and etching are typically used to form multiple dielectric holes K1 in the dielectric layer 40. Due to the limitations of photolithography and etching processes, the final dielectric hole K1's orthogonal projection in a plane parallel to the plane of the bonding substrate is circular.
[0070] Furthermore, considering the limitations of photolithography and etching processes, the radius of the innermost dielectric aperture's projection K1' along the direction away from the second electrode's projection T2' should be no less than (i.e., greater than or equal to) 2 μm. However, considering that the ohmic contact point corresponding to the dielectric aperture K1 will also block the emitted light, the radius of the outermost dielectric aperture's projection K1' along the direction away from the second electrode's projection T2' should preferably be no greater than (i.e., less than or equal to) 5 μm, and the spacing between the projections K1' of each dielectric aperture should be no less than 5 μm, in order to minimize the influence of the ohmic contact point corresponding to the dielectric aperture K1 on the emitted light.
[0071] Based on any of the above embodiments, optionally, in some embodiments of this application, in a plane parallel to the plane where the bonding substrate is located, the distance between the orthographic projection K1' of each dielectric hole and the orthographic projection T2' of the second electrode is not less than 15μm, so as to avoid the current distribution in the region corresponding to the second electrode T2 and its vicinity, because the light emitted by the active layer corresponding to the second electrode T2 and its vicinity will still be blocked by the second electrode T2; and, in a plane parallel to the plane where the bonding substrate is located, the distance between the orthographic projection K1' of each dielectric hole and the edge of the LED chip is not less than 15μm, so as to avoid the current being too close to the edge of the LED chip, because the light emitted by the active layer that is too close to the edge of the LED chip cannot be emitted as effective light; that is, in a plane parallel to the plane where the bonding substrate is located, the dielectric holes K1 in the dielectric layer are mainly distributed in the middle region between the second electrode T2 and the edge of the LED chip, and the active layer corresponding to this part can form effective light emission.
[0072] Based on any of the above embodiments, optionally, in some embodiments of this application, the dielectric layer 40 may include a low-refractive-index and insulating transparent film layer such as a SiO2 layer or a MgF2 layer; the specular reflection layer may be a metal reflection layer.
[0073] Accordingly, embodiments of this application also provide a method for fabricating an LED chip, the method comprising:
[0074] S1: Reference Figure 2 As shown, a growth substrate 11 is provided.
[0075] Optionally, the growth substrate 11 can be a GaAs substrate.
[0076] S2: Reference Figure 2 As shown, an epitaxial stack 50 is formed on one side of the growth substrate 11. The epitaxial stack 50 includes a second type semiconductor layer 51, an active layer 52, a first type semiconductor layer 53, and a window layer 54 stacked in a direction away from the growth substrate 11.
[0077] Optionally, the second type semiconductor layer 51 can be an N-type AlGaInP confinement layer, the first type semiconductor layer 53 can be a P-type AlGaInP confinement layer, and the window layer 54 can be a P-type GaP window layer. Furthermore, the thickness of the P-type GaP window layer can be 0.1 μm-10 μm, preferably 0.5 μm-3 μm, and the doping concentration of the main body of the P-type GaP window layer can be 1E18 / cm². 3 The doping concentration of the surface layer of the p-type GaP window layer can reach 1E19 / cm². 3 above.
[0078] In practical applications, such as Figure 1 As shown, the epitaxial stack 50 may further include a buffer layer 501 (specifically, an N-type GaAs buffer layer), an etching stop layer 502 (specifically, an N-type GaInP etching stop layer), an ohmic contact layer 503 (specifically, an N-type GaAs ohmic contact layer), an electrode bonding layer 504 (specifically, an N-type GaInP electrode bonding layer), a roughening layer 505 (specifically, an N-type AlGaInP roughening layer), and a current spreading layer 506 (specifically, an N-type AlGaInP current spreading layer) located between the growth substrate 11 and the second type semiconductor layer 51 and stacked in a direction away from the growth substrate 11.
[0079] S3: Reference Figure 1 and Figure 2 As shown, a dielectric layer 40 is formed on the side of the window layer 54 away from the growth substrate 11, and a plurality of dielectric holes K1 are formed in the dielectric layer 40.
[0080] Optionally, the dielectric layer 40 may include a low-refractive-index and insulating transparent film layer such as a SiO2 layer or a MgF2 layer.
[0081] In actual processes, photolithography and etching are typically used to form multiple dielectric holes K1 in the dielectric layer 40.
[0082] S4: Reference Figure 1 and Figure 2 As shown, a mirror reflection layer 30 is formed on the side of the dielectric layer 40 away from the growth substrate 11. The mirror reflection layer 30 fills the dielectric hole K1 and forms an ohmic contact with the window layer 54.
[0083] Specifically, a metal reflective layer can be deposited on the surface of the dielectric layer 40 away from the growth substrate 11 as a mirror reflective layer 30. The metal reflective layer is electrically connected to the window layer 54 through the dielectric hole K1 and forms an ohmic contact after annealing.
[0084] S5: Reference Figure 1 and Figure 2 As shown, a first subbonding layer is formed on the side of the mirror reflection layer 30 opposite to the growth substrate 11.
[0085] S6: Reference Figure 2 As shown, a bonding substrate 10 is provided, and a second sub-bonding layer is formed on one side of the bonding substrate 10.
[0086] Optionally, the bonding substrate 10 can be a P-type low-resistivity silicon wafer.
[0087] S6: Reference Figure 2 As shown, the first sub-bonding layer and the second sub-bonding layer are bonded together to form a bonding layer 20.
[0088] Specifically, a first sub-bonding layer is deposited on the surface of the mirror reflection layer 30 away from the growth substrate 11, and a second sub-bonding layer is deposited on one side of the bonding substrate 10. Then, the first sub-bonding layer and the second sub-bonding layer are combined together by interdiffusion during the bonding process of heating and pressurization, so that the epitaxial stack 50 is bonded to the bonding substrate 10 from the side of its mirror reflection layer 30 through the bonding layer 20.
[0089] S7: Remove growth substrate 11.
[0090] It is understandable that when removing the growth substrate 11, the buffer layer 501 (specifically, an N-type GaAs buffer layer) and the etching stop layer 502 (specifically, an N-type GaInP etching stop layer) will also be removed along with the high selectivity of the etchant.
[0091] S8: Reference Figure 2 As shown, a first electrode T1 is formed on the side of the bonding substrate 10 away from the bonding layer 20, and a second electrode T2 is formed on the side of the epitaxial stack 50 away from the bonding substrate 10.
[0092] In the plane parallel to the bonding substrate, the orthographic projection of the dielectric hole K1 is located outside the orthographic projection of the second electrode T2, and the area of the orthographic projection of the dielectric hole K1 gradually increases along the direction away from the orthographic projection of the second electrode T2.
[0093] Unlike existing omnidirectional reflector structures where the dielectric holes in the dielectric layer have uniform dimensions, leading to uneven current distribution, the LED chip fabricated using the method provided in this application has a dielectric hole K1 whose orthogonal projection is located outside the orthogonal projection of the second electrode T2 in a plane parallel to the plane of the bonding substrate 10. That is, in a direction perpendicular to the plane of the bonding substrate 10, the dielectric hole K1 does not overlap with the second electrode T2. This allows the current to be extended away from the second electrode T2 through the ohmic contact point at the dielectric hole K1, preventing current accumulation below the second electrode T2. Furthermore, the plane of the orthogonal projection of the dielectric hole K1 is set along the direction away from the orthogonal projection of the second electrode T2. The area gradually increases, meaning that in the region near the orthogonal projection of the second electrode T2, the area of the orthogonal projection of the dielectric via K1 is relatively small, resulting in a smaller contact area between the metal and semiconductor within the dielectric via K1 and a larger contact resistance, thus reducing the current flow. Conversely, in the region further away from the orthogonal projection of the second electrode T2, the area of the orthogonal projection of the dielectric via K1 is larger, resulting in a larger contact area between the metal and semiconductor within the dielectric via K1 and a smaller contact resistance. This causes the current to extend further away from the orthogonal projection of the second electrode T2, i.e., towards the edge of the chip, making the current distribution more uniform and thereby improving the chip brightness.
[0094] Other structural features of the LED chip prepared by the method provided in the embodiments of this application have been described in detail in the foregoing embodiments, and can be referred to the foregoing embodiments, and will not be repeated here.
[0095] In addition, this application also provides a light-emitting device, including the LED chip provided in any of the above embodiments. Optionally, the light-emitting device can be a display device.
[0096] For example, this light-emitting device can be applied in the following fields:
[0097] In the home display field: LED chips serve as the core backlight source for televisions, creating an immersive home theater experience; or LED chips serve as the light source engine for smart projectors, providing high brightness and wide color gamut for large-screen viewing.
[0098] In the commercial display sector: LED chips empower large digital billboards and information display screens, and are integrated into conference tablets and interactive whiteboards.
[0099] In the professional display field: LED chips are used in the backlight system of medical image diagnostic monitors; LED chips are used in the lighting source of industrial inspection equipment to provide stable, uniform, high-brightness illumination to identify minute defects.
[0100] In the field of intelligent transportation: LED chips serve as backlight units for in-vehicle displays (central control screen, instrument panel, HUD), meeting automotive-grade requirements for high reliability, wide temperature range, and vibration resistance; LED chips are also embedded in traffic lights and roadside information screens to achieve all-weather, high-visibility traffic indication.
[0101] In the field of smart home: LED chips are integrated into the interactive panels of smart home appliances such as refrigerators and air conditioners, providing a clear touch feedback interface; LED chips are applied to smart mirror display systems, realizing the integration of information interaction and ambient lighting in bathroom scenarios.
[0102] Since the structural features of the LED chip have been described in detail in the foregoing embodiments, please refer to the foregoing embodiments; they will not be repeated here.
[0103] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.
[0104] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An LED chip, characterized in that, include: Bonded substrate; The bonding layer, the specular reflection layer, the dielectric layer, and the epitaxial stack are stacked on one side of the bonding substrate in a direction away from the bonding substrate; the epitaxial stack includes a window layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked in a direction away from the bonding substrate; the dielectric layer has a plurality of dielectric holes; the specular reflection layer fills the dielectric holes and forms an ohmic contact with the window layer. A first electrode located on the side of the bonding substrate opposite to the bonding layer; And a second electrode located on the side of the epitaxial stack opposite to the bonding substrate; In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is located outside the orthographic projection of the second electrode, and the area of the orthographic projection of the dielectric hole gradually increases along the direction away from the orthographic projection of the second electrode.
2. The LED chip according to claim 1, characterized in that, In a plane parallel to the plane of the bonding substrate, the orthographic projections of the dielectric holes are arranged around the orthographic projections of the second electrode in at least two circles, and along the direction away from the orthographic projections of the second electrode, the area of the orthographic projections of the dielectric holes in the (i+1)th circle is greater than the area of the orthographic projections of the dielectric holes in the ith circle, i≥1, and i is an integer.
3. The LED chip according to claim 2, characterized in that, In a plane parallel to the plane of the bonding substrate, the orthographic projections of the dielectric vias in each ring have the same arrangement pattern, or at least some rings of the dielectric vias have different orthographic projection arrangements.
4. The LED chip according to claim 2, characterized in that, In a plane parallel to the plane of the bonding substrate, at least a portion of the orthographic projections of the dielectric holes are arranged in a circular or polygonal ring.
5. The LED chip according to claim 1, characterized in that, In a plane parallel to the plane of the bonding substrate, the orthographic projections of the dielectric holes are arranged radially around the center of the orthographic projection of the second electrode, and the area of the orthographic projection of the dielectric holes gradually increases along any arrangement direction away from the orthographic projection of the second electrode.
6. The LED chip according to claim 5, characterized in that, In a plane parallel to the plane of the bonding substrate, the number of orthographic projections of the dielectric vias along the first arrangement direction is greater than the number of orthographic projections of the dielectric vias along the second arrangement direction, wherein the size of the LED chip along the first arrangement direction is greater than the size of the LED chip along the second arrangement direction.
7. The LED chip according to any one of claims 1-6, characterized in that, In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is circular; along the direction away from the orthographic projection of the second electrode, the radius of the orthographic projection of the innermost dielectric hole is not less than 2 μm, the radius of the orthographic projection of the outermost dielectric hole is not greater than 5 μm, and the spacing between the orthographic projections of each dielectric hole is not less than 5 μm.
8. The LED chip according to any one of claims 1-6, characterized in that, In a plane parallel to the plane of the bonding substrate, the distance between the orthographic projection of each dielectric hole and the orthographic projection of the second electrode is not less than 15 μm, and the distance between the orthographic projection of each dielectric hole and the edge of the LED chip is not less than 15 μm.
9. The LED chip according to any one of claims 1-6, characterized in that, The dielectric layer includes a SiO2 layer or a MgF2 layer.
10. A method for fabricating an LED chip, characterized in that, include: Provide a growth substrate; An epitaxial stack is formed on one side of the growth substrate, the epitaxial stack comprising a second type semiconductor layer, an active layer, a first type semiconductor layer and a window layer stacked along a direction away from the growth substrate; A dielectric layer is formed on the side of the window layer opposite to the growth substrate, and a plurality of dielectric holes are formed in the dielectric layer; A mirror reflection layer is formed on the side of the dielectric layer opposite to the growth substrate. The mirror reflection layer fills the dielectric holes and forms an ohmic contact with the window layer. A first sub-bonding layer is formed on the side of the mirror-reflective layer opposite to the growth substrate; A bonding substrate is provided, and a second sub-bonding layer is formed on one side of the bonding substrate; The first sub-bonding layer and the second sub-bonding layer are bonded together to form a bonding layer; Remove the growth substrate; A first electrode is formed on the side of the bonding substrate away from the bonding layer, and a second electrode is formed on the side of the epitaxial stack away from the bonding substrate; In a plane parallel to the plane of the bonding substrate, the orthographic projection of the dielectric hole is located outside the orthographic projection of the second electrode, and the area of the orthographic projection of the dielectric hole gradually increases along the direction away from the orthographic projection of the second electrode.