Wafer cutting method

Abstract

A wafer dicing method includes forming a plurality of grooves by scanning a laser beam onto a front surface of a wafer, where the wafer includes a plurality of layers, and the laser beam includes at least two beams of light; polishing the back surface of the wafer; mounting the wafer on a slicing belt; the step of forming the plurality of grooves includes forming at least two grooves by using the at least two beams of light, the at least two grooves having different widths on at least two layers among the plurality of layers of the wafer.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0160557, filed on November 12, 2024, Korean Patent Application No. 10-2024-0163192, filed on November 15, 2024, and Korean Patent Application No. 10-2025-0010699, filed on January 13, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments described herein relate to methods for cutting wafers using laser cutting equipment. Background Technology

[0003] Multiple semiconductor chips are formed together on a semiconductor substrate (such as a wafer), and a monolithic process can be performed to separate the multiple semiconductor chips from each other. Furthermore, to increase productivity with the rapid development of the electronics industry, semiconductor packages comprising multiple semiconductor chips are also formed together using a semiconductor substrate (such as a wafer), or by attaching them to a support substrate and then performing a monolithic process.

[0004] Recently, as the complexity of semiconductor devices has increased, the monolithic process of various semiconductor chips has become essential, and methods for efficiently dicing wafers without defects are needed. Summary of the Invention

[0005] The embodiments of this disclosure provide a highly reliable wafer dicing method using laser dicing equipment.

[0006] According to one aspect of an example embodiment, a wafer dicing method includes: forming a plurality of grooves by scanning a laser beam onto a front surface of a wafer, wherein the wafer includes a plurality of layers and the laser beam includes at least two beams of light; polishing a rear surface of the wafer; mounting the wafer on a slicing tape; and dicing the wafer by extending the slicing tape, wherein the step of forming the plurality of grooves includes: forming at least two grooves by using the at least two beams of light, the at least two grooves having different widths on at least two of the plurality of layers of the wafer.

[0007] According to one aspect of an example embodiment, a wafer dicing method includes: polishing the back surface of a wafer, the wafer comprising a plurality of layers; mounting the wafer on a dicing tape; forming a plurality of grooves by scanning a laser beam onto the front surface of the wafer, the laser beam comprising at least two beams of light; and dicing the wafer by extending the dicing tape, wherein the step of forming the plurality of grooves includes: forming at least two grooves of different widths on at least two of the plurality of layers of the wafer by using the at least two beams of light. Attached Figure Description

[0008] The above and other objects and features of this disclosure will become clear from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0009] Figure 1 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0011] Figure 3 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0012] Figure 4 It is shown that by using according to Figure 3 The embodiment of the laser cutting equipment is used in the process of cutting wafers by scanning and modulating a beam.

[0013] Figure 5 Is with Figure 4 A magnified view of the beam corresponding to part P1.

[0014] Figure 6 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0015] Figures 7A to 7C This is a schematic diagram illustrating the use of a two-dimensional beam-splitting optical system to split (or “split”, “divide”, or “branch”) a light beam according to an embodiment.

[0016] Figure 8 It shows when Figure 7C The etched state of the wafer when the beams of light shine on it together.

[0017] Figures 9A to 9C This is a schematic diagram illustrating the use of a two-dimensional beam-splitting optical system to split a light beam according to an embodiment.

[0018] Figure 10 It shows Figure 9C The image shows the etched state of the wafer when the beams are simultaneously irradiated onto it.

[0019] Figure 11 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0020] Figure 12 It shows Figure 11 One of the beams in the laser cutting equipment.

[0021] Figure 13 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0022] Figure 14 Showing departure Figure 13 One of the beams in the laser cutting equipment.

[0023] Figure 15 This is a block diagram illustrating a laser cutting apparatus according to an embodiment of the present disclosure.

[0024] Figure 16 This is a schematic diagram illustrating a secondary segmentation of some of the beams segmented by the first birefringent optical system of this disclosure.

[0025] Figure 17 This is a flowchart illustrating a method for processing a semiconductor element according to an embodiment.

[0026] Figures 18A to 18E This is a schematic diagram showing the methods for processing semiconductor elements in sequence.

[0027] Figure 19A and Figure 19B This is a view showing a wafer including the substrate and component layers.

[0028] Figure 20 This is a flowchart illustrating a method for processing a semiconductor element according to an embodiment.

[0029] Figures 21A to 21E This is a schematic diagram showing the methods for processing semiconductor elements in sequence.

[0030] Figure 22 This is a schematic diagram illustrating the operation of processing a wafer using a laser.

[0031] Figure 23 This is a schematic diagram illustrating the operation of processing a wafer using a laser.

[0032] Figure 24A and Figure 24B This is a schematic diagram illustrating the operation of processing a wafer with multiple element layers using a laser.

[0033] Figures 25A to 25E This is a schematic diagram illustrating a method for processing a wafer according to an embodiment of the present disclosure.

[0034] Figure 26A and Figure 26B This is a schematic diagram illustrating a method for processing a wafer according to an embodiment of the present disclosure.

[0035] Figure 27A This illustrates that when grooves are to be formed in a component layer, the presence or absence of grooving (or "grooving") defects, depending on laser irradiation conditions, can occur as regions. Figure 27B This illustrates whether grooving defects exist as regions or not, depending on the laser irradiation conditions, when a groove is to be formed in the substrate layer.

[0036] Figure 28 This is a schematic diagram showing a semiconductor element manufactured by the method described above for manufacturing a semiconductor device.

[0037] Figure 29A and Figure 29B This is a schematic diagram illustrating a semiconductor element manufactured using a method for manufacturing semiconductor elements.

[0038] Figures 30A to 30E This is a schematic diagram illustrating, by way of example, a semiconductor element manufactured using the method for manufacturing a semiconductor element according to the present disclosure.

[0039] Figure 31A This is a cross-sectional view illustrating a semiconductor element according to an embodiment of the present disclosure, and Figure 31B It is specifically shown Figure 31A A cross-sectional view of a semiconductor device.

[0040] Figures 32A to 32E This is a schematic diagram showing the methods for manufacturing semiconductor devices in sequence.

[0041] Figure 33 A semiconductor device manufactured by the above method is shown.

[0042] Figure 34 A semiconductor package according to an embodiment of the present disclosure is shown.

[0043] Figure 35 A semiconductor package according to an embodiment of the present disclosure is shown. Detailed Implementation

[0044] Embodiments of this disclosure may include a semiconductor device manufacturing apparatus for manufacturing semiconductor devices, a method for manufacturing semiconductor devices using the apparatus, and semiconductor devices manufactured by the method for manufacturing semiconductor devices.

[0045] Semiconductor devices can be manufactured by forming semiconductor elements (such as integrated circuits) on the surface of a basic disk-shaped semiconductor substrate (e.g., a silicon wafer) and then cutting the semiconductor elements along a defined area using a laser cutting device. Hereinafter, a semiconductor substrate (including semiconductor substrates on which semiconductor elements are formed on or within its upper surface) will be referred to as a wafer.

[0046] First, a laser cutting apparatus will be described, followed by a method for manufacturing a semiconductor chip using the laser cutting apparatus and a semiconductor device manufactured using that method. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] Figure 1 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure.

[0048] Reference Figure 1 A laser cutting apparatus (LCA) can be a device that uses a laser to cut a target object (e.g., a wafer WF). The wafer WF may include a substrate layer (SUB) and at least one element layer (DV) disposed on the substrate layer (SUB), and can be cut to form at least one semiconductor chip. In other words, a semiconductor chip can be manufactured by cutting a wafer WF.

[0049] The laser cutting equipment LCA may include a light source LG, a first optical modulator MD1, a second optical modulator MD2, and a focusing lens FC.

[0050] The light source LG can be a laser generator that produces a laser beam "L" of femtosecond pulses. The laser beam "L" can be a laser with a short pulse width of about 10 to 15 seconds. However, the type of laser beam "L" is not limited to this. For example, the light source LG can produce a laser beam of picosecond pulses.

[0051] The light source LG may include a laser gain medium for oscillating a laser beam "L" and a nonlinear crystal medium for modulating the wavelength of the laser beam "L". The laser gain medium may include a solid-state medium or a non-solid-state medium. The properties of the laser beam "L" may vary depending on the laser gain medium. For example, the laser gain medium may include neodymium yttrium aluminum garnet (Nd:yAG), neodymium yttrium orthovanadate (Nd:yVO4), aluminum gallium arsenide (AlGaAs), aluminum gallium indium (AlGaInP), gallium nitride (GaN), neodymium optical fiber (Nd-Fiber), sapphire, etc. In one embodiment, the nonlinear crystal medium may include a KTiOPO4 (KTP) crystal.

[0052] A laser beam "L" can be applied to a target point on a target object (e.g., a wafer WF) to form a groove through laser ablation. The focal point generated by the laser beam "L" can be formed on the surface of the target object or at a point close to the surface of the target object. The focus spot of the laser beam "L" can be located at the target point (e.g., the surface of the wafer WF, at a specific depth from the surface of the wafer WF, or above the surface of the wafer WF). The laser focus spot can scan along a direction on the surface of the target object. The scanning direction can correspond to the cutting line used to cut the target object.

[0053] The laser beam “L” generated by the light source LG may have a laser power in the range of about 1W to about 100W or about 10W to about 70W, a laser pulse duration in the range of about 100fs to about 500ps or about 500fs to about 500ps, a laser pulse repetition rate in the range of about 10kHz to about 2000kHz, a nominal pulse energy in the range of about 50μJ to about 300μJ, a laser wavelength in the range of about 300nm to about 1100nm, and a laser scanning speed in the range of about 10mm / s to about 3000mm / s.

[0054] For example, in order to minimize the generation of the heat-affected zone, the laser beam "L" generated by the light source LG may have a laser power in the range of about 30W to about 70W, a laser pulse duration in the range of about 200fs to about 15ps, a laser pulse repetition rate in the range of about 300kHz to about 3MHz, a nominal pulse energy in the range of about 80μJ to about 200μJ, a wavelength in the range of about 330nm to about 600nm, and a laser scanning speed in the range of about 50mm / s to about 2000mm / s.

[0055] In another embodiment, in order to minimize the generation of the heat-affected zone, the laser beam "L" generated by the light source LG may have a laser power in the range of about 0.1W to about 30W, a laser pulse duration in the range of about 500fs to about 50ps, a laser pulse repetition rate in the range of about 100kHz to about 1000kHz, a nominal pulse energy in the range of about 0.1μJ to about 200μJ, a wavelength in the range of about 330nm to about 600nm, and a laser scanning speed in the range of about 50mm / s to about 2000mm / s.

[0056] The first optical modulator MD1 can be a beam-splitting optical system that splits the laser beam "L" exiting the light source LG into multiple beams. The first optical modulator MD1 can split the emitted laser beam "L" into multiple beams along the scanning direction of the laser. When the scanning direction of the laser beam "L" is assumed to be the y-axis direction or the y-direction, and the direction perpendicular to the scanning direction is assumed to be the x-axis direction or the x-direction, the first optical modulator MD1 can, for example, split the laser beam "L" into multiple beams split along the y-axis.

[0057] Figure 1 The image shows the light leaving the light source LG being split into seven beams, but this is for ease of description, and the first optical modulator MD1 can split the laser beam "L" into fewer or more beams. By splitting along the direction of the scan (e.g., the y-axis direction), defects caused by heat (e.g., heat-affected zones (HAZ)) can be minimized even when the laser beam "L" is provided to the wafer WF.

[0058] The first optical modulator MD1 can split the laser beam "L" leaving the light source LG into multiple beams, and may include a beam splitter (e.g., a one-dimensional diffractive optical element DOE) and / or at least one optical lens. However, the first optical modulator MD1 is not limited thereto.

[0059] The second optical modulator MD2 can modulate the segmented beam into multiple sets of beams with different properties. In one embodiment, the second optical modulator MD2 can modulate some of the segmented beams to modulate the segmented beams into two sets with different properties (i.e., a first set of beams G1 and a second set of beams G2). The first set of beams G1 can be a beam modulated by the second optical modulator MD2, and the second set of beams G2 can be the original, unmodulated beam.

[0060] As an example, Figure 1 The diagram shows that the light leaving the light source LG is split into a total of seven beams. Of these split beams, five beams remain unmodulated, while the remaining two beams are modulated. Here, the five unmodulated beams correspond to the second group of beams G2, and the two modulated beams correspond to the first group of beams G1.

[0061] In embodiments of this disclosure, different properties of the light beam may mean differences in the beam waveform, additional segmentation, differences in the spatial spacing between additionally segmented beams, polarization, birefringence, etc. Differences in waveform may include differences in the peak shape of the laser beam. Differences in peak shape may include variations in the full width at half maximum (FWHM), differences in the shape of the peak (e.g., Gaussian or flat-topped), and whether the shape is symmetrical or asymmetrical. Hereinafter, the waveform of the laser beam refers to the intensity distribution of the laser beam along the x-axis.

[0062] In one embodiment, the beam G1 of the first group may have a different waveform compared to the beam G2 of the second group. For example, the beam before modulation (e.g., beam G2 of the second group) may have a Gaussian shape, and the beam after modulation (e.g., beam G1 of the first group) may have a flat-top shape. Optionally, the beam G1 of the first group may have a different full width at half maximum (FWHM) compared to the beam G2 of the second group. For example, the beam G1 of the first group may have a larger FWHM than the beam G2 of the second group. In one embodiment, the beam G1 of the first group may have the same waveform as the beam G2 of the second group, but may be split in a different direction. Optionally, the beam G1 of the first group may be polarized in a direction different from the polarization direction of the beam G2 of the second group. Optionally, the beam G1 of the first group may be birefringent and further split into two beams propagating in a form different from that of the beam G2 of the second group.

[0063] In one embodiment, the second optical modulator MD2 can modulate all of the laser beam "L" incident on the second optical modulator MD2 into light with different properties. Alternatively, the second optical modulator MD2 can modulate only a portion of the light incident on the second optical modulator MD2 to produce light with different properties from the unmodulated remainder.

[0064] In one embodiment, the second optical modulator MD2 can modulate some of the light in the segmented beams and additionally modulate some of the light in the remaining segmented beams. For example, the first set of beams G1 can be modulated two or more times to have two or more different properties. For example, the first set of beams G1 can have a waveform and polarization direction different from that of the second set of beams G2.

[0065] In one embodiment, the beam that has passed through the second optical modulator MD2 may include a first group of beams G1 containing an unmodulated beam, a second group of beams G2 containing a modulated beam, and a third group of beams (not shown), and the second group of beams G2 and the third group of beams may have different properties. For example, the first group of beams G1 may be an unmodulated Gaussian beam, the second group of beams G2 may be a Gaussian beam with a full width at half maximum (FWHM) larger than that of the first group of beams G1, and the third group of beams may be a flat-top beam.

[0066] The number of beam groups with different properties that can be modulated by the second optical modulator MD2 is not limited to this, and it is clear that the second optical modulator MD2 can modulate the beam into a greater number of different beam groups.

[0067] In one embodiment, the second optical modulator MD2 modulates the beam so that the beams in each group have different areas. Specifically, taking into account the direction along which the scan is performed, the second optical modulator MD2 modulates the beams into beams with different areas based on the group in front (or "forward") and the group behind (or "rear"). Here, being in front or behind in the scanning direction can mean being in front or behind in time and / or space.

[0068] In terms of space, when the scanning direction of the laser beam "L" is indicated by the arrow, it can be seen that the group spatially closer to the head of the arrow is in front of the group spatially closer to the tail of the arrow. In terms of time, when the scanning of the laser beam "L" is performed and the scanning direction of the laser beam "L" is indicated by the arrow, the beams of the group closer to the head of the arrow can be applied to the target point of the target object first (e.g., relatively early), and the beams of the group closer to the tail of the arrow can be applied to the target point of the target object later (e.g., relatively late).

[0069] However, even when the laser beam "L" is segmented in time and / or space, the degree of temporal / spatial interval may be small, and overlap may exist between two adjacent beams. For this reason, even when the beam is segmented in time and / or space, the difference between individual beams may not be entirely clear (clear), and there may be no significant difference compared to using it as a single applied beam.

[0070] In the description of the seven-beam configuration again as an example, with reference to the accompanying drawings, a single laser beam "L" output from the light source LG can be split into seven spatially divided beams. In this case, the seven divided beams can be modulated, after passing through the second optical modulator MD2, into two spatially divided beams in a first group G1 and five in a second group G2.

[0071] In one embodiment, the first beam G1 and the second beam G2 may not be split in time and may be emitted simultaneously. However, the first beam G1 may be positioned spatially closer to the head of the arrow in the scanning direction than the second beam G2, and therefore, when performing a laser scan, the first beam G1 may reach the target point first.

[0072] Alternatively, in another embodiment, the total of seven beams, consisting of the first group of beams G1 and the second group of beams G2, can be divided in time and thus emitted at different times. For example, the first group of beams G1 may illuminate the target point first, and the second group of beams G2 may illuminate the target point later.

[0073] In one embodiment, when a scan is performed, the beams of the group that first illuminate the target point may have a wider area. In other words, when a scan is performed and "n" groups are sequentially set from the preceding group, the area of ​​the beams in the first group may be the largest, and the areas of the beams in the remaining(one or more) groups that follow may decrease sequentially in that order. For example, when the beam G1 of the first group is in front of the beam G2 of the second group, the area of ​​the beam G1 of the first group may be larger than the area of ​​the beam G2 of the second group.

[0074] In one embodiment, the second optical modulator MD2 can modulate the beam of each group into beams with different widths in a direction perpendicular to the scanning direction (e.g., the x-direction). Specifically, taking into account the direction along which the scan is performed, the second optical modulator MD2 can modulate the beams into beams with different widths according to the preceding and following groups. When performing a scan and sequentially setting "n" groups from the preceding group, the beam width of the first group can be the largest, and the beam width of the remaining(s) in the following groups can decrease sequentially in the subsequent order. In one embodiment, when the beam G1 of the first group is in front of the beam G2 of the second group during laser scanning, the width of the beam G1 of the first group can be larger than the width of the beam G2 of the second group.

[0075] The beam modulated by the second optical modulator MD2 can be focused by the focusing lens FC and applied to the target object (i.e., the wafer WF).

[0076] A laser cutting apparatus (LCA) with the above-described structure can simultaneously apply multiple spatially arranged groups of laser beams (e.g., beam G1 in the first group and beam G2 in the second group) to a target object in a single scan. Because each group of beams has a different area (e.g., width), lasers with different areas (e.g., width) can be applied to target points on the target object simultaneously or sequentially. Beams with a large area (e.g., width) can etch target points with a large area (e.g., width), and beams with a small area (e.g., width) can etch target points with a small area (e.g., width). Thus, a cutting structure with both large and small areas (e.g., width) can be positioned at the target point of the target object in a single scan.

[0077] Figure 2 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure. In the following embodiments, the differences from the above embodiments will be primarily described to avoid repetition.

[0078] Reference Figure 2 Laser cutting equipment (LCA) may also include a power controller (CTL), a beam expander (BEX), and / or a delay line system (DLS).

[0079] The power controller CTL controls the intensity of the laser beam leaving the light source LG, and the beam expander BEX expands the laser beam leaving the light source LG. The power controller CTL and the beam expander BEX can be positioned between the light source LG and the first optical modulator MD1.

[0080] The delay line system DLS can be positioned between the second optical modulator MD2 and the focusing lens FC.

[0081] The Delay Line System (DLS) can be used for time synchronization or desynchronization of beams G1 in the first group and beams G2 in the second group, and can control the time departure (emission) order of beams G1 and G2. For example, when beam G1 in the first group is delayed by the beam modulation process in the first optical modulator MD1 and the second optical modulator MD2, beam G2 in the second group can also be delayed to synchronize with beam G1 in the first group. Optionally, the incident timing of beams G1 in the first group and beams G2 in the second group can be adjusted to different degrees.

[0082] Although not shown, the laser cutting equipment LCA may include additional components in addition to those described above. For example, the laser cutting equipment LCA may include at least one lens, at least one prism, at least one mirror, bandpass filter, etc., which can change or control the path of light.

[0083] Furthermore, although not shown, components may be physically and / or electrically connected to a controller (not shown), and the operation of the components may be controlled by the controller. In one embodiment, the controller may be implemented using computer components. The controller may include, for example, a central processing unit (CPU) that performs calculations according to a control program, a read-only memory (ROM) that stores the control program, random access memory (RAM) that allows recording (for temporary storage of detection values, calculation results, etc.) and reading, input interfaces, and / or output interfaces.

[0084] Figure 3 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure.

[0085] Reference Figure 3 The laser cutting equipment LCA may include an acousto-optic modulator (AOM) and a flat-top modulator (FTM) as one of the optical modulators.

[0086] The acousto-optic modulator (AOM) can be an optical deflection adjustment device that temporally divides the beam segmented in the first optical modulator (MD1) and deflects the optical axis of the beam in a specific direction. The beam that has passed through the acousto-optic modulator (AOM) can be modulated into multiple beams with different optical axes.

[0087] An acousto-optic modulator (AOM) can modulate the amplitude (or frequency) of a light beam using the acousto-optic effect, and / or deflect the light beam in a specific direction. In other words, by using the diffraction effect of light, the amplitude, frequency, phase, polarization, spatial position, and / or optical axis of the light beam can be changed.

[0088] More specifically, the acousto-optic modulator (AOM) may include: an acousto-optic element that deflects the optical axis of a beam in a specific direction; a radio frequency (RF) oscillator that generates the radio frequency (RF) to be applied to the acousto-optic element; an RF amplifier that amplifies the power of the RF generated by the RF oscillator and applies the amplified RF to the acousto-optic element; a deflection angle adjuster that adjusts the frequency of the RF generated by the RF oscillator; and an output adjuster that adjusts the amplitude of the RF generated by the RF oscillator. The acousto-optic element can adjust the angle used to deflect the optical path of the beam in response to the frequency of the applied RF, and can adjust the output of the pulsed laser beam in response to the amplitude of the applied RF. For example, modulation of the acousto-optic modulator (AOM) can be performed using an RF signal of 1 MHz or greater, and different directions can be selectively assigned to various numbers of incident beams.

[0089] In one embodiment, the acousto-optic modulator (AOM) can be positioned at an angle relative to the incident light, such that the segmented beams are incident on the AOM at different time intervals. For example, the AOM can be positioned at an angle of approximately 45 degrees relative to the propagation direction of the segmented beams. Because the AOM is positioned at an angle, the beams can be incident on the AOM with time differences.

[0090] The acousto-optic modulator AOM can deflect the first beam G1 and the second beam G2 to have different optical axes. Therefore, the deflected first beam G1 and the second beam G2 can travel on different paths.

[0091] The flat-top modulator (FTM) can be positioned on the path of the first beam G1. The FTM modulates the waveform of the first beam G1.

[0092] In one embodiment, the flat-top modulator (FTM) modulates the first group of beams G1 into a flat-top beam instead of a Gaussian beam. A flat-top beam can be referred to as a U-shaped beam. The FTM produces a flat beam by expanding each Gaussian beam and then shielding its outskirt. Alternatively, the FTM can split the Gaussian beam into multiple beams and then modulate them into a flat beam by overlapping them.

[0093] In one embodiment, along the scanning direction, the first beam G1 may be in front, and the second beam G2 may be behind. In this case, the second beam G2 may have a Gaussian shape, and the first beam G1 may have a flat-top shape with a width greater than that of the second beam G2.

[0094] In one embodiment, the outputs of the first group of beams G1 and the second group of beams G2 can be controlled independently by the controller. That is, the controller can control the outputs of the first group of beams G1 and / or the second group of beams G2. In one embodiment, the controller can control only the output of the second group of beams G2. When the controller can control only the output of a specific group of beams, various cutting processes can be set by combining the groups differently.

[0095] Figure 4 It is shown that by using according to Figure 3 The embodiment of the laser cutting equipment is used in the process of cutting wafers (WF) using a scan-modulated beam. Figure 5 Is with Figure 4 The image shows a magnified view of the beam corresponding to P1, and also shows the etch state of the wafer WF when the beams are irradiated together on the wafer WF.

[0096] Reference Figure 4 and Figure 5 It can output the laser beam leaving the laser cutting equipment to the wafer WF along the scanning direction.

[0097] A wafer fabrication (WF) may include a chip region CA in which semiconductor elements are disposed, and a scriber region SA in which semiconductor elements are disposed in the chip region CA and then dicing is performed. An outgoing beam may scan along a dicing line CL in the scriber region SA. The dicing line CL may be a hypothetical line (imaginary line) along which dicing is performed.

[0098] In laser cutting equipment, when the beam emitted simultaneously with a single output is assumed to be a unit beam UNB, the sequentially irradiated unit beams UNB can overlap each other in the area to be processed. Laser cutting equipment can cut wafers (WF) by sequentially providing unit beams UNB while moving along each scanning direction.

[0099] Each unit beam (UNB) may include multiple beams modulated by an optical modulator (MD). For example... Figure 5As shown, each unit beam may include a first group of beams G1 and a second group of beams G2, with the first group of beams G1 positioned in front and the second group of beams G2 positioned behind along the scanning direction. Because the second group of beams G2 has a Gaussian form, it can therefore be provided in a spot configuration. The first group of beams G1 can be provided in a flat-top configuration, having a width in the x-direction greater than that of the second group of beams G2. Here, the width of the first group of beams G1 in the y-axis direction can be substantially the same as the width of the second group of beams G2 in the y-axis direction.

[0100] When the width of the first beam G1 in the x-direction is assumed to be a first width W1, and the width of the second beam G2 in the x-direction is assumed to be a second width W2, the first width W1 can be larger than the second width W2.

[0101] When a light beam is directed along the y-direction onto the wafer WF, the wafer WF can be etched by the beam. The wafer WF can be etched from its surface in the depth direction. Here, the depth direction from the surface of the wafer WF can correspond to the z-direction (or z-axis direction) which is perpendicular to both the x and y directions.

[0102] When scanning the beam, a first groove GV1 corresponding to the width of the first group of beams G1 can first be formed on the wafer WF. Next, a second group of beams G2 located behind is irradiated along the scanning direction, and a second groove GV2 having a width corresponding to the width of the second group of beams G2 can be formed on the wafer WF. The first groove GV1 and the second groove GV2 can be formed to have dimensions corresponding to the first width W1 and the second width W2, respectively.

[0103] Here, because the first set of beams G1 is provided first, and then the second set of beams G2 is provided, the first trench GV1 can be formed in the wafer WF first, and then the second trench GV2 can be formed in the first trench GV1.

[0104] Figure 6 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure.

[0105] Reference Figure 6 The laser cutting equipment LCA may include a two-dimensional diffractive optical element DOE and an attenuator ATT as an optical modulator MD.

[0106] A two-dimensional diffractive optical element (DOE) can be a two-dimensional beam-splitting optical system that can split light leaving the light source LG into multiple two-dimensional beams.

[0107] In one embodiment, a two-dimensional diffractive optical element (DOE) can simultaneously split multiple beams along the x-axis and y-axis. However, the embodiments are not limited to this, and the x-axis beam-splitting optical system that splits the beams along the x-axis direction and the y-axis beam-splitting optical system that splits the beams along the y-axis direction can be separately configured together. The x-axis beam-splitting optical system and the y-axis beam-splitting optical system can be sequentially configured to first split the beams in the x-axis direction and then split the beams in the y-axis direction, and conversely, the y-axis beam-splitting optical system and the x-axis beam-splitting optical system can be sequentially configured to first split the beams in the y-axis direction and then split the beams in the x-axis direction.

[0108] A two-dimensional diffractive optical element (DOE) can split light into "m" beams in the x-direction and "n" beams in the y-direction. Beam splitting can be performed temporally and / or spatially. The splitting in the x-direction and the splitting in the y-direction can be performed in different ways. In this case, the two-dimensional diffractive optical element (DOE) can split the beam independently or consequently along the x and y directions.

[0109] An attenuator ATT can selectively alter certain properties of the light beam exiting a two-dimensional diffractive optical element (DOE). The attenuator ATT can change the power, amplitude, and transmittance of the light beam exiting the DOE in the x-axis and y-axis directions. For example, the attenuator ATT can sequentially decrease or increase the intensity of individual beams according to the scanning direction, and the degree of decrease or increase can be selectively adjusted if necessary. In one embodiment, the attenuator ATT can set the transmittance of the beam in the x-axis and y-axis directions differently depending on the beam's position in space, and for example, the transmittance on the y-axis can be selectively changed.

[0110] In one embodiment, the two-dimensional beam-splitting optical system including a two-dimensional diffractive optical element (DOE) and / or an attenuator (ATT) can be passive components. The two-dimensional beam-splitting optical system and / or the attenuator (ATT) can be fixed by predetermined settings and can be replaced with other components when different operations are required. For example, a laser cutting device may include components similar to those described later. Figures 7A to 7C The corresponding two-dimensional beam-splitting optical system, and can be used when more splitting in the x-direction is needed. Figures 9A to 9C A corresponding two-dimensional beam splitting optical system can replace it.

[0111] Similarly, the attenuator ATT can be fixed with specific settings or replaced with attenuators having different settings. Replacement of the two-dimensional beam-splitting optical system and / or attenuator ATT can be performed automatically (e.g., by user selection). However, this disclosure is not limited thereto, and manual replacement is also possible. However, this disclosure is not limited thereto, and when the two-dimensional beam-splitting optical system and / or attenuator ATT are integrated into active elements and configured as an active assembly, separate replacement may not be necessary.

[0112] Figures 7A to 7C This is a schematic diagram illustrating the use of a two-dimensional beam-splitting optical system to split a light beam according to an embodiment, wherein, Figure 7A This is a schematic diagram showing the optical refraction pattern along the x-axis. Figure 7B This is a schematic diagram showing the optical refraction pattern in the y-axis direction, and Figure 7C This is a schematic diagram showing the optical refraction patterns in both the x-axis and y-axis directions. Figure 7C In this design, a segmented beam of light is refracted by an optical refractive pattern in the x-axis and / or y-axis directions and illuminates the wafer WF corresponding to the overlapping portion. Here, the beams refracted by the optical refractive pattern are intentionally shown to be spaced apart from each other to indicate spatial separation between the beams, and the size of the beams and the spacing between the beams do not perfectly match the size of the beams and the spacing between the beams.

[0113] Reference Figures 7A to 7C Light leaving the light source can be split into multiple beams as it is refracted along both the x-axis and y-axis. The degree of splitting along the x-axis can differ from the degree of splitting along the y-axis. For example, splitting along the y-axis can result in a total of seven beams, which can be arranged regularly in space at specific intervals. On the other hand, splitting along the x-axis can result in multiple beams (e.g., seven beams) at the front portion along the scanning direction (e.g., closer to the head of the arrow indicating the scanning direction), but no splitting and a single beam at the rear portion along the scanning direction (e.g., closer to the tail of the arrow). In this case, the light can be split along the x-axis in some segments along the y-axis of the scanning direction. For example, each beam can be split into seven beams along the x-axis in some segments along the y-axis. In this way, the number of beams split in the x-direction can vary along the y-axis. The beams split along the x-axis may or may not overlap each other along the x-axis.

[0114] Figure 8 It shows when Figure 7C The etching state of the wafer WF when the light beams together irradiate the wafer WF.

[0115] Reference Figure 8The laser beam leaving the laser cutting equipment can be output to the wafer WF along the scanning direction.

[0116] Each unit beam (UNB) exiting the processing apparatus used for wafer WF can comprise multiple beams modulated by a two-dimensional beam-splitting optical system. For example... Figure 8 As shown, each unit beam may include a second group of beams G2 split along the y-axis and a first group of beams G1 split along both the x-axis and y-axis. The first group of beams G1 may be in front along the scanning direction, and the second group of beams G2 may be behind along the scanning direction.

[0117] Because the second beam G2 only undergoes y-axis segmentation and not x-axis segmentation, it can be provided in a spot-like form. The first beam G1 can be segmented along the x-axis, allowing multiple beams to be provided in a spot-like form and arranged along the x-axis. Therefore, the sum of the widths of the individual segmented beams can be the width of the first beam G1. Here, when the sum of the x-direction widths of the first beam G1 is assumed to be a first width W1, and the x-direction width of the second beam G2 is assumed to be a second width W2, the first width W1 can be larger than the second width W2.

[0118] When a light beam illuminates the wafer (WF) along the y-direction, the wafer (WF) can be etched by the beam. The wafer (WF) can be etched from its surface in the depth direction. The depth direction from the surface of the wafer (WF) can correspond to the z-direction (or z-axis direction) which is perpendicular to both the x and y directions.

[0119] The first beam G1 can be positioned in front along the scanning direction, and therefore, a first groove GV1 corresponding to the width (e.g., total width) of the first beam G1 can be formed on the wafer WF. Next, the second beam G2 can illuminate along the scanning direction, and a second groove GV2 corresponding to the width of the second beam G2 can be formed on the wafer WF. The first groove GV1 and the second groove GV2 can be formed to have dimensions corresponding to the first width W1 and the second width W2, respectively.

[0120] Here, because the first set of beams G1 is provided first, and then the second set of beams G2 is provided, the first trench GV1 can be formed in the wafer WF first, and then the second trench GV2 can be formed in the first trench GV1.

[0121] Although not shown, in one embodiment, the form of some of the beams refracted and segmented by the two-dimensional beam-splitting optical system can be modulated. For example, some of the leading beams among the beams segmented along the y-axis can be modulated into a flat-top shape using a flat-top modulator such as an FTM. For example, at least some of the beams G1 in the first group can also be modulated into a flat-top form.

[0122] Figures 9A to 9C This is a schematic diagram illustrating the use of a two-dimensional beam-splitting optical system to split a light beam according to an embodiment, wherein, Figure 9A This is a schematic diagram showing the optical refraction pattern along the x-axis. Figure 9B This is a schematic diagram showing the optical refraction pattern in the y-axis direction, and Figure 9C This is a schematic diagram showing the optical refraction patterns in both the x-axis and y-axis directions. Figure 9C In this process, a beam of light, segmented by an optical refraction pattern in the x-axis and / or y-axis directions, is irradiated onto the wafer WF corresponding to the overlapping portion.

[0123] Reference Figures 9A to 9C When light leaving the light source LG along the x-axis is split into multiple beams, the splitting can occur multiple times. For example, the number of beams split in the x-direction can gradually change along the y-direction.

[0124] Here, the degree of splitting along the x-axis can differ from the degree of splitting along the y-axis, and the beams split along the y-axis can be arranged regularly in space at specific intervals. On the other hand, splitting along the x-axis can be done by dividing the beams into multiple stages (or "levels") at the leading portion along the scanning direction. In this case, primary splitting can be performed in some segments along the y-axis along the scanning direction, secondary splitting in some additional segments along the y-axis, and tertiary splitting in some other segments along the y-axis. The number of beams split along the x-axis can vary along the y-axis. The beams split along the x-axis may or may not overlap each other along the x-axis.

[0125] Figure 10 It shows Figure 9C The beam of light, and showed when Figure 9C The etching state of the wafer WF when the light beams together irradiate the wafer WF.

[0126] Reference Figure 10 The beam exiting the laser cutting equipment can be output to the wafer WF along the scanning direction. Each unit beam exiting the processing device for the wafer WF can include multiple beams modulated by a two-dimensional beam splitting optical system.

[0127] like Figure 9C and Figure 10As illustrated in the example, each unit beam may include a fourth group of beams G4, divided only in the y-axis direction; a third group of beams G3, divided once in the x-axis direction in addition to the y-axis division; a second group of beams G2, divided twice in the x-axis direction in addition to the y-axis division; and a first group of beams G1, divided three times in the x-axis direction in addition to the y-axis division. A beam of light can be divided into three beams arranged in the x-axis direction by a single division in the x-axis direction, a beam of light can be divided into five beams arranged in the x-axis direction by a double division in the x-axis direction, and a beam of light can be divided into seven beams arranged in the x-axis direction by a triple division in the x-axis direction.

[0128] The segmented beams can illuminate the wafer WF along the scanning direction, with the first group of beams G1 in front, and the second group of beams G2, the third group of beams G3, and the fourth group of beams G4 following in that order. Because the fourth group of beams G4 only undergoes y-axis segmentation and not x-axis segmentation, it can be provided in a spot-like form. The first group of beams G1 to the third group of beams G3 can also be segmented in the x-axis direction in addition to the y-axis segmentation, allowing multiple beams to be provided in a spot-like form and arranged in the x-axis direction. Therefore, the sum of the widths of each segmented beam can be the width of the beam in each group. Here, when the x-direction width of the first group of beams G1 is assumed to be a first width W1, and the x-direction widths of the second group of beams G2 to the fourth group of beams G4 are assumed to be second widths W2 to fourth widths W4, the first width W1 to the fourth width W1 can sequentially have smaller values.

[0129] When a light beam illuminates the wafer (WF) along the y-direction, the wafer (WF) can be etched by the beam. The wafer (WF) can be etched from its surface in the depth direction. The depth direction from the surface of the wafer (WF) can correspond to the z-direction (or z-axis direction) which is perpendicular to both the x and y directions.

[0130] Because the first group of beams G1, the second group of beams G2, the third group of beams G3, and the fourth group of beams G4 are sequentially positioned in front along the scanning direction, a groove GV with a width corresponding to the width of each group of beams can be formed on the wafer WF. Here, the groove GVs formed by etching with the first group of beams G1, the second group of beams G2, the third group of beams G3, and the fourth group of beams G4 are assumed to be the first groove GV1 to the fourth groove GV4, and the first groove GV1 to the fourth groove GV4 can be formed to have dimensions corresponding to the first width W1 to the fourth width W4, respectively.

[0131] Although not shown, in one embodiment, the form of some of the beams segmented by the two-dimensional beam-splitting optical system can be modulated. For example, some of the leading beams among the beams segmented along the y-axis can be modulated into a flat-top shape using a flat-top modulator such as an FTM. For example, at least some of the beams G2 in the second group can also be modulated into a flat-top form.

[0132] Figure 11 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure.

[0133] Reference Figure 11 The laser cutting equipment LCA may include a light source LG, a beam expander BEX, a first optical modulator MD1, a second optical modulator MD2, and a focusing lens FC. In one embodiment, the second optical modulator MD2 may include a birefringent optical system BRF and a polarizer PLZ. The focusing lens FC may be a birefringent lens that focuses the birefringent beam.

[0134] A birefringent optical system (BRF) may include components with optical anisotropy (e.g., birefringent lenses). The BRF may have different refractive indices depending on the polarization direction of the light, and the refractive indices in the direction perpendicular to the optical axis and in the direction parallel to the optical axis may differ from each other. Therefore, a beam passing through the BRF can be divided into beams in the direction perpendicular to the optical axis and beams in the direction parallel to the optical axis. When the beam perpendicular to the optical axis is assumed to be beam G1 of the first group, and the beam parallel to the optical axis is assumed to be beam G2 of the second group, beam G1 of the first group may correspond to an ordinary ray, and beam G2 of the second group may correspond to an extraordinary ray.

[0135] The polarizer PLZ can polarize at least a portion of two beams (i.e., beams G1 and G2 of the first group separated by the birefringent optical system BRF) to different degrees.

[0136] In one embodiment, the polarizer PLZ modulates the first group of beams G1 and the second group of beams G2 exiting the birefringent optical system BRF, such that the power ratios of the polarization components are different. For example, the polarizer PLZ modulates the first group of beams G1 and the second group of beams G2, such that the power ratios of the x-axis polarization components and the y-axis polarization components are different. In one embodiment, the first group of beams G1 may have a larger ratio of x-axis polarization components than the y-axis polarization components, and the second group of beams G2 may have a smaller ratio of x-axis polarization components than the y-axis polarization components.

[0137] In another embodiment, the polarizer PLZ can polarize at least a portion of the light leaving the birefringent optical system BRF at a specific angle. For example, the polarizer PLZ can polarize light into light that vibrates primarily in the x-axis direction, or it can polarize light into light that vibrates primarily in the y-axis direction. In one embodiment, some of the light in the first beam G1 can be polarized in the x-axis direction, and the remaining portion of the light in the first beam G1 can be polarized in the y-axis direction. Optionally, the polarizer PLZ can polarize some of the light in the second beam G2 in the x-axis direction, and the remaining portion of the light in the second beam G2 can be polarized in the y-axis direction. In one embodiment, the polarizer PLZ can adjust the degree of polarization in the x-axis direction and / or the ratio of polarized light in the y-axis direction.

[0138] Although not shown, the laser cutting apparatus LCA may also include an attenuator that selectively alters some properties of the beam exiting the polarizer PLZ. The attenuator can change the power, amplitude, transmittance, etc., of the beam exiting the polarizer PLZ in the x-axis and y-axis directions.

[0139] Light polarized in different directions can irradiate the wafer WF, thereby etching the wafer WF to different degrees.

[0140] Figure 12 Show Figure 11 One of the beams in the laser cutting equipment.

[0141] Reference Figure 12 The first beam G1 and the second beam G2 can be separated by a birefringent optical system BRF. A polarizer PLZ polarizes the first beam G1 in a specific direction (e.g., along the x-axis as shown). The beam polarized in this specific direction can be applied to the wafer WF to achieve etching in that direction. However, the polarization direction may not be the same as the etching direction.

[0142] Compared to the unpolarized second beam G2, the first beam G1, polarized in a specific direction (e.g., the x-direction), can etch the wafer WF in that specific direction (e.g., the x-direction). Therefore, the width etched by the first beam G1 can be larger than the width etched by the second beam G2.

[0143] The laser cutting apparatus according to the above embodiments and the components constituting each laser cutting apparatus can be combined in various forms, except where they are incompatible with each other. For example, when a component such as an attenuator or a delay line system is not shown in the laser cutting apparatus, such a component is not excluded, and it can be combined in various forms.

[0144] Figure 13 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure.

[0145] Reference Figure 13 The laser cutting equipment LCA may include a light source LG, a beam expander BEX, a first optical modulator MD1, a second optical modulator MD2, and a third optical modulator MD3. The second optical modulator MD2 may include an acousto-optic modulator AOM and a flat-top modulator FTM, and the third optical modulator MD3 may include a birefringent optical system BRF and a polarizer PLZ.

[0146] The first optical modulator MD1 can be a beam-splitting optical system that splits the laser beam "L" exiting the light source LG into multiple beams. The first optical modulator MD1 can split the emitted laser beam "L" into multiple beams along the scanning direction of the laser. When the scanning direction of the laser beam "L" is assumed to be the y-axis direction and the direction perpendicular to the scanning direction is assumed to be the x-axis direction, the first optical modulator MD1 can, for example, split the laser beam "L" into multiple beams split along the y-axis.

[0147] The beam split in the first optical modulator MD1 can be modulated into beams with multiple different optical axes in the acousto-optic modulator AOM of the second optical modulator MD2. The acousto-optic modulator AOM can change the amplitude, frequency, phase, polarization, spatial position, and / or optical axis of the split beams by using the diffraction effect of light. The acousto-optic modulator AOM can deflect the first group of beams G1 and the second group of beams G2 onto different optical axes. Therefore, the deflected first group of beams G1 and the second group of beams G2 can travel on different paths.

[0148] A flat-top modulator (FTM) can be positioned along the path of the first beam G1. The FTM modulates the waveform of the first beam G1. In one embodiment, the FTM modulates the first beam G1 into a flat-top beam instead of a Gaussian beam.

[0149] The beams G1 from the first group and G2 from the second group exiting the second optical modulator MD2 can propagate to the third optical modulator MD3. For example, the beam G1 from the first group exiting the flat-top modulator FTM can propagate to the third optical modulator MD3. For example, the beam G2 from the second group exiting the acousto-optic modulator AOM can propagate to the third optical modulator MD3.

[0150] The beams G1 in the first group and G2 in the second group can be split into multiple beams by a birefringent optical system (BRF). A polarizer (PLZ) can polarize the beams that have passed through the BRF. For example, the polarizer (PLZ) can polarize the beams to split them into beams polarized along the x-axis and beams polarized along the y-axis.

[0151] The light beam leaving the polarizer PLZ passes through the focusing lens FC and illuminates the wafer WF, allowing the wafer WF to be etched to different degrees.

[0152] Figure 14 Showing departure Figure 13 One of the beams in the LCA laser cutting equipment.

[0153] Reference Figure 13 and Figure 14 The first beam G1 and the second beam G2 can be modulated into light with different waveforms by an acousto-optic modulator (AOM) and a flat-top modulator (FTM). The second beam G2 can have a Gaussian form, and the first beam G1 can have a flat-top form. The birefringent optical system (BRF) and the polarization system (e.g., a polarizer (PLZ)) can modulate the light polarized along the x-axis or y-axis into different intensities, amplitudes, etc., while simultaneously polarizing the first beam G1 and the second beam G2 along the x-axis or y-axis, respectively.

[0154] In one embodiment, beams polarized along the x-axis or y-axis may be alternately arranged, and they may have different intensities and amplitudes. For example, a beam polarized along the y-axis may have a greater intensity and / or amplitude than a beam polarized along the x-axis. To illustrate this, in Figure 14 In the diagram, the shape and area of ​​the spot of a beam polarized along the y-axis are shown to be larger than the shape and area of ​​the spot of a beam polarized along the x-axis.

[0155] In one embodiment, besides the first group of beams G1 and the second group of beams G2 being modulated to have different widths, the degree of etching can be varied according to the type of etch target by differently setting the polarization components of each beam. For example, a polarized beam with relatively high intensity and / or amplitude can be used during a main processing phase requiring relatively high intensity, and a polarized beam with relatively low intensity and / or amplitude can be used during auxiliary processing phases. In one embodiment, the main processing may include a process of etching at least a portion of the component layer or substrate layer of the wafer, and the auxiliary processing may include a process of removing foreign matter, damaged areas, etc., present before or after the main processing. The auxiliary processing may, for example, include a process of removing debris and / or heat-affected zones (HAZs) generated during the process of removing the component layer and / or substrate layer of the wafer.

[0156] Figure 15 This is a block diagram illustrating a laser cutting apparatus LCA according to an embodiment of the present disclosure.

[0157] Reference Figure 15The laser cutting equipment LCA may include a light source LG, a first optical modulator MD1, a second optical modulator MD2, and a third optical modulator MD3. The second optical modulator MD2 may include a first birefringent optical system BRF1 and a second birefringent optical system BRF2. The third optical modulator MD3 may include an acousto-optic modulator AOM and a flat-top modulator FTM.

[0158] The first optical modulator MD1 can be a beam-splitting optical system that splits the laser beam "L" exiting the light source LG into multiple beams. The first optical modulator MD1 can split the emitted laser beam "L" into multiple beams spatially spaced along the scanning direction of the laser. When the scanning direction of the laser beam "L" is assumed to be the y-axis direction and the direction perpendicular to the scanning direction is assumed to be the x-axis direction, the first optical modulator MD1 can, for example, split the laser beam "L" into multiple beams split along the y-axis. For ease of description, Figure 15 The first optical modulator MD1 is shown splitting the laser beam into two beams.

[0159] The beam split in the first optical modulator MD1 can be modulated into multiple beams that are spatially and / or temporally separated by the birefringent optical system of the second optical modulator MD2.

[0160] The birefringent optical system may include a first birefringent optical system BRF1 for spatially splitting a beam that has already been split once in the first optical modulator MD1, and a second birefringent optical system BRF2 for temporally splitting the beam that has been split twice.

[0161] The first birefringent optical system BRF1 can spatially separate the split beams along the optical axis of the beams propagating through the birefringent optical system. In one embodiment, the first birefringent optical system BRF1 can modulate the beams propagating within it into a first set of beams G1 and a second set of beams G2 that are spatially separated by polarizing at least some of them in a particular direction.

[0162] Figure 16 This is a schematic diagram illustrating a secondary segmentation of some of the beams segmented by the first birefringent optical system BRF1 of this disclosure.

[0163] Reference Figure 16The first birefringent optical system BRF1 may include anisotropic materials (e.g., a birefringent crystal that polarizes a beam in different optical axis directions). For example, when the optical axis of the birefringent crystal in the first birefringent optical system BRF1 and the optical axis of the beam propagating into the first birefringent optical system BRF1 (e.g., the angle between the optical axis of the birefringent crystal in the first birefringent optical system BRF1 and the optical axis of the beam propagating into the first birefringent optical system BRF1) are set to 10 degrees to 80 degrees, the beam propagating into the first birefringent optical system BRF1 can be split into a first group of beams G1 polarized in the x-axis direction and a second group of beams G2 polarized in the y-axis direction.

[0164] Refer again Figure 15 The second birefringent optical system BRF2 can vary the propagation speed of the beam according to the polarization direction and optical axis of the beam propagating within the second birefringent optical system BRF2. This allows either the first group of beams G1 or the second group of beams G2 to be delayed in time relative to the other. In one embodiment, the second birefringent optical system BRF2 may include a uniaxial crystal having one optical axis. The propagation speed of the beam perpendicular to the optical axis of the second birefringent optical system BRF2 and the propagation speed of the beam parallel to the optical axis may differ in the uniaxial crystal. For example, when the optical axis of the crystal in the second birefringent optical system BRF2 and the optical axis of the beam propagating into the second birefringent optical system BRF2 (e.g., the angle between the optical axis of the crystal in the second birefringent optical system BRF2 and the optical axis of the beam propagating into the second birefringent optical system BRF2) are set to 90 degrees (the polarization direction of the split beams), for example, the second group of beams G2 polarized in the y-axis direction may propagate more slowly than the first group of beams G1 polarized in the x-axis direction. Therefore, compared to the first group of beams G1 polarized in the x-axis direction, the second group of beams G2 polarized in the y-axis direction can have a waveform that is time-delayed. In this way, the second birefringent optical system BRF2 can actually be used as a phase delay plate for the beam passing through the second birefringent optical system BRF2.

[0165] The temporally / spatially segmented beams in the second optical modulator MD2 can be modulated into beams with multiple different paths in the acousto-optic modulator AOM of the third optical modulator MD3. The acousto-optic modulator AOM can alter the amplitude, frequency, phase, polarization, spatial position, and / or optical axis of the segmented beams by utilizing the diffraction effect of light, and in one embodiment, the spatial position can be altered. Thus, the first set of deflected beams G1 and the second set of deflected beams G2 can be spatially separated from each other and can propagate in different paths.

[0166] A flat-top modulator (FTM) can be positioned along the path of the first beam G1. The FTM modulates the waveform of the first beam G1. In one embodiment, the FTM modulates the first beam G1 into a flat-top beam instead of a Gaussian beam.

[0167] The beams G1 and G2 of the first group leaving the third optical modulator MD3 (e.g., the beams G1 of the first group leaving the flat-top modulator FTM and the beams G2 of the second group leaving the acousto-optic modulator AOM) pass through the focusing lens FC and illuminate the wafer WF, thereby etching the wafer WF to different degrees.

[0168] Laser cutting equipment with the above-described structure can be driven in various ways (in particular, in various irradiation modes of the laser beam).

[0169] In the following description, for ease of description, beams with the same properties are grouped and described as beams represented by the same number. For example, Figure 4 and Figure 5 The beams in the first group have essentially the same properties and will be described as the first light, while the beams in the second group have essentially the same properties but differ from the first light and will be described as the second light. Lights represented by different numbers are light with different properties. For example, in... Figure 10 In the diagram, the beams from the first group to the fourth group are sequentially assumed to be the first light, the second light, the third light, and the fourth light with different properties.

[0170] The illumination modes of a laser cutting device may include a first mode that irradiates different beams sequentially and / or a second mode that irradiates at least some of the different beams simultaneously.

[0171] At least one of the first and second modes can be implemented by a single laser cutting device, or by multiple laser cutting devices. When at least one of the first and second modes is executed by multiple laser cutting devices, an individual laser cutting device may implement only one of the first and second modes.

[0172] In one embodiment, the user can choose whether to continue with a first mode or a second mode. The user can choose between a manual illumination mode or an automatic illumination mode. When the automatic illumination mode is selected, the illumination mode can be selected according to an automation manual for specific conditions.

[0173] The first mode could be a mode in which the illumination of the first of "n" beams is completed, and then the illumination of the subsequent beams is performed sequentially. For example, in the first mode, the illumination of the second beam can be performed sequentially after the illumination of the first beam is completed. Here, the first mode can be performed in multiple scans, and a beam of light can be provided for each scan. That is, one of the "n" beams of light can be illuminated in one scan.

[0174] The “n” beams of light can illuminate multiple times. For example, the first beam of light can illuminate multiple times, and the second beam of light can also illuminate multiple times. In one embodiment, both the first and second beams of light can be illuminated once. In another embodiment, both the first and second beams of light can be illuminated multiple times, and the illuminating of the first and second beams of light can be performed alternately. Optionally, the second beam of light can illuminate multiple times after the first beam of light has illuminated multiple times.

[0175] The second mode can be a mode in which "n" beams of light are irradiated in one scan. That is, in the second mode, the irradiation of the first light and the second light can be included in one scan. The "n" beams of light can be included in a single beam. For example, the first light and the second light can irradiate substantially simultaneously. In the second mode, the scan can be repeated multiple times.

[0176] The following describes a method for manufacturing semiconductor components using a laser cutting apparatus.

[0177] Figure 17 This is a flowchart illustrating a method for processing a semiconductor element according to an embodiment.

[0178] Reference Figure 17 According to embodiments of this disclosure, a wafer is formed (S110), grooves are formed on the wafer using a laser (S120), and a protective sheet PRT (see reference) is stacked on the upper surface of the wafer with the grooves formed. Figure 18C (S130), polish the back surface of the wafer (S140), mount the wafer on the dicing tape (S150), and then cut the wafer using the dicing tape (S160) to manufacture semiconductor devices.

[0179] Figures 18A to 18E This is a schematic diagram showing the methods for processing semiconductor elements in sequence.

[0180] Reference Figure 17 and Figure 18A This forms a wafer wafer fabrication (WF). The wafer WF may include a substrate and at least one element layer (DV) disposed on the substrate. Figures 18A to 18E In this diagram, the component layer DV is shown as a single layer for ease of description, but the component layer DV may include various components.

[0181] Figure 19A and Figure 19B This is a view showing a wafer fab (WF) including the substrate and the device layer (DV). Figure 19A yes Figure 18B A magnified plan view of part P2, and Figure 19B It is along Figure 19A The side section view taken by line A-A'.

[0182] Reference Figure 18A , Figure 19A and Figure 19B The wafer WF may include a substrate SUB having a front surface and a rear surface opposite to the front surface, and a component layer DV disposed on the front surface of the substrate SUB.

[0183] A wafer wafer fabrication (WF) may include multiple chip regions (CA) and multiple scribe regions (SA). Here, the multiple chip regions (CA) and multiple scribe regions (SA) may extend to the substrate layer (SUB) and the device layer (DV) respectively in a direction perpendicular to the front surface, and may also be used as terms to distinguish wafer wafer fabrication (WF).

[0184] The substrate SUB can be a wafer with a constant thickness and a circular shape. In one embodiment, the substrate SUB can mean a substrate formed of semiconductor material or a substrate including semiconductor material, and / or a substrate used as a substrate for forming semiconductor devices (even if the substrate does not include semiconductor material). In one embodiment, the substrate SUB can be a silicon wafer. The substrate SUB is not limited thereto and can be a wafer including semiconductor elements (such as germanium) or compounds (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). Optionally, the substrate SUB can have a silicon-on-insulator (SOI) structure. In some embodiments, the substrate SUB can include impurity-doped wells or impurity-doped structures corresponding to conductive regions. Furthermore, the substrate SUB can have various device isolation structures (such as shallow trench isolation (STI) structures).

[0185] The component layer (DV) can have multiple integrated circuit regions and can be formed on the front surface of the substrate layer (SUB). Multiple chip regions (CA) can be separated from each other and provided together with the substrate layer (SUB) as a semiconductor chip in subsequent processes.

[0186] Multiple chip regions (CA) can include multiple semiconductor elements (SD). Semiconductor elements (SD) can be divided into memory elements and logic elements.

[0187] Memory devices or elements may include volatile memory elements or non-volatile memory elements. For example, volatile memory elements may include, but are not limited to, memory elements such as, but not limited to, dynamic random access memory (DRAM), static RAM (SRAM), thyristor RAM (TRAM), zero-capacitor RAM (ZRAM), or dual-transistor RAM (TTRAM). Furthermore, non-volatile memory elements may include, for example, memory elements such as flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM, nanofloating gate memory, holographic memory, molecular electronic memory, or insulator resistive switching memory.

[0188] Logic elements may be implemented, for example, but not limited to, microprocessors, graphics processors, signal processors, network processors, audio codecs, video codecs, application processors, or systems on a chip, but this disclosure is not limited thereto.

[0189] Each of the multiple chip regions CA can be configured to be isolated from each other by multiple scribe regions SA. The multiple scribe regions SA may include areas traversed by dicing lines CL. Here, the dicing line CL can be a hypothetical line. In the dicing process described later, the wafer WF can be diced along the dicing line CL. The scribe regions SA can be configured such that portions extending in the row direction and portions extending in the column direction intersect each other. The scribe regions SA can be in the form of straight tracks with a constant width. Figure 19A As shown, chip regions CA can be arranged in multiple rows and columns, with stripe regions SA positioned between them. Chip regions CA can be spaced apart from each other, with each chip region surrounded by a corresponding stripe region SA.

[0190] Each of the plurality of chip regions CA can be a region in which a semiconductor element SD for memory or logic functions is formed. A scribing region SA can be a region in which no semiconductor element is formed. In some embodiments, a plurality of semiconductor dummy elements may be arranged in one or more scribing regions SA.

[0191] In one embodiment, the element layer DV may be configured to include an interlayer insulating film IDL disposed on the front surface of the substrate layer SUB and covering the semiconductor element SD, and a wiring structure WS disposed on the interlayer insulating film IDL and connected to the semiconductor element SD. The wiring structure WS may have a multilayer wiring structure in which insulating layers INS and conductive wiring CDWs are alternately disposed. Furthermore, each layer of conductive wiring CDW may include a plurality of conductive vias CDVs disposed in a direction perpendicular to the front surface of the substrate layer SUB. For example, the conductive wiring CDWs and conductive vias CDVs may be formed of a conductive material including, but not limited to, at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten, platinum (Pt), and gold (Au). In one embodiment, the multilayer conductive wiring CDW is shown as three layers, but this disclosure is not limited thereto. Unlike the embodiment, the multilayer conductive wiring CDW may be formed of two layers or four or more layers.

[0192] The interlayer insulating film (IDL) can be formed of a low-dielectric material. Low-dielectric materials are materials with a lower dielectric constant compared to silicon oxide, and when used as an interlayer insulating film (IDL) in a semiconductor device (SD), they can benefit from improved insulation capabilities, enabling high integration and high speed in the SD. Dummy structures similar to the wiring structure (WS) can be formed in the scribe region (SA). For example, the dummy structures disposed in the scribe region (SA) may include an interlayer insulating film (IDL) and multiple layers of dummy wiring corresponding to the conductive wiring (CDW) and the interlayer insulating film (IDL). In some embodiments, the scribe region (SA) may include test patterns for testing the semiconductor device (SD) in the chip region (CA), redistribution layers for connecting the test patterns, and / or alignment keys for aligning masks. Furthermore, in some embodiments, material films with various functions (such as passivation films) may be additionally formed on the device layer (DV).

[0193] The process for forming a semiconductor device (SD) may include oxidation processes for forming oxide films, photolithography processes including spin coating, exposure and development, thin film deposition processes, dry etching processes or wet etching processes, and metal wiring processes.

[0194] An oxidation process can be a process that forms a thin and uniform (consistent) silicon oxide film by chemically reacting oxygen or water vapor with the surface of a silicon substrate at a high temperature of about 800°C to about 1200°C. Oxidation processes can include dry oxidation and wet oxidation. In dry oxidation, an oxide film is formed by reaction with oxygen, while in wet oxidation, an oxide film is formed by reaction between oxygen and water vapor.

[0195] Photolithography is a process that transfers circuit patterns pre-formed on a photomask onto a substrate through exposure. The photolithography process can be performed in the order of spin coating, exposure, and development.

[0196] Thin film deposition processes may include, for example, but not limited to, any of atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal-organic CVD (MOCVD), physical vapor deposition (PVD), reactive pulsed laser deposition, molecular beam epitaxy, and direct current (DC) magnetron sputtering.

[0197] Dry etching processes may include, for example, but not limited to, any of reactive ion etching (RIE), deep RIE (DRIE), ion beam etching (IBE), and Ar milling. As another example, a dry etching process that can be performed on a wafer may be atomic layer etching (ALE). Furthermore, a dry etching process that can be performed on a wafer wafer (WF) may use at least any one of the following as etchant gases: Cl2, HCl, CHF3, CH2F2, CH3F, H2, BCL3, SiCl4, Br2, HBr, NF3, CF4, C2F6, C4F8, SF6, O2, SO2, and COS.

[0198] Conductive wiring CDW process can be a process of forming conductive wiring CDW (e.g., metallic wiring) to realize a circuit pattern for operation of semiconductor device SD. Conductive wiring CDW process can form ground paths, power paths, and signal transmission paths for operating semiconductor device SD. Conductive wiring CDW may include metallic elements (such as, but not limited to, at least any one of Au, Pt, Ag, Cu, Al, Ti, Ta, and W).

[0199] In some embodiments, planarization processes (such as chemical mechanical polishing (CMP) or ion implantation processes) may also be performed in the semiconductor device SD formation process.

[0200] Reference Figure 17 and Figure 18B Multiple trenches can be formed on the wafer (WF). The trenches can be formed along the dicing line (CL) in the scribing region (SA).

[0201] The operation of forming multiple slots is called a slicing operation. A slicing operation can be an operation that removes only a portion of the wafer's wedge (WF), and can also be called a half-slicing operation.

[0202] A laser beam can be irradiated onto the wafer WF using the aforementioned laser cutting equipment through multiple slots. However, this disclosure is not limited to this, and a laser beam can be irradiated onto the wafer WF using another laser cutting equipment instead of the aforementioned laser cutting equipment, as long as it does not depart from the concept of this disclosure. In the accompanying drawings, only a portion of the laser cutting equipment is disclosed for ease of description.

[0203] The laser cutting equipment can irradiate a laser beam "L" from the upper surface of the wafer (WF) toward the lower surface. The laser beam "L" can be irradiated by a laser irradiation unit (LIR), which is connected to the main body of the laser cutting equipment (LCA) and irradiates the laser beam "L".

[0204] The laser beam "L" irradiated by the laser cutting equipment LCA can be selected from light having the following properties. In one embodiment, the wavelength of the laser beam "L" can be from about 100 nm to about 600 nm. In one embodiment, the pulse width of the laser beam "L" can be from about 1 fs to 1000 ns (e.g., from about 1 fs to about 20 ps). In one embodiment, the energy per pulse of the laser beam "L" can be from about 0.1 μJ to about 50 μJ. In one embodiment, the cumulative energy per unit area of ​​the laser beam "L" can be about 0.1 J / m². 2 Up to 1000J / m 2 The width of the laser beam “L” can range from approximately 1 μm to approximately 1000 μm.

[0205] The laser irradiation unit (LIR) can move along the dicing region (SA) of the wafer (WF). For example, the LIR can move in a horizontal direction (e.g., parallel to the front surface (FS) of the wafer (WF)) and in a direction perpendicular to the horizontal direction, so that the laser beam "L" can irradiate along the dicing region (SA). Alternatively, the LIR can be fixed, and the stage on which the wafer (WF) is mounted can be movable, so that the laser beam "L" irradiates the dicing region (SA). Furthermore, the LIR and the stage on which the wafer (WF) is mounted can move simultaneously, so that the laser beam "L" irradiates the dicing region (SA).

[0206] A groove can be formed by removing a corresponding area of ​​the wafer WF by irradiating a laser beam "L" onto the wafer WF. The groove can be formed to pass through at least a portion of the wafer WF. The groove can pass through at least a portion of the device layer DV and can pass through a portion of the substrate layer SUB disposed below the device layer DV.

[0207] The groove can be used as a crack site, where a crack can appear due to external physical impact.

[0208] In one embodiment, the process of irradiating a laser beam onto a wafer WF can be performed under various conditions, depending on the wafer WF. This will be described later.

[0209] Reference Figure 17 and Figure 18C A protective film (PRT) can be stacked on the front surface of the wafer wafer (WF). The PRT prevents the surface of the wafer WF from being damaged in subsequent processes. For example, the PRT prevents foreign matter from adhering to the upper surface of the component layer (DV).

[0210] Although not shown, the protective sheet PRT may comprise a polymeric resin. The type of polymeric resin is not particularly limited. In one embodiment, the protective sheet PRT may be formed by forming and curing a thermosetting resin or by forming a thermoplastic resin. The protective sheet PRT may be formed using a resin that ensures adhesion to the wafer wafer (WF), prevention of foreign matter intrusion, and cleanability after dicing of the semiconductor wafer. As an example, the protective sheet PRT may comprise a fat-soluble resin or a water-soluble resin. The protective sheet PRT may be formed at various thicknesses as needed.

[0211] In one embodiment, the fat-soluble resin may include a polyurethane resin containing urea groups, polymerized by reacting an alcohol or amine with an isocyanate (salt), or a thermoplastic resin (such as polystyrene (PS), polyethylene terephthalate (PET), or polypropylene (PP)). The thermoplastic resin may have a molecular weight in the range of about 1,000 Mw to 1,000,000 Mw. The water-soluble resin may include polyvinyl alcohol (PVA), polyvinylpyrrolidone (PVP), or an ionomer having ionic functional groups.

[0212] Reference Figure 17 and Figure 18D The back surface (RS) of the wafer (WF) can be polished. The back surface of the wafer (WF) can be polished using a CMP polishing device.

[0213] A wafer WF with a protective sheet PRT attached to its upper surface can be placed on a chuck stage TB with its rear surface RS inverted to face upwards. The rear surface RS of the wafer WF can be a surface on which no device layer DV is formed, and can correspond to a passive surface.

[0214] The thickness of the substrate layer SUB in the wafer WF can be reduced by polishing the back surface RS of the wafer WF.

[0215] The polishing equipment CMP may include a suction table TB that supports the substrate SUB and a polisher GR that polishes the substrate SUB disposed on the suction table TB. The polisher GR can move while rotating, and a polishing pad GP can be attached to the lower part of the polisher GR.

[0216] The polishing process can be a grinding process in which physical pressure is applied to the substrate SUB. The polished substrate SUB can have a smaller thickness compared to before polishing.

[0217] In one embodiment, cracks generated by the trench can easily propagate via a polishing process on the back surface RS of the wafer WF. In one embodiment, at least some of the cracks generated by the trench can propagate toward the back surface of the substrate SUB during the polishing process. However, the propagation of cracks generated by the trench GV may not occur during the polishing operation on the wafer WF, but may occur during the expansion (expansion) operation on the slicing strip, which will be described later.

[0218] Reference Figure 17 and Figure 18E The wafer WF can be mounted on the slicing tape DCT.

[0219] The wafer WF can be inverted again so that the upper surface (or front surface) of the wafer WF with the protective film PRT attached faces upward, and can be mounted on the dicing tape DCT. In one embodiment, the rear surface of the wafer WF can be attached to the dicing tape DCT.

[0220] Although not shown separately, an adhesive film can be attached to the back surface of the wafer WF. The adhesive film supports the wafer WF and facilitates subsequent processing of the wafer WF. An adhesive film can be provided on the back surface RS of the wafer WF before attaching the wafer WF to the dicing tape DCT. In this case, the wafer WF can be attached to the dicing tape DCT, with the adhesive film positioned between the wafer WF and the dicing tape DCT. Alternatively, the adhesive film can be attached to the back surface of the wafer WF before forming grooves in the wafer WF.

[0221] After the wafer wafer (WF) is mounted on the dicing tape (DCT), the protective film (PRT) can be removed. The PRT can be peeled off using a film stripper or removed via a wet cleaning process. The wet cleaning process can be performed using organic or inorganic solvents, depending on the material of the PRT.

[0222] The sliced ​​strip DCT can be supported and fixed by a ring frame RFM attached to one surface of the sliced ​​strip DCT.

[0223] Next, an external force "F" can be applied to the DCT of the slicing strip to expand the DCT, allowing individual semiconductor chips to be separated from the wafer WF. The DCT of the slicing strip can be expanded radially as shown.

[0224] In one embodiment, the sliced ​​DCT can be placed on a clamp, and the clamp can be pushed upward to expand the sliced ​​DCT.

[0225] By extending the slicing tape (DCT), the wafer fabrication layer (WF) can be diced into individual semiconductor chips along the scribe line region (SA). As the slicing tape (DCT) extends simultaneously with the wafer WF, the substrate layer (SUB) can undergo brittle fracture. Brittle fracture refers to the failure of an object without permanent deformation when a force at or greater than its elastic limit is applied. The substrate layer (SUB) can undergo brittle fracture due to cracks (CR) that have propagated from the grooved region. As the slicing tape (DCT) extends, the cracks (CR) generated by the grooves can propagate towards the rear surface of the substrate layer (SUB). Ultimately, as cracks form along the scribe line region (SA) of the isolating chip region (CA), the chip region (CA) can be separated into individual semiconductor chips (CHP) due to the brittle fracture of the substrate layer (SUB).

[0226] Although not shown, individual semiconductor chips can be picked up by other process equipment and transferred to a separate support substrate. The support substrate can be a temporary carrier that supports and secures the semiconductor chip prior to the die attachment process.

[0227] According to embodiments of this disclosure, the process of dicing wafers (WF) to manufacture semiconductor chips can be performed in a different order than described above.

[0228] Figure 20 This is a flowchart illustrating a method for processing a semiconductor element according to an embodiment.

[0229] Reference Figure 20 According to embodiments of the present disclosure, a semiconductor device can be manufactured by forming a wafer (S210), stacking a protective sheet on the upper surface of the wafer (S220), polishing the back surface of the wafer (S230), mounting the wafer on a slicing tape (S240), forming grooves on the wafer with a laser (S250), and cutting the wafer with grooves by using the slicing tape (S260).

[0230] Figures 21A to 21E This is a schematic diagram showing the methods for processing semiconductor elements in sequence.

[0231] Reference Figure 20 and Figure 21A This forms a wafer WF. The wafer WF may include a substrate SUB and at least one element layer DV disposed on the substrate SUB.

[0232] Reference Figure 20 and Figure 21B A protective film (PRT) can be stacked on the front surface (FS) of the wafer (WF). The PRT prevents the surface of the wafer (WF) from being damaged in subsequent processes.

[0233] Reference Figure 20 and Figure 21CThe back surface RS of a wafer WF can be polished. The back surface RS of a wafer WF can be polished using a CMP polishing device. A wafer WF with a protective sheet PRT attached can be placed on a chuck stage TB with the back surface RS inverted to face upwards. The back surface RS of a wafer WF can be a surface on which no device layer DV is formed, and can correspond to a passive surface.

[0234] By polishing the back surface RS of the wafer WF, the thickness of the substrate layer SUB in the wafer WF can be reduced.

[0235] Reference Figure 20 and Figure 21D The wafer WF can be mounted on the slicing tape DCT.

[0236] The wafer WF can be inverted again so that the upper surface with the protective sheet PRT attached is facing upwards, and can be mounted on the dicing tape DCT. In one embodiment, the rear surface RS of the wafer WF can be attached to the dicing tape DCT. After the wafer WF is mounted on the dicing tape DCT, the protective sheet PRT can be removed.

[0237] Next, multiple grooves can be formed on the wafer WF. The grooves can be formed along the dicing line CL in the scribing region SA. Through the multiple grooves, a laser beam can be irradiated onto the wafer WF using the aforementioned laser cutting equipment. However, this disclosure is not limited to this, and a laser beam can be irradiated onto the wafer WF using another laser cutting equipment instead of the aforementioned laser cutting equipment, as long as it does not depart from the concept of this disclosure.

[0238] Reference Figure 20 and Figure 21E Scalable slices with DCT ( Figure 17 (S150 in the diagram) allows individual semiconductor chips to be separated from the wafer WF. The slicing strip DCT can be radially extended as shown.

[0239] In one embodiment, a sliced ​​tape DCT can be placed on a jig, and the jig can be pushed upwards to expand the sliced ​​tape DCT. As the sliced ​​tape DCT expands, an external force "F" is applied to the wafer WF due to the expansion. Due to the external force "F", a crack can appear from the apex of the groove formed in the substrate SUB in a downward direction. Adjacent semiconductor chips can be separated due to the crack, and ultimately, due to the expansion of the sliced ​​tape DCT, the wafer WF can be diced into individual semiconductor chips along the scribing region SA. When the substrate SUB is formed from crystal, the crack can occur along a specific plane in the crystal. The area of ​​the substrate SUB cut by the crack, excluding the area where the groove is formed, can have a substantially flat cut surface.

[0240] When the DCT (Distributed Transformer Cross) is extended to apply tension to the wafer's wafer fracturing (WF), the extension rate of the DCT can be from about 1 mm / s to about 1000 mm / s. For example, the extension rate of the DCT can be about 5 mm / s or greater, or about 10 mm / s or greater. The extension length of the DCT in one direction can be from about 0.1 mm to about 100 mm or from about 0.1 mm to about 30 mm (e.g., from about 1 mm to about 20 mm).

[0241] Individual semiconductor chips can be picked up by other process equipment and transferred to a separate support substrate. The support substrate can be a temporary carrier that supports and secures the semiconductor chip prior to the die attachment process.

[0242] As described above, according to embodiments of the present disclosure, a laser beam can be irradiated using a laser dicing apparatus before or after mounting the wafer WF onto the dicing tape DCT. Therefore, in the method for dicing a wafer WF according to embodiments of the present disclosure, the process sequence can be modified in various ways.

[0243] According to existing technology, in wafer dicing processes using blades, the wafer can only be diced after it has been mounted on the dicing ribbon; therefore, the order of the dicing process cannot be fixed. Furthermore, stealth dicing methods where the laser beam does not pass through the ribbon are only possible before grinding, thus limiting the choice of process sequence.

[0244] Therefore, the method for dicing wafers (WF) according to embodiments of this disclosure is more advantageous in terms of managing raw material dwell time, equipment layout, and logistics activities (logistics movement).

[0245] Figure 22 This is a schematic diagram illustrating the operation of processing a wafer using a laser. Figure 22 This corresponds to the case where the laser cutting equipment is implemented in the first mode. In the following text, for ease of description, the “width” of the light and the “width” of the groove GV in the figures may correspond to the cross-sectional diameter of the light at the position corresponding to the surface of the target object.

[0246] Reference Figure 22 Light with different properties can be sequentially irradiated onto the scribe region SA of the wafer WF. For example, in a first mode, after the first light LS1 is irradiated, the second light LS2 can be irradiated sequentially. In one embodiment, the light with different properties may include, for example, the first light LS1 and the second light LS2.

[0247] The first light LS1 can be set as the light of the etchable element layer DV. Taking into account the material constituting the element layer DV, the thickness of the element layer DV, etc., variables such as the power, pulse repetition rate, scan speed, focal position, width, light shape, number of light segments (e.g., the number of segmented light), wavelength and / or position of the optical axis of the first light LS1 can be determined. For example, the first light LS1 can be light with a first width W1.

[0248] When the first light LS1 illuminates the wafer WF, a portion of the wafer WF (e.g., the device layer DV) can be etched by the first light LS1. Due to the etching of the device layer DV, a first trench GV1 can be formed on the wafer WF. The upper surface of the substrate layer SUB can be exposed through the first trench GV1. That is, the bottom surface of the first trench GV1 can correspond to the upper surface of the substrate layer SUB. The first trench GV1 can be formed to have dimensions corresponding to the width of the first light LS1.

[0249] In one embodiment, the bottom surface of the first groove GV1 can be flat. When the bottom surface of the first groove GV1 is not flat, when the second light LS2 is irradiated, scattering, reflection, refraction, etc. of the second light LS2 may occur due to the non-flat bottom surface of the first groove GV1. Therefore, the second groove GV2 can be formed at an undesired point, and the shape of the second groove GV2 may also be different from the expected shape.

[0250] After the first trench GV1 is formed by the first light LS1, the second light LS2 can be irradiated onto the wafer WF. The second light LS2 can irradiate the first trench GV1 formed by the first light LS1.

[0251] The illumination angle of the first beam LS1 relative to the upper surface of the wafer WF can be smaller than that of the second beam LS2. When the illumination angle of the first beam LS1 is large, the second beam LS2 may have difficulty propagating effectively into the first groove GV1 due to the tilt of the side surface of the first groove GV1.

[0252] In one embodiment, the second light LS2 can be irradiated onto a portion of the lower surface of the first slot GV1. In other words, when viewed in a plane, the area where the first light LS1 is provided may be larger than the area where the second light LS2 is provided, and at least a portion of the area where the second light LS2 is provided may overlap with the area where the first light LS1 is provided. In one embodiment, the area where the second light LS2 is provided may be located within the area where the first light LS1 is provided and may completely overlap with the area where the first light LS1 is provided.

[0253] The second light LS2 can be set as the light of the etchable substrate SUB. Taking into account the material constituting the substrate SUB, the thickness of the substrate SUB, etc., variables such as the power, pulse repetition rate, scanning speed, focal position, width, light shape, number of light segments (e.g., the number of segmented light), wavelength, and / or optical axis position of the second light LS2 can be determined. The second light LS2 can be light with properties different from those of the first light LS1, and at least one variable such as the power, pulse repetition rate, scanning speed, focal position, width, light shape, number of light segments, wavelength, and / or optical axis position of the first light LS1 can be set differently.

[0254] In one embodiment, the second light LS2 can be light with a second width W2. The second width W2 may be smaller than the first width W1.

[0255] When a second light beam LS2 is irradiated onto the wafer WF, a portion of the wafer WF (e.g., the substrate SUB) can be etched by the second light beam LS2. Due to the etching of the substrate SUB, a second trench GV2 can be formed in the substrate SUB. The second trench GV2 can have a depth extending from the upper surface of the substrate SUB toward the rear surface of the substrate SUB. The depth of the second trench GV2 can be smaller than the thickness of the substrate SUB. That is, the second trench GV2 may not penetrate the substrate SUB, and the substrate SUB can be joined as a single component without being separated in the area where the second trench GV2 is not formed. The second trench GV2 can have a shape in which its width decreases from the upper surface to the rear surface of the substrate SUB. For example, when viewed in cross-section, the second trench GV2 can have a cone shape (or "V" shape) with its apex located at its bottom. Alternatively, the second trench GV2 can have an "I" shape with a narrow width and a constant width. The second groove GV2 (specifically, the lower end of the second groove GV2) can be used as a crack site, where a crack can appear due to external physical impact.

[0256] In one embodiment, when the substrate layer SUB comprises silicon and the element layer DV has an insulating layer INS comprising a low dielectric material, the intensity of the first light LS1 may be less than the intensity of the second light LS2.

[0257] The wafer WF can be partially cut (e.g., half-cut) through the first trench GV1 and the second trench GV2.

[0258] In one embodiment, the processes for forming the first groove GV1 and the second groove GV2 can be performed using a single laser cutting device. However, this disclosure is not limited thereto, and the processes for forming the first groove GV1 and the second groove GV2 can be performed using multiple laser cutting devices. When multiple laser cutting devices are used, the multiple laser cutting devices can be devices with different specifications.

[0259] Figure 23 This is a schematic diagram illustrating the operation of processing a wafer using a laser. Figure 23 This corresponds to the case where the laser cutting equipment is implemented in the second mode.

[0260] Reference Figure 23 Lights with different properties can be irradiated together in a single scan. For example, the first light LS1 and the second light LS2 can be irradiated substantially simultaneously in each scan. However, in a single scan, the first light LS1 may be positioned in front of the second light LS2.

[0261] The first light LS1 can be set as the light of the etchable element layer DV, and the second light LS2 can be set as the light of the etchable substrate layer SUB.

[0262] Here, the illumination position, illumination area, and illumination intensity of the first light LS1 and the second light LS2 can be controlled, such that the second groove GV2 formed by the second light LS2 is disposed within the first groove GV1 formed by the first light LS1. Furthermore, considering the material and thickness of the layer to be etched, variables such as the power, pulse repetition rate, scanning speed, focal position, width, shape of the light, number of light segments, wavelength, and position of the optical axis of the first light LS1 and the second light LS2 can be determined. For example, when viewed on a plane, the area where the first light LS1 is provided may be larger than the area where the second light LS2 is provided, and at least a portion of the area where the second light LS2 is provided may overlap with the area where the first light LS1 is provided. In one embodiment, the area where the second light LS2 is provided may be disposed within the area where the first light LS1 is provided.

[0263] When the first light LS1 illuminates the wafer WF, a portion of the wafer WF (e.g., the element layer DV) can be etched by the first light LS1. Due to the etching of the element layer DV, a first trench GV1 can be formed on the wafer WF. The upper surface of the substrate layer SUB can be exposed through the first trench GV1. That is, the bottom surface of the first trench GV1 can correspond to the upper surface of the substrate layer SUB. The first trench GV1 can have dimensions corresponding to the width of the first light LS1.

[0264] When a second light beam LS2 is irradiated onto the wafer WF, a portion of the wafer WF (e.g., the substrate SUB) can be etched by the second light beam LS2. Due to the etching of the substrate SUB, a second trench GV2 can be formed in the substrate SUB. The second trench GV2 can have a depth extending from the upper surface of the substrate SUB toward the rear surface. The depth of the second trench GV2 can be smaller than the thickness of the substrate SUB. That is, the second trench GV2 may not penetrate the substrate SUB, and the substrate SUB can be joined as a single component without separation in the area where the second trench GV2 is not formed. The second trench GV2 can have a shape in which its width decreases from the upper surface of the substrate SUB to the rear surface. For example, when viewed in cross-section, the second trench GV2 can have a conical shape with its apex located at its bottom. The second trench GV2 can serve as a crack site where a crack can appear due to external physical impact.

[0265] In one embodiment, when the first light LS1 and the second light LS2 are illuminated substantially simultaneously, and the first light LS1 is positioned in front of the second light LS2 within a single scan, the first groove GV1 and the second groove GV2 can be formed simultaneously. When the first groove GV1 and the second groove GV2 are formed simultaneously, the time required and process cost for forming the first groove GV1 and the second groove GV2 can be reduced compared to a process where the second groove GV2 is formed after the first groove GV1 is formed.

[0266] In one embodiment, the processes for forming the first groove GV1 and the second groove GV2 can be performed using a single laser cutting device. Specifically, the processes for forming the first groove GV1 and the second groove GV2 can be performed using the laser cutting device according to the above embodiment.

[0267] Figure 24A and Figure 24B This is a schematic diagram illustrating the operation of processing a wafer with multiple element layers using a laser, and shows the laser cutting equipment implemented in a first mode and a second mode, respectively. Figure 24A and Figure 24B The accompanying drawings show that the irradiation timing of the first light to the mth light and the formation sequence of the first trench to the mth trench differ according to the first mode and the second mode, and in other respects, the wafer WF can be processed in a manner substantially the same as that described in the above (one or more) example embodiments.

[0268] Reference Figure 24A and Figure 24BIn embodiments of this disclosure, the wafer WF may include multiple layers including a substrate SUB. The wafer WF may include the substrate SUB and device layers DV stacked on the substrate SUB. For example, the wafer WF may include "n" layers ("n" is a natural number greater than or equal to 2) stacked sequentially from top to bottom. That is, the wafer WF may include a first layer L1, a second layer L2, ..., and an nth layer Ln disposed from top to bottom, and the first layer L1 to the (n-1)th layer Ln-1 may be device layers DV, and the nth layer Ln may be the substrate SUB.

[0269] In one embodiment, each of the "n" layers may be a layer that can be laser-scanned to form a groove under the same conditions without changing the laser irradiation conditions. In one embodiment, each of the "n" layers may have different materials, component strengths, etc., forming its internal components from the other layers, and therefore, two different layers may not be etched simultaneously under one etching condition.

[0270] Furthermore, in one embodiment, one of the "n" layers may be a layer formed with elements different from those formed in adjacent layers. Each element may be an active element or a passive element.

[0271] In one embodiment, each element layer DV can be fabricated in the form of a semiconductor chip. Each element layer DV constructed in the form of a semiconductor chip may include a separate substrate and semiconductor elements formed on the substrate. Layers including separate substrates and semiconductor elements can be stacked on the substrate layer SUB either as is or in an inverted manner. Multiple element layer DVs, all fabricated in the form of semiconductor chips, can also be prepared, and the multiple element layer DVs can be sequentially stacked on the substrate layer SUB.

[0272] In one embodiment, all of two or more of the “n” layers may constitute a single element. In this case, each of the layers constituting a single element may be etched under different etching conditions. In this case, the irradiation conditions of the laser beam used for each layer may vary in at least any of the following variables: laser beam power, pulse repetition rate, scan speed, focal position, width, shape of light, number of light segments, wavelength, and / or position of the optical axis.

[0273] However, the laser irradiation conditions for multiple layers do not need to be the same for each layer, and in other embodiments, two or more layers can be etched simultaneously by adjusting variables such as the power of the laser beam, pulse repetition rate, scanning speed, focal position, width, shape of the light, number of light segments, wavelength and / or position of the optical axis.

[0274] In one embodiment, “m” beams of light (“m” is a natural number greater than or equal to 2) can be irradiated onto “n” layers. For example, the first light LS1, the second light LS2, ……, and the m-th light LSm can be irradiated.

[0275] Here, from the first light LS1, the second light LS2, ……, to the m-th light LSm, the irradiation angles of the first light LS1, the second light LS2, ……, and the m-th light LSm can have relatively large values with respect to the upper surface of the layer to be etched. In other words, the light in the front can be irradiated at a relatively smaller angle with respect to the upper surface of the layer to be removed compared to the light in the back. When the irradiation angle of the front first light LS1 is larger than the irradiation angle of the light in the back, it may be difficult to effectively propagate into the subsequent trench GV due to the inclination of the side surface of the trench GV.

[0276] In one embodiment, “n” and “m” can be the same or different. The drawings show by way of example that n and m are the same.

[0277] The first light LS1 can be irradiated onto the first layer L1 to form the first trench GV1. The first trench GV1 can be formed by etching and removing a part of the first layer L1 via the first light LS1, and can have a width substantially corresponding to the first width W1. A part of the upper surface of the second layer L2 can be exposed through the first trench GV1, and the bottom surface of the first trench GV1 can be the upper surface of the second layer L2. The second light LS2 can be irradiated onto the second layer L2 to form the second trench GV2 in the second layer L2. The second trench GV2 can be formed by etching a part of the second layer L2 via the second light LS2, and can have a width corresponding to the second width W2. In the same manner, the third trench GV3, the fourth trench GV4, ……, and the m-th trench GVm can be formed in the third layer L3, the fourth layer L4, ……, and the n-th layer Ln through the third light LS3, the fourth light LS4, ……, and the m-th light LSm respectively. When the j-th light (j is a natural number, where 1 < j < m) is irradiated onto the i-th layer Li (i is a natural number, where 1 < i < n) to form the j-th trench GVj, the (j + 1)-th light LSj+1 can be irradiated into the j-th trench GVj formed by the j-th light LSj. Here, the j-th width Wj of the j-th trench GVj can be greater than or at least equal to the (j + 1)-th width Wj+1 of the (j + 1)-th trench GVj+1. This is because when the j-th width Wj of the j-th trench GVj is smaller than the (j + 1)-th width Wj+1 of the (j + 1)-th trench GVj+1, the (j + 1)-th light LSj+1 may not be sufficiently irradiated because the (j + 1)-th light LSj+1 is blocked (shielded) by the side wall of the j-th trench GVj.

[0278] In one embodiment, the (j+1)th light LSj+1 may illuminate a portion of the bottom surface of the j-th slot GVj. In other words, when viewed in a plane, the area where the j-th light LSj is provided may be larger than the area where the (j+1)-th light LSj+1 is provided, and at least a portion of the area where the (j+1)-th light LSj+1 is provided may overlap with the area where the j-th light LSj is provided. In one embodiment, the area where the (j+1)-th light LSj+1 is provided may be located within the area where the j-th light LSj is provided and may completely overlap with the area where the j-th light LSj is provided.

[0279] In one embodiment, the first to (n-1)th slots GV1, GV2, ..., GVn-1 can be configured such that they pass through the corresponding layers upward and downward (i.e., in a fully cut manner). Conversely, the mth slot GVm can be configured such that it only passes through a portion of the base layer SUB (i.e., in a partially cut manner (e.g., half-cut)). The mth slot GVm can have a depth in the direction from the upper surface of the base layer SUB toward the rear surface. The depth of the mth slot GVm can be less than the thickness of the base layer SUB. That is, the mth slot GVm may not pass through the base layer SUB, and the base layer SUB can be joined as a single component without separation in the area where the mth slot GVm is not formed. The mth slot GVm can have a shape in which its width decreases from the upper surface of the base layer SUB to the rear surface. For example, when viewed in cross-section, the mth slot GVm can have a conical shape (or "V" shape) with its apex located at its bottom. Alternatively, the mth slot GVm can have an "I" shape with a narrow width and a constant width. The m-th groove GVm can serve as a crack site, where a crack can appear due to external physical impact. In the substrate SUB, when the layer in which the m-th groove GVm is formed is assumed to be the upper layer and the layer in which the m-th groove GVm is not formed is assumed to be the lower layer, the thickness of the lower layer can be 1 micrometer or greater.

[0280] In one embodiment, the bottom surface of the (m-1)th groove GVm-1 can be flat. When the bottom surface of the (m-1)th groove GVm-1 is not flat, during the irradiation of the m-th light LSm used to form crack sites, scattering, reflection, or refraction of the m-th light LSm can occur due to the uneven bottom surface of the (m-1)th groove GVm-1, and therefore, the m-th groove GVm can be formed at an undesired point, and the shape of the m-th groove GVm can also be different from the expected shape.

[0281] In one embodiment, "n" and "m" can be different values. When "n" is larger than "m", two or more layers can be etched with a single beam of light, and when "n" is smaller than "m", one layer can be etched with two or more beams of light. The number of layers and the number of lasers in the wafer WF can be set taking into account the properties of each layer. For example, by setting different laser irradiation conditions according to the materials of the components constituting each layer, the strength of the components, the difference in the coefficient of thermal expansion between interfaces, etc., transverse cracks occurring at the interfaces between adjacent layers can be prevented or reduced.

[0282] In one embodiment, the wafer wafer funnel (WF) can be placed on the dicing tape divider (DCT) after the funnel is formed using a laser, or the funnel can be formed using a laser while the wafer funnel is placed on the DCT. The accompanying drawings illustrate an example where the wafer funnel is positioned on the DCT and the funnel is formed while the wafer funnel is being placed on the DCT.

[0283] As shown, after forming the m-th groove GVm, the slicing tape DCT can be extended to separate individual semiconductor chips (CHPs) from the wafer WF. The extension direction of the slicing tape DCT is indicated by the arrows in the figure. As the slicing tape DCT extends, an external force "F" is applied to the wafer WF due to the extension. Due to the external force "F", cracks can appear from the apex of the m-th groove GVm in a downward direction. Two adjacent semiconductor chips (CHPs) can be separated due to the cracks, and ultimately, the wafer WF can be cut into individual semiconductor chips (CHPs) along the scribe line region SA due to the extension of the slicing tape DCT.

[0284] Figures 25A to 25E This is a schematic diagram illustrating a method for processing a wafer according to an embodiment of the present disclosure.

[0285] Reference Figure 25A A groove can be formed by shining a single beam of light onto a wafer configured as a single layer. That is, a first groove GV1 can be formed by shining a first beam of light LS1 onto a wafer comprising only a first layer L1. Here, the wafer can be a substrate layer SUB or a device layer DV. Subsequently, the wafer can be diced into two semiconductor chips due to cracks (not shown) generated by the first groove GV1 caused by the expansion of the dicing band DCT.

[0286] Reference Figure 25B A groove can be formed by irradiating a wafer consisting of two layers with a single beam of light. Specifically, a first groove GV1 can be formed by irradiating a wafer comprising a first layer L1 and a second layer L2 with a first light beam LS1. The first layer L1 and the second layer L2 can share the first groove GV1. The inner surface of the first layer L1 corresponding to the first groove GV1 can be substantially coplanar with the inner surface of the second layer L2 corresponding to the first groove GV1.

[0287] Subsequently, the wafer can be cut into two semiconductor chips due to the crack (not shown) generated by the first groove GV1 caused by the expansion of the slicing band DCT.

[0288] Reference Figure 25C Three trenches (GV1, GV2, and GV3) can be formed by irradiating a wafer consisting of two layers with three types of light. Specifically, the first to third trenches GV1, GV2, and GV3 can be formed by irradiating a wafer formed from a first layer L1 and a second layer L2 with first to third light beams LS1, LS2, and LS3. The first light beam LS1 and the second light beam LS2 can irradiate the first layer L1. The first to third light beams LS1, LS2, and LS3 can be light beams with first to third widths W1, W2, and W3, respectively, and the first to third widths W1, W2, and W3 can sequentially have smaller values. Here, the first light beam LS1 may not penetrate the first layer L1 and can only etch a portion from the upper surface of the first layer L1 to a specific depth. Therefore, the first trench GV1 can be formed to a depth smaller than the thickness of the first layer L1. The second light beam LS2 can be provided in the region where the first trench GV1 is formed and can form a second trench GV2 that penetrates the remaining portion of the first layer L1. The second trench GV2 can expose a portion of the upper surface of the second layer L2.

[0289] Subsequently, the wafer can be cut into two semiconductor chips due to the crack (not shown) generated by the third groove GV3 caused by the expansion of the slicing band DCT.

[0290] Reference Figure 25D Two trenches (GVs) can be formed by irradiating a wafer consisting of three layers with two types of light. Specifically, a first trench (GV1) and a second trench (GV2) can be formed by irradiating a wafer comprising a first layer (L1), a second layer (L2), and a third layer (L3). In this case, the first trench (GV1) can be disposed on the first layer (L1) and the second layer (L2) to expose a portion of the upper surface of the third layer (L3). The first layer (L1) and the second layer (L2) can share the first trench (GV1). The inner surface in the first layer (L1) corresponding to the first trench (GV1) can be substantially coplanar with the inner surface in the second layer (L2) corresponding to the first trench (GV1).

[0291] Subsequently, the wafer can be cut into two semiconductor chips due to the crack (not shown) generated by the second trench GV2 caused by the expansion of the slicing band DCT.

[0292] Reference Figure 25EThree trenches (GVs) can be formed by irradiating a wafer consisting of three layers with three types of light. Specifically, the first trench GV1 to the third trench GV3 can be formed by irradiating a wafer comprising the first to third layers L1, L2, and L3 with first to third light beams LS1, LS2, and LS3. The first to third light beams LS1, LS2, and LS3 can be light beams having first to third widths W1, W2, and W3, respectively, and the first to third widths W1, W2, and W3 can sequentially have smaller values. In this case, the first trench GV1 can be disposed on the first layer L1 to expose a portion of the upper surface of the second layer L2. The second trench GV2 can be disposed on the second layer L2 to expose a portion of the upper surface of the third layer L3.

[0293] Subsequently, the wafer can be cut into two semiconductor chips due to the crack (not shown) generated by the third groove GV3 caused by the expansion of the slicing band DCT.

[0294] Figure 26A and Figure 26B This is a schematic diagram illustrating a method for processing a wafer according to an embodiment of the present disclosure, and a schematic diagram illustrating the operation of processing a wafer having multiple element layers by using a laser.

[0295] Reference Figure 26A The first light LS1 can be irradiated onto the first layer L1 to form the first groove GV1. Here, the first light LS1 may have a width corresponding to the width of the first groove GV1.

[0296] The second light LS2 can be irradiated onto the second layer L2 to form the second groove GV2. In this case, the second light LS2 may include two beams of light (i.e., the first sub-light LS2a and the second sub-light LS2b) that will be formed with a single width.

[0297] Here, both the first sub-beam LS2a and the second sub-beam LS2b can have a width different from the width of the second slot GV2. For example, both the first sub-beam LS2a and the second sub-beam LS2b can have a width smaller than the width of the second slot GV2. The first sub-beam LS2a and the second sub-beam LS2b may or may not overlap each other, and the total width of the area illuminated by the first sub-beam LS2a and the second sub-beam LS2b can substantially correspond to the width of the second slot GV2.

[0298] In one embodiment, the first sub-light LS2a and the second sub-light LS2b can be simultaneously irradiated onto the second layer L2. However, this disclosure is not limited thereto, and the first sub-light LS2a and the second sub-light LS2b can be irradiated sequentially over time. For example, the first sub-light LS2a can be irradiated first, followed by the second sub-light LS2b. The first sub-light LS2a and the second sub-light LS2b can be light with the same properties or light with different properties.

[0299] The third light LS3 can be irradiated onto the third layer L3 to form the third groove GV3.

[0300] Subsequently, the wafer can be cut into two semiconductor chips due to the crack (not shown) generated by the third groove GV3 caused by the expansion of the slicing band DCT.

[0301] In one embodiment, the second slot GV2 is shown to be formed by two sub-beams LS2a and LS2b, but this disclosure is not limited thereto, and one or more slots may be formed by a greater number of sub-beams. Furthermore, in one embodiment, only the second slot GV2 is shown to be formed by two sub-beams LS2a and LS2b, but this disclosure is not limited thereto, and it is clear that other slots in other layers may also be formed by multiple beams (i.e., multiple sub-beams).

[0302] In one embodiment, at least some of the light illuminating the layer may have different optical axes than the remaining light. In other words, the optical axes of the light illuminating the layer may or may not coincide with each other. For example, in Figure 26A In the embodiment shown, the optical axes of the first light LS1 and the third light LS3 may coincide, but the optical axes of the first light LS1 and the second light LS2 may not coincide. Specifically, in the case of the second light LS2, the optical axes of the first sub-light LS2a and the second sub-light LS2b may not coincide.

[0303] Reference Figure 26B The first light beam LS1 to the third light beam LS3 can be irradiated onto the first layer L1 to the third layer L3 to form the first groove to the third groove GV1, GV2 and GV3. In this case, the first light beam LS1 to the third light beam LS3 can all have different optical axes.

[0304] As described above, the process of forming a groove can be performed using a single beam of light or multiple beams of light. For example, a groove can be formed by irradiating a single beam of light having a specific width corresponding to the groove to be manufactured. Alternatively, a groove can be formed by irradiating multiple beams of light having a specific width smaller than the width of the groove to be manufactured. In this case, the multiple beams of light can be multiple beams of light with the same width or multiple beams of light with different widths.

[0305] Furthermore, in one embodiment, when multiple slots are formed, the optical axes of the light corresponding to the slots may all be the same or at least some may be different. When multiple beams of light are used to form a slot, the optical axes of each beam of light may all be the same or at least some may be different.

[0306] In embodiments of this disclosure, the laser irradiation conditions can vary depending on the material and properties of the layer to which the trench will be formed. For example, laser beams under different conditions can be used in processes that form trenches in a substrate layer including silicon, and in processes that form trenches in a component layer DV including conductors (e.g., metal wires) and an insulating film. The substrate layer including silicon is a highly brittle material, and the component layer including conductors and an insulating film can have lower brittleness than the substrate layer SUB but higher ductility than the substrate layer SUB.

[0307] The component layer can be disposed on the substrate layer, and a groove having a width greater than that of the substrate layer can be formed as described above. The groove can have a structure with a flat bottom. Whether the structure of the groove has good quality (e.g., no defects) can be determined based on the presence of component layer residue (especially conductive wiring residue) in the groove and the number of damages per unit length caused by heat generated during grooving. In other words, the presence or absence of two defects can be determined: one defect may be the presence of component layer residue (especially conductive wiring residue) in the groove due to insufficient grooving, and the other defect is the occurrence of HAZ(s) outside a certain range and damage to the protective film. The presence or absence of defects can be affected by derived parameters calculated from output (power) (W), pulse repetition rate (frequency) (kHz), laser beam width (μm), number of beam divisions (e.g., number of split beams), and number of processing times.

[0308] Figure 27A This illustrates that when grooves are to be formed in the component layer, the presence or absence of groove defects, depending on the laser irradiation conditions, may occur as regions. Figure 27B This illustrates whether grooving defects exist as regions or not, depending on the laser irradiation conditions, when a groove is to be formed in the substrate layer.

[0309] exist Figure 27A and Figure 27B The areas marked with circles are those whose defects have been confirmed through actual experiments, indicating whether defects are present or absent. Defects include residues in the component layer due to insufficient slotting (especially residues of conductive wiring) (indicated by area "A"), and damage to HAZ(one or more) and protective film outside a specific area (indicated by area "B").

[0310] exist Figure 27A In this context, UPE is the energy per unit pulse, UAE is the energy per unit area, and OF is the pulse-to-pulse overlap ratio (or overlap factor) that can be defined by the equations in Table 1 below.

[0311] [Table 1]

[0312] In this equation, Split# represents the number of splits, and Pass# represents the number of scans. OF is an arbitrary value representing the degree of overlap of light during the scan. Furthermore, in Figure 27A In this context, UPE and UAE are functions proportional to the laser power, and OF is a function proportional to the laser scanning speed. They are not represented as separate numerical values ​​but are expressed in arbitrary units for ease of description. Here, LSL signifies the lower limit indicating a defect, and USL signifies the upper limit indicating a defect.

[0313] Reference Figure 27A The success of laser cutting when grooving the element layer can be determined based on the energy per unit pulse, the energy per unit area, and the degree of overlap of light during scanning.

[0314] To perform defect-free grooving of the component layer during laser cutting, the energy per unit area needs to be within a region that is greater than the lower limit and less than the upper limit. Laser cutting defects occur when the energy per unit area is outside this region. When the energy per unit area is greater than the upper limit, there is the problem of insufficient grooving, and when the energy per unit area is less than the lower limit, there are problems with HAZ (high energy density area) or damage to the protective film. The slope of the upper limit of energy per unit area relative to the power of energy per unit area is greater than the slope of the lower limit of energy per unit area relative to the power of energy per unit area.

[0315] Furthermore, in order to perform defect-free grooving on the component layer during laser cutting, the unit pulse energy needs to be within a region greater than the lower limit and less than the upper limit. Laser cutting defects occur when the unit pulse energy is outside this region. When the unit pulse energy is less than the lower limit, there is a problem of insufficient grooving, and when the unit pulse energy is greater than the upper limit, there is a problem of HAZ (hyper-zone) or damage to the protective film.

[0316] Furthermore, when the energy per unit area is less than its upper limit and the overlap of light during scanning is greater than its upper limit, there is a problem of insufficient grooving.

[0317] Reference Figure 27B The success of laser cutting of a substrate layer when grooving can be determined based on the energy per unit pulse, energy per unit area, and the degree of overlap of light during scanning. However, the conditions for the energy per unit pulse, energy per unit area, and degree of overlap of light during scanning used to perform defect-free grooving of a substrate layer are quite different from those used for laser cutting of a component layer to perform defect-free grooving.

[0318] To perform defect grooving on the substrate during laser cutting, the energy per unit area needs to be in a region greater than a lower limit and less than an upper limit. Laser cutting defects occur when the energy per unit area is outside this region. When the energy per unit area is greater than the upper limit, there is a problem of insufficient grooving, and when the energy per unit area is less than the lower limit, there is a problem of HAZ (high energy density area) or damage to the protective film. Here, the upper limit of the energy per unit area relative to the power has a specific inclination relative to the power, but for the power range of energy per unit area shown, there is no lower limit for the energy per unit area.

[0319] Furthermore, in order to perform defect-free grooving of the substrate during laser cutting, the unit pulse energy needs to be in a region greater than the lower limit and less than the upper limit, and laser cutting defects occur when the unit pulse energy is outside this region. When the unit pulse energy is greater than the upper limit, there are problems with HAZ or damage to the protective film, but no lower limit for the unit pulse energy was found for the power range shown.

[0320] In addition, when the energy per unit area is less than its upper limit and the overlap of light during scanning is greater than its upper limit, there is a problem of insufficient grooving, and when the overlap of light during scanning is less than its lower limit, there is a problem of damage to the HAZ or protective film.

[0321] When semiconductor chips are manufactured using the methods described above, defects that may occur during the wafer dicing process can be minimized or prevented compared to methods that use blades to diced wafers. Specifically, when wafers are diced using blades, the yield of semiconductor chips decreases due to crack defects, the presence of foreign matter, reduced chip strength, and increased risk of breakage. However, such problems can be solved when semiconductor chips are manufactured using the manufacturing method according to embodiments of this disclosure.

[0322] Figure 28 This is a schematic diagram showing a semiconductor element manufactured by the method described above for manufacturing a semiconductor device.

[0323] Reference Figure 28 The semiconductor chip CHP may include a substrate SUB and a plurality of element layers DV sequentially stacked on the substrate SUB. In one embodiment, the semiconductor chip CHP may include n+1 layers ("n" is a natural number) sequentially stacked from top to bottom.

[0324] The semiconductor chip CHP may include a chip region CA containing semiconductor elements, etc., and a peripheral region adjacent to the chip region CA. In one embodiment, the peripheral region corresponds to the region corresponding to the scribe region SA before wafer dicing, and therefore, the peripheral region will be referred to as the scribe region SA below.

[0325] The semiconductor chip CHP may include a first layer L1, a second layer L2, ..., and an (n+1)th layer Ln+1 disposed from the top, and the first layer L1 to the (n-1)th layer Ln-1 may be a device layer (DV), and the nth layer Ln and the (n+1)th layer Ln+1 may be a substrate layer (SUB). The nth layer Ln and the (n+1)th layer Ln+1 may be formed as a non-separable integral component, and may be a substrate layer (SUB) formed, for example, from silicon. In one embodiment, the first layer L1 to the (n-1)th layer Ln-1 may have a thickness of about 1 μm or greater, or about 5 μm or greater, or about 10 μm or greater.

[0326] The side surfaces of a semiconductor chip CHP can have different shapes depending on the wafer processing method. The shape of the semiconductor chip CHP can also vary depending on the laser irradiation conditions. In one embodiment, in the scribe region SA, the layers irradiated by the laser beam and the layers subjected to physical force in the absence of a laser beam can have different side surfaces. That is, the side surfaces of the first layer L1 to the nth layer Ln irradiated by the laser beam have different shapes than the side surface of the (n+1)th layer Ln+1 not irradiated by the laser beam.

[0327] Each of the side surfaces of the first layer L1 to the nth layer Ln can be an inclined surface relative to the lower surface of the corresponding layer. The side surface of the (n+1)th layer Ln+1, which is not illuminated by the laser beam, can be a vertical surface relative to the lower surface of the substrate layer SUB. Here, the side surface of the (n+1)th layer Ln+1 can be an inclined surface that is not perfectly vertical, but the side surface of the (n+1)th layer Ln+1 can have a small degree of inclination and can correspond to a substantially vertical surface.

[0328] In one embodiment, from the first layer L1 to the nth layer Ln, the inclined surface of each of the first layers L1 to the nth layer Ln may have a larger inclination angle relative to the lower surface of the corresponding layer. For example, from the first layer L1 to the nth layer Ln, the inclined surface of each of the first layers L1 to the nth layer Ln may have an inclination angle closer to the vertical (i.e., 90 degrees) relative to the lower surface of the corresponding layer. Here, the angles (or inclination angles) θ1, θ2, ..., θn of the inclined surfaces of the first layers L1 to the nth layer Ln relative to the lower surface of the corresponding layer are θ1, θ2, ..., θn. n The temperature should not exceed 90 degrees Celsius.

[0329] The angles θ1, θ2, ..., θ of the inclined surfaces from the first layer L1 to the (n-1)th layer Ln-1 are: n-1 It can have various values. The angles θ1, θ2, ..., θn-1 of the inclined surfaces from the first layer L1 to the (n-1)th layer Ln-1, and θ n-1 It can be approximately 55 degrees to approximately 87 degrees, or approximately 60 degrees to approximately 85 degrees. The tilt angle θ of the nth layer Ln. nComparable tilt angles θ1, θ2, ……, and θ n-1 is large and can be about 85 degrees or greater and less than 90 degrees, or about 80 degrees or greater and less than about 90 degrees. The tilt angle θ of the (n + 1)-th layer n+1 is comparable to the tilt angles θ1, θ2, ……, and θ of the first layer to the n-th layer L1, L2, ……, and Ln n is large and can have an angle close to the vertical line. That is, the tilt angle θ of the (n + 1)-th layer Ln+1 n+1 can be about 85 degrees or greater. The tilt angle θ of the (n + 1)-th layer Ln+1 close to the vertical line n+1 is attributed to the separation during the semiconductor chip CHP manufacturing process by utilizing the tension of the dicing tape DCT without separate mechanical optical processing. Here, the side surface of the (n + 1)-th layer Ln+1 can be flat without any traces of treatment (such as irradiation with a laser beam).

[0330] In one embodiment, the side surfaces of the first layer L1 to the n-th layer Ln can become further away from the chip area CA from the first layer L1 to the n-th layer Ln. In addition, the side surfaces of the first layer L1 to the n-th layer Ln can become closer to the outer boundary of the semiconductor chip CHP from the first layer L1 to the n-th layer Ln. When the distances between the highest points on the side surfaces of the first layer L1 to the n-th layer Ln and the outermost boundaries of the lowermost layer (i.e., the (n + 1)-th layer Ln+1) of the semiconductor chip CHP are assumed to be the first distance to the n-th distance D1, D2, ……, and Dn, the first distance to the n-th distance D1, D2, ……, and Dn can decrease (i.e., become closer to the outer boundary of the semiconductor chip CHP from the first layer L1 to the n-th layer Ln). In other words, the side surfaces of the stacked layers can become further away from the outermost boundary of the (n + 1)-th layer Ln+1 from the lower side to the upper side of the stacked layers. Here, the (i + 1)-th distance Di+1 (1 < i < n) can not exceed the i-th distance Di. That is, the (i + 1)-th distance Di+1 can be less than or equal to the i-th distance Di.

[0331] The tilt angles θ1, θ2, ……, and θ of the inclined surfaces of the first layer L1 to the n-th layer Ln n and the distances D1, D2, ……, and Dn from the outer boundary of the semiconductor chip CHP can be attributed to the conditions for grooving using a laser beam. For example, the tilt angle of the inclined surface can change in response to the shape of the light irradiated onto the first layer L1 to the n-th layer Ln. That is, in the process of forming the side surfaces of the first layer L1 to the n-th layer Ln, the irradiation angles of the first light LS1, the second light LS2, ……, and the m-th light LSm with respect to the upper surface of the layer to be irradiated and removed can have larger values from the first light LS1, the second light LS2, ……, to the m-th light LSm. Therefore, the angles θ1, θ2, ……, and θ of the inclined surfaces of the first layer L1 to the n-th layer Lnn The angle from the first layer L1 to the nth layer Ln can approach 90 degrees. Furthermore, the distance from the outer boundary of the semiconductor chip CHP to the first layer L1 to the nth layer Ln can be increased proportionally to the width of the light illuminating the first layer L1 to the nth layer Ln.

[0332] In one embodiment, the (n+1)th layer Ln+1 may have a specific thickness or greater (e.g., 1 micrometer or greater). However, the (n+1)th layer Ln+1 may have a thickness that allows for dicing by slicing during the dicing process for wafer fabrication (WF). For example, the (n+1)th layer Ln+1 may have a thickness of about 40 μm or less, or about 30 μm or less, or about 20 μm or less. The nth layer Ln may have a thickness of about 1 μm to about 300 μm, or about 2 μm to 200 μm, or about 5 μm to about 150 μm. The first to (n-1)th layers L1, L2, ..., and Ln-1 may have various thicknesses as element layers. For example, the first to (n-1)th layers L1, L2, ..., and Ln-1 may each have a thickness of about 5 μm to about 300 μm, or about 10 μm to about 200 μm, or about 15 μm to about 150 μm.

[0333] In one embodiment, the first to nth layers L1, L2, ..., and Ln may include a heat-affected zone (HAZ) formed from the groove irradiated by the laser beam. A heat-affected zone is a region in which material and / or structure changes due to heat when irradiated by the laser beam. The HAZ may be formed from its side surface toward the interior to a depth of about 0.01 μm or greater (e.g., about 0.5 μm or about 0.1 μm or greater). For example, when the substrate SUB is formed of silicon, in the case of the nth layer Ln, a silicon crystal damage region may exist to a depth of about 0.1 μm or greater from the side surface. The (n+1)th layer Ln+1 may be a region not irradiated by the laser beam and may not have a HAZ.

[0334] In embodiments of this disclosure, each of the second to nth layers L2, L3, ..., and Ln may have an upper flat surface exposed and not covered by a layer directly disposed thereon. For example, the i-th layer Li may have an upper flat surface exposed and not covered by the (i-1)-th layer Li-1. This is due to the change in the width of light irradiating each layer during the grooving process for wafer framing (WF). In one embodiment, when viewed in cross-section, the flat surfaces of the first layer L1 to the (n-1)-th layer Ln-1 may have a width of about 0.1 μm to about 15 μm, or about 0.2 μm to about 12 μm, or about 0.5 μm to about 10 μm.

[0335] Figure 29A and Figure 29B This is a schematic diagram illustrating a semiconductor device manufactured using a method for manufacturing semiconductor devices. Figure 29A An example of a V-groove formed in the substrate SUB is shown, and Figure 29B An example of an I-shaped (or basic I-shaped) groove formed in the base layer SUB is shown.

[0336] Reference Figure 29A The CHP semiconductor chip can have a three-layer stacked structure. In the CHP semiconductor chip, the first layer L1 can be the element layer DV, and the second layer L2 and the third layer L3 can correspond to the substrate layer SUB. The second layer L2 can be disposed on the third layer L3. The second layer L2 and the third layer L3 can be formed as a single component without separation.

[0337] The side surfaces of the first layer L1 and the second layer L2 may have different shapes. The first layer L1 and the second layer L2 may each have an inclined surface relative to the lower surface of the first layer L1 and the second layer L2, respectively. The side surface of the third layer L3 may be a substantially vertical plane relative to the lower surface of the third layer L3.

[0338] The inclined surface of the second layer L2 may have an inclined angle θ2 larger than that of the first layer L1, but may have a value smaller than 90 degrees. In one embodiment, the inclined angle θ1 of the first layer L1 may be from about 60 degrees to about 85 degrees. The inclined angle θ2 of the second layer L2 may have a larger value than that of the first layer L1, and may be from about 60 degrees to about 85 degrees. The inclined angle θ3 of the third layer L3 may be a value close to the vertical line, and may be from about 85 degrees to about 90 degrees.

[0339] In one embodiment, the first layer L1 may serve as a component layer DV, comprising various circuits, wiring, and insulating films, and may have a thickness of approximately 15 μm to approximately 150 μm. The second layer L2 may have a thickness of approximately 5 μm to approximately 50 μm. The third layer L3 may have a thickness of approximately 5 μm to approximately 20 μm.

[0340] The side surface of the first layer L1 can be farther from the outer boundary of the semiconductor chip CHP than the side surface of the second layer L2. The second layer L2 can cover the third layer L3. Therefore, the exposed upper flat surface may not be provided on the third layer L3.

[0341] Reference Figure 29B ,and Figure 29A Similarly, a semiconductor chip CHP can have a three-layer stacked structure. In a semiconductor chip CHP, the first layer L1 can be a component layer (DV), and the second layer L2 and the third layer L3 can correspond to the substrate layer (SUB). The second layer L2 can be disposed on the third layer L3. The second layer L2 and the third layer L3 can be formed as a single component without separation.

[0342] The side surfaces of the first layer L1 and the second layer L2 may have different shapes. The side surface of the first layer L1 may be an inclined surface relative to the lower surface of the first layer L1, and the side surfaces of the second layer L2 and the third layer L3 may be surfaces that are substantially perpendicular to their respective lower surfaces. However, the side surface of the second layer L2 may be substantially close to a vertical plane, but may not be a perfectly vertical plane, and in this case, the side surface of the second layer L2 may have a smaller angle of inclination compared to the side surface of the third layer L3.

[0343] In one embodiment, the tilt angle θ1 of the first layer L1 can be from about 60 degrees to about 85 degrees. The tilt angle θ2 of the second layer L2 can have a larger value than the tilt angle θ1 of the first layer L1, and can be from about 80 degrees to about 89 degrees. The tilt angle θ3 of the third layer L3 can be a value close to the vertical line, and can be from about 85 degrees to about 90 degrees.

[0344] In one embodiment, the first layer L1 may serve as a component layer DV, comprising various circuits, wiring, and insulating films, and may have a thickness of approximately 15 μm to approximately 150 μm. The second layer L2 may have a thickness of approximately 5 μm to approximately 50 μm. The third layer L3 may have a thickness of approximately 5 μm to approximately 20 μm.

[0345] The side surface of the first layer L1 may be farther from the outer boundary of the semiconductor chip CHP than the side surface of the second layer L2. The second layer L2 may not completely cover the third layer L3, and a portion of the upper surface of the third layer L3 may be exposed. Therefore, an exposed upper flat surface may be disposed on the third layer L3.

[0346] Figures 30A to 30E This is a schematic diagram illustrating a semiconductor device manufactured by the method for manufacturing semiconductor devices according to the present disclosure, and showing the semiconductor device manufactured by way of example. Figures 25A to 25E The corresponding semiconductor chip is CHP.

[0347] Reference Figure 30A The semiconductor chip CHP may have a structure in which two layers (i.e., a first layer L1 and a second layer L2) are stacked. The first layer L1 and the second layer L2 may correspond to one of the element layer DV and the substrate layer SUB, and may be formed as a non-separate integral component.

[0348] The side surfaces of the first layer L1 and the second layer L2 may have different shapes. The side surface of the first layer L1 may be an inclined surface relative to the lower surface of the first layer L1. The side surface of the second layer L2 may be a substantially vertical plane relative to the lower surface of the second layer L2. The inclination angle θ2 of the side surface of the second layer L2 may have a larger value than the inclination angle θ1 of the first layer L1. The inclination angle θ1 of the first layer L1 may be from about 60 degrees to about 85 degrees. The inclination angle θ2 of the second layer L2 may be a value close to the vertical line and may be from about 85 degrees to about 90 degrees.

[0349] The first layer L1 can cover the second layer L2. Therefore, the exposed upper flat surface may not be provided on the second layer L2.

[0350] Reference Figure 30B The semiconductor chip CHP can have a structure in which three layers are stacked (i.e., the first layer L1, the second layer L2 and the third layer L3).

[0351] In a semiconductor chip CHP, the first layer L1 can be a component layer DV, the second layer L2 and the third layer L3 can be a substrate layer SUB, and the second layer L2 and the third layer L3 can be formed as a non-separable integrated component.

[0352] The side surfaces of the first layer L1 and the second layer L2 can be inclined surfaces and can be substantially coplanar. The side surface of the third layer L3 can be a substantially vertical plane relative to the lower surface of the third layer L3. The angle θ1 of the side surface of the first layer L1 and the angle θ2 of the side surface of the second layer L2 can be the same value smaller than the angle θ3 of the side surface of the third layer L3, and the inclination angles θ1 and θ2 of the first layer L1 and the second layer L2 can be from about 60 degrees to about 85 degrees. The inclination angle θ3 of the third layer L3 can be a value close to the vertical line and can be from about 85 degrees to about 90 degrees.

[0353] The first layer L1 can completely cover the upper surface of the second layer L2, and the second layer L2 can completely cover the upper surface of the third layer L3. Therefore, the exposed upper flat surface may not be provided on the second layer L2 and the third layer L3.

[0354] Reference Figure 30C The semiconductor chip CHP can have a structure in which three layers are stacked (i.e., the first layer L1, the second layer L2 and the third layer L3).

[0355] In a semiconductor chip CHP, the first layer L1 can be a component layer DV, the second layer L2 and the third layer L3 can be a substrate layer SUB, and the second layer L2 and the third layer L3 can be formed as a non-separable integrated component.

[0356] The side surfaces of the first layer L1 and the second layer L2 can be inclined surfaces and can have different inclination angles. The inclination angle θ1 of the first layer L1 can be smaller than the inclination angle θ2 of the second layer L2, and the inclination angles θ1 of the first layer L1 and θ2 of the second layer L2 can be from about 60 degrees to about 85 degrees. The inclination angle θ3 of the third layer L3 can be a value close to the vertical line and can be from about 85 degrees to about 90 degrees.

[0357] The first layer L1 may cover a portion of the upper surface of the second layer L2, and the exposed upper flat surface may be provided in the uncovered portion of the second layer L2. The second layer L2 may cover the entire upper surface of the third layer L3. Therefore, the third layer L3 may not have an exposed upper flat surface.

[0358] Reference Figure 30D The semiconductor chip CHP can have a structure in which three layers are stacked (i.e., the first layer L1, the second layer L2 and the third layer L3).

[0359] In a semiconductor chip CHP, the first layer L1 can be a device layer (DV), and the second layer L2 and the third layer L3 can be substrate layers (SUB). The second layer L2 and the third layer L3 can be formed as a non-separable, integrated component. The first layer L1 may include a first sublayer L11 and a second sublayer L12. The first sublayer L11 can be disposed on the second sublayer L12.

[0360] Here, the side surfaces of each of the first sublayer L11, the second sublayer L12, and the second layer L2 can be inclined surfaces and can have different inclination angles. The inclination angle of each of the side surfaces of the first sublayer L11, the second sublayer L12, and the second layer L2 relative to its lower surface can have a larger value towards the lower side (i.e., from the first sublayer L11 to the second layer L2). For example, the inclination angle θ of the side surface of the first sublayer L11... 11 The tilt angle θ of the side surface of the comparable second sublayer L12 12 Small, and the tilt angle θ of the side surface of the second sublayer L12 12 The tilt angle θ2 of the side surface of the first sub-layer L11, the second sub-layer L12, and the second layer L2 can be set within the above limitations to be from about 60 degrees to about 85 degrees. The tilt angle θ3 of the third layer L3 can be a value close to the vertical line and can be from about 85 degrees to about 90 degrees.

[0361] The first sublayer L11 may cover a portion of the upper surface of the second sublayer L12, and the uncovered upper surface of the second sublayer L12 may be configured as a flat surface. Furthermore, the second sublayer L12 may cover a portion of the upper surface of the second layer L2, and the uncovered upper surface of the second layer L2 may be configured as an exposed flat surface. The second layer L2 may cover the entire upper surface of the third layer L3. Therefore, the third layer L3 may not have an exposed upper flat surface.

[0362] In this way, at least one of the multiple layers of the semiconductor chip CHP may include two or more sublayers, and therefore may include two or more side surfaces with different tilt angles.

[0363] Reference Figure 30EThe semiconductor chip CHP can have a structure in which four layers are stacked (i.e., the first layer L1, the second layer L2, the third layer L3 and the fourth layer L4).

[0364] In a semiconductor chip CHP, the first layer L1 and the second layer L2 can be component layers (DV), and the third layer L3 and the fourth layer L4 can be substrate layers (SUB). The third layer L3 and the fourth layer L4 can be formed as a non-separable integrated component.

[0365] The side surfaces of the first layer L1 and the second layer L2 can be inclined surfaces and can be substantially coplanar. The side surface of the third layer L3 can be an inclined surface. The side surface of the fourth layer L4 can be a substantially vertical plane relative to the lower surface of the fourth layer L4. The inclination angle θ1 of the side surface of the first layer L1 and the inclination angle θ2 of the side surface of the second layer L2 can have a smaller value than the inclination angle θ3 of the side surface of the third layer L3, and the inclination angle θ3 of the side surface of the third layer L3 can have a smaller value than the inclination angle θ4 of the side surface of the fourth layer L4. The inclination angle of the first layer L1 to the inclination angle of the third layer L3 can be from about 60 degrees to about 85 degrees. The inclination angle of the fourth layer L4 can be a value close to the vertical line and can be from about 85 degrees to about 90 degrees.

[0366] The first layer L1 may completely cover the upper surface of the second layer L2, and therefore, the exposed upper flat surface may not be formed on the upper surface of the second layer L2. The second layer L2 may cover a portion of the upper surface of the third layer L3, and the uncovered upper surface of the third layer L3 may be set as an exposed upper flat surface. The third layer L3 may completely cover the upper surface of the fourth layer L4.

[0367] This disclosure can be used in processes that form various semiconductor chips. For example, a semiconductor chip can be a logic semiconductor chip, a memory semiconductor chip, or any combination thereof. For example, a logic semiconductor chip can include, but is not limited to, an application processor (AP), a microprocessor, a central processing unit (CPU), a controller, a graphics processing unit (GPU), a system-on-a-chip (SoC), or an application-specific integrated circuit (ASIC). Furthermore, a memory semiconductor chip can include volatile memory (such as, for example, but not limited to, dynamic random access memory (DRAM), static random access memory (SRAM)) or non-volatile memory (such as, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)).

[0368] In the following text, one of the various semiconductor chips described above will be described, and the process for manufacturing it using a laser cutting method will be described.

[0369] Figure 31AThis is a cross-sectional view illustrating a semiconductor element according to an embodiment of the present disclosure, and Figure 31B It is specifically shown Figure 31A A cross-sectional view of a semiconductor device.

[0370] Reference Figure 31A and Figure 31B The semiconductor device 100 according to embodiments of the present disclosure may include a plurality of semiconductor chips 110 (e.g., four semiconductor chips 110). The plurality of semiconductor chips 110 may be stacked sequentially, and an adhesive layer 120 is disposed between the plurality of semiconductor chips 110.

[0371] Semiconductor chip 110 may be a logic chip and / or a memory chip. For example, multiple semiconductor chips 110 may all be memory chips of the same type, or some of the multiple semiconductor chips 110 may be memory chips while others may be logic chips. Memory chips may be, for example, volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM)) or non-volatile memory (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) and / or resistive random access memory (RRAM), but are not limited thereto. In embodiments of this disclosure, semiconductor chip 110 may be high-bandwidth memory (HBM) DRAM. Furthermore, logic chips may be, for example, microprocessors, analog elements and / or digital signal processors, but are not limited thereto.

[0372] exist Figure 31A and Figure 31B In the example shown, a semiconductor device 100 in which four semiconductor chips 110 are stacked is illustrated, but the number of semiconductor chips 110 stacked in the semiconductor device 100 is not limited thereto. For example, two, three, five or more semiconductor chips 110 may be stacked in the semiconductor device 100.

[0373] Each of the semiconductor chips 110 may include a chip substrate 111 and a component layer 113 disposed on the chip substrate 111.

[0374] The chip substrate 111 may include a front surface 101a and a rear surface 101b. The front surface 101a and the rear surface 101b are surfaces opposite to each other. The front surface 101a may be the surface on which the component layer 113 is formed, and the rear surface 101b may be the surface opposite to the front surface 101a. The front surface 101a may be an active surface on which multiple integrated circuits are formed, and the rear surface 101b may be a passive surface.

[0375] The chip substrate 111 may be, for example, a doped or undoped silicon (Si) substrate. In other embodiments, the chip substrate 111 may include other semiconductor materials (such as, for example, but not limited to, germanium, compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide compounds and / or indium antimony compounds, mixed semiconductors comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or any combination thereof). The chip substrate 111 may be formed of a single layer or multiple layers. In one embodiment, the chip substrate 111 may have a silicon-on-insulator (SOI) structure. For example, the chip substrate 111 may include a buried oxide (BOx) layer. The chip substrate 111 may include conductive regions (e.g., impurity-doped wells or impurity-doped structures). Furthermore, the chip substrate 111 may have various element isolation structures (such as shallow trench isolation (STI) structures).

[0376] Component layer 113 may be disposed on the front surface 101a of chip substrate 111. Component layer 113 may include multiple individual components and / or wiring connecting the individual components.

[0377] The semiconductor chip 110 may also include a through-via 115, a first pad 131, and a second pad 133. The through-via 115 may pass through the chip substrate 111 and extend from the front surface 101a toward the rear surface 101b or from the rear surface 101b toward the front surface 101a. The through-via 115 may be connected to wiring (not shown) disposed in the component layer 113, or may pass through the component layer 113 to be connected to the first pad 131 and / or the second pad 133. The through-via 115, the first pad 131, and / or the second pad 133 may be directly connected to each other as shown, but may also be electrically connected to each other through various other wiring (not shown).

[0378] In each semiconductor chip 110, a second pad 133 may be disposed on the component layer 113. The second pad 133 may be electrically connected to a wiring structure (not shown) inside the component layer 113, or may be directly connected to a through-via 115. A first pad 131 may be disposed on the rear surface 101b of the chip substrate 111 and may be electrically connected to the through-via 115.

[0379] The first pad 131 and / or the second pad 133 may comprise, for example, but not limited to, metals, metal nitrides, metal oxides, metal silicides, conductive carbon, or any combination thereof. For example, the first pad 131 and / or the second pad 133 may comprise Ag, Al, AlN, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Sn, Ta, TaN, Te, Ti, TiN, W, WN, Zn, Zr, or any combination thereof, but are not limited thereto. In one embodiment, the first pad 131 and / or the second pad 133 may comprise, for example, but not limited to, one of Al, Cu, Ni, W, Pt, and Au.

[0380] Two adjacent semiconductor chips 110 can be connected to each other via connector 135. Connector 135 can be disposed between two adjacent semiconductor chips 110 and a first pad 131 and a second pad 133 facing each other. Connector 135 connecting two adjacent semiconductor chips 110 may include, for example, but not limited to, at least one of conductive bumps, conductive balls, conductive pins, conductive leads, conductive posts, and any combination thereof. For example, each of connectors 135 may include under-bump metal (UBM) and conductive bumps.

[0381] The first pad 131, the second pad 133, and the connector 135 can form a connection terminal 130 to connect two adjacent semiconductor chips 110. The connection terminal 130 can be disposed in the adhesive layer 120. The space between the two semiconductor chips 110 where the connection terminal 130 is disposed can be filled with the adhesive layer 120.

[0382] Connector 135, connected to the lower surface or active surface of the lowest semiconductor chip 110, can be used to electrically connect the semiconductor device 100 to external components (such as a substrate, interposer, package substrate, etc.), which will be described later. Connector 135, connected to the lower surface or active surface of the lowest semiconductor chip 110, can transmit at least one of control signals, power signals, and ground signals for the operation of the semiconductor chip 110 from the outside to a direct circuit chip, receive data signals stored in the semiconductor chip 110 from the outside, and / or provide data stored in the semiconductor chip 110 to the outside.

[0383] The first pad 131 may not be disposed on the chip substrate 111 of the uppermost semiconductor chip 110. Because the first pad 131 is not disposed in the uppermost semiconductor chip 110, the through via 115 connected to the first pad 131 may not be disposed in the uppermost semiconductor chip 110.

[0384] The adhesive layer 120 can attach two adjacent semiconductor chips 110 to each other and may include a polymeric material that is thermally and / or photocured. For example, the adhesive layer 120 may include a resin and a filler. In one embodiment, the resin may have thermosetting properties, and the filler may include fine particles (such as silicon dioxide), but this disclosure is not limited thereto. In one embodiment, the adhesive layer 120 may be a non-conductive film (NCF). Furthermore, the adhesive layer 120 may be a die attach film (DAF).

[0385] The semiconductor device 100 may also include an encapsulation material 150 surrounding the upper surface of the uppermost semiconductor chip 110, the side surfaces of the semiconductor chip 110, and the side surfaces of the adhesive layer 120. The encapsulation material 150 may be formed of a material including, for example, epoxy molding compound (EMC).

[0386] Figures 32A to 32E This is a view showing, in sequence, a method for manufacturing a semiconductor device using the embodiments described above. In the following, reference will be made to... Figures 32A to 32E Describe in detail the methods for manufacturing semiconductor devices.

[0387] Reference Figure 32A A substrate layer 101 is prepared for forming a semiconductor chip. The substrate layer 101 may include a chip region CA and a scribe region SA between the chip regions CA.

[0388] When viewed in a plane, the scribing region SA can surround the four sides of the chip region CA. The width of the scribing region SA corresponding to the four side surfaces of the chip region CA can be the same or different.

[0389] The chip region CA may include a component layer 113 containing multiple integrated circuits and / or wiring. The scribe region SA may be disposed outside the chip region CA in a manner that surrounds the chip region CA.

[0390] Reference Figure 32B The base layer 101 and the element layer 113 can be cut along the cutting line CL defined on the scribing area SA.

[0391] The cutting process of cutting the substrate layer 101 and the component layer 113 along the cutting line CL to separate them into a semiconductor chip 110 can be a laser cutting process according to the above embodiment.

[0392] Reference Figure 32C Multiple stacked semiconductor chips 110 can be placed on the carrier substrate CS.

[0393] Reference Figure 32DAn encapsulation material 150 covering multiple stacked semiconductor chips 110 can be formed on a carrier substrate CS. The encapsulation material 150 may surround the upper surface of the uppermost semiconductor chip 110, the side surfaces of the semiconductor chip 110, and the side surfaces of the adhesive layer 120. The encapsulation material 150 may include various materials, such as epoxy molding compound (EMC).

[0394] Then, the semiconductor element on which the encapsulation material 150 is formed can be cut along the cutting line CL using a cutter CT, and the semiconductor element on which the encapsulation material 150 is formed can be separated into individual semiconductor elements. The cutting process of cutting the semiconductor element on which the encapsulation material 150 is formed along the cutting line CL and separating it into semiconductor elements can be laser cutting according to the method described above. In one embodiment, the cutting process can be a process in which cutting is performed by grinding after laser irradiation.

[0395] Although not shown, the carrier substrate CS can be separated and removed from the semiconductor element on which the encapsulation material 150 is formed before cutting the semiconductor element on which the encapsulation material 150 is formed.

[0396] like Figure 32E As shown, multiple individual semiconductor elements (e.g., semiconductor device 100) can be manufactured by cutting semiconductor elements on which encapsulation material 150 is formed.

[0397] Figure 33 A semiconductor device manufactured by the above method is shown.

[0398] Reference Figure 33 The semiconductor device 100 according to embodiments of the present disclosure may include a substrate chip 140 and a plurality of semiconductor chips 110. The plurality of semiconductor chips 110 may include, for example, four semiconductor chips 110. The substrate chip 140 and the plurality of semiconductor chips 110 may be stacked sequentially, and an adhesive layer 120 is disposed between the substrate chip 140 and the plurality of semiconductor chips 110.

[0399] The substrate chip 140 may include a substrate chip substrate 141 and a substrate circuit layer 143 disposed on the substrate chip substrate 141. Each of the semiconductor chips 110 may include a chip substrate 111 and a component layer 113. The substrate chip 140 and the semiconductor chip 110 may also include a through via 115, a first pad 131 and a second pad 133.

[0400] Both the substrate chip 140 and the semiconductor chip 110 can be logic chips and / or memory chips. For example, multiple substrate chips 140 and semiconductor chips 110 can all be the same type of memory chips, or some of the multiple semiconductor chips 110 can be memory chips and others can be logic chips.

[0401] In embodiments of this disclosure, the substrate chip 140 and the semiconductor chip 110 may be high-bandwidth memory (HBM) DRAM. In this case, the substrate chip 140 may serve as a buffer chip or control chip, integrating signals from multiple DRAM chips and sending them to the outside, and also sending signals and power from the outside to multiple DRAM chips. For example, in one embodiment, the substrate chip 140 may correspond to a master chip. Each of the semiconductor chips 110 stacked on the substrate chip 140 may correspond to a slave chip.

[0402] Encapsulating material 150 may be disposed on the substrate chip 140 and the semiconductor chip 110, surrounding the upper surface of the uppermost semiconductor chip 110, the side surfaces of the semiconductor chip 110, and the side surfaces of the adhesive layer 120. When viewed in a plane, the substrate chip 140 may have a larger area compared to the semiconductor chip 110. The encapsulating material 150 may be disposed on the substrate chip 140 but may not cover the side surfaces of the substrate chip 140. The outer surface of the encapsulating material 150 may define the same plane as the outer surface of the substrate chip 140.

[0403] Semiconductor elements manufactured by the above method according to embodiments of the present disclosure can be applied to various semiconductor packages.

[0404] Figure 34 A semiconductor package according to an embodiment of the present disclosure is shown.

[0405] Reference Figure 34 According to embodiments of the present disclosure, a semiconductor package 10 may include a package substrate 200, a main semiconductor chip 210 mounted on the package substrate 200, and a semiconductor device 100 stacked on the main semiconductor chip 210.

[0406] The main semiconductor chip 210 may be a processor unit. The main semiconductor chip 210 may be, for example, a microprocessor unit (MPU) or a graphics processing unit (GPU). The main semiconductor chip 210 may include a main chip substrate 211, a circuit layer 213, and a main through-hole 115. The main through-hole 115 may have a structure similar to the through-hole 115 of the substrate chip 140 and the semiconductor chip 110, and therefore its detailed description will be omitted.

[0407] Connection terminals 130' and 130'' may be disposed between the semiconductor device 100 and the main semiconductor chip 210, and between the main semiconductor chip 210 and the package substrate 200, respectively. Connection terminals 130' and 130'' may include a first pad and a second pad arranged facing each other, and a connector disposed between the first pad and the second pad. The connector may be at least one of conductive bumps, conductive balls, conductive pins, conductive leads, conductive posts, and any combination thereof. For example, each of the connectors may include conductive filler and / or solder balls.

[0408] The upper surface of the packaging substrate 200, the upper and side surfaces of the semiconductor device 100, and the main semiconductor chip 210 may be covered by the encapsulation material 160.

[0409] External connection terminal 130p can be attached to the lower surface of package substrate 200. External connection terminal 130p can be attached to, for example, a lower surface pad. External connection terminal 130p can be, for example, a solder ball or a bump. External connection terminal 130p can electrically connect semiconductor package 10 and external device.

[0410] Figure 35 A semiconductor package according to an embodiment of the present disclosure is shown.

[0411] Reference Figure 35 According to embodiments of the present disclosure, a semiconductor package 10' may include a package substrate 200, a first semiconductor device 100 mounted on the package substrate 200, and a second semiconductor device 100a.

[0412] The first semiconductor device 100 can be manufactured according to the above embodiment. In this embodiment, for ease of description, it is referred to as... Figure 33 and Figure 34 The corresponding semiconductor element / device is shown as an example.

[0413] The second semiconductor device 100a may be the same as or different from the first semiconductor device 100. In one embodiment, the second semiconductor device 100a may include high-bandwidth memory (HBM), hybrid memory cube (HMC), generation 5 double data rate (DDR5) DRAM, or any combination thereof. Optionally, the second semiconductor device 100a may include a microprocessor, logic chip, application processor, graphics processor, buffer chip, or any combination thereof.

[0414] The upper surface of the packaging substrate 200, as well as the upper and side surfaces of the first semiconductor device 100 and the second semiconductor device 100a, may be covered by the encapsulation material 160.

[0415] External connection terminal 130p may be attached to the lower surface of package substrate 200. External connection terminal 130p may be attached to, for example, a lower surface pad. External connection terminal 130p may include, for example, solder balls and / or bumps. External connection terminal can electrically connect semiconductor package 10' to external devices.

[0416] The semiconductor element according to the embodiments of this disclosure can be applied to one or more semiconductor packages as described above, but this is only an example and can be applied to various semiconductor elements and semiconductor packages other than those described above.

[0417] According to embodiments of the present disclosure, a laser cutting method is provided that can reduce defects in a target object (e.g., a wafer) and reduce the required time and process costs.

[0418] While exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications and substitutions are possible without departing from the scope and spirit of this disclosure as disclosed in the appended claims and their equivalents.

[0419] Therefore, the scope of this disclosure is not limited to the detailed description herein, but should be defined by the claims and their equivalents.

Claims

1. A wafer dicing method, comprising: Multiple grooves are formed by scanning a laser beam onto the front surface of a wafer, wherein the wafer comprises multiple layers and the laser beam comprises at least two beams of light; Polishing the back surface of a wafer; Mounting the wafer onto the slicing tape; and Extended slicing enables wafer cutting. The step of forming the plurality of trenches includes: forming at least two trenches by using the at least two beams of light, wherein the at least two trenches have different widths on at least two of the plurality of layers of the wafer.

2. The wafer dicing method according to claim 1, wherein, The at least two beams of light comprise light divided along the scanning direction and / or in a direction perpendicular to the scanning direction.

3. The wafer dicing method according to claim 2, wherein, The at least two beams of light include light split along the scanning direction.

4. The wafer dicing method according to claim 3, wherein, Of the at least two beams, the beam in front along the scanning direction has a wider width than the beam behind along the scanning direction.

5. The wafer dicing method according to claim 3, wherein, The step of scanning laser beams includes: sequentially or simultaneously irradiating the front surface of the wafer with the at least two beams of light.

6. The wafer dicing method according to claim 3, wherein, The step of scanning a laser beam includes: irradiating a first region on the front surface of a wafer with one of the at least two beams of light positioned in front along the scanning direction, and irradiating a second region of the wafer superimposed on the first region with one of the at least two beams of light positioned behind along the scanning direction.

7. The wafer dicing method according to claim 1, wherein, The number of the plurality of layers of the wafer is the same as the number of the at least two beams of light.

8. The wafer dicing method according to claim 1, wherein, The number of the plurality of layers of the wafer is different from the number of the at least two beams of light.

9. The wafer dicing method according to claim 1, wherein, The wafer comprises layers 1 to n, stacked sequentially from the top to the bottom of the wafer, where n is a natural number greater than or equal to 2. The laser beam comprises beams 1 to m, where m is a natural number greater than or equal to 2. The step of forming the plurality of slots includes: forming the first slot to the mth slot.

10. The wafer dicing method according to claim 9, wherein, The first to the (n-1)th layers of the wafer are set as the device layers, and the nth layer of the wafer is set as the substrate layer.

11. The wafer dicing method according to claim 10, wherein, The step of forming the plurality of slots includes: forming the first slot to the (m-1)th slot to pass through the corresponding layers from the first layer to the (n-1)th layer respectively, and forming the mth slot to pass through only a portion of the nth layer.

12. The wafer dicing method according to claim 11, wherein, m and n are different natural numbers.

13. The wafer dicing method according to claim 2, wherein, The at least two beams of light differ from each other in at least one of the following when they irradiate the wafer: power, pulse repetition rate, scan speed, focal position, light shape, number of slits, wavelength, optical axis position, and pulse width.

14. The wafer dicing method according to claim 1, wherein, The step of scanning the laser beam includes: sequentially or simultaneously irradiating the wafer with the at least two beams of light, the at least two beams of light coming from a single laser cutting device.

15. The wafer dicing method according to claim 1, wherein, The step of scanning the laser beams includes: sequentially irradiating the wafer with the at least two beams of light, the at least two beams of light coming from at least two different laser cutting devices.

16. The wafer dicing method according to claim 1, further comprising: Before the step of polishing the back surface of the wafer, A protective film is stacked on the front surface of the wafer.

17. The wafer dicing method according to claim 1, wherein, A wafer includes chip regions and scribe lines disposed between the chip regions, and The step of scanning the laser beam includes irradiating the wafer with the laser beam along the dicing line in the dicing area.

18. The wafer dicing method according to claim 1, wherein, The steps for forming the plurality of grooves include: Choose one of the first and second modes; Based on the selection of the first mode, during multiple scans of the laser beam, the first beam, which is in front of the at least two beams, illuminates the front surface of the wafer, and the second beam, which is behind the at least two beams, illuminates the front surface of the wafer. Based on the selection of the second mode, during one scan of the laser beam, all of the at least two beams are irradiated onto the front surface of the wafer.

19. A wafer dicing method, comprising: Polishing the back surface of a wafer, which comprises multiple layers; Mount the wafer onto the slicing tape; Multiple grooves are formed by scanning a laser beam onto the front surface of a wafer; the laser beam comprises at least two beams of light. as well as Extended slicing enables wafer cutting. The step of forming the plurality of grooves includes: forming at least two grooves with different widths on at least two of the plurality of layers of the wafer by using the at least two beams of light.

20. The wafer dicing method according to claim 19, further comprising: Before the step of polishing the back surface of the wafer, A protective film is stacked on the front surface of the wafer.

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