Electronic chip comprising crack detection device

Abstract

Embodiments of the disclosure relate to an electronic chip including a crack detection device. An electronic chip includes crack detection devices formed on the interior and top of a substrate or on the top of the substrate. The device includes a conductive path formed by alternating lower and upper conductive strips, where each lower strip includes first and second conductive vias in contact with the lower conductive strip, third and fourth conductive vias in contact with the upper strip and another upper strip, respectively, and first and second conductive traces connecting the first and third vias and the second and fourth vias, respectively. The first and second through holes are positioned vertically aligned with the first and second ends of the lower strip, respectively, and the third and fourth through holes are positioned vertically aligned with one end of the upper strip and one end of the other upper strip, respectively.

Description

Priority requirements

[0001] This application claims priority to French patent application number FR 2412129, filed on November 6, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0002] This disclosure generally relates to electronic chips or integrated circuits, and particularly to electronic chips including, for example, crack detection devices integrated in a sealing ring. Background Technology

[0003] In industry, most electronic devices are manufactured in series. Therefore, multiple electronic chips are typically fabricated inside and on top of the same semiconductor substrate (e.g., the same semiconductor wafer). These electronic chips can then be separated, either individually or singulated, so that they can be used, for example, individually or in electronic devices that include other components. This individualization is usually performed by cutting, for example, using a saw.

[0004] During this process of individualization, such as during the dicing of a semiconductor wafer, cracks can form at one edge of the chip and propagate into the chip. Such cracks can lead to electronic circuit failures in the chip.

[0005] In addition, for example, due to temperature changes in the electronic chip, cracks may form during the chip's lifespan, especially at one edge of the chip.

[0006] To protect electronic chips, particularly during manufacturing, individualization, or use, a sealing ring may be included around the chip. The purpose of the sealing ring is to prevent cracks from propagating from the edges into the electronic circuitry areas of the chip. The sealing ring also aims to prevent moisture from penetrating into the active areas of the chip. However, the sealing ring does not always prevent the formation and propagation of cracks within the electronic chip. Therefore, the chip may include, for example, a crack detection device integrated into the sealing ring. The crack detection device can be used to test the integrity of the chip during manufacturing (e.g., after a dicing step) or during use.

[0007] The goal is to at least partially improve electronic chips, and in particular, to improve crack detection devices incorporated into electronic chips. Summary of the Invention

[0008] In an embodiment, an electronic chip includes: a semiconductor substrate; and a crack detection device formed inside and on top of the semiconductor substrate, or formed on top of the semiconductor substrate; the crack detection device includes a serpentine conductive path between first and second electrical connection terminals of the device, the serpentine conductive path including alternating lower and upper conductive strips connected in series; wherein the conductive path includes, for each lower conductive strip: a first conductive via on top of and in contact with the lower conductive strip; a second conductive via on top of and in contact with the lower conductive strip; a third conductive via below and in contact with an overlying upper conductive strip; and a fourth conductive via on another overlying upper conductive strip. The device comprises a lower conductive strip that contacts the other overlying upper conductive strip; at least one first intermediate conductive trace connecting the first conductive via and the third conductive via; and at least one second intermediate conductive trace connecting the second conductive via and the fourth conductive via; the first conductive via being positioned vertically aligned with a first end of the lower conductive strip, and the second conductive via being positioned aligned with a second end of the lower conductive strip; the third conductive via being positioned vertically aligned with an end of the overlying upper conductive strip, and the fourth conductive via being positioned vertically aligned with an end of the other overlying upper conductive strip; at least 80% of the length of the crack detection device is occupied by the upper conductive strip in a top view, and at least 80% of the length of the crack detection device is occupied by the lower conductive strip in a bottom view; and wherein the lower conductive strip is made of a doped semiconductor material, and the upper conductive strip is made of metal.

[0009] According to an embodiment, in a crack detection device: a first conductive via is positioned aligned with the center portion of an overlying upper conductive strip; a second conductive via is positioned vertically aligned with the center portion of another overlying upper conductive strip; a third conductive via is positioned vertically aligned with the center portion of a lower conductive strip; and a fourth conductive via is positioned vertically aligned with the center portion of the lower conductive strip.

[0010] According to an embodiment, in a crack detection device, a fourth conductive via is aligned with a second conductive via, the fourth conductive via is positioned vertically aligned with the second end of the lower conductive layer, and the second conductive via is positioned vertically aligned with the end of another overlying upper conductive strip.

[0011] According to an embodiment, in the detection device, a third conductive via is positioned vertically aligned with a middle portion of the lower conductive strip located near the second end of the lower conductive strip, the middle portion being located between the center portion of the lower conductive strip and the second end.

[0012] According to an embodiment, for each lower conductive strip, the first through hole is fully positioned vertically aligned with 25% (e.g., 20%) of the strip length furthest from the second end of the lower conductive strip, and the second through hole is fully positioned vertically aligned with 25% (e.g., 20%, e.g., 10%) of the length of the lower conductive strip furthest from the first end of the lower conductive strip.

[0013] According to an embodiment, for each lower conductive strip, the central portion of the lower conductive strip occupies less than 50% of the length of the lower conductive strip, preferably less than 30%, and more preferably less than 20%.

[0014] According to an embodiment, the lower conductive strip is made of silicon.

[0015] According to an embodiment, the chip is defined by an edge, and a crack detection device is arranged between the edge of the electronic chip and the area of ​​the electronic circuitry of the electronic chip.

[0016] According to an embodiment, the semiconductor substrate includes a doped portion of a first conductivity type, and a lower conductive strip is formed entirely in this portion of the semiconductor substrate.

[0017] According to an embodiment, the lower conductive strips are separated by insulating trenches in pairs.

[0018] According to an embodiment, a third conductive via and a fourth conductive via connected to the same upper conductive strip are associated with two consecutive lower conductive strips, the third conductive via being associated with one lower conductive strip and the fourth conductive via being associated with another lower conductive strip.

[0019] According to an embodiment, the lower conductive strip is separated from another lower conductive strip by a distance ranging from 5 nm to 10 μm.

[0020] According to an embodiment, the upper conductive strip is separated from another upper conductive strip by a distance ranging from 20 nm to 10 μm.

[0021] According to an embodiment, the crack detection device includes multiple parts, each part including first and second electrical connection terminals of the device.

[0022] Another embodiment provides a method of manufacturing an electronic chip, including the step of forming a crack detection device inside and on top of a semiconductor substrate or on top of a semiconductor substrate. The crack detection device includes a serpentine conductive path between first and second electrical connection terminals of the device. The serpentine conductive path includes alternating lower and upper conductive strips connected in series. The conductive path includes, for each lower conductive strip: a first conductive via on top of and in contact with the lower conductive strip; a second conductive via on top of and in contact with the lower conductive strip; a third conductive via under an overlying upper conductive strip and in contact with the overlying upper conductive strip; and a fourth conductive via under another overlying upper conductive strip and... The device is in contact with the other overlying upper conductive strip; at least one first intermediate conductive trace connecting the first conductive via and the third conductive via; and at least one second intermediate conductive trace connecting the second conductive via and the fourth conductive via; the first conductive via is positioned vertically aligned with a first end of the lower conductive strip, and the second conductive via is positioned vertically aligned with a second end of the lower conductive strip; the third conductive via is positioned vertically aligned with an end of the overlying upper conductive strip, and the fourth conductive via is positioned vertically aligned with an end of the other overlying upper conductive strip; the length of the crack detection device is 80% occupied by the upper conductive strip in the top view and 80% occupied by the lower conductive strip in the bottom view; and wherein the lower conductive strip is made of a doped semiconductor material, and the upper conductive strip is made of metal.

[0023] According to an embodiment, the method includes the step of testing the conductivity between a first terminal of a crack detection device and a second terminal of a crack detection device in order to detect possible cracks cutting through the conductive path. Attached Figure Description

[0024] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of this disclosure with reference to the accompanying drawings, which are given by way of illustration and not limitation, in which:

[0025] Figures 1A to 1C This is a partial and simplified view of an example of an electronic chip;

[0026] Figure 2A and Figure 2B This is a partial and simplified view of an example of an electronic chip according to an embodiment; and

[0027] Figure 3 This is a partial and simplified cross-sectional view of an example of an electronic chip according to another embodiment. Detailed Implementation

[0028] In the various figures, the same features have been indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0029] For clarity, only those steps and elements useful for understanding the described embodiments have been shown and described in detail. In particular, not all manufacturing steps and details of the electronic chip have been described, and the described embodiments are compatible with common electronic chip manufacturing methods. Specifically, the electronic circuitry of the electronic chip has not been described in detail, and the embodiments are compatible with different electronic circuits in electronic chips. Furthermore, not all manufacturing steps and details of the sealing ring and crack detector have been described, and the described embodiments can be implemented using common sealing ring and crack detector manufacturing methods.

[0030] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0031] In the following description, references to absolute positional qualifiers (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or relative positional qualifiers (such as the terms "top", "bottom", "upper", "lower", etc.) or orientational qualifiers (such as "horizontal", "vertical", etc.) are for reference only unless the orientation of the figures is otherwise specified.

[0032] Unless otherwise specified, the expressions “about,” “approximately,” “basically,” and “in the order of” indicate addition or subtraction of 10% or 10°, preferably 5% or 5°.

[0033] In the following description, unless otherwise specified, the terms "insulating" and "conductive" mean electrically insulating and electrically conductive, respectively. Similarly, unless otherwise specified, the term "insulating" means electrically insulating.

[0034] In the following description, unless otherwise specified, when referring to a chip, the meaning is electronic chip, and when referring to a via, the meaning is conductive via. Furthermore, in the following description, the term via does not necessarily refer to a single element, but can be formed, for example, by multiple elements that enable electrical connection functionality.

[0035] In the following description, when referring to a crack detection device or simply a crack detector, it refers to a device capable of detecting structural defects, not limited to cracks, such as fissures or delaminations. For the sake of brevity, when referring to a crack, this can include fissures, delaminations, or any other similar structural defects.

[0036] In the following description, the first metallization layer of the interconnect structure generally corresponds to the metallization layer closest to the semiconductor substrate having the interconnect structure formed thereon and having interconnect structures connected thereto. The second metallization layer of the interconnect structure corresponds to a metallization layer further away from the semiconductor substrate than the first metallization layer. More generally, metallization layer N+1 corresponds to a metallization layer further away from the semiconductor substrate than metallization layer N.

[0037] Figures 1A to 1C This is a partial and simplified view of an example of electronic chip 100. Specifically, Figure 1A It is a top view. Figure 1B It is along Figure 1A The cross-sectional view of the cross-sectional plane BB, and Figure 1C It is along Figure 1A A cross-sectional view of the cross-sectional plane CC.

[0038] exist Figures 1A to 1C In this design, electronic chip 100 is shown as being individually isolated. However, in practice, this disclosure can also be applied to non-individualized chips when the chip is still part of a semiconductor wafer that includes, for example, multiple chips.

[0039] Chip 100 includes a semiconductor substrate 101, made of silicon, such as monocrystalline silicon. Chip 100 includes electronic circuitry formed, for example, on top of and within the substrate 101. In a top view, the electronic circuitry is formed in a region or circuit region of electronic circuitry 105 of chip 100. As an example, in a top view, circuit region 105 is located in the central portion of chip 100. Region 105 is defined, for example, by a perimeter 105L. As an example, circuit region 105 includes all the electronic circuitry of chip 100.

[0040] As an example, the circuit region 105 of chip 100 is laterally surrounded by a sealing structure 107 or a sealing ring. In other words, the sealing structure 107 is formed on the periphery of chip 100, i.e., between the circuit region 105 and the edge 110 of chip 100. The sealing structure 107 has a ring shape, for example, in a top view. As an example, chip 100 includes an electrical connection between the circuit region 105 and the sealing structure 107.

[0041] In this example, a sealing structure 107 is formed in an interconnect structure 102 disposed above a semiconductor substrate 101, for example, in contact with the semiconductor substrate 101. This interconnect structure 102 is also designated as a "back-end line interconnect structure" or simply a "BEOL" interconnect structure. The interconnect structure 102 may, for example, include metal elements for interconnecting electronic circuitry within the central portion of the chip.

[0042] The sealing structure 107 is arranged in the interconnect structure 102, at the periphery of the chip 100.

[0043] The interconnect structure 102 includes, for example, multiple metallization layers. Figure 1B and Figure 1C The diagram shows six metallization layers: M1, M2, M3, M4, M5, and M6. In reality, the number of metallization layers can be more than six.

[0044] As an example, within circuit region 105, each metallization layer includes at least a portion 103C of conductive layer 103. As an example, each portion 103C corresponds to a conductive element in the form of a conductive trace or conductive line.

[0045] The conductive layer 103 is, for example, a metal layer, such as one made of copper.

[0046] Different portions 103C of the metallization layers are electrically connected to each other, for example, through conductive vias 106. As an example, the upper metallization layer (e.g., metallization layer M6) is connected to the connection pad 104 through its upper surface. As an example, the pad 104 is arranged on the upper surface 102A of the interconnect structure 102, and the lower surface 102B of the interconnect structure opposite to the upper surface 102A is in contact with the semiconductor substrate 101.

[0047] For example, pads 104 are distributed in a substantially circular shape (in this case, square rings) in the circuit region 105 of chip 100. However, the described embodiments are not limited to this particular arrangement.

[0048] The pad 104 is configured to contact a conductive element located outside the chip 100 in order to electrically connect the chip to an external system.

[0049] For example, the metallization layer of interconnect structure 102 is surrounded by an insulating layer, which is entirely represented by one and the same reference numeral 111.

[0050] The objective function of the sealing structure 107 is to prevent cracks from propagating from the edge 110 of the chip 100 to the circuit area 105 of the chip 100.

[0051] Another objective function of the sealing structure 107 is to prevent moisture from propagating from the outside of the chip 100 (i.e. from the edge 110 of the chip 100) to the electronic circuitry of the circuit region 105 of the chip 100.

[0052] To achieve one or more of these functions, the sealing structure 107 may include one or more sealing elements 108, each sealing element 108 having an annular shape in top view.

[0053] Each sealing element 108 extends vertically from the semiconductor substrate 101 through all or part of the metallization layers M1-M6 of the interconnect structure 102, for example through one or more lower metallization layers of the interconnect structure 102. However, for moisture protection, the sealing element 108 preferably extends all the way to the upper metallization layer, here layer M6.

[0054] The sealing element 108 shown forms a closed loop around the circuit region 105 of the chip 100, or in other words, the sealing element 108 completely surrounds the circuit region 105 of the chip 100.

[0055] exist Figure 1B In the illustrated embodiment, the sealing element 108 forms an annular wall comprising other portions 103A of the conductive layer 103 of the interconnect structure 102. More specifically, the sealing element 108 includes a portion 103A of the conductive layer 103 of each metallization layer M1-M6 of the interconnect structure 102. Each portion 103A of the conductive layer 103 forms an annular conductive plate at each metallization layer. The continuous annular conductive plates 103A of the sealing element 108 are interconnected by one or more annular conductive strips 112, which extend continuously between two consecutive annular conductive plates 103A.

[0056] like Figure 1B As shown, the continuous annular conductive plates 103A of the sealing element 108 can also be coupled to each other through conductive vias 106 of the interconnecting structure 102, for example, to increase the mechanical resistance of the sealing element 108 to crack propagation.

[0057] The sealing element 108 can form a protective wall to prevent moisture from spreading to the circuit area 105 of the chip 100.

[0058] like Figure 1B As shown, the sealing element 108 may include a dummy pad 104A, which is formed, for example, simultaneously with the pad 104. The dummy pad 104A rests on the annular conductive plate 103A at the upper metallization layer M6 of the interconnect structure 102. The dummy pad 104A may be arranged in a substantially annular shape, here forming a square ring. Multiple dummy pads may be present.

[0059] To detect cracks in chip 100, the sealing structure 107 may include a crack detection device 116 or a crack detector. In this example, the crack detector 116 is formed on the semiconductor substrate, within the interconnect structure 102. Figure 1A , Figure 1B and Figure 1CAs shown, the crack detection device 116 can be arranged in the region between the edge 110 of the chip 100 and the sealing element 108. Therefore, if a crack appears at the edge 110 of the chip 100 and propagates towards the circuit region 105, the crack can be detected by the crack detection device 116 before the sealing element 108. However, other structures are also conceivable.

[0060] As an example, the crack detection device 116 is placed between two separate sealing elements 108. The crack detection device 116 and the sealing element 108 are not limited to those described. Furthermore, the number of crack detection devices 116 and sealing elements 108 is not limited. Therefore, multiple copies of the crack detection device 116 and sealing element 108 can be provided in the sealing structure 107.

[0061] The crack detection device 116 corresponds to a conductive structure that forms a conductive path (preferably an open loop) between a first terminal or node 118 (e.g., the first end of the detection device 116) and a second terminal 119 (e.g., the second end of the detection device 116). Cracks can be detected by the detection device 116 by testing the conductivity between the first terminal 118 and the second terminal 119 of the detection device 116. As a variation, the crack detection device 116 includes multiple portions that are not electrically coupled together, each portion including two terminals.

[0062] exist Figure 1B and Figure 1C In the example of the embodiment shown, the crack detection device 116 includes a plurality of metal stacks 109, each metal stack including an additional portion 103B of a conductive layer 103 coupled through a conductive via 106 of an interconnect structure 102. For example, the metal stacks 109 are organized along the length of the crack detection device 116. More precisely, each metal stack 109 extends in height in the Z direction perpendicular to the XY plane of the semiconductor substrate 101 through all or part of the metallization layers M1–M6 of the interconnect structure 102, extending in the example shown all the way to the upper metallization layer M6. As an example, each metal stack 109 includes two opposing (e.g., identical) vertical portions coupled together only through the upper metallization layer (e.g., layer M6). Thus, each metal stack 109 has a bridge shape, having feet or pillars as the two vertical portions and a deck corresponding to the conductive layer 103 of the metallization layer M6.

[0063] In the example shown, adjacent legs of two adjacent metal stacks 109 are coupled only through metal layer 114 formed in metallization layer M1. Therefore, along... Figure 1CIn a cross-sectional view of the cross-sectional plane, the crack detection device 116 has a crenellated serpentine shape, which has a vertical portion corresponding to the vertical pillar of the metal stack 109 and a horizontal portion that alternately consists of a portion of the lower layer 114 of the lower metallization layer M1 and a portion of the layer 103 of the upper metallization layer M6.

[0064] The inventors have observed that cracks can propagate within the sealing structure 107, or even pass through the sealing structure, without being detected by the crack detector 116.

[0065] Specifically, some vertical cracks may propagate through the crack detection device 116, and due to the ductility of layer 114, may deform the lower metal layer 114 but not break it. Therefore, these cracks will not cause a break in the conductive path between terminals 118 and 119 of the detection device 116, and thus will not be detected.

[0066] Furthermore, horizontal cracks propagating beneath the sealing structure 107, and particularly between layer 114 and substrate 101, may also go undetected.

[0067] Figure 2A and Figure 2B Here is a partial and simplified view of an example of an electronic chip 200 according to an embodiment: Figure 2B It is an illustrative photograph of an overhead view, and Figure 2A It is along Figure 2B A simplified cross-sectional view of section AA.

[0068] Electronic chip 200, for example, similar to Figures 1A to 1C The electronic chip 100 shown in the figure differs from the chip 200 in that it includes a crack detection device 216, which is different from the crack detection device 116.

[0069] and Figures 1A to 1C Similar to device 116, device 216 includes two connection terminals (in Figure 2A and Figure 2B The conductive path between (not visible in the middle) is, for example, in the form of an open loop laterally surrounding the active portion of the chip, with the connection terminals corresponding, for example, to terminals 118 and 119 of device 116. In a top view, the arrangement of crack detection device 216 is, for example, similar to the arrangement of device 116. Similar to the arrangement of... Figures 1A to 1C As already described, the crack detection device 216 may include multiple portions connected by additional terminals. Therefore, the number of terminals within the crack detection device 216 is not limited to two.

[0070] Figure 2A and Figure 2BThe detection device includes a serpentine conductive path comprising alternating lower conductive strip 201 and upper conductive strip 203 connected in series between the device's connection terminals.

[0071] According to one aspect of the described embodiment, the lower conductive strip is made of a doped semiconductor material, such as doped silicon.

[0072] According to an embodiment, each lower conductive strip 201 is formed from a doped region of the substrate 101 such that the strips 201 are flush with the upper surface of the substrate 101 through their upper surfaces. As an example, the strips 201 extend downward in the substrate 101 to a depth ranging from a few nm (e.g., 10 nm to 100 nm).

[0073] As a variation, the conductive strips 201 are embedded in the substrate 101. In this variation, each conductive strip 201 extends to the upper surface of the substrate 101, at least at its two ends, for example, only at its two ends. As an example, the extended portions of the strips 201 are formed by another conductive layer. Therefore, the conductive layer 201 does not appear on the upper surface of the substrate 101, but only the extended portions of other conductive layers appear on the upper surface of the substrate 101.

[0074] As an example, substrate 101 includes a doped portion 101P of a first conductivity type (e.g., P-type).

[0075] As an example, the first portion 101P of the substrate 101 extends deeper than the conductive strip 201. That is, the conductive strip 201 is entirely formed in the upper portion 101P of the substrate 101.

[0076] The lower conductive strip 201 is, for example, doped with a second conductivity type opposite to that of region 101P. As an example, the lower conductive strip 201 is N-type doped.

[0077] This construction ensures that the strips 201 are electrically insulated from each other and from the substrate.

[0078] As an example, the conductive strip 201 is made of a semiconductor material. As an example, the conductive strip 201 is made of a non-ductile material (that is, a material that cannot be stretched, pulled or extended without breaking), for example, having less ductility than the metal of the interconnect structure.

[0079] As a variation, the lower conductive strip 201 is formed on the substrate 101, for example, on the layer forming the doped polysilicon conductive gate. More generally, the lower conductive strip 201 can be formed in any other forming layer present beneath the metallization layer M1.

[0080] The conductive strips 201 are aligned, for example, along the longitudinal axis of the conductive path of the crack detector and are not directly connected together. As an example, the conductive strips 201 are separated from each other by insulating trenches 202 made of an insulating material (e.g., silicon oxide). As an example, the trenches 202 extend deeper than the conductive strips 201. For example, trench 202 is formed simultaneously with other insulating trenches formed around the transistor in circuit region 105. Trench 202 is, for example, an STI (shallow trench isolation) trench. As a variation, trench 202 is, for example, a DTI (deep trench isolation) type trench.

[0081] As an example, the distance between two adjacent stripes 201 is greater than 5 nm. The distance between two adjacent stripes 201 is, for example, less than 10 μm. The distance between two adjacent stripes 201 is, for example, less than 5 μm. In fact, the reliability of the crack detection device 216 depends particularly on the distance between two adjacent stripes 201, therefore this distance must be as short as possible to increase the reliability of the device.

[0082] The upper conductive strips 203 are aligned, for example, along the longitudinal axis of the conductive path of the crack detector, parallel to the lower conductive strips 201, and are not directly connected to each other. For example, they are separated from each other by thin regions made of dielectric material of the interconnect structure.

[0083] As an example, the distance between two adjacent stripes 203 is greater than 20 nm. The distance between two adjacent stripes 203 is, for example, less than 10 μm. The distance between two adjacent stripes 203 is, for example, less than 5 μm. In fact, similar to what has already been described regarding the distance between stripes 201, the reliability of the crack detection device 216 depends particularly on the distance between two adjacent stripes 203, therefore this distance must be as short as possible to increase the reliability of the device.

[0084] As an example, the lower conductive strip 201 is mainly covered by the upper conductive strip 203. That is, most of the surface area of ​​the lower conductive strip 201 is covered by the upper conductive strip 203.

[0085] As an example, a lower strip 201 is formed below and opposite the upper strip 203. However, the lower strip 201 is offset from the upper strip 203 such that the central portion of the upper strip 203 is vertically aligned with the dividing region between the two consecutive lower strips 201, and the central portion of the lower strip 201 is vertically aligned with the dividing region between the two consecutive upper strips 203. The lower conductive strip 201 and the upper conductive strip 203 have, for example, substantially the same length. As a variation, the lower conductive strip 201 and the upper conductive strip 203 have different lengths.

[0086] Each of the lower conductive strips 201 is connected to a first conductive via 205A, and each first via 205A is formed on and in contact with the conductive strip 201 to which it is connected.

[0087] Each first conductive via 205A is positioned vertically aligned with the first end of the lower conductive strip 201 to which it is connected. As an example, each first via 205A is thus perfectly vertically aligned with 25% (e.g., 20%, e.g., 10%) of the length of the lower conductive strip 201 at the second end furthest from the first end. Furthermore, in Figure 2A In the embodiment illustrated herein, each first through-hole 205A is positioned vertically aligned with the center portion of the overlying upper conductive strip 203.

[0088] Each of the lower conductive strips 201 is also connected to a second conductive via 205B, and each second via 205B is formed on and in contact with the conductive strip 201 to which it is connected.

[0089] Each second conductive via 205B is positioned vertically aligned with the second end of the lower conductive strip 201 to which it is connected. As an example, each second via 205B is thus positioned vertically aligned with 25% (e.g., 20%, e.g., 10%) of the length of the lower conductive strip 201 furthest from the first end of that lower conductive strip 201. Furthermore, in Figure 2A In the embodiment illustrated herein, each second through-hole 205B is positioned vertically aligned with the center portion of the overlying upper conductive strip 203.

[0090] As an example, vias 205A and 205B associated with the same lower conductive strip 201 are covered by two consecutive upper conductive strips 203. Figure 2A In the example, the through-hole 205A is covered by the upper strip 203 and is formed opposite to the central portion of the upper strip 203. Figure 2A In the example, the through hole 205B is covered by the upper strip 203' and is formed opposite to the central portion of the upper strip 203'.

[0091] As an example, the central portion of the upper conductive strip 203, which is vertically aligned with the positions of the first through hole 205A and the second through hole 205B, occupies less than 50% of the length of the upper conductive strip 203, preferably less than 30%, and more preferably less than 20%.

[0092] The crack detection device 216 also includes a third conductive via 207A opposite to each conductive strip 201. The third via 207A is formed under and in contact with the overlying upper conductive strip 203.

[0093] Each third conductive via 207A is vertically positioned above the first end of the upper conductive strip 203 to which it is connected. As an example, each third via 207A is thus vertically aligned with 25% (e.g., 20%, e.g., 10%) of the length of the upper conductive strip at the second end furthest from the first end of the upper conductive strip 203. Furthermore, in Figure 2A In the embodiment illustrated, each third through-hole 207A is positioned vertically aligned with the center portion of the underlying lower conductive strip 201.

[0094] The crack detection device 216 also includes a fourth conductive via 207B opposite to each conductive strip 201. The fourth via 207B is formed under and in contact with the overlying upper conductive strip 203.

[0095] Through-holes 207A and 207B are formed under two consecutive upper conductive strips 203. Figure 2A In the example, through-hole 207A is formed below upper strip 203. Figure 2A In the example, through-hole 207B is formed under the upper strip 203′.

[0096] Each fourth conductive via 207B is positioned vertically aligned with the first end of the overlying upper conductive strip 203'. As an example, each fourth via 207B is thus positioned vertically aligned with 25% (e.g., 20%, e.g., 10%) of the length of the upper conductive strip at the second end furthest from the first end of the upper conductive strip 203. Furthermore, in Figure 2A In the embodiment illustrated herein, each fourth through-hole 207B is positioned vertically aligned with the center portion of the underlying lower conductive strip 201.

[0097] As an example, the central portion of the lower conductive strip 201, which is vertically aligned with the positions of the third through hole 207A and the fourth through hole 207B, occupies less than 50% of the length of the lower conductive strip 201, preferably less than 30%, and more preferably less than 20%.

[0098] As an example, each upper conductive strip (e.g.) Figure 2A The strip 203' in the middle is connected to the fourth conductive via, for example... Figure 2A Through-hole 207B; and to the third conductive through-hole, for example Figure 2A The through-hole 207A′, the third conductive through-hole and the fourth conductive through-hole are formed opposite to the two continuous lower strips.

[0099] The crack detection device 216 further includes at least one first intermediate conductive trace 209A and at least one second intermediate conductive trace 209B vertically aligned with each lower strip 201. The first intermediate conductive trace 209A connects to the first conductive via 205A and the third conductive via 207A, and the second intermediate conductive trace 209B connects to the second conductive via 205B and the fourth conductive via 207B.

[0100] As an example, a first conductive via 205A is connected to a first intermediate conductive trace 209A, the first intermediate conductive trace 209A being vertically aligned with a first end of the first trace 209A. As an example, a third via 207A is connected to the first intermediate conductive trace 209A, the first intermediate conductive trace 209A being vertically aligned with a second end of the first trace 209A, the second end of the first trace 209A being opposite to the first end of the first trace 209A.

[0101] Similarly, as an example, a second conductive via 205B is connected to a second intermediate conductive trace 209B, the second intermediate conductive trace 209B being vertically aligned with the first end of the second trace 209B. As an example, a fourth via 207B is connected to the second intermediate conductive trace 209B, the second intermediate conductive trace 209B being vertically aligned with the second end of the second trace 209B, the second end of the second trace 209B being opposite to the first end of the second trace 209B.

[0102] As an example, the serpentine conductive path of the crack detection device 216 includes continuous upper conductive strips 203, 203′, 203′′, continuous third conductive vias 207A, 207A′, 207A′′, continuous first intermediate conductive traces 209A, 209A′, 209A′′, continuous first conductive vias 205A, 205A′, 205A′′, continuous lower conductive strips 201, 201′, 201′′, continuous second conductive vias 205B, 205B′, continuous second intermediate conductive traces 209B, 209B′, and continuous fourth conductive vias 207B, 207B′.

[0103] The upper conductive strip 203 is made of metal or a metal alloy. As an example, strip 203 is made of copper, aluminum, or an alloy of copper and aluminum.

[0104] The third conductive via 207A and the fourth conductive via 207B are made of metal, for example, copper, aluminum or a mixture of copper and aluminum.

[0105] The first conductive via 205A and the second conductive via 205B are made of a metallic material, such as tungsten or tantalum, or a mixture of copper and tantalum.

[0106] As an example, although this is in Figure 2ANot shown, but conductive vias 207A and 207B can each correspond to a conductive stack formed by vias of other conductive intermediate traces and coupling intermediate traces.

[0107] In this example, the conductive vias formed between the intermediate conductive traces are vertically oriented to align with one of the ends of the overlay and underlay conductive traces, or opposite to the central portion of these intermediate conductive traces.

[0108] As an example, the vias coupling the two intermediate conductive traces are vertically aligned.

[0109] As a variation, the vias coupling the two intermediate conductive traces are not vertically aligned.

[0110] like Figure 2B As shown, the sealing structure 107 may include an internal crack detection device 216I, which is disposed in the interconnect structure 102 around or at the edge of the circuit region 105 and surrounded by a sealing element 108 or an internal sealing element. The internal crack detection device 216I can detect cracks that have propagated from the edge 110 of the chip 100 through the sealing elements(s) and can reach the circuit region 105.

[0111] like Figure 2B As shown, the sealing structure 107 may also include an external crack detection device 216E arranged around the sealing element 108 in the interconnect structure 102.

[0112] As a variation, one or the other crack detection device in crack detection devices 216I and 216E can be omitted. Furthermore, sealing element 108 can be omitted.

[0113] Figure 3 This is a partial and simplified cross-sectional view of an example of an electronic chip 300 according to another embodiment.

[0114] Electronic chip 300 includes, for example, with Figure 2A and 2B The chip 200 shown has the same components. The chip 300 also includes a crack detection device 316 similar to the crack detection device 216, except that the structure formed by the through holes 205A, 205B, 207A and 207B, the lower strip 201, the upper stripes 203 and 203′, and the traces 209A and 209′ is not symmetrical.

[0115] In this embodiment, through holes 205B and 207B are aligned.

[0116] In this embodiment, each through-hole 207B is positioned vertically aligned with through-hole 205B. In this embodiment, each of through-holes 205B and 207B is positioned vertically aligned with the second end of the underlying lower conductive strip 201. Furthermore, in this embodiment, each of through-holes 205B and 207B is positioned vertically aligned with the first end of the overlying upper conductive strip 203'.

[0117] As an example, the third conductive via 207A is positioned vertically aligned with the middle portion located near the second end of the underlying lower conductive strip 201, which is situated between the second end and the center portion of the lower conductive strip 201.

[0118] As an example, the first conductive via 205A is positioned vertically aligned with a middle portion located near the second end of the overlying upper conductive strip 203, the middle portion being positioned between the second end and the center portion of the upper conductive strip 203.

[0119] More generally, conductive traces 201 and 203 may have, in addition to, regarding Figure 2A and Figure 3 Other arrangements besides those described. According to aspects of the described embodiments, in a top view or in a horizontal section FF in the upper metallization layer of conductive traces 203, 203′, 203′′, at least 80%, preferably at least 90%, of the length of the crack detection device is occupied by the upper conductive traces 203, 203′, 203′′.

[0120] Similarly, according to aspects of the described embodiments, at least 80%, preferably at least 90%, of the length of the crack detection device is occupied by the lower conductive strips 201, 201', 201'' in the top view or in the horizontal section BB of the layer of the lower conductive strips 201, 201''.

[0121] The advantages of the described embodiments relate to the serpentine shape of the conductive path forming the crack detection device 216, which includes continuous nested loops, thereby providing good coverage of the detection surface by both the upper conductive strip 203 and the lower conductive strip 201. This enables increased detection sensitivity.

[0122] The short distance between the continuous lower conductive strip 201 and the short distance between the continuous upper conductive strip 203 also increases the detection sensitivity.

[0123] Another advantage of the described embodiments is that the presence of intermediate conductive traces enables the detection of intermetallic delamination.

[0124] Another advantage of the described embodiments relates to the use of non-ductile semiconductor materials (i.e., materials that cannot be stretched, pulled, or extended without breaking) or semiconductor materials with less ductility than the metals of the interconnect structures to form the lower conductive strip 201. This allows for better detection of vertical cracks or delamination between the metallization layer and the semiconductor substrate.

[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, although this has not yet been described... Figure 2A and 2B As shown, however, each of the conductive vias 205A, 205B, 207A and 207B may be provided with a conductive via corresponding to a group of multiple groups (i.e., conductive vias formed close to each other).

[0126] In any case, the contact surfaces between the conductive vias 205A, 207A, 207B and the conductive strips 201, 203 are preferably entirely within 25%, for example 20%, or for example 10%, of the length of the conductive strip closest to its end. That is, preferably, in the central portion extending beyond 60% (preferably 80%) of the length of each strip, no electrically connected vias contact the upper surface of the conductive strip 201, and in the central portion extending beyond 60% (preferably 80%) of the length of each strip, no electrically connected vias contact the lower side of the conductive strip 203.

[0127] In other words, the connection surfaces of conductive strips 201 and 203 are preferably entirely within 25% of the length of the conductive strip closest to its end, for example, within 20% or 10%. More specifically, the connection surfaces of each lower conductive strip 201 to the two upper conductive strips 203 above it (i.e., the surfaces through which the lower conductive strip 201 connects to the two upper conductive strips 203 above it) are preferably entirely within 25% of the length of the lower conductive strip 201 closest to its two ends, for example, within 20% or 10%. Similarly, the connection regions of each upper conductive strip 203 to the two underlying lower conductive strips 201 (i.e., the regions through which the upper conductive strip 203 connects to the underlying lower conductive strips 201) are preferably entirely within 25% of the length of the upper conductive strip 203 closest to its two ends, for example, within 20% or 10%.

[0128] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A crack detection device, comprising: Alternating series connection of the lower and upper conductive strips The interconnecting surfaces of the conductive strips are positioned within 25% of the length of the conductive strip closest to its end.

2. A crack detection device, comprising: Alternating series connection of the lower and upper conductive strips The interconnecting surfaces of the conductive strips are positioned within 20% of the length of the conductive strip closest to its end.

3. The device according to claim 1 or 2, wherein when viewed from above, at least 80% of the length of the device is occupied by the upper conductive strip, and when viewed from below, at least 80% of the length of the device is occupied by the lower conductive strip.

4. The device according to claim 1 or 2, wherein the lower conductive strip is made of a doped semiconductor material and the upper conductive strip is made of metal.

5. The device according to claim 1 or 2, wherein the lower conductive strip and the upper conductive strip respectively define a conductive path between the first electrical connection terminal and the second electrical connection terminal of the device.

6. The device of claim 5, wherein for each lower conductive strip, the conductive path comprises: The first conductive via is located on the top of the lower conductive strip and is in contact with the lower conductive strip; The second conductive via is located on the top of the lower conductive strip and is in contact with the lower conductive strip; The third conductive via is located below and in contact with the upper conductive strip. The fourth conductive via is located below and in contact with another overlying conductive strip. At least one first intermediate conductive trace connects the first conductive via and the third conductive via; as well as At least one second intermediate conductive trace connects the second conductive via and the fourth conductive via; The first conductive via is positioned vertically aligned with the first end of the lower conductive strip, and the second conductive via is positioned aligned with the second end of the lower conductive strip; and The third conductive via is positioned vertically aligned with one end of the overlying upper conductive strip, and the fourth conductive via is positioned vertically aligned with one end of the other overlying upper conductive strip.

7. The device according to claim 6, wherein: The first conductive via is positioned vertically aligned with the center portion of the overlying upper conductive strip; The second conductive via is positioned to be vertically aligned with the center portion of the other overlying upper conductive strip; The third conductive through hole is positioned so as to be vertically aligned with the center portion of the lower conductive strip; as well as The fourth conductive via is positioned vertically aligned with the center portion of the lower conductive strip.

8. The device according to claim 7, wherein, For each lower conductive strip, the central portion of the lower conductive strip occupies less than 50% of the length of the lower conductive strip.

9. The device according to claim 6, wherein: The fourth conductive through hole is aligned with the second conductive through hole; The fourth conductive via is positioned to be vertically aligned with the second end of the lower conductive layer; as well as The second conductive via is positioned to be vertically aligned with the end of the other overlying conductive strip.

10. The device according to claim 9, wherein, The third conductive via is positioned vertically aligned with the middle portion of the lower conductive strip located near the second end of the lower conductive strip, the middle portion being located between the center portion of the lower conductive strip and the second end.

11. The device of claim 6, wherein for each lower conductive strip, the first through-hole is fully positioned vertically aligned with 25% of the length of the strip at the second end furthest from the lower conductive strip, and the second through-hole is fully positioned vertically aligned with 25% of the length of the lower conductive strip at the first end furthest from the lower conductive strip.

12. The device according to claim 1 or 2, wherein the lower conductive strip is made of silicon.

13. The device according to claim 1 or 2, formed in and on a semiconductor substrate, wherein the semiconductor substrate includes a doped portion of a first conductivity type, and the lower conductive strip is formed entirely in the doped portion of the semiconductor substrate.

14. The device according to claim 1 or 2, wherein the lower conductive strips are separated by insulating trenches in pairs.

15. The device according to claim 1 or 2, wherein each lower conductive strip is spaced from the adjacent lower conductive strip by a distance in the range of 5 nm to 10 μm.

16. The device according to claim 1 or 2, wherein each upper conductive strip is spaced from the adjacent upper conductive strip by a distance ranging from 20 nm to 10 μm.

17. An electronic chip including a crack detection device according to claim 1 or 2, wherein the electronic chip is defined by an edge, and the crack detection device is disposed between the edge of the electronic chip and an electronic circuit region of the electronic chip.

18. An electronic chip, comprising: Semiconductor substrate; as well as A crack detection device is formed inside the semiconductor substrate and on top of the semiconductor substrate, or formed on top of the semiconductor substrate; The crack detection device includes a serpentine conductive path between a first electrical connection terminal and a second electrical connection terminal of the device, the serpentine conductive path including alternating lower and upper conductive strips connected in series; The serpentine conductive path for each lower conductive strip includes: The first conductive via is located on the top of the lower conductive strip and is in contact with the lower conductive strip; The second conductive via is located on the top of the lower conductive strip and is in contact with the lower conductive strip; The third conductive via is located below and in contact with the upper conductive strip. The fourth conductive via is located below and in contact with another overlying conductive strip. At least one first intermediate conductive trace connects the first conductive via and the third conductive via; and At least one second intermediate conductive trace connects the second conductive via and the fourth conductive via; The first conductive through hole is positioned vertically aligned with the first end of the lower conductive strip, and the second conductive through hole is positioned aligned with the second end of the lower conductive strip; The third conductive via is positioned vertically aligned with one end of the overlying upper conductive strip, and the fourth conductive via is positioned vertically aligned with one end of the other overlying upper conductive strip. In the top view, at least 80% of the length of the crack detection device is occupied by the upper conductive strip, and in the bottom view, at least 80% of the length of the crack detection device is occupied by the lower conductive strip; and The lower conductive strip is made of a doped semiconductor material, and the upper conductive strip is made of metal.

19. The electronic chip of claim 18, wherein the conductive vias contacting the lower conductive strip are positioned completely opposite to the lower conductive strip at 25% of its length closest to each end, and wherein the conductive vias contacting the upper conductive strip are positioned completely opposite to the upper conductive strip at 25% of its length closest to each end.

20. The electronic chip of claim 18, wherein for each lower conductive strip, the first via is fully positioned vertically aligned with 25% of the length of the strip at the second end furthest from the lower conductive strip, and the second via is fully positioned vertically aligned with 25% of the length of the lower conductive strip at the first end furthest from the lower conductive strip.

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