Package carrier and preparation method thereof, and semiconductor package structure

Abstract

The invention provides a packaging substrate and a preparation method thereof, and a semiconductor packaging structure, the packaging substrate comprises a packaging substrate, the packaging substrate comprises an inorganic substrate and an organic substrate, the inorganic substrate is provided with a through groove penetrating along the thickness direction, the organic substrate is embedded in the through groove, and the inorganic substrate is provided with a plurality of through holes; the organic substrate comprises a first through hole penetrating through the organic substrate in the thickness direction; and the conductive structure is at least partially located in the first through hole. According to the invention, the inorganic substrate provides support for the whole body, so that warping of the large-size carrier plate in a heating process can be inhibited; meanwhile, the hole opening and filling process of the organic substrate is mature, the crack risk is low, the packaging substrate integrates the characteristics of the inorganic substrate and the organic substrate, and the problem that in large-size packaging, rigidity is insufficient, and wiring requirements are difficult to consider is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and its preparation method, and a semiconductor packaging structure. Background Technology

[0002] With the development of high-performance chips, chip integration is becoming increasingly higher, and interconnect density is also becoming denser. Multi-chip stacking places higher demands on IC substrates, requiring larger dimensions, lower warpage, and high flatness to avoid solder layer failure. Traditional organic substrates cannot support large-size packaging due to mechanical strength limitations. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a packaging substrate and its preparation method, as well as a semiconductor packaging structure, to reduce the risk of substrate warping.

[0004] In view of the above objectives, firstly, this application provides a packaging carrier board, comprising: The packaging substrate includes an inorganic substrate and an organic substrate. The inorganic substrate has a through groove that extends through the substrate along its thickness direction. The organic substrate is embedded in the through groove. The organic substrate includes a first through hole that extends through the organic substrate along its thickness direction. A conductive structure is located at least partially within the first through-hole.

[0005] Optionally, the inorganic substrate is a glass substrate.

[0006] Optionally, the conductive structure includes a conductive layer, the conductive layer including an annular structure and surrounding a first opening extending along the thickness direction, the first opening being filled with an insulating structure.

[0007] Optionally, the packaging substrate further includes a seed layer, which is located at least between the wall of the first through hole and the conductive structure; Optionally, the seed layer includes an adhesive sublayer and a conductive sublayer stacked together, wherein the adhesive sublayer contacts the wall of the first through hole, and the conductive sublayer contacts the conductive structure; Optionally, the seed layer includes a first portion covering the wall of the first through-hole, a second portion covering at least a portion of the surface of the organic substrate, and a third portion covering at least a portion of the surface of the inorganic substrate.

[0008] Optionally, at least one surface of the organic substrate is flush with the surface of the inorganic substrate located on the same side; Optionally, the surfaces on opposite sides of the organic substrate are flush with the surface of the inorganic substrate.

[0009] Optionally, the packaging substrate further includes a bonding layer, which is located between the organic substrate and the inorganic substrate, and the organic substrate is fixed to the wall of the through groove through the bonding layer; Optionally, the through groove is a rectangular groove; Optionally, the material of the bonding layer includes resin.

[0010] Optionally, the packaging substrate further includes a redistribution layer, which is disposed on at least one side of the packaging substrate. The redistribution layer includes at least one dielectric layer and at least one circuit layer, and the circuit layer is electrically connected to the conductive structure. Optionally, the redistribution layer covers at least a portion of the surface of the organic substrate and at least a portion of the surface of the inorganic substrate.

[0011] Secondly, this application also provides a method for preparing a packaging carrier, comprising: An inorganic substrate is provided, and a through groove extending along the thickness direction is formed in the inorganic substrate; An organic substrate is embedded in the through groove to form an encapsulation substrate; A first through-hole is formed in the organic substrate, extending along the thickness direction; A conductive structure is formed within the first through-hole.

[0012] Optionally, a conductive structure is formed within the first through-hole, including: A conductive layer is formed that at least covers the wall of the first through hole, the conductive layer forming the first opening; The first opening is filled with insulating material to form an insulating structure; Optionally, after forming the insulating structure, the method further includes: At least one layer of conductive material is deposited on the surface of the packaging substrate, and a circuit layer is formed by patterning. Create at least one dielectric layer to form a redistribution layer; Optionally, the circuit layer covers the ends of the insulation structure; Optionally, a conductive structure is formed within the first through-hole, including: A seed layer is prepared, the seed layer comprising a first portion covering the wall of the first through-hole, a second portion covering at least a portion of the surface of the organic substrate, and a third portion covering at least a portion of the surface of the inorganic substrate; The conductive layer and the first opening are formed on the seed layer by a conformal electroplating process.

[0013] Thirdly, this application also provides a semiconductor packaging structure, including a packaging substrate as described in any of the first aspects above.

[0014] The packaging substrate provided in this application is composed of an inorganic substrate and an organic substrate embedded in a through groove of the inorganic substrate. The organic substrate has a first through hole, and at least part of the first through hole has a conductive structure. The inorganic substrate provides rigid support for the entire substrate, suppressing warping of large-size substrates during heating processes. Meanwhile, the opening and filling processes of the organic substrate are mature and have a low risk of cracking. The packaging substrate of this application combines the characteristics of both inorganic and organic substrates, thereby improving the rigidity and flatness of the substrate while solving the problem of insufficient rigidity and difficulty in meeting wiring requirements in large-size packaging. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic cross-sectional view of a packaging carrier provided in an embodiment of this application; Figure 2 This is a schematic cross-sectional view of another packaging carrier provided in an embodiment of this application; Figure 3 This is a schematic cross-sectional view of another packaging carrier provided in an embodiment of this application; Figure 4 This is a schematic cross-sectional view of another packaging carrier provided in an embodiment of this application; Figure 5 This is a top view schematic diagram of the packaging substrate of the packaging carrier provided in the embodiments of this application; Figure 6 This is a schematic flowchart of a method for preparing a packaging substrate provided in an embodiment of this application; Figure 7 This is a schematic diagram illustrating the structural changes of the packaging carrier provided in the embodiments of this application during the manufacturing process; Figure 8 This is a schematic diagram illustrating the structural changes of the packaging carrier provided in the embodiments of this application during the manufacturing process; Figure 9 This is a schematic diagram of the structural changes of the packaging substrate provided in the embodiments of this application during the manufacturing process.

[0017] Marker explanation: 100. Packaging carrier board; 10. Encapsulation substrate; 11. Organic substrate; 111. First through-hole; 12. Inorganic substrate; 121. Through-groove; 122. Bonding layer; 13. Conductive structure; 130. First opening; 131. Conductive layer; 132. Insulating structure; 20. Seed layer; 21. Adhesive sublayer; 22. Conductive sublayer; 201. First portion; 202. Second portion; 203. Third portion; 30. Redundancy layer; 31. Circuit layer; 32. Dielectric layer; 40. Surface treatment layer; 50. Solder mask layer; 51. First opening; 60. Conductive bump. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] Driven by the development of high-performance chips, chip integration is constantly increasing, and multi-chip stacking packaging places higher demands on IC substrates. To meet the needs of multi-chip stacking, packaging substrates need to have larger dimensions, lower warpage, and higher flatness to avoid solder layer failure. In related technologies, commonly used packaging substrates are mainly organic substrates. However, organic materials themselves have low mechanical strength and insufficient rigidity. When manufacturing large-size substrates, they are prone to warping and deformation during thermal processing due to mismatched coefficients of thermal expansion or curing shrinkage. This warpage problem directly affects the accuracy and reliability of subsequent chip mounting, and in severe cases, can lead to solder layer cracking or connection failure. Therefore, how to improve the rigidity of large-size packaging substrates and reduce warpage while ensuring high-density interconnect capabilities is an urgent problem to be solved in this field.

[0021] It should be noted that with the development of semiconductor packaging, substrates need to simultaneously support multiple side-by-side or stacked chips, and their planar dimensions have expanded from the traditional 20-30mm range to 50mm or even over 100mm. At this size, traditional organic substrates, due to their low material modulus and significant difference in thermal expansion coefficients compared to silicon chips, typically experience warpage exceeding 80-100μm after reflow soldering or multiple thermal cycles, exceeding the tolerance limit for warpage in chip mounting processes (typically ≤50μm). Therefore, this application addresses the large-size scenarios where insufficient rigidity of organic substrates leads to pronounced warpage problems.

[0022] This application provides a packaging carrier 100 with a composite structure of an organic substrate and an inorganic substrate. Specifically, by forming a through-groove in the highly rigid inorganic substrate and embedding the organic substrate within the through-groove, the high strength of the inorganic substrate provides rigid support for the entire composite substrate, suppressing warping. Simultaneously, through-holes and conductive structures are fabricated within the organic substrate, leveraging its ease of high-density wiring to achieve electrical interconnection. The inorganic substrate primarily serves a structural support function, while the organic substrate primarily serves an electrical interconnection function. The organic and inorganic substrates are combined through an embedded structure, solving the warping problem of large-size carriers while retaining the capability for high-density wiring.

[0023] like Figure 1 As shown, the encapsulation carrier 100 includes an encapsulation substrate 10, which includes an inorganic substrate 12 and an organic substrate 11. The inorganic substrate 12 has a through groove 121 extending through the substrate in the thickness direction. The organic substrate 11 is embedded within the through groove 121. The organic substrate 11 includes a first through hole 111 extending through the substrate in the thickness direction. The encapsulation carrier 100 also includes a conductive structure 13, which is at least partially located within the first through hole 111.

[0024] In some embodiments, the inorganic substrate 12 is a glass substrate. Glass materials have high elastic modulus and mechanical strength, and low coefficient of thermal expansion, which can provide good rigid support for the composite substrate and suppress warping deformation of the organic substrate 11 during heating. As an alternative embodiment, the inorganic substrate 12 can also be made of other inorganic materials with high strength, such as ceramics, silicon, etc., as long as they can provide sufficient rigid support.

[0025] The organic substrate 11 is a polymer material substrate, such as ajinomoto stacked film, bismaleimide triazine resin, polyimide, etc. The organic substrate 11 has dielectric properties and processability, making it easy to fabricate fine lines and microvias, and is suitable for high-density interconnects.

[0026] The shape and size of the through groove 121 can be set according to actual needs, for example, it can be a rectangular groove. The size of the organic substrate 11 matches the through groove 121, and the organic substrate 11 is fixed after being embedded in the inorganic substrate 12.

[0027] The organic substrate 11 includes a plurality of spaced-apart first vias 111, which are used to achieve vertical electrical interconnection. Conductive structures 13 fill the first vias 111 to form vertical conductive channels. The conductive structures 13 may include metallic materials, such as copper, aluminum, nickel, gold, etc., preferably copper.

[0028] The packaging substrate 100 provided in this application embodiment forms a composite structure packaging substrate 10 by embedding an organic substrate 11 into a through groove 121 of an inorganic substrate 12. The inorganic substrate 12, acting as a rigid framework, provides the main mechanical support, improving the overall rigidity and warpage resistance of the substrate. Compared to a pure organic substrate of the same size, the packaging substrate 100 of this application exhibits reduced warpage after undergoing thermal processes such as reflow soldering. Simultaneously, the opening and filling processes of the organic substrate 11 are mature, with a low risk of cracking, and it possesses the capability for high-density wiring, allowing for the fabrication of fine lines and microvias to meet the interconnection requirements of multi-chip stacking.

[0029] In some embodiments, such as Figure 2 As shown, the conductive structure 13 includes a conductive layer 131, which includes an annular structure and forms a first opening 130 extending along the thickness direction. The first opening 130 is filled with an insulating structure 132.

[0030] Specifically, the conductive layer 131 can be formed, for example, by a conformal electroplating process. The conductive layer 131 can cover the wall of the first through-hole 111, forming a cylindrical or cup-shaped metal layer. Since the conductive layer 131 only covers the hole wall, a first opening 130 is formed in the central region of the first through-hole 111. An insulating material, such as epoxy resin or polyimide, is filled into the first opening 130 to form an insulating structure 132. The conductive structure 13 forms a "conformal electroplating + resin plugging" structure, which has the following effects: on the one hand, the conductive layer 131, as the main channel for electrical interconnection, has a controllable thickness and low resistance; on the other hand, the filled insulating structure 132 can flatten the surface, providing a flat base for subsequent fabrication of the redistribution layer, while preventing electroplating solution residue or contaminants from accumulating in the first opening 130. In addition, the insulating structure 132 can also buffer stress and improve the reliability of the packaging substrate.

[0031] In other embodiments, the conductive structure 13 includes only the conductive layer 131 and does not include the insulating structure 132. That is, the conductive structure 13 is a solid metal pillar that completely fills the first through-hole 111. This structure is suitable for scenarios with high current carrying capacity requirements, such as power transmission paths.

[0032] In some embodiments, the packaging substrate 100 further includes a seed layer 20, which is located at least between the wall of the first through hole 111 and the conductive structure 13.

[0033] Specifically, the seed layer 20 is used to enhance the bonding force between the conductive structure 13 and the organic substrate 11, and serves as a conductive substrate for electroplating. The seed layer 20 can be formed by methods such as electroless copper plating or physical vapor deposition, and the material can be copper, titanium, chromium, nickel, or a combination thereof.

[0034] In some embodiments, such as Figure 2 As shown, the seed layer 20 includes an adhesive sublayer 21 and a conductive sublayer 22 stacked together. The adhesive sublayer 21 contacts the wall of the first through-hole 111, and the conductive sublayer 22 contacts the conductive structure 13. The adhesive sublayer 21, which contacts the wall of the first through-hole 111, is used to improve adhesion; the material can be titanium, chromium, etc. The conductive sublayer 22, which contacts the conductive structure 13, is formed on the adhesive sublayer 21 and is used for subsequent electroplating growth; the material can be copper. The dual-layer structure of the seed layer 20 can balance adhesion and conductivity.

[0035] In some embodiments, the seed layer 20 includes a first portion 201, a second portion 202, and a third portion 203, wherein the first portion 201 covers the wall of the first through-hole 111, the second portion 202 covers at least a portion of the surface of the organic substrate 11, and the third portion 203 covers at least a portion of the surface of the inorganic substrate 12. Using a seed layer 20 with a large coverage area facilitates full-surface metallization during subsequent electroplating, making it easier to form circuit layers or other conductive structures on the surface of the packaging substrate.

[0036] In some embodiments, at least one surface of the organic substrate 11 is flush with the surface of the inorganic substrate 12 located on the same side.

[0037] Specifically, after the organic substrate 11 is embedded and fixed, planarization processes such as grinding are used to make the upper and / or lower surfaces of the organic substrate 11 flush with the corresponding surfaces of the inorganic substrate 12. This planarization structure has the following beneficial effects: First, it provides a flat process surface for the subsequent fabrication of redistribution layers, which is beneficial to improving photolithography accuracy and circuit quality; second, it eliminates the height difference between the organic substrate 11 and the inorganic substrate 12, avoiding stress concentration or cracks caused by steps in subsequent processing; finally, the flat surface facilitates full-surface coating and photolithography operations, simplifying the process.

[0038] Furthermore, the surfaces on opposite sides of the organic substrate 11 are flush with the corresponding surfaces of the inorganic substrate 12. That is, after the organic substrate 11 is embedded and fixed, a double-sided grinding process is used to make the upper and lower surfaces of the organic substrate 11 flush with the upper and lower surfaces of the inorganic substrate 12. This double-sided planarization structure is suitable for scenarios where redistribution layers 30 need to be fabricated on both sides of the packaging substrate 10, providing a flat process surface for double-sided wiring.

[0039] In some embodiments, the packaging carrier 100 further includes a bonding layer 122, which is located between the organic substrate 11 and the inorganic substrate 12, and the organic substrate 11 is fixed to the wall of the through groove 121 by the bonding layer 122.

[0040] Specifically, the bonding layer 122 serves to bond and fix the substrate, while also buffering thermal stress between the organic substrate 11 and the inorganic substrate 12. The bonding layer 122 can be made of a resin with good adhesion and a certain degree of flexibility, such as epoxy resin, acrylic resin, or polyimide resin. During manufacturing, the bonding layer material can be first applied to the through-groove 121 or the edge of the organic substrate 11, then the organic substrate 11 can be embedded and fixed by heating or curing.

[0041] In some embodiments, the through-groove 121 is a rectangular groove, meaning that the outer contour of the through-groove 121 is rectangular. Rectangular grooves are easy to process and match the shape of conventional organic substrates 11, making it easy to achieve precise positioning and alignment. Of course, the through-groove 121 can also be set to other shapes, such as circular, elliptical, or polygonal, which can be adjusted according to application requirements.

[0042] In some embodiments, the material of the bonding layer 122 includes resin. The resin material has good flowability, can fully fill gaps, provides sufficient adhesive strength after curing, and also has a certain elastic modulus to buffer thermal stress.

[0043] In some embodiments, such as Figure 4 As shown, the packaging substrate 100 also includes a redistribution layer 30, which is disposed on at least one side of the packaging substrate 10. The redistribution layer 30 includes at least one dielectric layer 32 and at least one circuit layer 31, and the circuit layer 31 is electrically connected to the conductive structure 13.

[0044] A redistribution layer 30 is provided on the upper and / or lower sides of the packaging substrate 10, wherein the circuit layer 31 is electrically connected to the conductive structure 13, and is used to lead out and rearrange the conductive structure 13 in the first through hole 111 to form a pad or bump under metal layer suitable for chip mounting.

[0045] The redistribution layer 30 can be fabricated using a layer-addition process. Specifically, a dielectric material is first coated or laminated onto the surface of the packaging substrate 10 to form a dielectric layer; then, vias are fabricated on the dielectric layer, and a circuit layer is formed through processes such as seed layer deposition, photolithography, electroplating, and etching; depending on the interconnection requirements, the above steps can be repeated to form a multilayer wiring structure.

[0046] In some embodiments, the redistribution layer 30 covers at least a portion of the surface of the organic substrate 11 and at least a portion of the surface of the inorganic substrate 12. That is, the wiring layer 31 of the redistribution layer 30 extends from the organic substrate 11 region to above the inorganic substrate 12 region. This structure has the following important functions: First, it allows signals from the organic substrate 11 region to be routed above the inorganic substrate 12 region, enabling subsequent solder balls or bumps to be arranged across the entire substrate, including the edge of the inorganic substrate 12 region, thereby achieving stable package mounting. Second, power or ground layers can be laid in the redistribution layer 30 above the inorganic substrate 12 region, forming a large-area low-impedance plane, improving power quality and electromagnetic shielding. Finally, if multiple chips are integrated on the package substrate, the redistribution layer 30 can serve as an interconnection bridge between the chips, enabling high-speed communication.

[0047] In other embodiments, the redistribution layer 30 may only cover the surface of the organic substrate 11 without extending to the surface of the inorganic substrate 12. This structure is suitable for packaging scenarios where signals do not need to be routed to the inorganic substrate area, simplifying wiring design.

[0048] The redistribution layer 30 is disposed on both sides of the packaging substrate 10, and is electrically connected to the two ends of the conductive structure 13. The redistribution layer 30 is used to fan out or rearrange the electrical signals led out from the conductive structure 13 to meet the subsequent connection requirements with chips or other electronic components.

[0049] The redistribution layer 30 may include one or more circuit layers 31, and the material of the circuit layer 31 may be metals such as copper, aluminum, nickel, and gold. A dielectric layer is provided between adjacent circuit layers for insulation and isolation. The dielectric layer material is selected from photosensitive or non-photosensitive media such as polyimide, Ajinomoto stacked film, and benzocyclobutene, and is formed by coating or lamination.

[0050] In some embodiments, such as Figure 2 As shown, the package substrate 100 also includes a solder mask layer 50 and conductive bumps 60. The solder mask layer 50 and conductive bumps 60 are disposed on the side of the redistribution layer 30 away from the package substrate 10. The solder mask layer 50 is used to protect the redistribution layer 30 and prevent bridging during soldering. The solder mask layer 50 has a plurality of first openings 51, which expose a portion of the redistribution layer 30 for subsequent formation of the conductive bumps 60. The first openings 51 are formed by exposure development or ultraviolet laser windowing.

[0051] The conductive bump 60 is at least partially located within the first opening 51 and is electrically connected to the redistribution layer 30. The conductive bump 60 is used to achieve physical and electrical connections with the chip or other packaged components. The material of the conductive bump 60 can be tin, tin-silver alloy, copper, copper-nickel-gold, etc., and its formation process can be electroplating, printing, or ball-mounting, etc.

[0052] Optionally, before forming the conductive bump 60 within the first opening 51, the exposed redistribution layer 30 surface may be surface-treated to form a surface treatment layer 40. The surface treatment layer 40 may be made of organic solderability inhibitors, electroless nickel plating, or other materials to improve solderability and prevent pad oxidation.

[0053] By setting up the redistribution layer 30, the solder mask layer 50, and the conductive bumps 60, a complete packaging interface is formed, enabling the packaging substrate 100 to be directly used for packaging processes such as flip-chip bonding.

[0054] Some embodiments of this application also provide a method for preparing a packaging carrier 100.

[0055] like Figure 6 As shown, the preparation method of the packaging substrate 100 specifically includes the following steps: Step S10: Provide an inorganic substrate 12 and form a through groove 121 extending along the thickness direction in the inorganic substrate 12. Step S20: Embed the organic substrate 11 in the through groove 121 to form the encapsulation substrate 10; Step S30: Form a first through hole 111 extending along the thickness direction in the organic substrate 11; Step S40: Form a conductive structure 13 within the first through hole 111.

[0056] Specifically, such as Figure 7 As shown, in step S10, the inorganic substrate 12 can be a glass substrate. The through-groove 121 can be formed by laser-induced etching, laser melting, plasma etching, or electrochemical discharge processing. Taking laser-induced etching as an example, a laser scan can be performed on the glass surface to induce glass modification, and then the modified area can be removed by wet etching to form the through-groove 121.

[0057] In step S20, the pre-prepared organic substrate 11 is embedded into the through-hole 121. A bonding layer 122 material (such as resin) can be coated first on the inner wall of the through-hole 121 or the edge of the organic substrate 11. Then, the organic substrate 11 is embedded, and the bonding layer 122 is cured by heating or ultraviolet light curing to fix the organic substrate 11 in the through-hole 121. Alternatively, the organic substrate 11 can be placed in the through-hole 121 first, and then the bonding layer 122 is filled into the gap between the edge of the organic substrate 11 and the inner wall of the through-hole 121.

[0058] In step S30, a first through hole 111 can be formed in the organic substrate 11 by means of mechanical drilling, laser drilling, or other methods. Laser drilling is suitable for high-density, small-diameter through hole fabrication and has high precision.

[0059] In step S40, the conductive structure 13 can be formed in a variety of ways.

[0060] In some embodiments, the conductive structure 13 can be formed by chemical plating or physical vapor deposition to form a seed layer 20 on the inner wall of the first through hole 111, and then by electroplating to fill the metal to form a solid conductive pillar.

[0061] In other embodiments, such as Figure 8 As shown, the conductive structure 13 is formed by conformal electroplating, where a conductive layer 131 is formed only on the inner wall of the first through hole 111, and then filled with resin.

[0062] The method for fabricating the packaging substrate 100 provided in this application embodiment can produce a packaging substrate 100 with an embedded composite structure. The inorganic substrate 12, acting as a rigid framework, provides the main mechanical support, improving the overall rigidity and warpage resistance of the substrate. Compared to a pure organic substrate of the same size, the packaging substrate 100 of this application exhibits reduced warpage after undergoing thermal processes such as reflow soldering. Simultaneously, the organic substrate 11 retains the capability for high-density wiring, allowing for the fabrication of fine lines and microvias to meet the interconnection requirements of multi-chip stacking.

[0063] In some embodiments, such as Figure 8 As shown, step S40, which forms a conductive structure 13 within the first through-hole 111, includes the following sub-steps: Step S41: Form a conductive layer 131 that at least covers the hole wall of the first through hole 111, the conductive layer 131 forming the first opening 130; Step S42: Fill the first opening 130 with insulating material to form an insulating structure 132.

[0064] The conductive layer 131 is formed using a conformal electroplating process. First, a seed layer 20 is formed on the inner wall of the first through-hole 111 and the surface of the substrate. Then, a metal material is deposited on the seed layer 20 by electroplating. During the electroplating process, the electroplating time is controlled so that the metal material is deposited only on the hole walls and surface, without filling the entire through-hole, thereby forming a cylindrical or cup-shaped conductive layer 131 with a central opening. Subsequently, an insulating material is filled into the first opening 130, for example, resin is filled by vacuum pressing or spin coating, and then cured. Finally, excess resin on the surface of the encapsulation substrate 10 can be removed by grinding to expose the conductive layer 131.

[0065] In some embodiments, after forming the insulating structure 132 in step S42, the method for preparing the encapsulation carrier 100 further includes the following steps: Step S50: Deposit at least one layer of conductive material on the surface of the packaging substrate 10 and form a circuit layer by patterning; fabricate at least one dielectric layer to form a redistribution layer 30.

[0066] Specifically, such as Figure 9 As shown, after forming the insulating structure 132, electroplating can be performed on the entire surface of the packaging substrate 10 to increase the thickness of the copper layer. Then, the first circuit layer 31 is formed through photoresist patterning, etching, and other processes. Next, a dielectric layer 32 is coated, and vias and the next circuit layer are formed on the dielectric layer 32. The above steps are repeated to form a multi-layer redistribution layer 30. Increasing the thickness of the conductive material on the surface of the packaging substrate 10 so that the insulating structure 132 inside the first opening 130 is covered with conductive material can protect the insulating structure 132 inside the opening, thereby preventing laser ablation of the insulating structure 132 when the opening is made in the dielectric layer 32.

[0067] In some embodiments, the circuit layer 31 covers the ends of the insulating structure 132, while simultaneously achieving a reliable electrical connection with the conductive structure 13.

[0068] In some embodiments, step S40, which forms a conductive structure 13 within the first through-hole 111, includes the following sub-steps: Step S401: Create a seed layer 20. The seed layer 20 includes a first portion 201 covering the wall of the first through hole 111, a second portion 202 covering at least a portion of the surface of the organic substrate 11, and a third portion 203 covering at least a portion of the surface of the inorganic substrate 12. Step S402: A conductive layer 131 and a first opening 130 are formed on the seed layer 20 by a conformal electroplating process.

[0069] The full coverage of the seed layer 20 ensures the uniformity and adhesion of subsequent electroplating, while providing a conductive substrate for the subsequent fabrication of circuit layers on the surface of the packaging substrate.

[0070] Some embodiments of this application also provide a semiconductor packaging structure, which includes the packaging carrier 100 of any of the above embodiments.

[0071] Furthermore, the semiconductor package structure also includes at least one electronic component (e.g., a chip, passive device, etc.) disposed on the package substrate 100. The electronic component can be electrically connected to the redistribution layer 30 of the package substrate 100 via conductive bumps (e.g., solder balls, copper pillars), or via wire bonding or other methods. This semiconductor package structure can be used to construct various electronic devices, such as high-performance computing devices, mobile terminals, and storage devices.

[0072] The packaging substrate 100 provided in this application embodiment can be applied to various semiconductor packaging scenarios.

[0073] In one implementation, in the packaging of an artificial intelligence accelerator chip, the organic substrate 11 region of the packaging carrier 100 can be used to mount high-bandwidth memory and computing chips, while the inorganic substrate 12 region provides rigid support. A redistribution layer 30 extends from the organic substrate 11 region to above the inorganic substrate 12 region, bringing out the interconnect lines between the high-bandwidth memory and the computing chip. Simultaneously, a power layer can be laid above the inorganic substrate 12 region to provide low-impedance power to the chip. Through the bonding layer 122, a stress buffer is formed between the organic substrate 11 and the inorganic substrate 12, which can absorb thermal stress caused by differences in thermal expansion during high-power operation of the chip, maintaining the reliability of the package.

[0074] In one implementation, the packaging substrate 100 of the RF front-end module can use glass as the inorganic substrate 12, utilizing the low dielectric loss characteristics of glass to reduce RF signal transmission loss. The through-groove 121 confines the organic substrate 11 and its conductive structures 13 within a specific area. In the wiring design of the redistribution layer 30, RF signal traces of different frequency bands can be separated into different areas, reducing signal crosstalk through the isolation effect of the inorganic substrate 12. Simultaneously, the area of ​​the organic substrate 11 can be used to integrate active devices such as RF switches and power amplifiers, achieving high-density integration.

[0075] In one implementation, in the microelectromechanical system (MEMS) sensor packaging, the packaging substrate 100 can serve as the supporting substrate for the sensor. The sensitive structure of the MEMS can be mounted on the organic substrate 11 area, and electrically led out through the conductive structure 13 within the first through-hole 111. The rigidity of the inorganic substrate 12 maintains the flatness of the entire packaging structure, while the resin material in the bonding layer 122 and the insulating structure 132 can absorb transient stresses generated by external mechanical impacts or thermal cycling, preventing stress transmission to the sensitive structure of the MEMS, thereby improving the measurement accuracy and long-term stability of the sensor.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A packaging carrier board, characterized in that, include: The packaging substrate includes an inorganic substrate and an organic substrate. The inorganic substrate has a through groove that extends through the substrate along its thickness direction. The organic substrate is embedded in the through groove. The organic substrate includes a first through hole that extends through the organic substrate along its thickness direction. A conductive structure is located at least partially within the first through-hole.

2. The packaging carrier board according to claim 1, characterized in that, The inorganic substrate is a glass substrate.

3. The packaging carrier board according to claim 1, characterized in that, The conductive structure includes a conductive layer, which includes an annular structure and forms a first opening extending along the thickness direction, the first opening being filled with an insulating structure.

4. The packaging carrier board according to claim 1, characterized in that, It also includes a seed layer, which includes a first portion located between the hole wall of the first through hole and the conductive structure, a second portion covering at least a portion of the surface of the organic substrate, and a third portion covering at least a portion of the surface of the inorganic substrate.

5. The packaging carrier board according to claim 4, characterized in that, The surface of at least one side of the organic substrate is flush with the surface of the inorganic substrate located on the same side.

6. The packaging carrier board according to claim 1, characterized in that, It also includes a bonding layer, which is located between the organic substrate and the inorganic substrate, and the organic substrate is fixed to the wall of the through groove through the bonding layer.

7. The packaging carrier board according to claim 1, characterized in that, It also includes a redistribution layer disposed on at least one side of the packaging substrate, the redistribution layer including at least one dielectric layer and at least one circuit layer, the circuit layer being electrically connected to the conductive structure; The redistribution layer covers at least a portion of the surface of the organic substrate and at least a portion of the surface of the inorganic substrate.

8. A method for preparing a packaging carrier, characterized in that, The method includes: An inorganic substrate is provided, and a through groove extending along the thickness direction is formed in the inorganic substrate; An organic substrate is embedded in the through groove to form an encapsulation substrate; A first through-hole is formed in the organic substrate, extending along the thickness direction; A conductive structure is formed within the first through hole.

9. The method for preparing the packaging carrier according to claim 8, characterized in that, A conductive structure is formed within the first through-hole, including: A conductive layer is formed that at least covers the wall of the first through hole, the conductive layer forming the first opening; The first opening is filled with insulating material to form an insulating structure; At least one layer of conductive material is deposited on the surface of the packaging substrate, and a circuit layer is formed by patterning. Create at least one dielectric layer to form a redistribution layer.

10. A semiconductor packaging structure, characterized in that, Includes the packaging carrier as described in any one of claims 1 to 7.

Images