Integrated circuit, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses an integrated circuit, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. An integrated circuit includes a substrate, a fin, a gate line, a source, a drain, an isolation layer, a power contact structure, and a power distribution network. The substrate has a first surface and a second surface. The fin is on the first surface. The grid lines are arranged across the fins. The isolation layer is located between two adjacent fins and divides the grid line into a plurality of sub-grid lines. The power contact structure penetrates through the substrate. The power contact structure includes a first power contact portion and a second power contact portion. The distribution network is on the second surface. The power distribution network is electrically connected with the first power supply contact. The second power supply contact is electrically connected with the source electrode or the drain electrode. In the second direction, the isolation layer is located on opposite sides of the second power contact portion. The power supply contact structure is divided into the first power supply contact part and the second power supply contact part, and the isolation layer is arranged, so that the process difficulty of the integrated circuit is reduced, and the reliability of the integrated circuit is improved.

Description

Integrated circuit and manufacturing method thereof, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit and a method for manufacturing the same, and an electronic device. Background Art

[0002] As semiconductor devices continue to shrink, transistor density within chips increases, placing increasing pressure on metal interconnects to scale. Backside power delivery network (BSPDN) technology shifts power supply traces (e.g., power and ground components) from the front of the chip to the back. This technology not only reduces chip area, but also improves current-resistance-voltage drop (IR drop), boosting chip performance and reducing power consumption.

[0003] To optimize power supply capabilities, a proposed method is to move the power rail into the substrate, creating a buried power rail (BPR). This approach includes a power contact (or power trench) that connects the chip's transistors to the backside power supply network.

[0004] The manufacturing process required for the aforementioned power contact structure is very difficult. Furthermore, the placement of structures such as the embedded power rail compresses the spacing between the power contact structure and existing chip structures (such as gate lines and fins). This not only further increases the manufacturing difficulty of the power contact structure but also introduces reliability risks.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an integrated circuit, a method for manufacturing the same, and an electronic device, which are used to reduce the process difficulty of the integrated circuit and improve the reliability of the integrated circuit.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, an integrated circuit is provided, comprising: a substrate, a plurality of fins, a gate line, a source, a drain, an isolation layer, a power contact structure, and a power distribution network. The substrate has a first surface and a second surface facing each other. A plurality of fins are located on the first surface. The plurality of fins extend along a first direction and are spaced apart along a second direction. The first direction and the second direction are both parallel to the first surface and intersect with each other. A gate line spans the plurality of fins. The gate line extends along the second direction. An isolation layer is located between two adjacent fins. The isolation layer divides the gate line into a plurality of sub-gate lines. A source and a drain are located on the fins, one of the source and the drain being a target electrode. The power contact structure extends through the substrate. Along the second surface pointing toward the first surface, the power contact structure comprises a first power contact portion and a second power contact portion located on the first power contact portion. The first power contact portion and the second power contact portion are connected. The second power contact portion is electrically connected to the target electrode. The power distribution network is located on the second surface. The power distribution network is electrically connected to the first power contact portion. The isolation layer is located on opposite sides of the second power contact portion along the second direction.

[0009] In the integrated circuits provided by some embodiments of the present application, by setting the power contact structure as a first power contact portion and a second power contact portion connected to each other, the first power contact portion and the second power contact portion can be prepared independently of each other, so that the groove for accommodating the power contact structure is formed in two steps, one of which can form the groove for accommodating the first power contact portion, and the other step can form the groove for accommodating the second power contact portion. Since the aspect ratio of the first power contact portion and the aspect ratio of the second power contact portion are both relatively small, the etching process and metal filling process required to prepare the first power contact portion are relatively easy compared to preparing the power contact structure that penetrates the substrate in one step, and the etching process and metal filling process required to prepare the second power contact portion are relatively easy. This can also reduce the process difficulty of forming the power contact structure in the embodiments of the present application.

[0010] Moreover, by setting an isolation layer, the embodiment of the present application can not only reduce the accuracy requirements of the alignment, photolithography, etching and other processes required to accommodate the second power contact part between two adjacent fins, thereby reducing the difficulty of the alignment, photolithography, etching and other processes; the isolation layer can also be used to provide a self-alignment effect for the formation of the second power contact part, so that in the process of filling and forming the second power contact part, the material of the second power contact part can be naturally filled in the area defined by the isolation layer, thereby avoiding damage to the fins or gate lines, and improving the reliability and yield of the integrated circuit.

[0011] In a possible implementation of the first aspect, the connection surface between the first power contact portion and the second power contact portion is located within the first surface, which facilitates the formation of a groove for accommodating the first power contact portion.

[0012] In a possible implementation of the first aspect, a side surface of the first power contact portion that is adjacent to the second power contact portion is a third surface, and a side surface of the second power contact portion that is adjacent to the first power contact portion is a fourth surface. The orthographic projection of the fourth surface on the first surface is within the orthographic projection of the third surface on the first surface. This not only increases the contact area between the first and second power contact portions, but also reduces the difficulty of aligning the first and second power contact portions, thereby improving the connection yield between the first and second power contact portions.

[0013] In a possible implementation of the first aspect, the integrated circuit further includes: a gate trimming structure spaced apart from the isolation layer. The gate trimming structure is located between two adjacent sub-gate lines and between two adjacent fins. The gate trimming structure and the isolation layer are made of the same material and are disposed in the same layer. The embodiment of the present application integrates the preparation process of the isolation layer with the preparation process of the gate trimming structure, and can simultaneously form multiple structures such as the gate trimming structure and the isolation layer in a single patterning process, which is conducive to simplifying the preparation process of the integrated circuit.

[0014] In a possible implementation of the first aspect, the height of the isolation layer, along a direction perpendicular to the first surface, is greater than the thickness of the gate-cut structure. Thus, during the deposition of the isolation layer and the thin film containing the gate-cut structure, the thin film can be ensured to completely fill the trench for accommodating the gate-cut structure while also ensuring that the thin film only partially fills the trench for accommodating the second power contact, leaving space for the second power contact.

[0015] In a possible implementation of the first aspect, the integrated circuit further includes an epitaxial contact structure. The epitaxial contact structure is located on the second power contact portion and the target electrode and contacts the second power contact portion and the target electrode. The epitaxial contact structure can serve as a bridge structure between the second power contact portion and the target electrode, thereby reducing the difficulty of electrical connection between the second power contact portion and the target electrode.

[0016] In a possible implementation of the first aspect, the integrated circuit further includes a first dielectric layer. The first dielectric layer is located between the second surface and the power distribution network, and between the first power contact and the substrate. A surface of the first power contact facing away from the second power contact is flush with a surface of the first dielectric layer facing away from the second surface. The first dielectric layer can provide electrical insulation between the first power contact and the substrate, and between the power distribution network and the substrate.

[0017] In a second aspect, a method for fabricating an integrated circuit is provided, the method comprising: forming an initial integrated circuit; the initial integrated circuit comprising a substrate, a plurality of fins, a second dielectric layer, and a sacrificial layer; the substrate having a first surface and a second surface opposite to each other, the plurality of fins being located on the first surface, extending in a first direction and spaced apart in a second direction; the second dielectric layer filling between two adjacent fins and covering the fins; the sacrificial layer being located on the second dielectric layer, the sacrificial layer comprising a sacrificial gate straddling the plurality of fins; the sacrificial gate extending in a second direction; the first direction and the second direction being parallel to and intersecting the first surface; forming a first gate trimming trench in the sacrificial layer; the first gate trimming trench being located between two adjacent fins and disconnecting the sacrificial gate; forming an isolation layer; the isolation layer at least covering the sidewalls of the first gate trimming trench; forming a second power contact in the first gate trimming trench; forming a first power contact on a side of the second power contact proximal to the second surface, the first power contact being connected to the second power contact; forming a power distribution network on the second surface; the power distribution network being electrically connected to the first power contact.

[0018] In a possible implementation of the second aspect, during the process of forming the first gate-trimming trench in the sacrificial layer, a second gate-trimming trench is also formed; the second gate-trimming trench is located between two adjacent fins and disconnects the sacrificial gate; the depth of the second gate-trimming trench in a direction perpendicular to the first surface is less than the depth of the first gate-trimming trench. During the process of forming the isolation layer, a gate-trimming structure is also formed; the gate-trimming structure is located within the second gate-trimming trench.

[0019] In a possible implementation of the second aspect, forming the first power contact portion on a side of the second power contact portion close to the second surface includes: etching the substrate from the side where the second surface is located to form a contact trench; the contact trench exposes a side surface of the second power contact portion close to the second surface; and forming the first power contact portion within the contact trench.

[0020] In a possible implementation of the second aspect, the isolation layer further covers a bottom wall of the first gate-cutting trench. Before forming the first power contact portion in the contact trench, the preparation method further includes: removing a portion of the isolation layer covering the bottom wall of the first gate-cutting trench through the contact trench, thereby exposing a side surface of the second power contact portion adjacent to the second surface.

[0021] In a possible implementation of the second aspect, before forming the power distribution network on the second surface, the preparation method further includes: removing the sacrificial gate to form a gate line trench, and filling the gate line trench with a conductive material to form a gate line.

[0022] In a third aspect, an electronic device is provided, comprising a circuit board and an integrated circuit as described in any embodiment of the first aspect, wherein the integrated circuit is connected to the circuit board.

[0023] The technical effects brought about by any design method in the second aspect and the third aspect can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0025] FIG2 is a partial structural diagram of an electronic device provided in an embodiment of the present application;

[0026] FIG3 is a structural diagram of an integrated circuit provided in an embodiment of the present application;

[0027] FIG4 is a cross-sectional view of the integrated circuit shown in FIG3 along line AA;

[0028] FIG5 is a structural diagram of another integrated circuit provided in an embodiment of the present application;

[0029] 6 and 7 illustrate structures corresponding to various steps in a method for manufacturing an integrated circuit according to a possible implementation;

[0030] FIG8 is a flow chart of a method for manufacturing an integrated circuit provided in an embodiment of the present application;

[0031] FIG9 a is a structural diagram of an initial integrated circuit provided in an embodiment of the present application;

[0032] FIG9 b is a structural diagram of another initial integrated circuit provided in an embodiment of the present application;

[0033] FIG9c is a structural diagram of another initial integrated circuit provided in an embodiment of the present application;

[0034] 10a to 10n are structural diagrams corresponding to the steps in a method for manufacturing an integrated circuit provided in an embodiment of the present application;

[0035] 11a to 11f are structural diagrams corresponding to the steps in another method for manufacturing an integrated circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0037] In the description of the embodiments of the present application, unless otherwise specified, "a plurality" refers to two or more than two. "At least one item" or similar expressions refers to any combination of these items, including any combination of a single item or plural items. For example, at least one item among a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0038] "And / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "a and / or b" can mean: a exists alone, a and b exist simultaneously, and b exists alone. A and b can be singular or plural. The character " / " generally indicates that the related objects are in an "or" relationship.

[0039] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0040] When describing some embodiments, the term "connected" and its derivatives are used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integral; it can be directly connected or indirectly connected through an intermediary. In addition, the use of "based on" is intended to be open and inclusive, as a process, step, calculation, or other action "based on" one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0041] As used in the embodiments of the present application, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equals is less than or equal to 5% of either one. "Flush" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, determined according to the actual process.

[0042] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to changes in the orientation of the components in the drawings. In the drawings, the thickness of the layers and regions are exaggerated for the sake of clarity, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device and are not intended to limit the scope of the exemplary embodiments.

[0043] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0044] The present application provides an electronic device. The electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device, and / or a smart city device. The present application does not impose any particular restrictions on the specific type of the electronic device.

[0045] FIG1 is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. As shown in FIG1 , the electronic device 1000 includes components such as a memory 100, a processor 200, an input device 300, and an output device 400. Those skilled in the art will appreciate that the structure of the electronic device shown in FIG1 does not limit the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in FIG1 , or may combine certain components shown in FIG1 , or may have a different arrangement of components than shown in FIG1 .

[0046] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, image data, a phone book, etc.). In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110 includes, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 120 includes, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a read-only memory, etc.

[0047] The processor 200 is the control center of the electronic device 1000. It connects the various parts of the entire electronic device 1000 using various interfaces and lines. By running or executing software programs and / or modules stored in the memory 100 and calling data stored in the memory 100, it performs various functions of the electronic device 1000 and processes data, thereby monitoring the electronic device 1000 as a whole. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, or other specific integrated circuits (ASICs). In Figure 1, the processor 200 is taken as a CPU as an example. The CPU may include an arithmetic unit 210 and a controller 220. The arithmetic unit 210 obtains data stored in the internal memory 120 and processes the data stored in the internal memory 120. The processed results are usually sent back to the internal memory 120. The controller 220 can control the arithmetic unit 210 to process data, and can also control the external memory 110 and the internal memory 120 to store data or read data. The memory 100 can store data generated by the processor 200.

[0048] The input device 300 is used to receive input digital or character information and generate key signal input related to user settings and function control of the electronic device 1000. For example, the input device 300 may include a touch screen and other input devices. A touch screen, also known as a touch panel, can detect user touch operations on or near the touch screen (e.g., operations performed on or near the touch screen using a finger, stylus, or any other suitable object or accessory) and drive corresponding connected devices according to a pre-set program. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch direction and detects signals generated by the touch operation, transmitting the signals to the touch controller. The touch controller receives the touch information from the touch detection device, converts it into touch point coordinates, and then sends it to the processor 200. It can also receive and execute commands sent by the processor 200. In addition, touch screens can be implemented using various types, such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control buttons, power on / off buttons, etc.), a trackball, a mouse, and a joystick. The controller 220 in the processor 200 may also control the input device 300 to receive or not receive input signals. In addition, the input digital or character information received by the input device 300, as well as the key signal input related to the user settings and function control of the electronic device, may be stored in the internal memory 120.

[0049] The output device 400 is used to output a signal corresponding to the data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the processor 200 can also control the output device 400 to output a signal or not output a signal.

[0050] It should be noted that the thick arrows in Figure 1 are used to represent the transmission of data, and the direction of the thick arrows represents the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 represents that the data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the operator 210 and the internal memory 120 represents that the data stored in the internal memory 120 can be transmitted to the operator 210, and the data processed by the operator 210 can be transmitted to the internal memory 120. The thin arrows in Figure 1 represent components that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, etc.

[0051] Optionally, the electronic device 1000 shown in FIG1 may further include various sensors. For example, a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which are not described in detail here. Optionally, the electronic device 1000 may further include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which are not described in detail here.

[0052] FIG2 schematically illustrates a partial structure of the electronic device 1000. As shown in FIG2, the electronic device 1000 may further include a circuit board 500 and an integrated circuit 600. The integrated circuit 600 is disposed on the circuit board 500 and electrically connected to the circuit board 500.

[0053] As shown in Figure 2, the electronic device 1000 further includes a connector provided between the circuit board 500 and the integrated circuit 600, and the integrated circuit 600 is electrically connected to the circuit board 500 via the connector. The connector may be, for example, a ball grid array (BGA).

[0054] Optionally, other structures, such as a packaging substrate, may be provided between the connector and the circuit board 500. That is, the integrated circuit 600 may be packaged on the packaging substrate and then connected to the circuit board 500 via the packaging substrate.

[0055] The number of the integrated circuit 600 can be one or more. When there are more than one integrated circuit 600, the integrated circuits 600 can be arranged in a flat pattern or in a stacked pattern.

[0056] The above-mentioned integrated circuit 600 can be a wafer or a chip. When the integrated circuit 600 is a chip, the chip can be a bare chip (also called a grain or particle) obtained by cutting the wafer, or it can be a packaged chip obtained by packaging the bare chip. Optionally, the above-mentioned integrated circuit 600 has a logic calculation function. In this case, the integrated circuit 600 can be applied to a logic device (such as the above-mentioned operator 210, controller 220, sensor, etc.); or, the above-mentioned integrated circuit 600 has a storage function. In this case, the integrated circuit 600 can also be applied to a storage device (such as the above-mentioned external memory 110, internal memory 120, etc.), which is not limited in this embodiment of the present application.

[0057] Some embodiments of the present application provide an integrated circuit and a method for manufacturing the same. The integrated circuit and the method for manufacturing the integrated circuit are schematically described below with reference to the accompanying drawings.

[0058] Figures 3 and 5 illustrate the structure of an integrated circuit respectively. Figure 4 illustrates a cross-sectional structure of the integrated circuit shown in Figure 3 along the reference AA direction.

[0059] As shown in FIG3 , the integrated circuit 600 includes a substrate 1 , a fin 2 , a second dielectric layer 3 , a gate line 4 , a source 5 , a drain 6 , an interlayer dielectric layer 7 , a power distribution network 8 and a power contact structure 9 .

[0060] Exemplarily, the material of the substrate 1 includes semiconductor materials, including but not limited to bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI), or other Group III or Group V materials.

[0061] As shown in Figures 3, 4, and 5, the substrate 1 has a first surface A1 and a second surface A2 that are opposite to each other. The first surface A1 and the second surface A2 are, for example, both planes. The fin 2 is located on the first surface A1. Optionally, the fin 2 and the substrate 1 are integrally structured. In this case, the substrate 1 and the fin 2 can be simultaneously obtained by etching a substrate.

[0062] The number of fins 2 can be multiple, and the multiple fins 2 extend, for example, along the first direction X and are arranged at intervals along the second direction Y. Among the multiple fins 2, along the second direction Y, the spacing between any two adjacent fins 2 can be equal or unequal, and can be set according to actual needs. The dimensions of each fin 2 in the third direction Z (which can also be called the height) can be equal or unequal, and can be set according to actual needs. The first direction X and the second direction Y are both parallel to the first surface A1, and the third direction Z is perpendicular to the first surface A1. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0063] The number of the fins 2 can be selected according to actual needs and is not limited in the present embodiment, as long as it can meet the functional and structural requirements of the integrated circuit 600. For example, six fins 2 are shown in FIG3 and eight fins 2 are shown in FIG5.

[0064] As shown in Figures 3 and 4 , the second dielectric layer 3 is located between any two adjacent fins 2 and covers all fins 2. The second dielectric layer 3 may also be referred to as a shallow trench isolation (STI) structure, which is used to separate two adjacent fins 2 and achieve isolation between adjacent devices.

[0065] 3 and 4 , the gate line 4 is located on the second dielectric layer 3 and spans across multiple fins 2. For example, the number of fins 2 spanned by the gate line 4 is three, six, eight, or even more.

[0066] There are a plurality of gate lines 4, which extend, for example, along the second direction Y and are spaced apart along the first direction X. Among the plurality of gate lines 4, the spacing between any two adjacent fins 2 may be equal or unequal, and may be set specifically based on actual needs. The number of fins 2 spanned by different gate lines 4 may be equal or unequal, and may be set specifically based on actual needs.

[0067] The number of gate lines 4 can be selected and set according to actual needs, and the embodiment of the present application does not limit this, as long as it can meet the functional and structural requirements of the integrated circuit 600.

[0068] As shown in Figures 3 and 5, the source 5 and drain 6 are located on the fin 2 and on both sides of the gate line 4. Exemplarily, the source 5 and drain 6 can be formed on the fin 2 by using an epitaxial process.

[0069] In conjunction with Figures 4 and 5 , the portion of the gate line 4 that spans the fin 2 forms the gate, and the portion of the fin 2 covered by the gate line 4 forms the channel. The gate, channel, and source 5 and drain 6 located on either side of the gate form a FinFET (or gate-around field-effect transistor). In other words, the same gate line 4 and the multiple fins 2 it spans can form multiple FinFETs, and the gate line 4 can control the conduction or cutoff of the multiple FinFETs.

[0070] 3 , the interlayer dielectric layer 7 is located on the second dielectric layer 3 and spans across the plurality of fins 2. There are multiple interlayer dielectric layers 7, which extend along the second direction Y and are spaced apart along the first direction X, for example.

[0071] The interlayer dielectric layers 7 and the gate lines 4 are alternately arranged along the first direction X. This facilitates the use of the interlayer dielectric layers 7 to isolate adjacent gate lines 4.

[0072] As shown in Figures 3, 4, and 5, the power distribution network 8 is located on the second surface A2. As shown in Figure 5, the power distribution network 8 includes multiple routing layers and multiple third dielectric layers. The multiple routing layers and the multiple third dielectric layers are arranged alternately, and the routing layers in different routing layers can be connected through through holes in the third dielectric layer. The power distribution network 8 includes, for example, a power supply (VSS or VDD, etc.) and a ground. The power distribution network 8 is primarily used to provide operating current and operating voltage.

[0073] As shown in Figures 3, 4 and 5, the power contact structure 9 passes through the gate line 4, the second dielectric layer 3 and the substrate 1, and is located between two adjacent fins 2. The top of the power contact structure 9 is electrically connected to the target electrode, which is one of the source 5 and the drain 6. The power contact structure 9 can be electrically connected to the target electrode of one transistor, or to the target electrodes of multiple transistors. For example, the power contact structure 9 in Figure 5 is electrically connected to the target electrodes of four transistors. The bottom end of the power contact structure 9 is electrically connected to the power distribution network 8. The operating current and operating voltage provided by the power distribution network 8 can be transmitted to the target electrode of the transistor to which the power contact structure 9 is electrically connected through the power contact structure 9, so that the transistor to which the power contact structure 9 is electrically connected works.

[0074] The material of the power contact structure 9 includes metal material.

[0075] In one possible implementation, as shown in Figures 6 and 7 , the power contact structure 9 is an integrated structure. During the fabrication process of the power contact structure 9, a trench (which may also be a through hole or deep hole) is first etched, and then the trench is filled with metal material. Due to the high aspect ratio of the power contact structure 9, this undoubtedly increases the difficulty of the etching process and the metal filling process.

[0076] Furthermore, the provision of structures such as embedded power rails reduces the spacing between the power contact structure 9 and existing structures in the integrated circuit. For example, as integrated circuits shrink, the spacing between adjacent fins 2 decreases. The alignment, photolithography, and etching processes required to form a trench between closely spaced fins 2 are challenging. Furthermore, deviations in alignment, photolithography, etching, metal filling, and other processes can easily damage the fins 2 or gate lines 4, thereby reducing the reliability and yield of the integrated circuit.

[0077] Based on this, referring to Figures 3, 4 and 5, the power contact structure 9 in the embodiment of the present application includes a first power contact portion 91 and a second power contact portion 92. Along the direction from the second surface A2 to the first surface A1 (that is, the positive direction of the third direction Z), the first power contact portion 91 and the second power contact portion 92 are arranged in sequence, and the second power contact portion 92 is located above the first power contact portion 91. The bottom end of the first power contact portion 91 is connected to the power distribution network 8, the top end of the first power contact portion 91 is connected to the bottom end of the second power contact portion 92, and the top end of the second power contact portion 92 is electrically connected to the target electrode. Electrical signals can be transmitted between the first power contact portion 91 and the second power contact portion 92.

[0078] Optionally, the top of the second power contact portion 92 and the target electrode can be directly electrically connected. Alternatively, the top of the second power contact portion 92 and the target electrode can be indirectly electrically connected, that is, the top of the second power contact portion 92 and the target electrode are connected via other structures. According to power supply requirements, when the top of the second power contact portion 92 is connected to the target electrode via other structures, the top of the second power contact portion 92 can be connected to different metal structures such as M0 and V0; further, the top of the second power contact portion 92 can also be connected to the metal structures in the interconnect layer or other routing layers mentioned below.

[0079] The aspect ratios of the first power contact portion 91 and the second power contact portion 92 are both smaller than the aspect ratio of the power contact structure 9. In the direction perpendicular to the first surface A1, the heights of the first power contact portion 91 and the second power contact portion 92 can be the same or different.

[0080] The material of the first power contact 91 includes, but is not limited to, one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum, and a combination thereof. The material of the second power contact 92 includes, but is not limited to, one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum, and a combination thereof. The materials of the first power contact 91 and the second power contact 92 can be the same or different.

[0081] By dividing the power contact structure 9 into a first power contact portion 91 and a second power contact portion 92, the process for forming the power contact structure 9 can be split into two steps to prepare the power contact structure 9. For example, a groove (or a through hole, a deep hole, etc.) for accommodating the second power contact portion 92 can be first formed, and a metal material can be filled in the groove to form the second power contact portion 92; then a groove (or a through hole, a deep hole, etc.) for accommodating the first power contact portion 91 can be formed, and a metal material can be filled in the groove to form the first power contact portion 91. Since the aspect ratio of the first power contact portion 91 and the aspect ratio of the second power contact portion 92 are both relatively small, the etching process and the metal filling process required to prepare the first power contact portion 91 are relatively easy, and the etching process and the metal filling process required to prepare the second power contact portion 92 are relatively easy, thereby reducing the process difficulty of forming the power contact structure 9.

[0082] Continuing with reference to Figures 3, 4, and 5, the integrated circuit 600 provided in the embodiment of the present application further includes an isolation layer 10. The isolation layer 10 is located on the substrate 1 and between two adjacent fins 2. The isolation layer 10 extends, for example, along the first direction X and penetrates at least a portion of the gate line 4 and the second dielectric layer 3. The isolation layer 10, for example, divides the gate line 4 into a plurality of sub-gate lines 41. The isolation layer 10 is located between two adjacent sub-gate lines 41 in the same gate line 4.

[0083] The isolation layer 10 is made of a dielectric material, so that the two sub-gate lines 41 separated by the same isolation layer 10 are electrically insulated. Optionally, the dielectric material includes but is not limited to silicon oxide (OX), silicon nitride (SiN), and the like.

[0084] There are multiple isolation layers 10, each of which is spaced apart. The number of gate lines 4 separated by different isolation layers 10 can be equal or unequal, depending on actual needs. For example, each isolation layer 10 separates one gate line 4; or, as shown in FIG3 , each isolation layer 10 separates four gate lines 4.

[0085] The above transistors include N-type transistors and P-type transistors. The isolation layer 10 is, for example, provided between the N-type transistor and the P-type transistor.

[0086] 3 , 4 and 5 , along the second direction Y, the isolation layer 10 is located on opposite sides of the second power contact 92. Along the second direction Y, the isolation layer 10 can separate the second power contact 92 from structures on both sides thereof (e.g., sub-gate line 41, fin 2, etc.).

[0087] Furthermore, along the first direction X, the isolation layer 10 is also located on two opposite sides of the second power contact portion 92 . In other words, the isolation layer 10 is annular and surrounds the second power contact portion 92 .

[0088] The isolation layer 10 is used to provide self-alignment for the second power contact 92. Before filling and forming the second power contact 92, the isolation layer 10 can be formed within the trench intended to accommodate the second power contact 92. This allows the material for the second power contact 92 to naturally fill within the area defined by the isolation layer 10 during the filling and forming process, avoiding damage to the fins 2 or gate lines 4. This reduces the difficulty of the metal filling process and improves the reliability and yield of the integrated circuit 600.

[0089] Moreover, the isolation layer 10 has a certain thickness, and the isolation layer 10 can be used to achieve electrical insulation between the sub-gate line 41 and the second power contact portion 92. The provision of the isolation layer 10 can reduce the precision requirements of processes such as alignment, photolithography, and etching, thereby reducing the difficulty of processes such as alignment, photolithography, and etching. The thickness of the isolation layer 10 can be selected and set according to the actual product requirements.

[0090] As will be understood, as shown in FIG4 , the first power contact portion 91 has a side surface proximate to the second power contact portion 92, which is defined, for example, as a third surface A3. The second power contact portion 92 has a side surface proximate to the first power contact portion 91, which is defined, for example, as a fourth surface A4. A connecting surface is defined between the first power contact portion 91 and the second power contact portion 92. This connecting surface is located within both the third surface A3 and the fourth surface A4.

[0091] In some examples, as shown in FIG4 , the connection surface is also located within the first surface A1 . That is, the third surface A3 and the fourth surface A4 are flush with the first surface A1 . The first surface A1 can also be considered the connection surface between the substrate 1 and the second dielectric layer 3 .

[0092] The trench for accommodating the first power contact portion 91 is etched, for example, starting from the side of the substrate 1 where the second surface A2 is located. The material of the substrate 1 is different from that of the second dielectric layer 3. Compared to the substrate 1, the second dielectric layer 3 is more suitable as an etch stop layer, making it easier for the etching of the trench for accommodating the first power contact portion 91 to stop at the second dielectric layer 3.

[0093] Of course, the above-mentioned connection surface can also be located near the first surface A1. For example, as shown in Figure 5, the connection surface is located above the first surface A1 and is slightly higher than the first surface A1. In this case, when forming the groove for accommodating the first power contact portion 91, the substrate 1 can be slightly overetched, thereby causing the groove to extend into the second dielectric layer 3. For another example, the connection surface is located below the first surface A1 and is slightly higher than the first surface A1. In this case, when forming the groove for accommodating the first power contact portion 91, the etching can be performed only to expose the fourth surface A4, or it can be slightly overetched to penetrate the substrate 1.

[0094] In some examples, as shown in FIG. 4 , the orthographic projection of the fourth surface A4 on the first surface A1 is located within the orthographic projection range of the third surface A3 on the first surface A1 .

[0095] Illustratively, a portion of the boundary of the orthographic projection of the fourth surface A4 on the first surface A1 coincides with a portion of the boundary of the orthographic projection of the third surface A3 on the first surface A1; and a distance exists between another portion of the boundary of the orthographic projection of the fourth surface A4 on the first surface A1 and another portion of the boundary of the orthographic projection of the third surface A3 on the first surface A1. Alternatively, a distance exists between both the boundary of the orthographic projection of the fourth surface A4 on the first surface A1 and the boundary of the orthographic projection of the third surface A3 on the first surface A1.

[0096] In any direction parallel to the first surface A1 , a size of the fourth surface A4 is smaller than a size of the third surface A3 .

[0097] This not only allows for a larger contact area between the first power contact portion 91 and the second power contact portion 92 , but also reduces the difficulty of aligning the first power contact portion 91 and the second power contact portion 92 , thereby improving the connection yield of the first power contact portion 91 and the second power contact portion 92 and improving the stability of the integrated circuit 600 .

[0098] In some embodiments, as shown in Figures 3 and 4, the integrated circuit 600 provided in the embodiment of the present application also includes: a gate cutting structure 11. The gate cutting structure 11 is located on the substrate 1 and between two adjacent fins 2. The gate cutting structure 11 extends, for example, along the first direction X and passes through the gate line 4. The gate cutting structure 11 is located, for example, on the second dielectric layer 3 and is in contact with the side surface of the second dielectric layer 3 away from the substrate 1. The gate cutting structure 11 also divides the gate line 4 into multiple sub-gate lines 41. The gate cutting structure 11 is located between two adjacent sub-gate lines 41 in the same gate line 4. The gate cutting structure 11 and the isolation layer 10 are spaced apart. The relative position between the gate cutting structure 11 and the isolation layer 10 can be selected and set according to actual needs.

[0099] The gate cutting structure 11 is made of a dielectric material, so that the two sub-gate lines 41 separated by the same gate cutting structure 11 are electrically insulated. Optionally, the dielectric material includes but is not limited to silicon oxide, silicon nitride, and the like.

[0100] There are multiple gate cutting structures 11, and the number of gate lines 4 separated by different gate cutting structures 11 can be equal or unequal, and can be set according to actual needs. The number of gate lines 4 separated by the gate cutting structure 11 and the number of gate lines 4 separated by the isolation layer 10 can be the same or different.

[0101] The cutout position of the gate trimming structure 11 can be selected and set according to actual needs. Optionally, the cutout position of the gate trimming structure 11 is set according to the type of FinFET. For example, the gate trimming structure 11 is set between an N-type transistor and a P-type transistor to separate the adjacent N-type transistors and P-type transistors, facilitating the preparation of different types of transistors and facilitating independent control of the different types of transistors.

[0102] In some examples, the gate trim structure 11 and the isolation layer 10 are made of the same material and are disposed in the same layer.

[0103] The term "same layer" used herein refers to a layer structure formed using the same film-forming process to form a specific pattern, followed by a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple etching steps, and the specific pattern within the resulting layer structure may be continuous or discontinuous, at varying heights or thicknesses.

[0104] In other words, the gate trim structure 11 and the isolation layer 10 are formed by patterning the same thin film. This embodiment of the present application integrates the fabrication process of the isolation layer 10 with that of the gate trim structure 11, enabling the simultaneous formation of multiple structures, including the gate trim structure 11 and the isolation layer 10, in a single patterning process, thereby simplifying the fabrication process of the integrated circuit 600.

[0105] In some examples, as shown in FIG4 , a height H1 of the isolation layer 10, along a direction perpendicular to the first surface A1, is greater than a thickness H2 of the gate trim structure 11. Here, "the height H1 of the isolation layer 10" refers to the distance between a surface of the isolation layer 10 closer to the substrate 1 and a surface of the isolation layer 10 further away from the substrate 1, along a direction perpendicular to the first surface A1.

[0106] In this way, during the process of depositing the thin film where the isolation layer 10 and the gate cut structure 11 are located, it can be ensured that the thin film fills the groove for accommodating the gate cut structure 11, and can also ensure that the thin film only fills a part of the groove for accommodating the second power contact portion 92, reserving space for the second power contact portion 92.

[0107] Since the above-mentioned thin film can provide a self-alignment effect in the above-mentioned reserved space after being formed, it is convenient for the second power contact portion 92 to be formed in the reserved space. Therefore, the preparation process of the second power contact portion 92 can also be compatible with the preparation process of the gate cutting structure 11, thereby simplifying the preparation process of the integrated circuit 600.

[0108] 5 , the integrated circuit 600 provided in the embodiment of the present application further includes an epitaxial contact structure 12. The epitaxial contact structure 12 is located on the second power contact portion 92 and the target electrode, and contacts the second power contact portion 92 and the target electrode.

[0109] The material of the epitaxial contact structure 12 includes, for example, a metal material. The location of the epitaxial contact structure 12 can be determined according to actual wiring requirements, and the present embodiment does not limit this. Optionally, as shown in FIG5 , the epitaxial contact structure 12 is located in the interconnect layer mentioned below.

[0110] Epitaxial contact structure 12 can serve as a bridge between second power contact 92 and the target electrode, reducing the difficulty of electrical connection between the two electrodes. In this case, the operating current and operating voltage provided by power distribution network 8 can be transmitted sequentially through first power contact 91, second power contact 92, and epitaxial contact structure 12 to the target electrode to which epitaxial contact structure 12 is electrically connected, thereby enabling the transistor electrically connected to epitaxial contact structure 12 to operate.

[0111] In some embodiments, as shown in FIG5 , the integrated circuit 600 provided in the embodiments of the present application further includes a first dielectric layer 13. The first dielectric layer 13 is located between the second surface A2 and the power distribution network 8, and between the first power contact 91 and the substrate 1. A surface of the first power contact 91 that is remote from the second power contact 92 is flush with a surface of the first dielectric layer 13 that is remote from the second surface A2.

[0112] The material of the first dielectric layer 13 includes a dielectric material, including but not limited to silicon oxide, silicon nitride, etc. The first dielectric layer 13 separates the first power contact portion 91 from the substrate 1, thereby achieving electrical insulation between the first power contact portion 91 and the substrate 1. The first dielectric layer 13 separates the power distribution network 8 from the substrate 1, thereby achieving electrical insulation between the power distribution network 8 and the substrate 1.

[0113] In some embodiments, as shown in FIG5 , the integrated circuit 600 provided in the embodiments of the present application further includes an interconnect layer 14. The interconnect layer 14 is located on a side of the epitaxial contact structure 12 away from the substrate 1. The interconnect layer 14 is used to interconnect various components (e.g., transistors, capacitors, resistors, etc.) on the substrate 1.

[0114] Some embodiments of the present application also provide a method for preparing an integrated circuit, which is used, for example, to prepare the integrated circuit 600 described in any of the above examples. FIG8 illustrates a flow chart of a method for preparing an integrated circuit; FIG10a to FIG10m illustrate structures corresponding to each step in a method for preparing an integrated circuit; and FIG11a to FIG11f illustrate structures corresponding to each step in another method for preparing an integrated circuit. It should be understood that the steps shown in FIG8 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in FIG8. In addition, some of the steps may be performed simultaneously, or may be performed in an order different from that shown in FIG8.

[0115] The following is a schematic illustration of the integrated circuit manufacturing method with reference to the accompanying drawings. As shown in FIG8 , the manufacturing method includes: S100 to S600.

[0116] S100, as shown in Figures 9a to 9c, forms an initial integrated circuit 600a. The initial integrated circuit 600a includes a substrate 1, a plurality of fins 2, a second dielectric layer 3, and a sacrificial layer 15. The substrate 1 has a first surface A1 and a second surface A2 opposite to each other, and the plurality of fins 2 are located on the first surface A1, extending along the first direction X and arranged at intervals along the second direction Y. The second dielectric layer 3 fills between two adjacent fins 2 and covers the fins 2. The sacrificial layer 15 is located on the second dielectric layer 3, and the sacrificial layer 15 includes a sacrificial gate 15a spanning the plurality of fins 2. The sacrificial gate 15a extends along the second direction Y. The first direction X and the second direction Y are both parallel to the first surface A1 and intersect with each other.

[0117] It is understood that in different examples, the structure of the initial integrated circuit 600a may be different. Here, in conjunction with the accompanying drawings, three structures of the initial integrated circuit 600a are schematically described. Of course, the structure of the initial integrated circuit 600a is not limited to this.

[0118] In some examples, as shown in FIG9 a , the sacrificial layer 15 includes a plurality of sacrificial gates 15 a , and the plurality of sacrificial gates 15 a are spaced apart along the first direction X. As shown in FIG9 a , the initial integrated circuit 600 further includes a plurality of interlayer dielectric layers 7 , each of which extends along the second direction Y, and the plurality of interlayer dielectric layers 7 and the plurality of sacrificial gates 15 a are alternately arranged.

[0119] For example, the method of forming the above-mentioned sacrificial layer 15 includes: forming a sacrificial film on the second dielectric layer 3, then removing part of the sacrificial film in a preset area, the remaining part of the sacrificial film forming a plurality of sacrificial gates 15a, and then forming an interlayer dielectric layer 7 between two adjacent sacrificial gates 15a.

[0120] In other examples, the sacrificial layer 15 is a monolithic structure. As shown in FIG9b , two adjacent sacrificial gates 15a are continuous and unseparated. In this case, after forming the first gate trimming trench (described below), the portion of the structure between the two adjacent sacrificial gates 15a can be replaced with an interlayer dielectric layer.

[0121] In yet other examples, as shown in FIG9c , the sacrificial layer 15 includes a plurality of sacrificial gates 15a, which are spaced apart along the first direction X, with at least one sacrificial gate 15a being, for example, disconnected. As shown in FIG9c , the initial integrated circuit 600 further includes a plurality of interlayer dielectric layers 7, each extending along the second direction Y. The plurality of interlayer dielectric layers 7 and the plurality of sacrificial gates 15a are alternately arranged. Furthermore, the initial integrated circuit 600 further includes an isolation portion 16, which is disposed at the disconnected position of the sacrificial gate 15a. A first gate trimming trench (described below) is also formed, for example, at the disconnected position of the sacrificial gate 15a.

[0122] The sacrificial layer 15 may be made of a variety of materials, as long as they are easy to etch and remove. Alternatively, the sacrificial layer 15 may be made of, but not limited to, polysilicon, amorphous silicon, amorphous carbon, and the like.

[0123] Regarding the substrate 1 , the fin 2 , and the second dielectric layer 3 , reference may be made to the relevant descriptions above, which will not be repeated here.

[0124] Figure 10a schematically shows a cross-sectional structure of an initial integrated circuit, which can be considered as a cross-sectional structure of the initial integrated circuit shown in Figure 9a or Figure 9b along the second direction Y. This embodiment of the application uses the structure shown in Figure 10a as an example to schematically illustrate a method for manufacturing an integrated circuit.

[0125] S200, as shown in Figures 10b-10c and 11a-11b, forms a first gate-trimming trench G1 in the sacrificial layer 15. The first gate-trimming trench G1 is located between two adjacent fins 2 and disconnects the sacrificial gate 15a. For example, there may be a plurality of first gate-trimming trenches G1, and the plurality of first gate-trimming trenches G1 are spaced apart.

[0126] The first gate cutting groove G1 extends along the first direction X. Along the first direction X, when the size of the first gate cutting groove G1 is relatively small, the first gate cutting groove G1 can also be called a first gate cutting through hole or a first gate cutting deep hole, etc. The embodiment of the present application takes a groove as an example for illustration.

[0127] Exemplarily, the method for forming the first gate trimming trench G1 includes: S210 to S220 .

[0128] S210 , as shown in FIG. 10 b and FIG. 11 a , a mask layer M is formed on the sacrificial layer 15 . The mask layer M1 has a plurality of openings O. The positions of the openings O are the same as those of the first gate cutting trenches to be formed.

[0129] The mask layer M may be a single-layer structure or a structure composed of multiple stacked sub-mask layers. In the case of a single-layer structure, the material of the mask layer M is, for example, photoresist. In the case of a structure composed of multiple stacked sub-mask layers, the multiple sub-mask layers may include, for example, at least one hard mask layer and at least one sub-mask layer formed of a photoresist material.

[0130] S220 , as shown in FIG. 10 c and FIG. 11 b , the sacrificial layer 15 is etched through the opening O using the mask layer M as a mask to form a first gate cutting trench G1 .

[0131] The etching of the first gate-cutting trench G1 stops, for example, at the first surface A1 of the substrate 1. That is, the first gate-cutting trench G1 penetrates the sacrificial gate 15a and the second dielectric layer 3 to the first surface A1.

[0132] Of course, due to unavoidable process errors or other reasons, the etching of the first gate cutting groove G1 may also stop above the first surface A1. At this time, the first gate cutting groove G1 does not completely penetrate the second dielectric layer 3, and there is a portion of the second dielectric layer 3 between the bottom wall of the first gate cutting groove G1 and the first surface A1. Alternatively, the etching of the first gate cutting groove G1 may also stop below the first surface A1. At this time, the first gate cutting groove G1 completely penetrates the second dielectric layer 3 and penetrates into the interior of the substrate 1. Among them, along the direction perpendicular to the first surface A1, the distance between the bottom wall of the first gate cutting groove G1 and the first surface A1 can be determined according to the actual preparation process, and the embodiments of the present application are no longer limited to this.

[0133] S300, as shown in FIG10d and FIG11c, forms an isolation layer 10. The isolation layer 10 at least covers the sidewalls of the first gate trimming trench G1.

[0134] For example, the isolation layer 10 may be formed by a deposition process, etc., in the embodiment of the present application. The deposition process includes but is not limited to an atomic layer deposition process. The isolation layer 10 formed by the atomic layer deposition process has a uniform thickness.

[0135] Optionally, the isolation layer 10 further covers the bottom wall of the first gate cutting trench G1 .

[0136] S400 , as shown in FIG. 10 e and FIG. 11 d , a second power contact portion 92 is formed in the first gate cutting trench G1 .

[0137] Illustratively, the embodiment of the present application may adopt a metal filling process to fill metal material in the first gate cutting groove G1 to form a metal film, which also covers the sacrificial layer 15; then a chemical mechanical polishing process may be adopted to grind away the portion of the metal film covering the sacrificial layer 15, and retain the portion of the metal film located in the first gate cutting groove G1 to obtain the second power contact portion 92.

[0138] The isolation layer 10 can provide a self-aligning effect. During the process of filling the first gate-cut trench G1 with metal material, the metal material can naturally fill within the area defined by the isolation layer 10, avoiding damage to the fin 2 or gate line 4. This helps reduce the difficulty of the metal filling process and improve the reliability and yield of the integrated circuit 600.

[0139] Moreover, the isolation layer 10 has a certain thickness, and the isolation layer 10 can achieve electrical insulation between the sub-gate line 41 and the second power contact portion 92. This means that the provision of the isolation layer 10 can reduce the precision requirements of the alignment, photolithography, etching and other processes required to form the first gate cutting groove G1, thereby reducing the difficulty of the alignment, photolithography, etching and other processes.

[0140] S500, as shown in FIG10m, a first power contact portion 91 is formed on the side of the second power contact portion 92 close to the second surface A2, and the first power contact portion 91 is connected to the second power contact portion 92. The first power contact portion 91 and the second power contact portion 92 constitute a power contact structure 9, for example.

[0141] Illustratively, the method of forming the first power contact portion 91 on the side of the second power contact portion 92 close to the second surface A2 includes: S510 to S520.

[0142] S510, as shown in FIG10k, the substrate 1 is etched from the side where the second surface A2 is located to form a contact groove CG. The contact groove CG exposes a side surface of the second power contact portion 92 close to the second surface A2.

[0143] In any direction parallel to the first surface A1, the size of the bottom wall of the contact groove CG (i.e., the side surface of the contact groove CG away from the second surface A2) is, for example, larger than the size of the side surface of the second power contact portion 92 closer to the second surface A2. In this way, even if the opening position of the contact groove CG deviates, it can be ensured that the contact groove CG can expose the side surface of the second power contact portion 92 closer to the second surface A2, which helps to reduce the precision requirements of the process required to form the contact groove CG, thereby ensuring that the contact area between the subsequently formed first power contact portion 91 and the second power contact portion 92 is larger.

[0144] Optionally, before etching to form the contact trench CG, as shown in Figures 10i and 10j, the initial integrated circuit can be flipped over and the substrate 1 can be thinned. The thickness of the substrate 1 can be thinned to less than 2 μm in a direction perpendicular to the first surface A1. For example, the thickness of the substrate 1 can be thinned to 2 μm, 1.8 μm, 1.5 μm, 1 μm, 0.5 μm, 0.1 μm, etc. This can reduce the depth of the contact trench CG and ease the difficulty of etching to form the contact trench CG.

[0145] The contact groove CG extends, for example, along the first direction X. Along the first direction X, when the contact groove CG is relatively small, the contact groove CG can also be called a contact through hole or a contact deep hole, etc. The embodiment of the present application is illustrated by taking a groove as an example.

[0146] S520 , as shown in FIG10 m , a first power contact portion 91 is formed in the contact trench CG.

[0147] For example, in the embodiment of the present application, a metal filling process can be used to fill the contact trench CG with a metal material to form a metal film, which also covers the second surface A2 of the substrate 1. A chemical mechanical polishing process can then be used to polish away the portion of the metal film covering the second surface A2, leaving the portion of the metal film within the contact trench CG, thereby obtaining the first power contact portion 91. The first power contact portion 91 is in direct contact with the second power contact portion 92 to form an electrical connection.

[0148] Exemplarily, when the isolation layer 10 also covers the bottom wall of the first gate-cutting trench G1, as shown in FIG10j, the cross-sectional shape of the isolation layer 10 along the second direction Y is an inverted "U" shape, and the isolation layer 10 contacts the side surface of the second power contact portion 92 near the second surface A2. In this case, as shown in FIG10k, before forming the first power contact portion 91 in the contact trench CG, the preparation method further includes: removing the portion of the isolation layer 10 covering the bottom wall of the first gate-cutting trench G1 through the contact trench CG. This opens the isolation layer 10, exposing the side surface of the second power contact portion 92 near the second surface A2, thereby facilitating electrical connection between the second power contact portion 92 and the first power contact portion 91.

[0149] Optionally, as shown in FIG101 , before forming the first power contact 91, a first dielectric layer 13 may be formed. The first dielectric layer 13 covers the sidewalls and second surface A2 of the contact trench CG and exposes the second power contact 92. Thus, after the first power contact 91 is formed in the contact trench CG, the first dielectric layer 13 can separate the substrate 1 from the first power contact 91. Furthermore, a side surface of the first power contact 91 that is remote from the second power contact 92 is flush with, for example, a side surface of the first dielectric layer 13 that is remote from the second surface A2.

[0150] S600 , as shown in FIG10 n , a power distribution network 8 is formed on the second surface A2 . The power distribution network 8 is electrically connected to the first power contact portion 91 .

[0151] 10 n , in the case where a first dielectric layer 13 is formed, the power distribution network 8 is formed on the first dielectric layer 13. The first dielectric layer 13 separates the power distribution network 8 from the substrate 1.

[0152] It can be understood that in the above-mentioned preparation method, the first gate cutting groove G1 and the contact groove CG are prepared and formed independently of each other, and the second power contact portion 92 and the first power contact portion 91 are prepared and formed independently of each other. The aspect ratios of the first gate cutting groove G1 and the contact groove CG are relatively small, and the aspect ratios of the second power contact portion 92 and the first power contact portion 91 are also relatively small. Compared with the above-mentioned possible implementation method, in the preparation method provided in the embodiment of the present application, the difficulty of the etching process required for the first gate cutting groove G1 and the contact groove CG is reduced, and the metal filling process required for the second power contact portion 92 and the first power contact portion 91 is reduced. This means that the preparation method provided in the embodiment of the present application can effectively reduce the process difficulty by splitting the preparation process of the power contact structure 9.

[0153] In some embodiments, as shown in Figures 11a and 11b, during S200, during the process of forming the first gate-trimming trench G1 in the sacrificial layer 15, a second gate-trimming trench G2 is also formed. The second gate-trimming trench G2 is located between two adjacent fins 2 and disconnects the sacrificial gate 15a. Along a direction perpendicular to the first surface A1, the depth of the second gate-trimming trench G2 is less than the depth of the first gate-trimming trench G1.

[0154] The number of the second gate cutting grooves G2 is, for example, multiple, and the multiple second gate cutting grooves G2 are spaced apart. Each second gate cutting groove G2 is also spaced apart from the first gate cutting groove G1.

[0155] The first gate-cutting trench G1 and the second gate-cutting trench G2 can be formed, for example, in the same etching process (as shown in FIG. 11 a and FIG. 11 b ), or in different etching processes. In the case of forming them in different etching processes, the order in which the first gate-cutting trench G1 and the second gate-cutting trench G2 are formed can be selected based on actual needs.

[0156] The etching of the second gate trimming trench G2 stops, for example, on the second dielectric layer 3. That is, the second gate trimming trench G2 penetrates the sacrificial gate 15a to the surface of the second dielectric layer 3 away from the substrate 1.

[0157] In some embodiments, as shown in FIG11 c , in the above S300 , during the process of forming the isolation layer 10 , a gate trimming structure 11 is also formed. The gate trimming structure 11 is located in the second gate trimming trench G2 .

[0158] For example, as shown in FIG11c , an embodiment of the present application can employ an atomic layer deposition process to deposit a dielectric material within the first gate-trimming trench G1 and the second gate-trimming trench G2 to form a dielectric film. A first portion of the dielectric film fills the second gate-trimming trench G2, a second portion covers the bottom and sidewalls of the first gate-trimming trench G1, and a third portion covers the sacrificial layer 15. The first portion is used to form the gate-trimming structure 11, the second portion is used to form the isolation layer 10, and the third portion is used, for example, as a grinding stop layer for forming the second power contact 92. Alternatively, the third portion can be removed during the grinding process to form the second power contact 92.

[0159] The embodiment of the present application integrates the preparation process of the isolation layer 10 and the preparation process of the gate cutting structure 11, and integrates the preparation process of the second power contact portion 92 into the preparation process of the gate cutting structure 11, effectively reducing the process flow required for preparing the integrated circuit and simplifying the preparation process of the integrated circuit.

[0160] In some embodiments, before the above S600 , that is, before forming the power distribution network 8 on the second surface A2 , the above preparation method further includes: S510 to S520 .

[0161] S510 , as shown in FIG. 10 e to FIG. 10 f and FIG. 11 d to FIG. 11 e , remove the sacrificial gate 15 a to form a gate line trench GG. The gate line trench GG exposes the second dielectric layer 3 .

[0162] S520, as shown in FIG10g and FIG11f, a conductive material is filled in the gate line trench GG to form a gate line 4. At this point, the gate replacement is completed.

[0163] Optionally, before forming the gate line 4 in the gate line trench GG, a high-k dielectric layer, a work function layer and other structures may be formed, which is not limited in the embodiment of the present application.

[0164] As can be seen from the above, the manufacturing method provided in the embodiment of the present application first forms the power contact structure 9 and then performs the gate replacement. This process concept is different from the process concept of the possible implementation method described above. This facilitates the preparation process of the second power contact portion 92 in the power contact structure 9 to be compatible with the preparation process of the gate cutting structure 11. Moreover, the embodiment of the present application can avoid etching the gate line 4 due to the provision of the second power contact portion 92, thereby avoiding damage to the gate line 4 and improving the yield of the integrated circuit.

[0165] In some embodiments, as shown in Figure 10h, after the gate replacement is performed, the above-mentioned preparation method also includes: forming an epitaxial contact structure 12 on the second power contact portion 92 and the target electrode, and the epitaxial contact structure 12 connects the second power contact portion 92 and the target electrode; then, forming an interconnection layer 14 on the epitaxial contact structure 12; then, bonding a carrier chip 17 on the interconnection layer 14, and the carrier chip 17 can be used to support the integrated circuit.

[0166] Optionally, the carrier wafer 17 may not have any components. In this way, after the integrated circuit is fabricated, the carrier wafer 17 can be peeled off and removed. Alternatively, the carrier wafer 17 may have multiple components (e.g., transistors, capacitors, resistors, etc.) formed therein, with the multiple components in the carrier wafer 17 being electrically connected to the interconnect layer 14. In this way, after the integrated circuit is fabricated, the carrier wafer 17 can serve as part of the integrated circuit.

[0167] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any appropriate manner in any one or more embodiments or examples. The above description is only a specific embodiment of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this disclosure should be included in the scope of protection of this application. Therefore, the scope of protection of this application shall be based on the scope of protection of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises: A substrate having a first surface and a second surface opposite to each other; A plurality of fins are located on the first surface; the plurality of fins extend along a first direction and are arranged at intervals along a second direction; the first direction and the second direction are both parallel to the first surface and intersect each other; A gate line is arranged across the plurality of fins; the gate line extends along the second direction; A source and a drain, located on the fin; one of the source and the drain is a target electrode; An isolation layer is located between two adjacent fins; the isolation layer divides the gate line into a plurality of sub-gate lines; A power contact structure, penetrating the substrate; along the direction from the second surface to the first surface, the power contact structure comprises a first power contact portion and a second power contact portion located on the first power contact portion; the first power contact portion and the second power contact portion are connected; the second power contact portion is electrically connected to the target electrode; A power distribution network is located on the second surface; the power distribution network is electrically connected to the first power contact portion; Wherein, along the second direction, the isolation layer is located on two opposite sides of the second power contact portion.

2. The integrated circuit according to claim 1, characterized in that The connection surface of the first power contact portion and the second power contact portion is located inside the first surface.

3. The integrated circuit according to claim 1 or 2, characterized in that: A side surface of the first power contact portion close to the second power contact portion is a third surface, and a side surface of the second power contact portion close to the first power contact portion is a fourth surface; The orthographic projection of the fourth surface on the first surface is located within the range of the orthographic projection of the third surface on the first surface.

4. The integrated circuit according to any one of claims 1 to 3, characterized in that: The integrated circuit further comprises: a gate cutting structure spaced apart from the isolation layer; the gate cutting structure is located between two adjacent sub-gate lines and between two adjacent fins; The grid cutting structure and the isolation layer are made of the same material and are arranged in the same layer.

5. The integrated circuit according to claim 4, characterized in that Along a direction perpendicular to the first surface, a height of the isolation layer is greater than a thickness of the gate cutting structure.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that: The integrated circuit further comprises: The epitaxial contact structure is located on the second power contact portion and the target electrode, and is in contact with the second power contact portion and the target electrode.

7. The integrated circuit according to any one of claims 1 to 6, characterized in that: The integrated circuit further comprises: a first dielectric layer; The first dielectric layer is located between the second surface and the power distribution network, and between the first power contact and the substrate; A side surface of the first power contact portion away from the second power contact portion is flush with a side surface of the first dielectric layer away from the second surface.

8. A method for preparing an integrated circuit, characterized in that: The preparation method comprises: An initial integrated circuit is formed; the initial integrated circuit comprises a substrate, a plurality of fins, a second dielectric layer, and a sacrificial layer; the substrate has a first surface and a second surface opposite to each other, a plurality of fins are located on the first surface, extend along a first direction, and are arranged at intervals along a second direction; the second dielectric layer is filled between two adjacent fins and covers the fins; the sacrificial layer is located on the second dielectric layer, and the sacrificial layer comprises a sacrificial gate straddling the plurality of fins; the sacrificial gate extends along the second direction; the first direction and the second direction are both parallel to the first surface, and the two intersect; forming a first gate cutting groove in the sacrificial layer; the first gate cutting groove is located between two adjacent fins and disconnects the sacrificial gate; forming an isolation layer; the isolation layer at least covers the sidewall of the first gate cutting groove; forming a second power contact in the first gate cutting trench; A first power contact portion is formed on a side of the second power contact portion close to the second surface, and the first power contact portion is connected to the second power contact portion; A power distribution network is formed on the second surface; the power distribution network is electrically connected to the first power contact portion.

9. The preparation method according to claim 8, characterized in that: In the process of forming the first gate cutting groove in the sacrificial layer, a second gate cutting groove is also formed; the second gate cutting groove is located between two adjacent fins and disconnects the sacrificial gate; along the direction perpendicular to the first surface, the depth of the second gate cutting groove is less than the depth of the first gate cutting groove; During the process of forming the isolation layer, a gate cutting structure is also formed; the gate cutting structure is located in the second gate cutting groove.

10. The preparation method according to claim 8 or 9, characterized in that: The forming of the first power contact portion on a side of the second power contact portion close to the second surface comprises: Etching the substrate from the side where the second surface is located to form a contact groove; the contact groove exposes a side surface of the second power contact portion close to the second surface; The first power contact is formed in the contact trench.

11. The preparation method according to claim 10, characterized in that: The isolation layer also covers the bottom wall of the first gate cutting groove; Before forming the first power contact portion in the contact groove, the preparation method further includes: A portion of the isolation layer covering the bottom wall of the first gate cutting groove is removed through the contact groove to expose a side surface of the second power contact portion close to the second surface.

12. The preparation method according to any one of claims 8 to 11, characterized in that: Before forming the power distribution network on the second surface, the preparation method further comprises: removing the sacrificial gate to form a gate line groove; A conductive material is filled in the gate line trench to form a gate line.

13. An electronic device, characterized in that: The electronic device comprises: Circuit boards; and, The integrated circuit according to any one of claims 1 to 7, wherein the integrated circuit is connected to the circuit board.

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