Power management circuit and electronic device

Abstract

The invention discloses a power supply management circuit and an electronic device, and aims to solve the problems of loop bandwidth limitation and stability caused by the fact that a dominant pole of an output loop of a traditional off-chip capacitor-free FVFLDO circuit is in a low frequency and the distance between the dominant pole and a secondary pole is relatively short, and the problem that the power supply rejection ratio is difficult to increase caused by relatively low FVF loop gain.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a power management circuit and electronic device. Background Technology

[0002] LDO (Low Dropout Regulator) is one of the most common linear regulated power supplies in power management circuits, and it dominates in portable, low-power electronic devices. Depending on whether external capacitors are used, LDOs can be divided into LDOs with external capacitors and CL_LDOs (Capacitor-Less LDOs) without external capacitors.

[0003] like Figure 1 As shown, a traditional LDO with an external capacitor operates using the negative feedback principle, obtaining the voltage V through the feedback resistor R1. OUT A proportional voltage is used as the input to the error amplifier EA, and then the voltage is compared with the reference voltage V through the error amplifier. REF The error voltage obtained by comparison is used to drive the power transistor and output a stable voltage. The large external capacitor in the μF range helps to maintain the stability of the output voltage during the charging and discharging of the load current when there are sudden changes. However, considering cost and area, the CL_LDO without external capacitors is easier to integrate into the system-on-chip (SoC).

[0004] To achieve good transient response performance without using external capacitors, the industry has proposed LDOs based on flipped voltage followers (FVFs) (i.e., FVF_LDOs), whose structure is as follows: Figure 2 As shown. Where EA is the error amplifier, M1 / M2 / M3 / M4 / M5 are conventional MOSFETs, M... P For power transistors, C L For load voltage, R L For load resistance, V REF Reference voltage, V IN V is the input voltage. OUT For output voltage, V MIR For V REF Mirror voltage, V SET The gate control voltage of M2 / M3, V B For bias voltage, V GThis is the gate drive voltage of the power transistor. The FVF structure features high input impedance and low output impedance, which helps reduce output voltage fluctuations caused by transient load changes, making the FVF_LDO more suitable as a voltage source. Furthermore, the control transistor connected to the power transistor in the FVF structure can detect transient changes in the output voltage and quickly control the gate voltage of the power transistor, forming a fast local negative feedback loop. Therefore, the FVF_LDO is advantageous for achieving fast transient response without using large external capacitors.

[0005] However, traditional FVF_LDO circuits without external capacitors have the following problems: First, the product of the equivalent resistance and parasitic capacitance at the gate of the power transistor in the FVF loop is large, making the pole at the gate of the power transistor the low-frequency dominant pole, thus limiting the bandwidth of the FVF loop. Moreover, the main and secondary poles are close to each other, making it difficult to ensure circuit stability. Second, the FVF loop gain is low, making it difficult to improve the power supply rejection ratio of the LDO. Summary of the Invention

[0006] The purpose of this application is to provide a power management circuit and electronic device to solve the problems of limited loop bandwidth and stability caused by the main pole of the output loop of the traditional FVF_LDO circuit without external capacitors being at a low frequency and the main and secondary poles being close together, as well as the problem that the power supply rejection ratio is difficult to improve due to the low gain of the FVF loop.

[0007] To achieve the above objectives, this application adopts the following technical solution.

[0008] According to a first aspect of this application, one embodiment of this application provides a power management circuit, which includes: An error amplifier includes a first input terminal, a second input terminal, and an amplified output terminal. The first input terminal is used to receive a reference voltage, and the second input terminal is used to receive a feedback signal. A flip-flop voltage follower output stage circuit includes: a power transistor, the source of which is coupled to an input voltage terminal, and the drain of which is coupled to a circuit output terminal, the power transistor being used to maintain the voltage stability of the circuit output terminal; a buffer circuit, the input terminal of which is coupled to the amplified output terminal of an error amplifier, and the output terminal of which is coupled to the gate of the power transistor, for buffering the driving of the power transistor; a first MOSFET, the source of which is coupled to the circuit output terminal, and the drain of which is coupled to the input terminal of the buffer circuit; the circuit output terminal is coupled to a second input terminal of the error amplifier to provide the feedback signal; the flip-flop voltage follower output stage circuit and the error amplifier form a negative feedback control loop, so that the voltage at the circuit output terminal is stabilized at the reference voltage; A power supply rejection ratio enhancement circuit includes: a feedforward circuit coupled to the input voltage terminal and the gate of the power transistor, used to detect the ripple voltage at the input voltage terminal and convert the ripple voltage into a small signal current injected into the gate of the power transistor; and a substrate voltage generation circuit used to generate a substrate voltage acting on the substrate terminal of the power transistor, wherein the small signal voltage of the substrate voltage is proportional to the ripple voltage at the input voltage terminal.

[0009] According to a second aspect of this application, one embodiment of this application provides an electronic device that includes the power management circuit described in any embodiment of this application.

[0010] This application incorporates a buffer circuit in the output stage of a flip-flop voltage follower. This buffer circuit buffers the power transistor's drive, utilizing its low output impedance to push the gate pole of the power transistor to a higher frequency, making it a secondary pole. This increases the unity-gain bandwidth of the FVF loop and improves loop stability. A power supply rejection ratio (PSRR) enhancement circuit is also included. The feedforward circuit detects the ripple voltage at the input voltage terminal and converts it into a small-signal current injected into the gate of the power transistor. This causes the small-signal voltage at the power transistor's gate to follow the ripple voltage at the input voltage terminal. A substrate voltage generation circuit generates a substrate voltage acting on the substrate of the power transistor. The small-signal voltage of this substrate voltage is proportional to the ripple voltage at the input voltage terminal. The two work together to increase the gate-source voltage and substrate-source voltage of the power transistor (gate-source voltage refers to the absolute value of the difference between the gate voltage and the source voltage of the power transistor, i.e., |V0|0). GS |Substrate-source voltage represents the absolute value of the difference between the substrate voltage and the source voltage of the power transistor, i.e., |V BS |) Maintain stability, thereby effectively improving the power supply rejection ratio (PSRR) of the output voltage.

[0011] Furthermore, in some embodiments, the buffer circuit employs a super source follower, which can utilize its low input equivalent capacitance to push the poles at the input node of the super source follower to higher frequencies, thereby further increasing the unity-gain bandwidth of the FVF loop. Additionally, the flip-flop voltage follower output stage circuit of this application can employ short-channel devices to increase the characteristic frequency of the MOSFET.

[0012] Furthermore, in some embodiments, this application provides a transient enhancement circuit (including a capacitive coupling unit and a current injection unit). When the load current decreases in a short time, the overshoot voltage is coupled through the capacitor (i.e., the capacitive coupling unit) to generate a transient charging current, which is then injected into the gate of the power transistor through the current mirror (i.e., the current injection unit). This increases the charging current of the power transistor gate, improves the slew rate, and thereby reduces the overshoot voltage and settling time of the output voltage. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a traditional LDO circuit.

[0015] Figure 2 This is a schematic diagram of a traditional FVF_LDO circuit without external capacitors.

[0016] Figure 3 This is a schematic diagram of a power management circuit in one embodiment of this application.

[0017] Figure 4 This is a schematic diagram of an electronic device in one embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] As mentioned earlier, existing FVF_LDO circuits employ an FVF structure, which allows the LDO to achieve good transient response performance without using external capacitors. However, they have the following drawbacks. Specifically, in the FVF loop, the product of the equivalent resistance and parasitic capacitance at the power transistor gate is relatively large, making the pole at the power transistor gate a low-frequency dominant pole, thus limiting the FVF loop bandwidth. Furthermore, the close proximity of the dominant and secondary poles makes it difficult to ensure circuit stability. Additionally, the FVF loop gain is low, making it difficult to improve the LDO's power supply rejection ratio.

[0020] Research revealed that the cause of the above problems is as follows: In the traditional FVF loop structure composed of two PMOS transistors, the product of the equivalent resistance and parasitic capacitance at the gate of the power transistor is relatively large, making the pole at the gate of the power transistor the low-frequency dominant pole, which limits the loop bandwidth and causes stability problems. In particular, the stability problem is more prominent when the pole at the gate of the power transistor is close to the pole at the output terminal. In addition, since the actual FVF loop gain is difficult to improve through conventional methods, and the power supply rejection ratio is proportional to the loop gain, other methods are needed to improve the power supply rejection ratio.

[0021] In view of this, this application proposes a power management circuit, which may include an error amplifier, a flip-flop voltage follower output stage circuit, and a power supply rejection ratio (PSRR) enhancement circuit. The flip-flop voltage follower output stage circuit uses a super source follower as a buffer circuit to split the original low-frequency pole into two high-frequency poles to ensure loop stability. The PSRR enhancement circuit includes a feedforward circuit and a substrate voltage generation circuit. Through the coordinated operation of the feedforward circuit and the substrate voltage generation circuit, the stability of the circuit output relative to the input voltage is maintained, and the power supply rejection capability of the output voltage is enhanced. Furthermore, this application may also include a transient enhancement circuit to further improve the transient characteristics of the LDO.

[0022] The specific structure and working principle of the power management circuit of this application will be further described in detail below with reference to the accompanying drawings.

[0023] like Figure 3 As shown, the power management circuit 1 provided in this application embodiment may include: an error amplifier 10, a flip-flop voltage follower output stage circuit 30, and a power supply rejection ratio enhancement circuit 40.

[0024] The error amplifier 10 may include a first input terminal, a second input terminal, and an amplified output terminal. The first input terminal is used to receive the reference voltage VREF.

[0025] In this embodiment, the flip-flop voltage follower output stage circuit 30 is coupled to the error amplifier 10. The flip-flop voltage follower output stage circuit 30 may include: a power transistor MP, a buffer circuit, and a first MOSFET M8.

[0026] In this embodiment, the source of the power transistor MP is coupled to the input voltage terminal VIN, and the drain of the power transistor MP is coupled to the circuit output terminal VOUT. The power transistor MP is used to adjust the current flowing through the power transistor MP according to the gate voltage of the power transistor MP in order to maintain the voltage stability of the circuit output terminal VOUT.

[0027] In this embodiment, the input terminal of the buffer circuit is coupled to the amplified output terminal of the error amplifier 10, and the output terminal of the buffer circuit is coupled to the gate of the power transistor MP (e.g., Figure 3 The V shown G (The same applies below), used to buffer the drive power transistor MP and push the secondary pole in the FVF loop to a higher frequency to ensure loop stability.

[0028] In this embodiment, the source of the first MOSFET M8 is coupled to the circuit output terminal VOUT, and the drain of the first MOSFET M8 is coupled to the input terminal of the buffer circuit.

[0029] In this embodiment, the circuit output terminal VOUT is coupled to the second input terminal of the error amplifier 10 to provide a feedback signal.

[0030] In this embodiment, the flip voltage follower output stage circuit 30 and the error amplifier 10 form a negative feedback control loop. Through the feedback effect of the error amplifier 10, the negative feedback control loop stabilizes the voltage at the circuit output terminal VOUT at the reference voltage VREF.

[0031] Furthermore, in the output stage circuit 30 of the flip voltage follower, the power transistor MP, the first MOSFET M8, and the buffer circuit (including the fifth MOSFET M9) form a local negative feedback loop to achieve a fast transient response.

[0032] Specifically, the first MOSFET M8 can detect the transient change of the circuit output VOUT and quickly control the gate voltage of the power transistor MP through the buffer circuit, thereby controlling the drain output voltage of the power transistor MP and forming a fast local negative feedback loop (see the description below for details).

[0033] In this embodiment, the power supply rejection ratio enhancement circuit 40 may include a feedforward circuit 41 and a substrate voltage generation circuit 42.

[0034] The feedforward circuit 41 is coupled to the input voltage terminal VIN and the gate of the power transistor MP. It is used to detect the ripple voltage of the input voltage terminal VIN, convert the ripple voltage into a small-signal current, and inject it into the gate of the power transistor MP. The substrate voltage generation circuit 42 is used to generate a substrate voltage acting on the substrate of the power transistor MP, and the small-signal voltage of the substrate voltage is proportional to the ripple voltage of the input voltage terminal.

[0035] In this embodiment, the feedforward circuit and the substrate voltage generation circuit work together to make the gate-source voltage and substrate-source voltage of the power transistor (the gate-source voltage refers to the absolute value of the difference between the gate voltage and the source voltage of the power transistor, i.e., |V0|) equal. GS |Substrate-source voltage refers to the absolute value of the difference between the substrate voltage and the source voltage of the power transistor, i.e., |V BS |) To maintain stability, thereby keeping the circuit output VOUT stable relative to the input voltage and improving the power supply rejection capability of the output voltage.

[0036] In some embodiments, the power management circuit 1 of this application may further include a transient enhancement circuit 20, the input terminal of which is coupled to the circuit output terminal VOUT, and the output terminal of which is coupled to the gate of the power transistor MP. The transient enhancement circuit 20 is used to improve the load transient response performance of the LDO.

[0037] In some embodiments, the power management circuit 1 of this application may further include a bias circuit 50 for providing bias voltages to the error amplifier 10, the transient enhancement circuit 20, the flip voltage follower output stage circuit 30, and the power supply rejection ratio enhancement circuit 40.

[0038] The specific structure and function of each circuit will be further described below.

[0039] In this embodiment, the error amplifier 10 may be a two-stage amplifier, specifically including a first-stage folded cascode amplifier stage and a second-stage cascode amplifier stage.

[0040] In one specific embodiment, the error amplifier 10 may include: a 23rd MOSFET M1, a 24th MOSFET M2, a 25th MOSFET M3, a 26th MOSFET M4, a 27th MOSFET M5, a 28th MOSFET M6, a 29th MOSFET M16, a 30th MOSFET M17, a 31st MOSFET M18, a 32nd MOSFET M19, a 33rd MOSFET M14, a 34th MOSFET M15, a third capacitor C1, and a 35th MOSFET M21.

[0041] Among them, the 23rd MOSFET M1, the 24th MOSFET M2, the 25th MOSFET M3, the 26th MOSFET M4, the 27th MOSFET M5, the 28th MOSFET M6, the 33rd MOSFET M14, the 34th MOSFET M15, the 29th MOSFET M16, the 30th MOSFET M17, the 31st MOSFET M18, and the 32nd MOSFET M19 together constitute the first stage of the folded common-source common-gate amplifier stage.

[0042] Specifically, the 23rd MOSFET M1 and the 24th MOSFET M2 serve as the first and second input terminals of the error amplifier 10, respectively. That is, the gate of the 23rd MOSFET M1 receives the reference voltage, and the gate of the 24th MOSFET M2 receives the feedback signal. The 23rd MOSFET M1 and the 24th MOSFET M2 form a differential input pair. The sources of the 23rd MOSFET M1 and the 24th MOSFET M2 are coupled to the drain of the 33rd MOSFET M14. The 33rd MOSFET M14 and the 34th MOSFET M15 are connected in series between the source of the 23rd MOSFET M1 and ground, serving as the tail current source for the first stage. The drains of the 23rd MOSFET M1 and the 24th MOSFET M2 are coupled to the drains of the 25th MOSFET M3 and the 26th MOSFET M4, respectively. The sources of both the 25th MOSFET M3 and the 26th MOSFET M4 are coupled to the input voltage terminal VIN, and the gates of the 25th MOSFET M3 and the 26th MOSFET M4 are coupled and receive the bias voltage. The 25th MOSFET M3 and the 26th MOSFET M4 act as folded transistors, with their drains coupled to the sources of the 27th MOSFET M5 and the 28th MOSFET M6, respectively. The gates of the 27th MOSFET M5 and the 28th MOSFET M6 are coupled, and their drains are coupled to the drains of the 29th MOSFET M16 and the 30th MOSFET M17, respectively. Together, these transistors form a folded cascode structure. The gates of the 29th MOSFET M16 and the 30th MOSFET M17 are coupled, and their sources are coupled to the drains of the 31st MOSFET M18 and the 32nd MOSFET M19, respectively. The gates of the 31st MOSFET M18 and the 32nd MOSFET M19 are coupled, and their sources are all grounded. The 29th MOSFET M16, the 30th MOSFET M17, the 31st MOSFET M18, and the 32nd MOSFET M19 form a cascode current mirror, serving as the first-stage active load to achieve more accurate current replication.

[0043] Furthermore, the 35th MOSFET M21 constitutes the second common-source amplifier stage. The gate of the 35th MOSFET M21 is coupled to the drain of the 28th MOSFET M6 (i.e., the output node of the first stage), and the source of the 35th MOSFET M21 is grounded. The drain of the 35th MOSFET M21 serves as the amplified output terminal of the error amplifier 10 and is coupled to the drain and gate of the 36th MOSFET M7. The third capacitor C1 serves as a compensation capacitor. The first terminal of the third capacitor C1 is coupled to the drains of the 28th MOSFET M6 and the 30th MOSFET M17, as well as the gate of the 35th MOSFET M21, while the second terminal is grounded to ensure the stability of the two amplifier stages.

[0044] It should be noted that, compared with conventional two-stage operational amplifiers, the error amplifier 10 in this embodiment of the application achieves higher speed while maintaining higher gain by using a folded cascode structure, thereby increasing the bandwidth of the negative feedback control loop (i.e., the main loop) and accelerating the response speed of the negative feedback control loop. Furthermore, the third capacitor C1 in this embodiment of the application is used to ensure the stability of the loop. The thirty-fifth MOSFET M21 serves as the second-stage amplifier.

[0045] In this embodiment, the buffer circuit of the flip voltage follower output stage circuit 30 is a super source follower, which may include: a second MOSFET M27, a third MOSFET M28, a fourth MOSFET M29, a fifth MOSFET M9, a sixth MOSFET M10, and a forty-third MOSFET M11.

[0046] In this embodiment, the gates of the second MOSFET M27, the third MOSFET M28, and the fourth MOSFET M29 are respectively connected to bias voltages. The second MOSFET M27 serves as a current source, while the third MOSFET M28 and the fourth MOSFET M29 together serve as a common-source, common-gate current source (when the MOSFETs are operating in the saturation region and the gate-source voltage (V...)...) GS When the bias voltage is fixed, it can be used as a current source; and compared with a single-transistor current source, the common-source common-gate current source composed of the third MOSFET M28 and the fourth MOSFET M29 has a higher output impedance due to the introduction of the common-gate transistor M28, making it closer to an ideal current source.

[0047] In this embodiment, the source of the second MOSFET M27 is coupled to the input voltage terminal VIN, and the drain of the second MOSFET M27 is coupled to the drain of the third MOSFET M28. The source of the third MOSFET M28 is coupled to the drain of the fourth MOSFET M29, and the source of the fourth MOSFET M29 is grounded. The gate of the fifth MOSFET M9 is coupled to the output terminal of the error amplifier 10 (specifically, through the first MOSFET M8, the thirty-sixth MOSFET M7 to the thirty-fifth MOSFET M21), and the source of the fifth MOSFET M9 is coupled to the input voltage terminal VIN through the second MOSFET M27. The gate of the sixth MOSFET M10 is coupled to the drain of the fifth MOSFET M9 and the drain of the third MOSFET M28, the source of the sixth MOSFET M10 is grounded, and the drain of the sixth MOSFET M10 is coupled to the gate of the power transistor MP. The source of the forty-third MOSFET M11 is coupled to the input voltage terminal VIN, and the gate and drain of the forty-third MOSFET M11 are coupled to the drain of the sixth MOSFET M10.

[0048] In this embodiment, the super source follower has low output impedance characteristics, and the pole at the gate of the power transistor MP is pushed to a higher frequency, becoming a secondary pole. Due to its low input equivalent capacitance, the node at the input node of the super source follower is also pushed to a higher frequency, thus increasing the unity-gain bandwidth of the FVF loop (described below). The super source follower's output impedance... It can be represented as: ,in, This indicates the transconductance of the fifth MOSFET M9. This represents the equivalent output resistance of the fifth MOSFET M9. This indicates the transconductance of the sixth MOSFET M10.

[0049] Furthermore, in the embodiments of this application, the second MOSFET M27, the fifth MOSFET M9, the sixth MOSFET M10, and the forty-third MOSFET M11 are all short-channel devices. The first MOSFET M8 is also a short-channel device. By using short-channel devices, the intrinsic gain of the MOSFETs is increased. A value between approximately 5 and 10 is beneficial for improving the frequency response characteristics of the circuit, thereby increasing the FVF loop bandwidth.

[0050] Furthermore, in this embodiment, the flip-flop voltage follower output stage circuit 30 may further include: a thirty-seventh MOSFET M30, the drain of which is coupled to the drain of the first MOSFET M8 (e.g., Figure 3 The V shown A (At the location), the source of the thirty-seventh MOSFET M30 is grounded. The power transistor MP, the first MOSFET M8, and the thirty-seventh MOSFET M30 form an FVF structure, which features high input impedance and low output impedance. The low output impedance can reduce output voltage fluctuations caused by load changes.

[0051] Furthermore, in this embodiment, the flip-flop voltage follower output stage circuit 30 may further include: a fourth capacitor C3 and a load capacitor C L and load resistance R L .

[0052] In this embodiment, the first terminal of the fourth capacitor C3 is coupled to the gates of the thirty-sixth MOSFET M7 and the first MOSFET M8, and the second terminal is grounded. Load capacitor C L The first terminal is coupled to the circuit output terminal VOUT, and the second terminal is grounded. Load resistor R L One end of the capacitor is coupled to the circuit output terminal VOUT, and the other end is grounded. The fourth capacitor, C3, serves as the compensation capacitor for the main loop, used to adjust the frequency characteristics of the main loop.

[0053] It should be noted that, in the embodiments of this application, the first MOSFET M8, the fifth MOSFET M9 in the super source follower, and the power transistor MP constitute a local negative feedback loop to achieve a fast transient response.

[0054] In this embodiment, the power management circuit 1 may further include a transient enhancement circuit 20 to improve the load transient response performance of the LDO. The transient enhancement circuit 20 may include a capacitive coupling unit and a current injection unit. The capacitive coupling unit detects transient voltage changes at the output terminal VOUT of the detection circuit through capacitive coupling. The current injection unit injects transient current into the gate of the power transistor MP to respond to transient changes.

[0055] Specifically, the capacitive coupling unit of the transient enhancement circuit 20 may include: a second capacitor C2, a fourth resistor R2, a sixteenth MOSFET M25, a seventeenth MOSFET M26, and a twentieth MOSFET M24.

[0056] In this embodiment, the first terminal of the second capacitor C2 is coupled to the circuit output terminal VOUT. One end of the fourth resistor R2 is coupled to the second capacitor C2. The gate of the sixteenth MOSFET M25 is coupled to the second terminal of the second capacitor C2 and one end of the fourth resistor R2. The source of the sixteenth MOSFET M25 is grounded, and the drain of the sixteenth MOSFET M25 is coupled to the drain of the eighteenth MOSFET M22. The gate of the seventeenth MOSFET M26 is coupled to the other end of the fourth resistor R2, and the source of the seventeenth MOSFET M26 is grounded. The drain of the twentieth MOSFET M24 is coupled to the input voltage terminal VIN, and the source of the twentieth MOSFET M24 is coupled to the drain of the seventeenth MOSFET M26.

[0057] Furthermore, the current injection unit of the transient enhancement circuit 20 may include: the eighteenth MOSFET M22 and the nineteenth MOSFET M23.

[0058] In this embodiment, the eighteenth MOSFET M22 and the nineteenth MOSFET M23 form a current mirror. The sources of both the eighteenth MOSFET M22 and the nineteenth MOSFET M23 are coupled to the input voltage terminal VIN. The gate and drain of the eighteenth MOSFET M22 are coupled together. The drain of the nineteenth MOSFET M23 is coupled to the drain of the second MOSFET M27, the source of the fifth MOSFET M9, the gate and drain of the forty-third MOSFET M11, and the gate of the power transistor MP.

[0059] In this embodiment, when the load current decreases briefly, an overshoot voltage is generated at the circuit output VOUT because there is no large external capacitor as a load. This overshoot voltage is coupled to the gates of the sixteenth MOSFET M25 and the seventeenth MOSFET M26 through the second capacitor C2, generating a transient charging current. This charging current is then injected into the gate of the power transistor MP through the current mirror formed by the eighteenth MOSFET M22 and the nineteenth MOSFET M23, increasing the charging current at the gate of the power transistor MP and thus increasing the slew rate. This reduces the overshoot and settling time of the output voltage. It should be noted that the slew rate is proportional to the current; therefore, increasing the charging current can improve the slew rate and thus improve the transient response performance.

[0060] In this embodiment, the power supply rejection ratio enhancement circuit 40 may include a feedforward circuit 41 and a substrate voltage generation circuit 42.

[0061] The feedforward circuit 41 may include: a first operational transconductance amplifier OTA2, a seventh MOSFET M31, an eighth MOSFET M33, a first resistor R3, and a first capacitor C4.

[0062] In this embodiment, the source of the seventh MOS transistor M31 is coupled to the input voltage terminal VIN, and the gate and drain of the seventh MOS transistor M31 are coupled to the inverting input terminal of the first operational transconductance amplifier OTA2. The gate and drain are coupled together.

[0063] In this embodiment, the source of the eighth MOS transistor M33 is coupled to the drain of the seventh MOS transistor M31, and the gate is coupled to the output of the first operational transconductance amplifier OTA2.

[0064] In this embodiment, the first resistor R3 and the first capacitor C4 are connected in series, and the non-inverting input of the first operational transconductance amplifier OTA2 is coupled to the connection node of the first resistor R3 and the first capacitor C4.

[0065] Furthermore, the feedforward circuit 41 may also include: a ninth MOSFET M34, a tenth MOSFET M35, an eleventh MOSFET M36, and a twelfth MOSFET M37.

[0066] Among them, the ninth MOSFET M34 and the tenth MOSFET M35 form a current mirror. The sources of the ninth MOSFET M34 and the tenth MOSFET M35 are both coupled to the input voltage terminal VIN. The drain of the ninth MOSFET M34 is coupled to the gate of the power transistor MP. The gate and drain of the tenth MOSFET M35 are coupled.

[0067] In this embodiment, the eleventh MOSFET M36 and the twelfth MOSFET M37 form a current mirror. The gate and drain of the eleventh MOSFET M36 are coupled to the drain of the eighth MOSFET M33, and the drain of the twelfth MOSFET M37 is coupled to the drain of the tenth MOSFET M35.

[0068] Among them, the ninth MOSFET M34, the tenth MOSFET M35, the eleventh MOSFET M36, and the twelfth MOSFET M37 are used to transfer the small signal current generated by the feedforward circuit 41 to the gate of the power transistor MP.

[0069] Furthermore, the feedforward circuit 41 may also include: the thirty-eighth MOSFET M32, the thirty-ninth MOSFET M38, and the fortieth MOSFET M39.

[0070] Specifically, the source of the thirty-eighth MOSFET M32 is coupled to the input voltage terminal VIN, the drain of the thirty-eighth MOSFET M32 is coupled to the drain of the thirty-ninth MOSFET M38, and the gate of the thirty-eighth MOSFET M32 is coupled to the drain and the first resistor R3. The source of the thirty-ninth MOSFET M38 is coupled to the drain of the fortieth MOSFET M39. The source of the fortieth MOSFET M39 is grounded.

[0071] In this embodiment, the inverting input of the first operational transconductance amplifier OTA2 is coupled to the gate of the seventh MOSFET M31. Due to the virtual short characteristic of the first operational transconductance amplifier OTA2, the gate voltage of the seventh MOSFET M31 remains stable, thus the seventh MOSFET M31 can function as a common-gate amplifier. When the power supply voltage at the input voltage terminal VIN is disturbed by noise, the gate of the seventh MOSFET M31 can be approximated as AC ground. The ripple voltage vin generated by the noise disturbance (vin is a small-signal voltage generated at the input voltage terminal VIN, which can be considered as a small-amplitude fluctuation voltage) is converted into a small-signal current ΔI through the common-gate MOSFET M31. M31 ΔI M31 =g m31 ×vin, where g m31 This is the transconductance of the seventh MOSFET M31. The small-signal current ΔI... M31 The current is transmitted to the gate of power transistor MP via the eighth MOSFET M33 and two sets of current mirrors (eleventh MOSFET M36, twelfth MOSFET M37, ninth MOSFET M34, and tenth MOSFET M35), injecting parasitic capacitance into the gate of power transistor MP. This causes the small-signal voltage at the gate of power transistor MP to follow the ripple voltage change at the input voltage terminal VIN. Because small fluctuations in the input voltage terminal VIN will cause changes in the source voltage V of power transistor MP... S The change, and the control of the power supply rejection ratio enhancement circuit 40, causes the gate voltage V of the power transistor MP to change. GThe voltages also change accordingly, with the changes being approximately the same, to ensure the gate-source voltage V of the power transistor MP. GS The voltage remains essentially unchanged, thus maintaining the stability of the output voltage VOUT.

[0072] In this embodiment, the substrate voltage generation circuit 42 of the power supply rejection ratio enhancement circuit 40 may include: a first replica power transistor MP1 and a second replica power transistor MP2, a second resistor R4 and a third resistor R5, and a second operational transconductance amplifier OTA3.

[0073] The channel width-to-length ratio of the first replica power transistor MP1 and the second replica power transistor MP2 is proportional to the channel width-to-length ratio of the power transistor MP (i.e., the width-to-length ratio is equal). The sources of both the first replica power transistor MP1 and the second replica power transistor MP2 are coupled to the input voltage terminal VIN.

[0074] In this embodiment, the second resistor R4 and the third resistor R5 are connected in series between the input voltage terminal VIN and the drain of the second replica power transistor MP2. The non-inverting input terminal of the second operational transconductance amplifier OTA3 is coupled to the connection node V of the second resistor R4 and the third resistor R5. X The inverting input of the second operational transconductance amplifier OTA3 is coupled to the reference voltage VREF. The output of the second operational transconductance amplifier OTA3 generates a substrate voltage SUB, and this output is coupled to the substrate of the second replica power transistor MP2 and the substrate of the power transistor MP.

[0075] Furthermore, the substrate voltage generation circuit 42 may also include: a third operational transconductance amplifier OTA4, a thirteenth MOSFET M40, a fourteenth MOSFET M41, a fifteenth MOSFET M42, a forty-first MOSFET M43, and a forty-second MOSFET M44.

[0076] The non-inverting input of the third operational transconductance amplifier OTA4 is coupled to the drain V of the first replica power transistor MP1. Y The inverting input of the third operational transconductance amplifier OTA4 is coupled to the reference voltage VREF, and the output of the third operational transconductance amplifier OTA4 is coupled to the gates of the thirteenth MOSFET M40 and the fourteenth MOSFET M41.

[0077] In this embodiment, the drain of the thirteenth MOSFET M40 is coupled to the drain of the second replica power transistor MP2 and the third resistor R5. The source of the thirteenth MOSFET M40 and the source of the fourteenth MOSFET M41 are both grounded, and the drain of the fourteenth MOSFET M41 is coupled to the drain of the first replica power transistor MP1.

[0078] In this embodiment, the gate and drain of the fifteenth MOS transistor M42 are coupled to the substrate of the first replica power transistor MP1, and the source of the fifteenth MOS transistor M42 is coupled to the input voltage terminal VIN.

[0079] In this embodiment, the drain of the forty-first MOS transistor M43 is coupled to the gate and drain of the fifteenth MOS transistor M42, the source of the forty-first MOS transistor M43 is coupled to the drain of the forty-second MOS transistor M44, and the source of the forty-second MOS transistor M44 is grounded.

[0080] In the embodiments of this application, the first operational transconductance amplifier OTA2, the second operational transconductance amplifier OTA3, and the third operational transconductance amplifier OTA4 are all classic five-transistor OTA structures.

[0081] It should be noted that the substrate voltage VSUB serves as the substrate voltage of the power transistor MP. The first and second replicated power transistors MP1 and MP2 are proportional replicas of power transistor MP. Therefore, it is easy to cause… ,in For the conductance of the second replica power transistor MP2, For the body transconductance of the second replica power transistor MP2, The conductance of the power transistor MP Let V be the body transconductance of the power transistor MP. The small-signal model of the circuit is used to determine V. X and V Y By listing Kirchhoff's Current Law (KCL) equations at the node, and taking the resistance values ​​of the second resistor R4 and the third resistor R5 to be both 1MΩ, the small-signal voltage of the substrate voltage VSUB can be obtained. The expression:

[0082] in, The small-signal voltage at the input voltage terminal VIN. For the conductance of the second replica power transistor MP2, For the body transconductance of the second replica power transistor MP2, The conductance of the power transistor MP Let be the body transconductance of the power transistor MP. The above expression shows that the substrate voltage VSUB is the small-signal voltage. The small-signal voltage of the substrate voltage VSUB is proportional to the ripple voltage at the input voltage terminal VIN. In other words, the small-signal voltage of the substrate voltage VSUB can follow the small-signal voltage at the input voltage terminal VIN. The changes.

[0083] The power supply rejection ratio expression of the power management circuit 1 of this application is derived below: Formula (1):

[0084] Formula (2):

[0085] Formula (3):

[0086] Formula (4):

[0087] Formula (5):

[0088] Formula (6):

[0089] Formula (7):

[0090] Formula (8):

[0091] Formula (1) above represents the source-to-drain voltage gain of power transistor MP. The output path of power transistor MP does not consider the effects of VREF and the error amplifier. Due to the negative feedback of the FVF loop, the voltage at the gate of power transistor MP is approximately stable. Therefore, power transistor MP can be considered a common-gate amplifier, and its gain is given by formula (1). Indicates equivalent transconductance. Indicates the equivalent output impedance. This represents the small-signal voltage at the circuit output. This represents the small-signal voltage at the input voltage terminal.

[0092] Formula (2) is the expression for the equivalent transconductance of power transistor MP as a common-gate amplifier, where, For the transconductance of the power transistor MP, For the body transconductance of the power transistor MP, The conductance of the power transistor MP This indicates the transconductance of the seventh MOSFET M31. This represents the output impedance of the super source follower. This indicates the transconductance of the 43rd MOSFET, M11. This represents the small-signal voltage on the substrate of the power transistor MP. The first two terms of this expression indicate the effect of incorporating the power supply rejection ratio (PSRR) enhancement circuit 40. Without the PSRR enhancement circuit 40,

[0093] Formula (3) is the expression for the output impedance of the output terminal of the flip voltage follower output stage circuit, where The small-signal resistor represents the power transistor MP. Represents the load resistance R L Load capacitor C L The parallel connection of the resistor from the circuit output terminal VOUT to the source of the first MOS transistor M8 is expressed by the above formula (4). The equivalent output impedance of the parallel negative feedback generated by the parallel negative feedback of the FVF output stage is expressed by formula (5).

[0094] In formula (4) Indicates the load resistance. Indicates the load capacitance. Represents complex frequency. This represents the equivalent output resistance of the first MOSFET M8. This represents the equivalent output resistance of the 37th MOSFET, M30. This indicates the transconductance of the first MOSFET M8.

[0095] In formula (5) This represents the equivalent output resistance of the power transistor MP. This represents the loop gain of the FVF loop. Represents the load resistance R L Load capacitor C L The parallel connection of the resistor from the circuit output terminal VOUT to the source of the first MOSFET M8. This represents the equivalent output impedance of the parallel negative feedback generated by the parallel negative feedback of the FVF output stage.

[0096] Formula (6) is the expression for the output impedance of the super source follower, where, This indicates the transconductance of the fifth MOSFET M9. This represents the equivalent output resistance of the fifth MOSFET M9. This indicates the transconductance of the sixth MOSFET M10. This represents the output impedance of the super source follower.

[0097] Formula (7) is the loop gain of the FVF loop (i.e., the local negative feedback loop), where, This represents the equivalent output resistance of the first MOSFET M8. This represents the equivalent output resistance of the 37th MOSFET, M30. This represents the equivalent output resistance of the power transistor MP. This represents the parallel connection of the load resistor, load capacitor, and the resistance seen from the output terminal towards the source of the first MOSFET M8. This represents the loop gain of the FVF loop.

[0098] Formula (8) is the PSR expression for the output voltage of the flip voltage follower output stage circuit.

[0099] It should be noted that, in order to improve the power supply rejection characteristics of the output voltage, the numerator of formula (8) needs to be close to 0. According to the above formula (6), assuming ,therefore, In this case, by configuring the circuit parameters, it is possible to... , This makes the numerator of equation (8) approximately 0. At this time, the power supply rejection ratio of the output voltage VOUT at the circuit output terminal is improved.

[0100] Furthermore, it should be noted that as the process node shrinks, the gate length L of the power transistor MP can be reduced, and the channel length modulation effect becomes more pronounced, resulting in a decrease in the conductance of the power transistor MP. As the gain increases, the intrinsic gain of the MOSFET decreases. At this point, the power supply rejection ratio (PSRR) enhancement effect of the feedforward circuit 41 and the substrate voltage generation circuit 42 on the output voltage becomes more pronounced as part of the power supply rejection ratio enhancement circuit 40. Therefore, the power supply rejection ratio enhancement circuit 40 of this application is more suitable for process nodes below 90nm.

[0101] In this embodiment, the power management circuit 1 may further include a fourth operational transconductance amplifier OTA1 and a forty-fourth MOSFET M20.

[0102] Specifically, the non-inverting input of the fourth operational transconductance amplifier OTA1 is coupled to the drain of the forty-fourth MOSFET M20 and the source of the thirty-sixth MOSFET M7. The inverting input of the fourth operational transconductance amplifier OTA1 is coupled to the reference voltage VREF. The output of the fourth operational transconductance amplifier OTA1 is coupled to the gate of the forty-fourth MOSFET M20. The source of the forty-fourth MOSFET M20 is coupled to the input voltage VIN, and the drain of the forty-fourth MOSFET M20 is coupled to the source of the thirty-sixth MOSFET M7.

[0103] In this embodiment, the power management circuit 1 may further include a bias circuit 50. The bias circuit 50 may include a current source Ibias connected in series between the input voltage terminal VIN and ground, a fifth resistor R1, a twenty-first MOSFET M12, and a twenty-second MOSFET M13.

[0104] Among them, the gate output of the twenty-first MOS transistor M12 is the first bias voltage V. B2 The drain of the twenty-first MOSFET M12 is coupled to the fifth resistor R1, and the source of the twenty-first MOSFET M12 is coupled to the drain of the twenty-second MOSFET M13.

[0105] In this embodiment, the gate output of the twenty-second MOS transistor M13 is a second bias voltage V. B3 It is coupled to the drain of the twenty-first MOSFET M12, and the source of the twenty-second MOSFET M13 is grounded.

[0106] In this embodiment, the first bias voltage V B2 Second bias voltage V B3 The bias voltage is transmitted to the gates of the corresponding MOS transistors in the error amplifier 10, transient enhancement circuit 20, flip voltage follower output stage circuit 30, and power supply rejection ratio enhancement circuit 40, respectively, to provide bias voltage for each circuit.

[0107] Specifically, the first bias voltage V B2 The voltage is transmitted to the gates of the 29th MOSFET M16 and 30th MOSFET M17 in error amplifier 10, the gate of the 20th MOSFET M24 in transient enhancement circuit 20, the gate of the 3rd MOSFET M28 in flip voltage follower output stage circuit 30, and the gates of the 39th MOSFET M38 and 41st MOSFET M43 in power supply rejection ratio enhancement circuit 40. The second bias voltage V B3 The bias voltages are transmitted to the gates of the thirty-first MOSFET M18 and thirty-second MOSFET M19 in error amplifier 10, the gates of the fourth MOSFET M29 and thirty-seventh MOSFET M30 in the flip voltage follower output stage circuit 30, and the gates of the fortieth MOSFET M39 and forty-second MOSFET M44 in power supply rejection ratio enhancement circuit 40. The twenty-first MOSFET M12 and the twenty-second MOSFET M13 output different bias voltages to meet the bias requirements of different circuits.

[0108] In addition, it should be noted that the bias voltage V generated by the gate of the thirty-eighth MOSFET M32 in the power supply rejection ratio enhancement circuit 40 is... B1 The power supply rejection ratio is transmitted to the gates of the 25th MOS transistor M3 and the 26th MOS transistor M4 of the error amplifier 10, the gate of the second MOS transistor M27 of the flip voltage follower output stage circuit 30, and the gates of the first replica power transistor MP1 and the second replica power transistor MP2 of the power supply rejection ratio enhancement circuit 40.

[0109] like Figure 4As shown, this application also provides an electronic device 100, which may include the power management circuit 1 described in any of the above embodiments. The electronic device 100 may be in the form of an integrated circuit chip, integrating the power management circuit 1 with other functional circuits on the same chip, or it may be a separate voltage source chip, serving as a general-purpose voltage source product for use in other systems. Due to the use of the power management circuit 1 of this application, the electronic device 100 can obtain a stable output voltage, fast transient response, and good power supply rejection performance, thereby improving the overall performance of the electronic device 100.

[0110] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments.

[0111] It is understood that those skilled in the art can combine various implementation methods in the above embodiments under the guidance of the above examples to obtain technical solutions with multiple implementation methods. The above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power management circuit, characterized in that, include: An error amplifier includes a first input terminal, a second input terminal, and an amplified output terminal, wherein the first input terminal is used to receive a reference voltage; A flip-flop voltage follower output stage circuit includes: a power transistor, the source of which is coupled to the input voltage terminal and the drain of which is coupled to the circuit output terminal, the power transistor being used to maintain the voltage stability of the circuit output terminal; a buffer circuit, the input terminal of which is coupled to the amplification output terminal and the output terminal of which is coupled to the gate of the power transistor, for buffering the driving of the power transistor; a first MOSFET, the source of which is coupled to the circuit output terminal and the drain of which is coupled to the input terminal of the buffer circuit; the circuit output terminal is coupled to a second input terminal to provide a feedback signal; the flip-flop voltage follower output stage circuit and the error amplifier form a negative feedback control loop, so that the voltage at the circuit output terminal is stabilized at the reference voltage; A power supply rejection ratio enhancement circuit includes: a feedforward circuit coupled to the input voltage terminal and the gate of the power transistor, used to detect the ripple voltage at the input voltage terminal and convert the ripple voltage into a small signal current injected into the gate of the power transistor; and a substrate voltage generation circuit used to generate a substrate voltage acting on the substrate terminal of the power transistor, wherein the small signal voltage of the substrate voltage is proportional to the ripple voltage at the input voltage terminal.

2. The power management circuit as described in claim 1, characterized in that, The error amplifier includes: a 23rd MOSFET and a 24th MOSFET, which serve as the first input terminal and the second input terminal, respectively, with their sources coupled together; a 33rd MOSFET and a 34th MOSFET connected in series between the source of the 23rd MOSFET and ground to provide tail current; a 25th MOSFET and a 26th MOSFET, both with their sources coupled to the input voltage terminal and their gates coupled to and receiving a bias voltage; a 27th MOSFET and a 28th MOSFET, with their sources coupled to the drains of the 25th MOSFET and the 26th MOSFET, respectively, with the drain of the 23rd MOSFET coupled to the drain of the 25th MOSFET and the drain of the 24th MOSFET coupled to the drain of the 26th MOSFET; a 29th MOSFET, a 30th MOSFET, a 31st MOSFET, and a 32nd MOSFET forming a common-source, common-gate current mirror; the drains of the 29th MOSFET and the 30th MOSFET are coupled to the drains of the 27th MOSFET and the 28th MOSFET, respectively; the gate of the 35th MOSFET is coupled to the drain of the 28th MOSFET, and the source of the 35th MOSFET is grounded.

3. The power management circuit as described in claim 1, characterized in that, The buffer circuit is a super source follower, comprising: A second MOSFET, a third MOSFET, and a fourth MOSFET; the gates of the second MOSFET, the third MOSFET, and the fourth MOSFET are respectively connected to a bias voltage; wherein, the second MOSFET serves as a current source, and the third MOSFET and the fourth MOSFET together serve as a common-source, common-gate current source; The fifth MOS transistor has its gate coupled to the amplification output terminal of the error amplifier, and its source coupled to the input voltage terminal through the second MOS transistor. The sixth MOS transistor has its gate coupled to the drain of the fifth MOS transistor and the drain of the third MOS transistor, its source grounded, and its drain coupled to the gate of the power transistor. The source of the third MOS transistor is coupled to the drain of the fourth MOS transistor, and the source of the fourth MOS transistor is grounded.

4. The power management circuit as described in claim 1, characterized in that, The feedforward circuit includes: First operational transconductance amplifier; The seventh MOS transistor has its source coupled to the input voltage terminal, and its gate and drain coupled to the inverting input terminal of the first operational transconductance amplifier. The eighth MOS transistor has its source coupled to the drain of the seventh MOS transistor and its gate coupled to the output of the first operational transconductance amplifier. A first resistor and a first capacitor are connected in series, and the non-inverting input of the first operational transconductance amplifier is coupled to the connection node of the first resistor and the first capacitor.

5. The power management circuit as described in claim 4, characterized in that, The feedforward circuit also includes: The ninth MOS transistor and the tenth MOS transistor are provided, with the source of the ninth MOS transistor and the source of the tenth MOS transistor both coupled to the input voltage terminal, and the drain of the ninth MOS transistor coupled to the gate of the power transistor; the gate and drain of the tenth MOS transistor are coupled together. The eleventh MOS transistor and the twelfth MOS transistor, wherein the gate and drain of the eleventh MOS transistor are coupled to the drain of the eighth MOS transistor; the drain of the twelfth MOS transistor is coupled to the drain of the tenth MOS transistor, wherein the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor and the twelfth MOS transistor are used to transmit the small signal current generated by the feedforward circuit to the gate of the power transistor.

6. The power management circuit as described in claim 1, characterized in that, The substrate voltage generating circuit includes: The first and second replica power transistors have a channel width-to-length ratio proportional to the channel width-to-length ratio of the power transistor, and their sources are both coupled to the input voltage terminal. The second and third resistors are connected in series between the input voltage terminal and the drain of the second replica power transistor; The second operational transconductance amplifier has a non-inverting input terminal coupled to the connection node of the second resistor and the third resistor, an inverting input terminal coupled to the reference voltage, and an output terminal that generates a substrate voltage and is coupled to the substrate terminal of the second replica power transistor and the substrate terminal of the power transistor. The third operational transconductance amplifier has its non-inverting input coupled to the drain of the first replica power transistor, its inverting input coupled to the reference voltage, and its output coupled to the gates of the thirteenth and fourteenth MOS transistors. The drain of the thirteenth MOS transistor is coupled to the drain of the second replica power transistor and the third resistor; the source of the thirteenth MOS transistor and the source of the fourteenth MOS transistor are both grounded; the drain of the fourteenth MOS transistor is coupled to the drain of the first replica power transistor. The fifteenth MOS transistor has its gate and drain coupled to the substrate of the first replica power transistor, and its source coupled to the input voltage terminal.

7. The power management circuit as described in claim 1, characterized in that, Also includes: The transient enhancement circuit has its input terminal coupled to the output terminal of the circuit, and its output terminal coupled to the gate of the power transistor. The transient enhancement circuit includes a capacitive coupling unit and a current injection unit. The capacitive coupling unit detects transient voltage changes at the output of the circuit through capacitive coupling. The current injection unit is used to inject transient current into the gate of the power transistor in response to transient changes.

8. The power management circuit as described in claim 7, characterized in that, The capacitive coupling unit includes: The second capacitor has its first end coupled to the output terminal of the circuit. The fourth resistor has its first end coupled to the second end of the second capacitor; The sixteenth MOS transistor has its gate coupled to the second terminal of the second capacitor and the first terminal of the fourth resistor, its source grounded, and its drain coupled to the drain of the eighteenth MOS transistor. The seventeenth MOSFET has its gate coupled to the second terminal of the fourth resistor and its source grounded. The eighteenth and nineteenth MOS transistors form a current mirror, with the drain of the nineteenth MOS transistor coupled to the gate of the power transistor. The twentieth MOSFET has its drain coupled to the input voltage terminal and its source coupled to the drain of the seventeenth MOSFET. The current injection unit includes: The eighteenth and nineteenth MOS transistors form a current mirror, with the drain of the nineteenth MOS transistor coupled to the gate of the power transistor.

9. The power management circuit as described in claim 1, characterized in that, Also includes: The bias circuit includes a current source, a fifth resistor, a twenty-first MOSFET, and a twenty-second MOSFET connected in series between the input voltage terminal and ground; The gate output of the 21st MOS transistor is the first bias voltage; The gate of the twelfth MOS transistor outputs a second bias voltage and is coupled to the drain of the eleventh MOS transistor, and the drain of the twelfth MOS transistor is coupled to the source of the eleventh MOS transistor. The first bias voltage and the second bias voltage are respectively coupled to the error amplifier, the transient enhancement circuit, the flip voltage follower output stage circuit and the power supply rejection ratio enhancement circuit to provide bias voltage.

10. An electronic device, characterized in that, The power management circuit includes any one of claims 1 to 9.

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