Reverse design method of LED chip surface gray scale micro-nano structure

Abstract

The invention discloses a reverse design method of an LED chip surface gray scale micro-nano structure, and relates to the technical field of LED chip manufacturing. By constructing a quantitative mapping relation model based on a machine learning algorithm, the corresponding relation between key parameters such as gray scale level and structure height and target performance such as light extraction efficiency and light distribution angle is defined, a scientific quantitative basis is provided for design, and blind trial and error of traditional design is abandoned; by defining a design target and constraint and reversely solving core logic of parameters based on a quantitative model, repeated parameter adjustment and processing verification are not needed, the defect of multiple iterations of traditional design is avoided, and the design efficiency is remarkably improved; through simulation verification and iterative optimization, an optimal parameter combination can be screened before actual processing, the number of trial and error times of entity processing is reduced, constraints such as multiple chip substrates and light emitting wavelengths are covered, the model is compatible with multiple micro-nano structure parameters, the design scheme can adapt to different types of LED chips, a design system does not need to be repeatedly built, and the adaptation cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of LED chip manufacturing technology, and in particular to a reverse design method for grayscale micro / nano structures on the surface of LED chips. Background Technology

[0002] The light extraction efficiency, light distribution characteristics, brightness consistency, and heat dissipation performance of LED chips are the core indicators that determine their application effects and market competitiveness, and the design and fabrication of the micro-nano structure on the chip surface directly affect the above key performances.

[0003] Currently, the design of micro / nano structures on LED chip surfaces generally adopts the traditional "trial and error" approach. The design process heavily relies on engineers' subjective experience, involving repeated adjustments to parameters such as the height, period, and density of the micro / nano structure, followed by multiple processing and verification steps to match expected performance. This lack of a quantitative correlation between micro / nano structure parameters and core LED performance results in a somewhat blind approach to each trial and error, leading to lengthy R&D cycles (typically exceeding two months) and high costs. For example, achieving a 30% improvement in light extraction efficiency often requires more than 10 processing iterations, resulting in a development cycle of over two months and significantly increasing both R&D and time costs. Furthermore, it is difficult to achieve synergistic optimization of multiple performance indicators. For instance, increasing structural density to pursue a wider light distribution angle often sacrifices effective heat dissipation area, leading to decreased chip reliability. Simultaneously, the design schemes lack versatility. Structural parameters optimized for a specific wavelength (such as blue light) are difficult to directly apply to LEDs of other wavelengths (such as green or red light). Each change in application scenario necessitates repeating the entire trial and error process, resulting in extremely low adaptation efficiency. Summary of the Invention

[0004] This invention provides a reverse design method for grayscale micro / nano structures on the surface of LED chips, which can solve the problem that the existing technology has not established a quantitative correlation between micro / nano structure parameters and LED core performance, resulting in blind trial and error, long R&D cycle and high cost.

[0005] A reverse design method for grayscale micro / nano structures on the surface of an LED chip includes the following steps: S1, determining target performance parameters and process constraints, wherein the target performance parameters include at least one of light extraction efficiency (η), light distribution angle (θ), brightness uniformity (ΔL), and heat dissipation efficiency (λ), and the constraints include LED chip substrate type, center emission wavelength (λ0), chip size (D), and laser processing precision; S2, establishing a quantitative mapping relationship model between grayscale micro / nano structure parameters and the target performance parameters, wherein the grayscale micro / nano structure parameters include at least one of grayscale level (G), structure height (h), structure density (ρ), or structure period (Λ), and the model is trained on a sample dataset using a machine learning algorithm; S3, using the target performance parameters as input, and based on the quantitative mapping model, using an optimization algorithm to solve for the optimal combination of grayscale micro / nano structure parameters that satisfies the constraints; S4, performing simulation verification on the solved grayscale micro / nano structure parameter combination, and if the deviation between the simulation results and the target performance parameters exceeds a predetermined threshold, performing iterative optimization, and finally outputting a design file that can be directly imported into a laser direct-etching device.

[0006] The present invention provides a reverse design method for grayscale micro / nano structures on the surface of LED chips, which, compared with the prior art, has the following beneficial effects, but is not limited to: This reverse design method for grayscale micro / nano structures on LED chip surfaces clarifies the correspondence between key parameters such as grayscale levels and structural height and target performance parameters such as light extraction efficiency and light distribution angle by constructing a quantitative mapping relationship model based on machine learning algorithms. This provides a scientific quantitative basis for design and avoids the blind trial and error of traditional design. By clarifying design goals and constraints and solving parameters in reverse based on the quantitative model, the core logic avoids the drawbacks of repeated parameter adjustments and processing verification, thus significantly improving design efficiency. Through simulation verification and iterative optimization, the optimal parameter combination can be screened before actual processing, reducing the number of trial and error attempts in physical processing. It covers constraints such as various chip substrates and emission wavelengths, and the model is compatible with various micro / nano structure parameters, enabling the design scheme to be adapted to different types of LED chips without the need to repeatedly build the design system, reducing adaptation costs.

[0007] Furthermore, in step S1, the LED chip substrate type is GaN-based or SiC-based, the central emission wavelength (λ0) ranges from 430nm to 660nm, and the chip size (D) ranges from 1μm to 1000μm.

[0008] Furthermore, in step S2, the number of samples in the sample dataset is no less than 1000 sets, and each set of data contains a set of grayscale micro / nano structure parameters and their corresponding LED performance parameters obtained through simulation or actual measurement.

[0009] Further, in step S2, the machine learning algorithm is a gradient boosting tree algorithm, and the quantization mapping model includes at least one of the following quantization relationships: The relationship between light extraction efficiency and the actual light extraction efficiency is: η = k1·ln(h) + k2·(Λ / λ0) + c1, where h is the structural height, Λ is the grating period, and k1, k2, and c1 are model coefficients. The relationship of the light distribution angle is: θ = k3·(ρ_max / ρ_min) + k4·√h + c2, where ρ_max / ρ_min is the ratio of the maximum to the minimum density of the microstructure lattice, and k3, k4, and c2 are model coefficients; Heat dissipation efficiency relationship: λ=k5·(S / S0)+c3, where S / S0 is the ratio of the surface area with microstructure to the original plane area, and k5 and c3 are model coefficients.

[0010] Furthermore, in the light extraction efficiency relationship, the structural height h ranges from 0.5μm to 3μm, and the grating period Λ ranges from 200nm to 1000nm.

[0011] Furthermore, in step S3, the optimization algorithm is a particle swarm optimization algorithm, and the optimization objective of the inverse solution is to ensure that the deviation between the model prediction performance and the target performance parameters is no more than 5%.

[0012] Furthermore, in step S3, the key structural size gradient ΔP corresponding to adjacent gray levels in the optimal gray-scale micro / nanostructure parameter combination obtained by the solution is... Within the range of 0.01μm-0.1μm.

[0013] Furthermore, in step S4, the simulation verification adopts at least one of FDTD optical simulation and ANSYS thermal simulation. If the performance deviation obtained from the simulation verification is >5%, then the weight coefficient of the quantization mapping model is adjusted and step S3 is repeated until the performance deviation is ≤5%.

[0014] Furthermore, in step S4, the design file is a control file format that can be directly imported into laser direct writing or laser interference lithography equipment.

[0015] Furthermore, in step S3, the grayscale micro / nano structure parameter combination obtained by solving has a grayscale level ≥ 256 levels. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a reverse design method for grayscale micro / nano structures on the surface of an LED chip, according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings showing multiple embodiments according to this application. It should be understood that the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without creative effort will fall within the scope of protection of this application.

[0018] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing specific embodiments only and is not intended to limit this application; the terms "comprising," "including," "having," "containing," etc., in the description, claims, and accompanying drawings of this application are open-ended terms. Therefore, "comprising," "including," or "having" refers to, for example, a method or apparatus having one or more steps or elements, but is not limited to having only these one or more elements. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0019] In the description of this invention, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0020] like Figure 1As shown in the figure, the reverse design method for grayscale micro / nano structures on the surface of an LED chip provided by this invention includes the following steps: S1, determining the target performance parameters and process constraints. The target performance parameters include at least one of light extraction efficiency (η), light distribution angle (θ), brightness uniformity (ΔL), and heat dissipation efficiency (λ). The constraints include the LED chip substrate type, center emission wavelength (λ0), chip size (D), and laser processing accuracy; S2, establishing a quantitative mapping relationship model between grayscale micro / nano structure parameters and target performance parameters. The grayscale micro / nano structure parameters include at least one of grayscale level (G), structure height (h), structure density (ρ), or structure period (Λ). The model is trained on a sample dataset based on a machine learning algorithm; S3, using the target performance parameters as input, and based on the quantitative mapping model, solving the optimal combination of grayscale micro / nano structure parameters that satisfies the constraints through an optimization algorithm; S4, performing simulation verification on the solved grayscale micro / nano structure parameter combination. If the deviation between the simulation result and the target performance parameters exceeds a predetermined threshold, iterative optimization is performed, and the final output is a design file that can be directly imported into a laser direct-etching device.

[0021] In this embodiment, by constructing a quantization mapping model based on machine learning algorithms, the correspondence between key parameters such as grayscale levels and structural height and target performance such as light extraction efficiency and light distribution angle is clarified, providing a scientific quantitative basis for design and eliminating the blind trial and error of traditional design. By clarifying design goals and constraints and solving parameters in reverse based on the quantization model, the core logic avoids the drawbacks of repeated parameter adjustments and processing verification, thus significantly improving design efficiency. Through simulation verification and iterative optimization, the optimal parameter combination can be screened before actual processing, reducing the number of trials and errors in physical processing. It covers constraints such as various chip substrates and emission wavelengths, and the model is compatible with various micro-nano structure parameters, enabling the design scheme to be adapted to different types of LED chips without the need to repeatedly build the design system, reducing adaptation costs. By solving the optimal parameter combination through optimization algorithms, it ensures that the parameters meet the constraints, and the output is a design file that can be directly imported into laser direct-etching equipment, achieving seamless connection between design and processing, and ensuring that the performance of the final product accurately matches the target requirements.

[0022] The design file is a control file format that can be directly imported into laser direct writing or laser interference lithography equipment. The grayscale micro-nano structure parameter combination obtained by solving has a grayscale level ≥ 256 levels.

[0023] In step S1, the LED chip substrate type is GaN-based or SiC-based, the center emission wavelength (λ0) ranges from 430nm to 660nm, and the chip size (D) ranges from 1μm to 1000μm.

[0024] In this embodiment, the accuracy of the model's physical foundation is ensured by explicitly defining the substrate type. Modeling is performed for the different optical and thermal properties of GaN and SiC, two mainstream wide-bandgap semiconductor materials, ensuring the predictive reliability of the quantization mapping model within this material system. Full wavelength range coverage directly addresses the issue of technical universality, incorporating the entire visible LED band from blue (~460nm) to red (~660nm) into the design system. This allows the same method to be adapted to different color chips without adjustment, fundamentally avoiding the cost of repeatedly building design systems for different wavelengths. Defining chip sizes across orders of magnitude enables seamless expansion of the design scale, covering the scale range from miniaturized Micro-LEDs (1μm level) to conventional power LEDs (1000μm level), ensuring the feasibility of optimizing micro / nano structure parameters under different light-emitting areas and process precision requirements. The combination of these three aspects provides accurate and complete physical boundaries for subsequent model training and parameter solving, significantly reducing redundant investment in multi-product line development.

[0025] In step S2, the number of samples in the sample dataset is no less than 1000 sets, and each set of data contains a set of gray-scale micro / nano structure parameters and their corresponding LED performance parameters obtained through simulation or actual measurement.

[0026] In this embodiment, the sufficiency and generalization ability of the model training are ensured by using a massive number of samples. No less than 1,000 sets of data cover a wide range of combinations of key parameters such as gray level, height, density, and period in multi-dimensional space, enabling the trained model to accurately capture the complex nonlinear relationship between structural parameters and optical and thermal properties, avoiding overfitting or prediction distortion caused by small samples. The dual reliability of the model is ensured by fusing simulation or measured dual-source data. Simulation data can efficiently generate a large number of training samples under ideal conditions, while measured data introduces actual process fluctuations and material properties. The combination of the two makes the model both rigorous.

[0027] In step S2, the machine learning algorithm is the gradient boosting tree algorithm, and the quantization mapping model includes at least one of the following quantization relationships: light extraction efficiency relationship: η=k1·ln(h)+k2·(Λ / λ0)+c1, where h is the structure height, Λ is the grating period, and k1, k2, and c1 are model coefficients; light distribution angle relationship: θ=k3·(ρ_max / ρ_min)+k4·√h+c2, where ρ_max / ρ_min is the ratio of the maximum to the minimum density of the microstructure lattice, and k3, k4, and c2 are model coefficients; heat dissipation efficiency relationship: λ=k5·(S / S0)+c3, where S / S0 is the ratio of the surface area with microstructure to the original plane area, and k5 and c3 are model coefficients.

[0028] In this embodiment, the gradient boosting tree algorithm can efficiently process sample data of multiple types, which may have complex nonlinear relationships, as defined in step S1, and automatically capture and integrate the prediction results of a large number of weak learners. The quantization relationship model deeply integrates physical insights and data-driven approaches. The mathematical expressions for light extraction efficiency, light distribution angle, and heat dissipation efficiency proposed are not pure black-box fittings, but semi-empirical frameworks built on the principles of optical and thermal physics. This makes the model have both excellent interpretability and extrapolation capabilities. The three quantization relationships can be used independently or in combination, directly supporting the collaborative modeling and optimization of single-objective or multi-objective performance in step S1. This provides accurate and efficient mathematical tools for on-demand design, replacing parameter tuning that relies on manual experience.

[0029] Specifically, firstly, based on the fundamental physical principles of optics and thermodynamics (such as diffraction theory and heat conduction equations), a mathematical framework for the formulas (such as logarithmic relationships and linear proportional relationships) is pre-defined. Then, through high-fidelity simulations (FDTD, ANSYS) and precise experiments, within a pre-defined feasible technological range (such as a height of 0.5-3 μm), a batch of paired samples (≥1000 sets) of structural parameters and performance data covering multi-dimensional parameter combinations are generated. Finally, machine learning algorithms such as gradient boosting trees are used to perform regression training on the sample set, automatically optimizing and fitting specific coefficients (such as 1.0, 20, 0.6) that minimize prediction errors. Simultaneously, cross-validation ensures that the model's prediction accuracy within a defined range is ≥95%, resulting in the following quantized mapping model: The relationship between light extraction efficiency and the given equation is: η = 1.0·ln(h) + 20·(Λ / λ0) + 0.6; Light distribution angle relationship: θ = 25·(ρ_max / ρ_min) + 12·√h; Heat dissipation efficiency relationship: λ=0.4·(S / S0)+0.6.

[0030] Specifically, when the target performance is: θ=30° (narrow angle high beam), η≥85%, and the constraint is: GaN-based blue LED (λ0=460nm), size D=500μm.

[0031] According to the quantization model: θ = 25 × (ρ_max / ρ_min) + 12 × √h, η = 1.0 × ln(h) + 20 × (Λ / 460) + 0.6; Inverse solution: ρ_max / ρ_min=1.2, h=2μm, Λ=500nm, G=512 levels, ΔP=0.008μm; Simulation: θ=31.2°, η=86.8%, deviation ≤4%, output "dot matrix + grating composite structure" design file; Processing verification: The measured θ=30.8° and η=86.2%, which meets the requirements of vehicle high beam.

[0032] In the relationship between light extraction efficiency and structural height h, the value ranges from 0.5μm to 3μm, and the value range of grating period Λ is from 200nm to 1000nm.

[0033] In step S3, the optimization algorithm is particle swarm optimization, and the optimization objective of the inverse solution is to make the deviation between the model prediction performance and the target performance parameters no greater than 5%.

[0034] In this embodiment, the swarm intelligence and parallel search characteristics of the particle swarm optimization algorithm are particularly suitable for processing the high-dimensional, nonlinear solution space constructed in step S2, which consists of multiple variables such as height, period, and density. It can efficiently explore massive combinations of gray-scale micro / nano structure parameters, avoiding the problem of traditional gradient-based algorithms easily getting trapped in local optima. By taking the explicit indicator of "the deviation between the model's predicted performance and the target performance parameters is no more than 5%" as the optimization objective, the algorithm's search process has a clear convergence direction. It can automatically and directionally screen and approximate parameter solutions that meet specific performance requirements such as light extraction efficiency and light distribution angle, directly replacing the parameter debugging process that relies on repeated trial and error based on human experience. This algorithm framework forms a closed loop with the simulation verification in the subsequent step S4, ensuring that the theoretical performance of the final output design file is highly consistent with the target.

[0035] In step S3, the key structural size gradient ΔP corresponding to adjacent gray levels in the optimal gray-scale micro / nanostructure parameter combination obtained by the solution is calculated. Within the range of 0.01μm-0.1μm.

[0036] In this embodiment, the gradient design with nanometer-level precision (10nm-100nm) enables the grayscale distribution of up to 256 levels or more obtained from step S3 to form a nearly continuous optical phase modulation layer on the chip surface. This effectively avoids diffraction efficiency loss or stray light caused by structural abrupt changes, and is the core physical guarantee for achieving high brightness consistency (ΔL≤±2%) and precise light distribution angle (θ). This gradient range directly corresponds to the typical resolution and positioning accuracy of current high-end laser direct writing or interference lithography equipment, enabling the optimal parameter combination obtained from reverse design to be fabricated with high fidelity. This range avoids the extreme requirements of excessively small gradients (e.g., <0.01μm) on equipment stability and production costs, and also prevents the problems of insufficient grayscale levels and coarse optical control caused by excessively large gradients (e.g., >0.1μm).

[0037] In step S4, the simulation verification uses at least one of FDTD optical simulation and ANSYS thermal simulation. If the performance deviation obtained from the simulation verification is >5%, then the weight coefficients of the quantization mapping model are adjusted and step S3 is repeated until the performance deviation is ≤5%.

[0038] In this embodiment, the FDTD method is used to rigorously solve Maxwell's equations to verify optical performance such as light extraction efficiency and light distribution angle. Simultaneously, ANSYS is used for finite element thermal analysis to verify heat dissipation efficiency. This constitutes a rigorous physical verification of the multi-objective performance defined in step S1, replacing the one-sided and indirect performance evaluation method in traditional trial-and-error methods. The "5% deviation threshold" establishes a precise quantitative control standard. This clear numerical criterion provides an objective and rapid decision-making basis for judging whether the design is qualified, transforming the design process from subjective experience-based judgment to objective data-driven. When the simulation detects a deviation, it does not simply restart, but feeds back to the quantitative mapping model in step S2. By adjusting its weight coefficients (such as k1, k2...), the model prediction is corrected, and the intelligent optimization in step S3 is triggered again. This iterative process allows the model to continuously self-calibrate and improve in application until it outputs a mature design scheme that theoretically (in simulation) can ensure a performance deviation of ≤5%, thereby increasing the design verification success rate before final processing to over 95%. This solves the problem of uncontrolled cycle and cost caused by repeated "processing-testing" in traditional processes.

[0039] The above-disclosed embodiments are merely a few specific examples of the present invention. However, the embodiments of the present invention are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A reverse design method for grayscale micro / nano structures on the surface of an LED chip, characterized in that, Includes the following steps: S1. Determine the target performance parameters and process constraints. The target performance parameters include at least one of light extraction efficiency (η), light distribution angle (θ), brightness uniformity (ΔL), and heat dissipation efficiency (λ). The constraints include LED chip substrate type, center emission wavelength (λ0), chip size (D), and laser processing accuracy. S2. Establish a quantitative mapping relationship model between gray-scale micro / nano structure parameters and the target performance parameters. The gray-scale micro / nano structure parameters include at least one of gray-scale level (G), structure height (h), structure density (ρ), or structure period (Λ). The model is trained on a sample dataset based on a machine learning algorithm. S3. Using the target performance parameters as input, and based on the quantization mapping model, the optimal combination of gray-scale micro / nano structure parameters that satisfies the constraints is solved in reverse using an optimization algorithm. S4. Perform simulation verification on the combination of gray-scale micro / nano structure parameters obtained by the solution. If the deviation between the simulation results and the target performance parameters exceeds the predetermined threshold, perform iterative optimization. The final output can be directly imported into the design file of the laser direct-printing equipment.

2. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S1, the LED chip substrate type is GaN-based or SiC-based, the central emission wavelength (λ0) ranges from 430nm to 660nm, and the chip size (D) ranges from 1μm to 1000μm.

3. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S2, the number of samples in the sample dataset is no less than 1000 sets, and each set of data contains a set of gray-scale micro / nano structure parameters and their corresponding LED performance parameters obtained through simulation or actual measurement.

4. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S2, the machine learning algorithm is a gradient boosting tree algorithm, and the quantization mapping model includes at least one of the following quantization relationships: The relationship between light extraction efficiency and the actual light extraction efficiency is: η = k1·ln(h) + k2·(Λ / λ0) + c1, where h is the structural height, Λ is the grating period, and k1, k2, and c1 are model coefficients. The relationship of the light distribution angle is: θ = k3·(ρ_max / ρ_min) + k4·√h + c2, where ρ_max / ρ_min is the ratio of the maximum to the minimum density of the microstructure lattice, and k3, k4, and c2 are model coefficients; Heat dissipation efficiency relationship: λ=k5·(S / S0)+c3, where S / S0 is the ratio of the surface area with microstructure to the original plane area, and k5 and c3 are model coefficients.

5. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 4, characterized in that, In the light extraction efficiency relationship, the structural height h ranges from 0.5μm to 3μm, and the grating period Λ ranges from 200nm to 1000nm.

6. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S3, the optimization algorithm is a particle swarm optimization algorithm, and the optimization objective of the inverse solution is to make the deviation between the model prediction performance and the target performance parameters no greater than 5%.

7. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S3, the key structural size gradient ΔP corresponding to adjacent gray levels in the optimal gray-scale micro / nanostructure parameter combination obtained by the solution is calculated. Within the range of 0.01μm-0.1μm.

8. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S4, the simulation verification adopts at least one of FDTD optical simulation and ANSYS thermal simulation. If the performance deviation obtained from the simulation verification is >5%, then the weight coefficient of the quantization mapping model is adjusted and step S3 is repeated until the performance deviation is ≤5%.

9. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S4, the design file is a control file format that can be directly imported into laser direct writing or laser interference lithography equipment.

10. The reverse design method for grayscale micro / nano structures on the surface of an LED chip as described in claim 1, characterized in that, In step S3, the grayscale micro / nano structure parameter combination obtained by solving has a grayscale level ≥ 256 levels.

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