Capacitance calculation method, electronic equipment and storage medium

Abstract

The invention relates to a capacitance calculation method, which comprises the following steps: constructing a capacitance model matched with a target structure, obtaining a first structure parameter corresponding to the capacitance model in the target structure, and calculating a first capacitance according to the first structure parameter and the capacitance model; calculating the capacitance change rate of the target structure according to a capacitance change rate model matched with the target structure; and correcting the first capacitance according to the capacitance change rate, and determining a second capacitance of the target structure. According to the method, the first capacitance is corrected through the capacitance change rate, the second capacitance of the target structure is determined, the influence of the micro load effect and other process effects on the capacitance can be reflected more accurately, and therefore the calculation precision is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a capacitance calculation method, a capacitance acquisition method, an electronic device, and a storage medium. Background Technology

[0002] Interconnect parasitic effects refer to the non-ideal electrical behavior in integrated circuits caused by the physical characteristics of the metal lines and their surrounding environment. With the development of manufacturing technology, circuit size is constantly increasing and feature dimensions are constantly decreasing; modern advanced chips contain hundreds of millions of devices. Interconnect parasitic effects have become a major factor affecting circuit delay, surpassing the influence of the devices themselves. Therefore, accurately calculating interconnect capacitance is crucial for ensuring the correctness of circuit simulation and verification.

[0003] However, during chip manufacturing, due to process iterations, technological advancements, or limitations imposed by optical and chemical principles, discrepancies may arise between the design drawings and the actual manufactured chips. These discrepancies are known as process effects. Ideally, the manufactured chips should closely resemble the designed chips. Figure 1 While these process effects are generally consistent, discrepancies often exist in practice. Therefore, it is necessary to comprehensively consider these process effects during the design phase to ensure that the design meets functional requirements, thereby reducing the risk and losses from producing defective chips. Chip manufacturers provide standard process description documents to design companies, but accurately simulating these process effects and extracting parasitic capacitances remains a significant challenge. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a capacitance calculation method that can more accurately reflect the impact of process effects such as micro-load effects on capacitance, thereby improving calculation accuracy.

[0005] To address the aforementioned technical problems, this application provides a capacitance calculation method, comprising the following steps: determining a capacitance model that matches a target structure; obtaining first structural parameters in the target structure corresponding to the capacitance model; calculating a first capacitance based on the first structural parameters and the capacitance model; calculating the capacitance change rate of the target structure based on a capacitance change rate model that matches the target structure; correcting the first capacitance based on the capacitance change rate; and determining a second capacitance of the target structure.

[0006] In one embodiment, determining the capacitance model that matches the target structure includes: if the target structure only includes conductors located in different layers, then obtaining a first capacitance model; If the target structure includes conductors located in different layers and conductors located in the same layer, then a second capacitor model is obtained.

[0007] In one embodiment, calculating the capacitance change rate of the target structure based on a capacitance change rate model matching the target structure includes: obtaining the capacitance change rate model matching the target structure; obtaining a second structural parameter and an etching effect parameter in the target structure corresponding to the capacitance change rate model; and calculating the capacitance change rate of the target structure based on the capacitance change rate model, the second structural parameter, and the etching effect parameter.

[0008] In one embodiment, obtaining the capacitance change rate model matching the target structure includes: when the capacitance model matching the target structure is the first capacitance model, obtaining a first capacitance change rate model and / or a second capacitance change rate model; when the capacitance model matching the target structure is the second capacitance model, obtaining a third capacitance change rate model.

[0009] In one embodiment, the method further includes: establishing the first capacitance change rate model; wherein, establishing the first capacitance change rate model includes: obtaining a first model capacitance and a first influencing capacitance corresponding to the first capacitance model, the first model capacitance including model surface capacitance; and obtaining the first capacitance change rate model corresponding to the first capacitance model based on the first model capacitance and the first influencing capacitance.

[0010] In one embodiment, the method further includes: establishing a second capacitance rate of change model; establishing the second capacitance rate of change model includes: obtaining a second model capacitance and a second influencing capacitance corresponding to the first capacitance model, wherein the second model capacitance includes model surface capacitance and model sidewall capacitance; and obtaining a second capacitance rate of change model corresponding to the first capacitance model based on the second model capacitance and the second influencing capacitance.

[0011] In one embodiment, the first capacitor model includes a dominant body, and the model parameters of the first capacitor model include at least the width of the dominant body, the thickness of the dominant body, the distance of each dielectric layer between the dominant body and other conductors, and etching effect parameters.

[0012] In one embodiment, the method further includes: establishing the third capacitance change rate model; wherein establishing the third capacitance change rate model further includes: obtaining the capacitance influence function corresponding to the second capacitance model; wherein the second capacitance model includes a dominant conductor and an environmental conductor, and the model parameters of the second capacitance model include at least the width of the dominant conductor, the distance from the dominant conductor to the environmental conductor, and the minimum value from the dominant conductor to the environmental conductor, and the second model capacitance includes the capacitance between the dominant conductor and the environmental conductor; obtaining the first capacitance influence rate model and the second capacitance influence rate model; and determining the third capacitance change rate model corresponding to the second capacitance model based on the first capacitance influence rate model, the second capacitance influence rate model, and the capacitance influence function.

[0013] This application also provides an electronic device, which includes a memory and a processor, the processor being able to implement the above-described method when executing a computer program in the memory.

[0014] This application also provides a storage medium on which a computer program is stored, which, when executed by a processor, can implement the above-described method.

[0015] The capacitance calculation method of this application involves: determining a capacitance model that matches a target structure; obtaining first structural parameters in the target structure corresponding to the capacitance model; calculating a first capacitance based on the first structural parameters and the capacitance model; calculating the capacitance change rate of the target structure based on a capacitance change rate model that matches the target structure; correcting the first capacitance based on the capacitance change rate; and determining a second capacitance for the target structure. This method, by correcting the first capacitance based on the capacitance change rate and determining the second capacitance of the target structure, can more accurately reflect the influence of process effects such as micro-load effects on capacitance, thereby improving calculation accuracy. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the change in conductor bottom thickness caused by microscopic load effects in existing technologies.

[0017] Figure 2 This is a schematic flowchart illustrating the capacitance calculation method according to an embodiment of this application.

[0018] Figure 3 This is a schematic cross-sectional view of a first capacitor model according to an embodiment of this application.

[0019] Figure 4 This is a cross-sectional schematic diagram of a second capacitor model according to an embodiment of this application. Detailed Implementation

[0020] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0021] In the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the present application. It should be understood that other embodiments may also be used, and mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered limiting, and the scope of the embodiments of the present application is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present application.

[0022] Although the terms first, second, etc., are used in some instances to describe various elements herein, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0023] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are to be interpreted inclusively, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

[0024] Micro-loading effect is one of the most common process effects in semiconductor etching, resulting in significant changes in the parasitic capacitance of interconnects. Micro-loading effect refers to the decrease in etching rate or uneven distribution caused by localized consumption of etching gas exceeding supply during semiconductor manufacturing. Figure 1 This demonstrates the thickness change at the bottom of the conductor during chip etching. For example... Figure 1 As shown, the micro-loading effect causes the conductor bottom thickness to vary, etching out multiple trenches of different depths, which in turn causes the dielectric layer thickness between conductors in different layers of the chip to vary, thus causing the actual parasitic capacitance between conductors to deviate from the theoretical value.

[0025] To address the aforementioned problems, this application proposes a capacitance calculation method. For example... Figure 2As shown, this capacitance calculation method can be implemented using software and / or hardware, such as computing devices like computers and servers, and specifically includes the following steps: S1. Determine the capacitance model that matches the target structure; The target structure is the structure in the integrated circuit layout that requires parasitic capacitance calculation, generally describing the circuit composition within the integrated circuit. In one embodiment, the target structure includes conductors located on different metal layers, and at least one dielectric layer located between the different metal layers or between the conductors. In another embodiment, the target structure may include conductors located on different metal layers, conductors located on the same metal layer, and at least one dielectric layer located between the different metal layers. Specifically, the conductors in the target structure may be interconnects in the integrated circuit, which are conductive paths used to connect different components or circuit modules in the integrated circuit to transmit electrical signals and power. The dielectric layer refers to an insulating material layer located between interconnects or between an interconnect and a substrate.

[0026] The capacitance model is used to simulate the parasitic capacitance between the first and second conductors under microscopic load effects. The capacitance model includes at least the first and second conductors located in different metal layers to simulate the parasitic capacitance generated between conductors on different metal layers. Alternatively, the capacitance model may also include different conductors located in the same metal layer to simulate the parasitic capacitance generated between adjacent conductors on the same metal layer.

[0027] The capacitance model includes a first capacitance model and a second capacitance model. The positional relationships between the conductors differ between the first and second capacitance models. The first capacitance model includes a dominant conductor and other conductors located in different metal layers. The dominant conductor is the conductor whose capacitance is calculated between it and other conductors. Specifically, as one implementation method of this embodiment, such as... Figure 3 As shown, Figure 3 This is a cross-sectional schematic diagram of a first capacitor model according to an embodiment of this application. The first capacitor model includes only a first conductor M and a second conductor A located in different metal layers. In one embodiment, the second conductor A is located below the first conductor M, and the area of ​​the second conductor A is larger than the area of ​​the first conductor M, but this application is not limited thereto. The second capacitor model includes a dominant conductor, an environmental conductor, and other conductors located in different metal layers from the dominant conductor. The environmental conductor refers to other conductors in the same layer that have a capacitive effect on the dominant conductor. As one implementation of this embodiment, such as... Figure 4 As shown, the second capacitor model includes a third conductor M1 and a fourth conductor B located in different metal layers, and also includes a third conductor M1 and a fifth conductor M2 located in the same metal layer. The third conductor M1 can be the main conductor, and the fifth conductor M2 can be the environmental conductor.

[0028] In one embodiment, determining a capacitance model that matches the target structure includes: if the target structure only includes conductors located in different layers, then obtaining a first capacitance model that matches the target structure; if the target structure includes conductors located in different layers and conductors located in the same layer, then obtaining a second capacitance model that matches the target structure. This allows for the acquisition of a matching capacitance model based on the specific structure of the target structure, thereby enabling the calculation of the parasitic capacitance of the target structure and further improving the accuracy of the calculation.

[0029] S2. Obtain the first structural parameters in the target structure that correspond to the capacitor model, and calculate the first capacitance based on the first structural parameters and the capacitor model; The first structural parameter is used to indicate the structural information of the target structure. Specifically, the first structural parameter may include at least one of the following: dimensional information parameters of each conductor and / or dielectric layer in the target structure, relative position parameters between each conductor and dielectric layer, and the type of dielectric layer. In one embodiment, such as... Figure 3 and Figure 4 As shown, the first structural parameter may include at least one of the following: the width of the conductor corresponding to the width w of the first conductor M in the first capacitor model; the thickness of the conductor corresponding to the thickness t of the first conductor M; and the distance between the conductors corresponding to the distance d between the first conductor M and the second conductor A in the first capacitor model. The first structural parameter may also include the width w' of the third conductor M1, the distance s between the third conductor M1 and the fifth conductor M2, etc. Wherein, as... Figure 3 In the cross-sectional view shown, the horizontal direction is the width direction and the vertical direction is the thickness direction. The width of the conductor is the length of the conductor in the width direction, and the thickness of the conductor is the length of the conductor in the height direction.

[0030] Specifically, in one embodiment, the first capacitance of the target structure can be solved using, but is not limited to, a 2.5D capacitance extraction method. In the 2.5D capacitance extraction method, a standard cell library containing various conductor geometry configurations with different capacitance models is first established. The parasitic capacitance of each cell is obtained through algorithmic calculation, simulation, or experimental measurement. Then, in the actual circuit layout, the conductor structure is decomposed into several basic cells and matched with cells in the standard cell library. By searching and matching the structural parameters of these basic cells, the parasitic capacitance value of the entire circuit layout can be quickly estimated.

[0031] S3. Calculate the capacitance change rate of the target structure based on the capacitance change rate model that matches the target structure; The capacitance change rate model is used to indicate the impact of process effects (such as micro-loading effects) on the capacitance between conductors, and represents the relationship between the second structural parameter and / or process effect parameter of the target structure and the capacitance change rate. The second structural parameter indicates the structural information of the target structure. The second structural parameter can be obtained from the process documentation and may be partially the same as, partially different from, completely identical to, or completely different from the first structural parameter. Specifically, the second structural parameter may include at least one of the following: the size information parameters of each conductor and / or dielectric layer in the target structure, the relative position parameters between each conductor and the dielectric layer, and the type of the dielectric layer. The process effect parameter indicates the impact of the process on the target structure. The process effect parameter may include etching effect parameters. The etching effect parameter is the amount of thickness change of the dielectric layer adjacent to the dominant conductor in the target structure, i.e., the amount of change in the actual thickness of the dielectric layer adjacent to the dominant conductor relative to the standard thickness caused by the micro-loading effect. The value of the etching effect thickness can be obtained, but is not limited to, from the process documentation, and is specifically provided by the user of the parasitic parameter tool or the wafer fabrication plant. Its magnitude is related to the width of the corresponding conductor and the spacing between conductors. In this context, standard thickness refers to the ideal or reference thickness selected during integrated circuit design and manufacturing to ensure optimal performance and reliability, based on specific process nodes, design rules, and technical requirements. It represents the ideal thickness without the influence of process effects. Since micro-load effects primarily affect the thickness of the dielectric layer adjacent to the conductor, a simplified capacitance model considers only the variation in this dielectric layer thickness, thus enabling more accurate capacitance calculations and circuit design optimization. Specifically, etching effect thickness can be positive, negative, or zero. Specifically, if the dielectric layer thickness is greater than the reference thickness, the etching effect thickness is positive; if the dielectric layer thickness is less than the reference thickness, the etching effect thickness is negative; and if the dielectric layer thickness is equal to the reference thickness, the etching effect thickness is zero.

[0032] The capacitance change rate model can be a pre-built model stored in association with the capacitance model. The capacitance change rate model can include at least one of a first capacitance change rate model, a second capacitance change rate model, and a third capacitance change rate model. Specifically, the first capacitance change rate model and / or the second capacitance change rate model can be stored in association with the first capacitance model, and the third capacitance change rate model can be stored in association with the second capacitance model. The first capacitance change rate model can be used to represent the relationship between the second structural parameters and / or process effect parameters of the target structure matched with the first capacitance model and the capacitance change rate of the areal capacitance. The second capacitance change rate model can be used to represent the relationship between the second structural parameters and / or process effect parameters of the target structure matched with the first capacitance model and the capacitance change rate of the coupling capacitor. The third capacitance change rate model can be used to represent the relationship between the second structural parameters and / or process effect parameters of the target structure matched with the second capacitance model and the capacitance change rate of the areal capacitance. The coupling capacitor refers to the capacitance generated due to the electric field interaction between adjacent conductors, and the coupling capacitor includes areal capacitance and sidewall capacitance. For example, Figure 3 As shown, surface capacitance is the capacitance where the electric field lines formed by the first conductor M and the second conductor A are perpendicular to the second conductor A, while sidewall capacitance is the capacitance where the electric field lines formed by the first conductor M and the second conductor A are not perpendicular to the first conductor M and the second conductor A.

[0033] In one embodiment, S3. Calculating the capacitance change rate of the target structure based on a capacitance change rate model matching the target structure includes: obtaining a capacitance change rate model matching the target structure. Specifically, in one embodiment, when the capacitance model matching the target structure is the first capacitance model, a first capacitance change rate model and / or a second capacitance change rate model are obtained. When the capacitance model matching the target structure is the second capacitance model, a third capacitance change rate model is obtained. In one embodiment, S3. Calculating the capacitance change rate of the target structure according to the capacitance change rate model matching the target structure further includes: obtaining a second structural parameter and an etching effect parameter in the target structure corresponding to the capacitance change rate model; and calculating the capacitance change rate of the target structure based on the capacitance change rate model, the second structural parameter, and the etching effect parameter. The etching effect parameter is the amount of change in structural parameters caused by process effects, such as the amount of change in the thickness of the dielectric layer caused by micro-loading effects.

[0034] S4. Correct the first capacitor according to the capacitance change rate, and determine the second capacitor of the target structure.

[0035] In this method, the second capacitor is obtained by adjusting the first capacitor using the capacitance change rate of the target structure. Since the capacitance change rate reflects process effects, such as the influence of micro-load effects on parasitic capacitance, the calculated second capacitor is more accurate and closely matches the actual condition of the integrated circuit layout. Specifically, the second capacitor can be obtained by multiplying the first capacitor by the capacitance change rate, or by obtaining the corresponding adjustment level based on the capacitance change rate level, and then adjusting the first capacitor up or down based on the adjustment level to obtain the second capacitor.

[0036] In this embodiment, the first capacitor is corrected based on the capacitance change rate matching the target structure, and the second capacitor of the target structure is determined. This can more accurately reflect the influence of micro-load effects on the capacitor, thereby improving the calculation accuracy.

[0037] In one embodiment, the method further includes: establishing a first capacitance change rate model; wherein establishing the first capacitance change rate model includes: obtaining a first model capacitance and a first influencing capacitance corresponding to the first capacitance model, the first model capacitance including a model surface capacitance; and obtaining the first capacitance change rate model corresponding to the first capacitance model based on the first model capacitance and the first influencing capacitance. The first model capacitance is used to represent the relationship between the surface capacitance corresponding to the first capacitance model and the model parameters of the first capacitance model under ideal conditions (i.e., without the influence of micro-load effects). The first influencing capacitance is used to represent the relationship between the surface capacitance corresponding to the first capacitance model and the model parameters of the first capacitance model under the influence of micro-load process effects. Figure 3 As shown, the model parameters of the first capacitor model include at least one of the following: the width w of the dominant conductor M (i.e., the first conductor M), the thickness t of the dominant conductor, the thickness of each dielectric layer between the first conductor M and other conductors (i.e., the second conductor A), and etching effect parameters. The first model capacitance and / or the first influencing capacitance can be represented by the model parameters of the first capacitor model, specifically by at least one of the following: the facing area S between the first conductor M (i.e., the dominant conductor) and the second conductor A, the number of dielectric layers between the first conductor M and the second conductor A, and the standard thickness. The first influencing capacitance can be represented by at least one of the following: the facing area S between the first conductor M and the second conductor A, the number of dielectric layers between the first conductor M and the second conductor A, and the actual thickness. Specifically, the first capacitance change rate model corresponding to the first capacitor model can be obtained by the ratio of the first model capacitance to the first influencing capacitance.

[0038] like Figure 3 As shown, in one embodiment of this invention, in the first capacitor model, the model surface capacitance between the first conductor M and the second conductor A can be approximated as the capacitance between two parallel plates. If there is a unique dielectric layer between the first conductor and the second conductor, the calculation formula for the model surface capacitance in the first model capacitor is as follows: (1) In the above formula, C area This represents the model surface capacitance in the first model capacitor. ε 0 represents the vacuum permittivity. ε d Represents the relative permittivity. S This represents the area of ​​the first conductor M and the second conductor A facing each other. d This represents the distance between the first conductor M and the second conductor A.

[0039] As one implementation of this embodiment, in the first capacitor model, the surface capacitance between the first conductor M and the second conductor A can be approximated as the capacitance between two parallel plates. If there are multiple dielectric layers between the first conductor and the second conductor, the calculation formula for the model surface capacitance in the first model capacitor can be obtained by connecting capacitors in series, as follows: (2) In the above formula, C area This represents the model surface capacitance in the first model capacitor. C n This represents the surface capacitance value of the nth dielectric layer.

[0040] Substituting formula (1) into formula (2), we can obtain the following formula: (3) In the above formula, C area This represents the model surface capacitance in the first model capacitor. ε 0 represents the vacuum permittivity. ε n Represents the relative permittivity of the nth dielectric layer. S This represents the area of ​​the first conductor M and the second conductor A facing each other. d n This represents the thickness of the nth dielectric layer.

[0041] Assume the etching effect parameter, i.e., the change in the thickness of the dielectric layer caused by the micro-loading effect, is... The formula for calculating the first-effect capacitance under the influence of micro-load effect is as follows: (4) Comparing formulas (3) and (4), we can obtain the formula for the first capacitance rate of change model corresponding to the first capacitance model as follows: (5) In one embodiment, the method further includes: establishing a second capacitance rate of change model; establishing the second capacitance rate of change model includes: obtaining a second model capacitance and a second influencing capacitance corresponding to the first capacitance model, the second model capacitance including model surface capacitance and model sidewall capacitance; obtaining the second capacitance rate of change model corresponding to the first capacitance model based on the second model capacitance and the second influencing capacitance. The second model capacitance represents the relationship between the coupling capacitance corresponding to the first capacitance model and the model parameters of the first capacitance model under ideal conditions (i.e., without the influence of micro-load effects). The second influencing capacitance represents the relationship between the coupling capacitance corresponding to the first capacitance model and the model parameters of the first capacitance model under the influence of micro-load process effects. Specifically, the second capacitance rate of change model corresponding to the first capacitance model can be obtained by the ratio of the second model capacitance and the second influencing capacitance. Figure 3 As shown, the width of the first conductor M in the first capacitor model can be... w The thickness of the first conductor M t And the distance between the first conductor M and the second conductor A under ideal conditions (i.e., without the influence of microscopic load effects). d As the independent variable, the capacitance of the second model is constructed. f(w,d,t) Specifically, this can be achieved by changing the width of the first conductor M. w The thickness of the first conductor M t and the distance between the first conductor M and the second conductor A d By taking values ​​of [value], multiple different capacitance values ​​are calculated. After recording the capacitance values ​​at different sizes to form a set of data points, mathematical fitting methods (such as least squares) are used to fit these data points to obtain the expression for the capacitance of the second model. f(w,d,t) Alternatively, the width of the first conductor M in the first capacitor model can be... w The thickness of the first conductor M t And the actual distance between the first conductor M and the second conductor A under the influence of micro-load effects. d+ As the independent variable, construct the second influencing capacitance. f(w, ,t) ,in, 。 The second capacitance rate of change model corresponding to the first capacitance model can be expressed by the following formula: (6) In one embodiment, the method further includes: establishing a third capacitance change rate model; wherein establishing the third capacitance change rate model includes: obtaining the capacitance influence function corresponding to the second capacitance model; wherein the second capacitance model includes a dominant conductor and an ambient conductor, and the model parameters of the second capacitance model include at least one of the width of the dominant conductor, the distance from the dominant conductor to the ambient conductor, and the minimum value from the dominant conductor to the ambient conductor; obtaining a first capacitance influence rate model and a second capacitance influence rate model; and determining the third capacitance change rate model corresponding to the second capacitance model based on the first capacitance influence rate model, the second capacitance influence rate model, and the capacitance influence function. The capacitance influence function is used to represent the influence of the ambient conductor on the dominant conductor and its relationship with the model parameters of the second capacitance model. The minimum value from the dominant conductor to the ambient conductor is determined by the limiting distance of the semiconductor process and can be set by the system default or by the user.

[0042] Please refer to Figure 4 The width of the dominant conductor, the third conductor M1, in the second capacitor model is... w’ The distance between the third conductor M1 and the environmental conductor, i.e., the fifth conductor M2. s As an independent variable, construct the function g(w',s) The width of the third conductor M1 w With the minimum value s min As an independent variable, construct the function g(w',s min ) The width of the third conductor M1 will also be... w Construct a function with positive infinity as the independent variable. g(w',+∞) This is to determine the capacitance effect function corresponding to the second capacitor model. Similarly, by changing the width of the third conductor M1... w’ and the distance between the third conductor M1 and the fifth conductor M2 s By taking the values ​​of , multiple different capacitance values ​​can be calculated. Recording the capacitance values ​​for different sizes forms a set of data points. Using mathematical fitting methods (such as least squares), these data points are fitted to obtain the function. g(w',s) Similarly, based on the above principles, the function can be obtained. g(w',s min ) sum function g (w’,+∞) Thus, the capacitance effect function can be determined.

[0043] When the distance between the third conductor M1 and the fifth conductor M2 in the same layer s When the capacitance is infinity, the capacitance values ​​from the dominant conductor (i.e., the first conductor M or the third conductor M1) to the lower flat conductor (i.e., the second conductor A or the fourth conductor B) in the first and second capacitance models can be considered approximately equal. In this case, the influence of the adjacent conductor in the same layer (i.e., the fifth conductor M2) on the dominant conductor can be ignored.

[0044] When the distance between the dominant conductor and the adjacent conductor in the same layer s Minimum value s set for semiconductor process min At this point, it can be approximated that the sidewall capacitance is less affected by adjacent conductors in the same layer, and the capacitance from the dominant conductor to the underlying flat conductor is mainly dominated by the surface capacitance. This is because when the distance between the dominant conductor and adjacent conductors in the same layer... s When the size is very small, the coupling effect between the dominant conductor and the adjacent conductor in the same layer becomes significant, but the main influence still comes from the surface capacitance between the dominant conductor and the underlying flat conductor.

[0045] Based on the above principles, the third capacitance change rate model can be determined according to the capacitance influence function, the first capacitance influence rate model, and the second capacitance influence rate model. The third capacitance change rate model can be expressed as follows:

[0046] in, The first capacitance change rate model corresponding to the second capacitance model can be constructed by referring to the first capacitance change rate model corresponding to the first capacitance model. When constructing, you only need to replace the first conductor in the first capacitance model with the third conductor and the second conductor in the first capacitance model with the third conductor. The second capacitance change rate model is the model corresponding to the second capacitance model. Its construction process can refer to the second capacitance change rate model corresponding to the first capacitance model, and will not be repeated here.

[0047] The capacitance calculation method of this application embodiment constructs a capacitance model that matches the target structure, obtains the first structural parameters in the target structure corresponding to the capacitance model, calculates the first capacitance based on the first structural parameters and the capacitance model, calculates the capacitance change rate of the target structure based on the capacitance change rate model that matches the target structure, corrects the first capacitance based on the capacitance change rate, and determines the second capacitance of the target structure. This application, by correcting the first capacitance based on the capacitance change rate and determining the second capacitance of the target structure, can more accurately reflect the influence of process effects such as micro-load effects on capacitance, thereby improving calculation accuracy.

[0048] This application also provides an electronic device, including a memory and a processor, wherein the processor is configured to implement the above-described method when executing a computer program in the memory.

[0049] Specifically, the processor may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0050] The memory may include a large-capacity storage device for data or instructions. For example, and not limitingly, the memory may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), flash memory, an optical disk drive, a magneto-optical disk drive, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory may include removable or non-removable (or fixed) media. Where appropriate, the memory may be internal or external to the fault image generation apparatus. In a particular embodiment, the memory is non-volatile memory. In a particular embodiment, the memory includes read-only memory (ROM) and random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), an electrically alterable read-only memory (EAROM), or flash memory, or a combination of two or more of these. Where appropriate, the RAM can be Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM). DRAM can be Fast Page Mode Dynamic Random-Access Memory (FPMDRAM), Extended Data Out Dynamic Random-Access Memory (EDODRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0051] Memory can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor.

[0052] The processor implements any of the methods described in the above embodiments by reading and executing computer program instructions stored in memory.

[0053] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0054] This application embodiment also provides a smart terminal, including: a memory and a processor, wherein the memory stores an operation program, and when the operation program is executed by the processor, it implements the steps of any of the methods described above.

[0055] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described above.

[0056] The embodiments of the smart terminal and computer-readable storage medium provided in this application may include all the technical features of any of the above embodiments. The extended and explanatory content of the specification is basically the same as the embodiments of the above methods, and will not be repeated here.

[0057] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the methods described in the various possible implementations above.

[0058] The capacitance calculation method, capacitance acquisition method, device, and dielectric of this application use normalization coefficients, the minimum first width of the first conductor, and the minimum second width of the second conductor as model sampling parameters for the model structure. This ensures the independence between the model sampling parameters, thereby enabling the creation of a more complete capacitance library and improving the efficiency and accuracy of capacitance acquisition.

[0059] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0060] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0061] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0062] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0063] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0064] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0065] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A capacitance calculation method, characterized in that, Includes the following steps: Determine the capacitance model that matches the target structure; Obtain the first structural parameter in the target structure that corresponds to the capacitor model, and calculate the first capacitance based on the first structural parameter and the capacitor model; The capacitance change rate of the target structure is calculated based on the capacitance change rate model that matches the target structure. The first capacitance is corrected based on the capacitance change rate, and the second capacitance of the target structure is determined.

2. The capacitance calculation method according to claim 1, characterized in that, The determination of the capacitance model that matches the target structure includes: If the target structure only includes conductors located in different layers, then a first capacitor model is obtained; If the target structure includes conductors located in different layers and conductors located in the same layer, then a second capacitor model is obtained.

3. The capacitance calculation method according to claim 2, characterized in that, The step of calculating the capacitance change rate of the target structure based on the capacitance change rate model matched with the target structure includes: Obtain the capacitance change rate model that matches the target structure; Obtain the second structural parameters and etching effect parameters in the target structure that correspond to the capacitance change rate model; The capacitance change rate of the target structure is calculated based on the capacitance change rate model, the second structural parameter, and the etching effect parameter.

4. The capacitance calculation method according to claim 3, characterized in that, The step of obtaining the capacitance change rate model that matches the target structure includes: When the capacitance model matching the target structure is the first capacitance model, obtain the first capacitance change rate model and / or the second capacitance change rate model; When the capacitance model matching the target structure is the second capacitance model, the third capacitance change rate model is obtained.

5. The capacitance calculation method according to claim 4, characterized in that, The method further includes: Establish a model for the rate of change of the first capacitance; The establishment of the first capacitance change rate model includes: Obtain the first model capacitance and the first influence capacitance corresponding to the first capacitor model, wherein the first model capacitance includes the model surface capacitance; Based on the first model capacitance and the first influencing capacitance, the first capacitance change rate model corresponding to the first capacitance model is obtained.

6. The capacitance calculation method according to claim 4 or 5, characterized in that, The method further includes: Establish the second capacitance change rate model; The second capacitance change rate model is established, including: Obtain the second model capacitance and the second influence capacitance corresponding to the first capacitor model. The second model capacitance includes the model surface capacitance and the model sidewall capacitance. Based on the second model capacitance and the second influencing capacitance, the second capacitance change rate model corresponding to the first capacitance model is obtained.

7. The capacitance calculation method according to claim 6, characterized in that, The first capacitor model includes a dominant conductor, and the model parameters of the first capacitor model include at least one of the following: the width of the dominant conductor, the thickness of the dominant conductor, the thickness of each dielectric layer between the dominant conductor and other conductors, and etching effect parameters.

8. The capacitance calculation method according to claim 6, characterized in that, The method further includes: Establish the model for the rate of change of the third capacitor; The establishment of the third capacitance change rate model includes: Obtain the capacitance influence function corresponding to the second capacitance model; wherein, the second capacitance model includes a dominant conductor and an environmental conductor, and the model parameters of the second capacitance model include at least the width of the dominant conductor, the distance from the dominant conductor to the environmental conductor, and the minimum value from the dominant conductor to the environmental conductor; Obtain the first capacitor influence rate model and the second capacitor influence rate model; Based on the first capacitance influence rate model, the second capacitance influence rate model, and the capacitance influence function, determine the third capacitance change rate model corresponding to the second capacitance model.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the processor being configured to implement the method as described in any one of claims 1 to 8 when executing a computer program in the memory.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method as described in any one of claims 1 to 8.

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