Current limiting circuit for charge pump, charge pump and chip

Abstract

The invention relates to the technical field of electronic circuits, in particular to a current limiting circuit for a charge pump, the charge pump and a chip. Wherein the current limiting circuit comprises a first current limiting circuit and a second current limiting circuit; the first current limiting circuit is used for clamping the grid voltage of the second transistor or the fourth transistor so as to control the current on the first charging and discharging branch to be smaller than or equal to a first current threshold value, and the second current limiting circuit is used for clamping the grid voltage of the first transistor or the third transistor so as to control the current on the second charging and discharging branch to be smaller than or equal to a second current threshold value. Therefore, the current on the second charging and discharging branch is controlled to be smaller than or equal to the second current threshold. According to the current limiting circuit provided by the invention, the current limiting processing of the charge pump can be realized by adopting a mode of clamping the gate-source voltage of the transistor in the charge pump, and compared with a mode of connecting a power tube with a relatively large size in parallel with a power tube with a relatively small size in the charge pump in the related technology, the space area occupied by the charge pump is saved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a current limiting circuit for a charge pump, a charge pump, and a chip. Background Technology

[0002] Charge pumps, as voltage conversion circuits, are widely used in electronic devices. They can operate in both forward buck and reverse boost modes. When a charge pump operates in reverse buck mode, the reverse input voltage is VIN, and the output voltage is VOUT, where VOUT = K * VIN, k = 1, 2, 3… Taking a 4:1 voltage conversion ratio as an example, during the reverse boost process, the input voltage VIN needs to be gradually increased from 1 * VIN to 4 * VIN through reverse startup. After startup, the charge pump starts operating at a 4:1 conversion ratio.

[0003] In related technologies, charge pumps typically employ a phased soft-start process during reverse startup: the input voltage VIN is initially reduced from one VIN, then current-limited in 1T2 operating mode to two VIN; then in 1T3 operating mode, current-limited again to three VIN; and finally, in 1T4 operating mode, current-limited again to four VIN. During this soft-start process, if current limiting is not implemented during the VIN boost phase, a voltage difference equal to one VIN will fall across the power transistor in the charge pump during the switch from 1T(K-1) operating mode to 1TK operating mode, generating a large current and potentially damaging the device. Since this voltage difference is caused by the operating mode switch and depends on the magnitude of the input voltage VIN, this phenomenon is difficult to avoid. In related technologies, to address this technical problem, a smaller power transistor is connected in parallel with a larger power transistor in the charge pump. The smaller power transistor, with its higher on-resistance, bears the voltage difference, thus suppressing the large current generated during soft start. After the charge pump finishes soft start, the larger power transistor is switched back to ensure the charge pump's efficiency. While existing solutions effectively limit the current, they increase the area occupied by the charge pump, and the smaller power transistor only operates during startup and cannot participate after soft start, thus failing to improve the charge pump's conversion efficiency. Summary of the Invention

[0004] This application provides a current limiting circuit, a charge pump, and a chip for a charge pump, to solve the problem that current limiting circuits in related technologies increase the area occupied by the charge pump.

[0005] In a first aspect, this application provides a current limiting circuit for a charge pump, the charge pump including a first capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor, the first capacitor, the second transistor, and the fourth transistor forming a first charge-discharge branch, the first capacitor, the first transistor, and the third transistor forming a second charge-discharge branch, the first charge-discharge branch and the second charge-discharge branch being alternately turned on to achieve voltage conversion; the current limiting circuit includes a first current limiting circuit and a second current limiting circuit; The first current limiting circuit is connected to the gate of the second transistor or the fourth transistor in the first charge-discharge branch. The first current limiting circuit is used to clamp the gate voltage of the second transistor or the fourth transistor, thereby controlling the current in the first charge-discharge branch to be less than or equal to the first current threshold. The second current limiting circuit is connected to the control electrode of the first transistor or the third transistor in the second charge-discharge branch. The second current limiting circuit is used to clamp the gate voltage of the first transistor or the third transistor, thereby controlling the current in the second charge-discharge branch to be less than or equal to the second current threshold.

[0006] In one possible design, the first current limiting circuit includes a first current mirror circuit, a second current mirror circuit, a current-to-voltage circuit, a first amplifier circuit, and a first drive circuit. The first current mirror circuit is used to generate a first current and output the first current to the second current mirror circuit and the first amplifier circuit, respectively. The second current mirror circuit is used to generate a second current based on the first current, and output the second current to the current-to-voltage circuit and the first amplifier circuit; The current-to-voltage circuit is used to generate a first clamping voltage based on the second current and output the first clamping voltage to the first amplifier circuit. The first amplifier circuit is configured to generate a first voltage clamping control signal based on the first current, the second current, and the first clamping voltage, and output the first voltage clamping control signal to the first driving circuit. The first driving circuit is used to generate a first driving control signal based on the first voltage clamping control signal. The first driving control signal is used to control the conduction degree of the second transistor or the fourth transistor, thereby controlling the current in the first charging and discharging branch to be less than or equal to the first current threshold.

[0007] In one possible design, the first current mirror circuit includes a first current source, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The negative terminal of the first current source is connected to the first terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor, the first terminal of the thirteenth transistor, the control terminal of the thirteenth transistor, and the control terminal of the fourteenth transistor, respectively. The second terminals of the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all grounded. The control electrode of the eleventh transistor is used to receive a second enable signal. The second enable signal is used to control the eleventh transistor to turn on when the charge pump reverse discharge is started, thereby controlling the first current mirror circuit to start working. The control electrode of the twelfth transistor is used to receive a third enable signal. The third enable signal is used to control the twelfth transistor to turn off after the charge pump reverse discharge is started, thereby controlling the first current mirror circuit to stop working.

[0008] In one possible design, the second current mirror circuit includes a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; The second terminal of the fifteenth transistor is used to receive the first supply voltage. The first terminal of the fifteenth transistor is connected to the first terminal of the fourteenth transistor, the control terminal of the fifteenth transistor, the first terminal of the sixteenth transistor, and the control terminal of the seventeenth transistor. The second terminals of the sixteenth transistor and the seventeenth transistor are both used to receive the first supply voltage. The first terminal of the seventeenth transistor is used to output the second current. The control electrode of the sixteenth transistor is also used to receive the second enable signal. The second enable signal is used to control the sixteenth transistor to turn on when the charge pump reverse discharge is started, thereby controlling the second current mirror circuit to start working.

[0009] In one possible design, the current-to-voltage circuit includes a first resistor and an eighteenth transistor; The first end of the first resistor is connected to the first electrode of the seventeenth transistor to receive the second current. The second end of the first resistor is connected to the first electrode of the eighteenth transistor and the control electrode of the eighteenth transistor, respectively. The second electrode of the eighteenth transistor is grounded. The first end of the first resistor is used to output the first clamping voltage.

[0010] In one possible design, the first amplifier circuit includes a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor; The second terminals of the nineteenth transistor and the twenty-fifth transistor are both used to receive the first power supply voltage. The control terminal of the nineteenth transistor is connected to the gate of the seventeenth transistor. The first terminal of the nineteenth transistor is connected to the second terminals of the twentyth and twenty-first transistors, respectively. The control terminal of the twentyth transistor is connected to the first terminal of the first resistor R1 to receive the first clamping voltage. The control terminal of the twenty-first transistor is connected to the second terminals of the twenty-fourth and twenty-fifth transistors, respectively. The first terminal of the twentyth transistor is connected to the first terminal of the twenty-second transistor, the control terminal of the twenty-second transistor, and the control terminal of the twenty-third transistor, respectively. The second terminals of the twenty-second and twenty-third transistors are both grounded. The control electrode of the 24th transistor is connected to the control electrode of the 14th transistor, and the second electrode of the 24th transistor is grounded; the control electrode of the 25th transistor is connected to the second electrode of the 23rd transistor, and the control electrode of the 25th transistor is used to output the first voltage clamping control signal.

[0011] In one possible design, the first driving circuit includes a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, and a twenty-ninth transistor; The control electrode of the 25th transistor is connected to the control electrode of the 26th transistor and the first electrode of the 27th transistor. The control electrode of the 26th transistor is used to receive the first voltage clamping control signal. The first electrode of the 26th transistor is connected to the first electrode of the 28th transistor. The second electrode of the 28th transistor is used to receive the first supply voltage. The control electrode of the 28th transistor is connected to the control electrode of the 29th transistor. The second electrode of the 26th transistor is connected to the first electrode of the 29th transistor. The second electrode of the 29th transistor is grounded. The second electrode of the 26th transistor is connected to the control electrode of the second transistor or the fourth transistor to output the first drive control signal to the second transistor or the fourth transistor. The second terminal of the 27th transistor is used to receive the first supply voltage, and the control terminal of the 27th transistor is used to receive the first enable signal. The first enable signal is used to control the 17th transistor to conduct when the charge pump reverse discharge is started, thereby controlling the first drive circuit to start working.

[0012] In one possible design, the second current limiting circuit includes a second amplifier circuit, a third current mirror circuit, a second resistor, and a second drive circuit. The input terminal of the second amplifier circuit is connected to the first terminal of the second thirteenth transistor. The second amplifier circuit is used to generate a third current based on the reference voltage on the first terminal of the second thirteenth transistor. The third current mirror circuit is used to generate a fourth current based on the third current and output the fourth current to the first terminal of the second resistor. The second terminal of the second resistor is connected to the second terminal of the third transistor. The second driving circuit is used to sample the second clamping voltage on the first terminal of the second resistor and generate a second driving control signal based on the second clamping voltage. The second driving control signal is used to control the conduction degree of the first transistor or the third transistor, thereby controlling the current in the second charging and discharging branch to be less than or equal to the second current threshold.

[0013] In one possible design, the second amplifier circuit includes an amplifier, a thirty-first transistor, and a third resistor; The non-inverting input of the amplifier is connected to the first terminal of the 23rd transistor to sample the reference voltage on the first terminal of the 23rd transistor. The inverting input of the amplifier is connected to the first terminal of the third resistor and the second terminal of the 31st transistor, and the second terminal of the third resistor is grounded. The output of the amplifier is connected to the control terminal of the 31st transistor.

[0014] In one possible design, the third current mirror circuit includes a thirty-second transistor and a thirty-third transistor. The first terminal and the control terminal of the thirty-second transistor are both connected to the first terminal of the thirty-first transistor. The first terminal of the thirty-second transistor is used to receive a second supply voltage. The control terminal of the thirty-second transistor is connected to the control terminal of the thirty-third transistor. The second terminal of the thirty-third transistor is used to receive the second supply voltage. The first terminal of the thirty-third transistor is connected to the first end of the second resistor.

[0015] In one possible design, the second drive circuit includes a thirty-fourth transistor, a thirty-fifth transistor, and a thirty-sixth transistor; The second terminal of the thirty-fourth transistor is used to receive the second power supply voltage. The first terminal of the thirty-fourth transistor is connected to the first terminal of the thirty-fifth transistor, the second terminal of the thirty-fifth transistor is connected to the first terminal of the thirty-sixth transistor, the second terminal of the thirty-sixth transistor is grounded, and the control terminal of the thirty-fourth transistor is connected to the control terminal of the thirty-sixth transistor. The second terminal of the thirty-fifth transistor is also connected to the control terminal of the first transistor or the third transistor to output the second drive control signal to the first transistor or the third transistor.

[0016] Secondly, this application also provides a charge pump, the charge pump including the current limiting circuit for the charge pump described in any of the above claims.

[0017] Thirdly, this application also provides a chip, the chip including the current limiting circuit for a charge pump as described in any of the above claims; or the chip including the charge pump as described above.

[0018] The current-limiting circuit for a charge pump provided in the first aspect above includes a first capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first capacitor, the second transistor, and the fourth transistor form a first charge-discharge branch, and the first capacitor, the first transistor, and the third transistor form a second charge-discharge branch. The first charge-discharge branch and the second charge-discharge branch are alternately turned on to achieve voltage conversion. The current-limiting circuit provided in this application includes a first current-limiting circuit and a second current-limiting circuit. The first current-limiting circuit is connected to the gate of the second transistor or the fourth transistor in the first charge-discharge branch. The first current-limiting circuit is used to clamp the gate voltage of the second transistor or the fourth transistor, thereby controlling the current in the first charge-discharge branch to be less than or equal to a first current threshold. The second current-limiting circuit is connected to the control electrode of the first transistor or the third transistor in the second charge-discharge branch. The second current-limiting circuit is used to clamp the gate voltage of the first transistor or the third transistor, thereby controlling the current in the second charge-discharge branch to be less than or equal to a second current threshold. According to the current limiting circuit provided in this application, the current limiting of the charge pump can be achieved by clamping the gate-source voltage of the transistor in the charge pump. Compared with the method of connecting a smaller power transistor in parallel with a larger power transistor in the charge pump in related technologies, the space occupied by the charge pump is saved.

[0019] The beneficial effects provided by the other aspects and the various possible designs of the other aspects can be found in the beneficial effects of the first aspect and the various possible implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0020] Figure 1 A schematic diagram of a charge pump and its current limiting circuit provided for the related technologies of this application; Figure 2 A schematic diagram of the overall structure of a current-limiting circuit for a charge pump provided in an embodiment of this application; Figure 3 This is a schematic diagram of the first current limiting circuit structure provided in an embodiment of this application; Figure 4 This is a schematic diagram of the second current limiting circuit structure provided in an embodiment of this application. Detailed Implementation

[0021] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0024] The transistor in this application is a three-terminal transistor, with its three terminals being a control terminal, a first terminal, and a second terminal. The transistor can be a bipolar transistor (BPT) or a field-effect transistor (FET), etc. For example, when the transistor is a BPT, its control terminal is the base of the BPT, the first terminal can be the collector or emitter of the BPT, and the corresponding second terminal can be the emitter or collector of the BPT; when the transistor is a FET, its control terminal is the gate of the FET, the first terminal can be the drain or source of the FET, and the corresponding second terminal can be the source or drain of the FET.

[0025] Charge pumps can operate in both forward buck and reverse boost modes. In related technologies, the reverse start-up process of a charge pump is typically a staged soft start. Taking a 1T4 charge pump amplifier as an example: the charge pump first operates in 1T2 mode, soft-starting the input voltage VIN from one times VIN to two times VIN using current-limited 1T2 mode. Then it enters 1T3 mode, soft-starting the input voltage VIN to three times VIN using current-limited 1T3 mode. Finally, it soft-starts the input voltage VIN to four times VIN using 1T4 mode. During this soft start process, if current limiting is not implemented during the VIN boost, a voltage difference of one times VIN will fall on the power transistor in the charge pump during the switch from 1T(K-1) mode to 1TK mode, generating a large current and potentially damaging the device. Since this voltage difference is caused by the mode switch and depends on the magnitude of the input voltage VIN, this phenomenon is difficult to avoid. In related technologies, to address this technical problem, a smaller power transistor is connected in parallel with a larger power transistor in the charge pump. The smaller power transistor, with its higher on-resistance, bears the voltage difference, thus suppressing the large current generated during soft start. After the charge pump finishes soft start, the larger power transistor is switched back to ensure the charge pump's efficiency. While existing solutions effectively limit the current, they increase the area occupied by the charge pump, and the smaller power transistor only operates during startup and cannot participate after soft start, thus failing to improve the charge pump's conversion efficiency.

[0026] Figure 1 For a schematic diagram of the charge pump and its current limiting circuit provided for the related technologies of this application, please refer to [link / reference]. Figure 1 As shown, this charge pump circuit is a 1T2 structure, which can achieve a forward conversion ratio of 2:1 for voltage reduction. The charge pump circuit includes a first capacitor C1, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. In this embodiment, all four transistors are NMOS (N-Metal-Oxide-Semiconductor) transistors to illustrate the structure of the charge pump circuit. It is understood that in other embodiments, the first transistor Q1, second transistor Q2, third transistor Q3, and fourth transistor Q4 in this embodiment can also be PMOS (P-Metal-Oxide-Semiconductor) transistors.

[0027] Please continue reading Figure 1As shown, the drain of the first transistor Q1 is connected to the first charge / discharge terminal S1. The source of the first transistor Q1 is connected to the first terminal of the first capacitor C1 and the drain of the second transistor Q2. The source of the second transistor Q2 is connected to the second charge / discharge terminal S2 and the drain of the third transistor Q3. The source of the third transistor Q3 is connected to the second terminal of the first capacitor C1 and the drain of the fourth transistor Q4. The source of the fourth transistor Q4 is grounded. The gates of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are connected to the drive terminals of the drive circuit. The drive circuit outputs corresponding level drive signals to control the conduction or cutoff of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4, thereby controlling the charge pump circuit to operate in forward buck mode or reverse boost mode to achieve voltage conversion.

[0028] In one embodiment, the charge pump circuit further includes an input capacitor CIN, with a first terminal connected to the first charge / discharge terminal S1 and a second terminal grounded. The input capacitor CIN serves to regulate voltage and filter. For example, when the charge pump operates in reverse boost mode, the input capacitor CIN can regulate the output voltage VOUT output from the first charge / discharge terminal S1.

[0029] by Figure 1 Taking the charge pump circuit shown as operating in reverse boost mode as an example, the second charge / discharge terminal S2 receives the input voltage VIN. After the charge pump circuit performs voltage conversion on the input voltage VIN, the first charge / discharge terminal S1 outputs the converted output voltage VOUT. The charge pump circuit mainly includes two operating stages in each working cycle. In the first operating stage of each working cycle, the driving circuit controls the second transistor Q2 and the fourth transistor Q4 to be turned on simultaneously. At this time, the second charge / discharge terminal S2, the second transistor Q2, the first capacitor C1, the fourth transistor Q4, and the common ground form a current loop. The second charge / discharge terminal S2 receives the input voltage VIN to charge the first capacitor C1, so that the first capacitor C1 stores energy. In the second operating stage of each working cycle, the driving circuit controls the first transistor Q1 and the third transistor Q3 to be turned on simultaneously. At this time, the second charge / discharge terminal S2, the third transistor Q3, the first capacitor C1, the first transistor Q1, and the first charge / discharge terminal S1 form a current loop. The second charge / discharge terminal S2 receives the input voltage VIN to discharge the first charge / discharge terminal S1. At the same time, the first capacitor C1 also discharges after the energy storage in the first stage. At this time, the output voltage VOUT of the first charge / discharge terminal S1 is 2*VIN. As can be seen, in this charge pump circuit, the first capacitor C1, the second transistor Q2 and the fourth transistor Q4 form the first charge-discharge branch, and the first capacitor C1, the first transistor Q1 and the third transistor Q3 form the second charge-discharge branch. The first charge-discharge branch and the second charge-discharge branch are alternately turned on to realize voltage conversion.

[0030] by Figure 1 Taking the reverse boost process of the 1T2 charge pump circuit as an example, during the reverse start-up process of the charge pump, the second charge / discharge terminal S2 receives the input voltage VIN and charges the first capacitor C1 until its voltage equals VIN. Then, the operating mode switches from direct charging to 1T2 operating mode, and the output voltage VOUT of the first charge / discharge terminal S1 is 2*VIN. During this soft-start process, if no current limiting is performed during the boost of the input voltage VIN, during the switch from the 1T1 (i.e., 1:1 voltage conversion ratio) operating mode to the 1T2 (i.e., 1:2 voltage conversion ratio) operating mode, in the first stage of each operating cycle, a voltage difference equal to one input voltage VIN will fall on the second transistor Q2 and the fourth transistor Q4 in the charge pump, and in the second stage of each operating cycle, a voltage difference equal to one input voltage VIN will fall on the first transistor Q1 and the third transistor Q3 in the charge pump. This causes a large current to be generated in the first and second charge / discharge branches, thereby damaging the device.

[0031] To overcome this technical problem, please continue to see Figure 1As shown, in the related technology, a first auxiliary transistor Q3S is connected in series across the source and drain of the third transistor Q3. The size of the first auxiliary transistor Q3S is smaller than that of the third transistor Q3 because its impedance is larger, thus limiting current. Similarly, a second auxiliary transistor Q4S ​​is connected in series across the source and drain of the fourth transistor Q4. The size of the second auxiliary transistor Q4S ​​is also smaller than that of the third transistor Q3 because its impedance is larger, thus limiting current. Thus, during soft-start with the first charge / discharge branch conducting, a voltage difference equal to one input voltage VIN (the voltage difference used to charge the first capacitor C1) falls across the second auxiliary transistor Q4S, limiting current. During soft-start with the second charge / discharge branch conducting, a voltage difference equal to one input voltage VIN falls across the first auxiliary transistor Q3S, similarly limiting current. While the technical solutions provided in related technologies can effectively limit the current, they increase the area occupied by the charge pump, and the small power transistor only participates in operation during startup and cannot participate after soft-start, thus failing to improve the conversion efficiency of the charge pump. Therefore, the current limiting schemes provided in related technologies still have certain technical defects and room for improvement.

[0032] To overcome the shortcomings of the aforementioned related technologies, this application provides a current limiting circuit for a charge pump. The current limiting circuit proposed in this application is conceived as follows: during the reverse boost soft-start process of the charge pump, gate voltage control is applied to one of the power transistors in the current path, limiting its maximum current to the saturation current. Gate voltage control is achieved by clamping the gate of the power transistor, and the clamping voltage is set according to the reference voltage during soft-start. The reference voltage during soft-start is generated in conjunction with the transistor's threshold voltage, with the aim of tracking fluctuations in the device's threshold voltage due to process variations.

[0033] Specifically, this application provides a current-limiting circuit for a charge pump. The current-limiting circuit includes a first current-limiting circuit and a second current-limiting circuit. The first current-limiting circuit is connected to the gate of a second or fourth transistor in a first charge-discharge branch. The first current-limiting circuit clamps the gate voltage of the second or fourth transistor, thereby controlling the current in the first charge-discharge branch to be less than or equal to a first current threshold. The second current-limiting circuit is connected to the control electrode of a first or third transistor in a second charge-discharge branch. The second current-limiting circuit clamps the gate voltage of the first or third transistor, thereby controlling the current in the second charge-discharge branch to be less than or equal to a second current threshold. According to the current-limiting circuit provided in this application, current limiting of the charge pump can be achieved by clamping the gate-source voltage of the transistors in the charge pump. Compared with the method of connecting a larger power transistor in parallel with a smaller power transistor in the charge pump in related technologies, this saves the space occupied by the charge pump.

[0034] Figure 2 For a schematic diagram of the overall structure of the current-limiting circuit for a charge pump provided in this application embodiment, please refer to [link / reference]. Figure 2 As shown, in this embodiment, Figure 1 For example, using a charge pump with a voltage conversion ratio of 2:1 as shown, please refer to [link to relevant documentation]. Figure 1 As shown, the charge pump circuit includes a first capacitor C1, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The first capacitor C1, the second transistor Q2, and the fourth transistor Q4 form a first charge-discharge branch, and the first capacitor C1, the first transistor Q1, and the third transistor Q3 form a second charge-discharge branch. The first charge-discharge branch and the second charge-discharge branch are alternately turned on and off to achieve voltage conversion.

[0035] Please see Figure 2 As shown, the current limiting circuit provided in this embodiment includes a first current limiting circuit 21 and a second current limiting circuit 22. The first current limiting circuit 21 is connected to the gate of the second transistor Q2 or the fourth transistor Q4 in the first charge-discharge branch. The first current limiting circuit 21 is used to clamp the gate voltage of the second transistor Q2 or the fourth transistor Q4 to control the conduction level of the second transistor Q2 or the fourth transistor Q4, thereby controlling the current in the first charge-discharge branch to be less than or equal to a first current threshold, so as to limit the current in the first charge-discharge branch at the moment of startup. The second current limiting circuit 22 is connected to the control electrode of the first transistor Q1 or the third transistor Q3 in the second charge-discharge branch. The second current limiting circuit is used to clamp the gate voltage of the first transistor Q1 or the third transistor Q3 to control the conduction level of the second transistor Q2 or the fourth transistor Q4, thereby controlling the current in the second charge-discharge branch to be less than or equal to a second current threshold, so as to limit the current in the second charge-discharge branch at the moment of startup.

[0036] According to the current limiting circuit provided in the embodiments of this application, the current limiting of the charge pump can be achieved by clamping the gate-source voltage of the transistor in the charge pump. Compared with the method of connecting a smaller power transistor in parallel with a larger power transistor in the charge pump in related technologies, the space occupied by the charge pump is saved.

[0037] Figure 3 For a schematic diagram of the first current limiting circuit structure provided in the embodiments of this application, please refer to [link / reference]. Figure 3 As shown, the first current limiting circuit 21 includes a first current mirror circuit 31, a second current mirror circuit 32, a current-to-voltage circuit 33, a first amplifier circuit 34, and a first drive circuit 35.

[0038] The circuit comprises: a first current mirror circuit 31, which generates a first current and outputs it to a second current mirror circuit 32 and a first amplifier circuit 34; a second current mirror circuit 32, which generates a second current based on the first current generated by the first current mirror circuit 31 and outputs it to a current-to-voltage circuit 33 and a first amplifier circuit 34; a current-to-voltage circuit 33, which generates a first clamping voltage based on the second current and outputs it to the first amplifier circuit 34; a first amplifier circuit 34, which generates a first voltage clamping control signal based on the first current, the second current, and the first clamping voltage and outputs it to a first drive circuit 35; and a first drive circuit 35, which generates a first drive control signal based on the first voltage clamping control signal. The first drive control signal controls the conduction level of the second transistor Q2 or the fourth transistor Q4, thereby controlling the current in the first charge / discharge branch to be less than or equal to a first current threshold.

[0039] It is understood that, in this embodiment, the current limiting of the current value in the first charge-discharge branch is achieved by controlling the conduction level of the fourth transistor Q4 in the first charge-discharge branch. In other embodiments, the current limiting of the current value in the first charge-discharge branch can also be achieved by controlling the conduction level of the second transistor Q2 in the first charge-discharge branch. Correspondingly, the current limiting circuit used to control the second transistor Q2 can be configured to have the same structure as the current limiting circuit described above, which will not be described in detail here.

[0040] Please continue reading Figure 3 As shown, the first current mirror circuit 31 provided in this embodiment includes a first current source IA1, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14. In this circuit, the negative terminal of the first current source IA1 is connected to the first terminal of the eleventh transistor M11. The second terminal of the eleventh transistor M11 is connected to the first terminal of the twelfth transistor M12, the first terminal of the thirteenth transistor M13, the control terminal of the thirteenth transistor M13, and the control terminal of the fourteenth transistor M14. The second terminals of the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all grounded. The control terminal of the eleventh transistor M11 receives the second enable signal EN_GC_B. The second enable signal EN_GC_B is used to control the eleventh transistor M11 to conduct when the charge pump reverse discharge is started, thereby controlling the first current mirror circuit 31 to start working. The control terminal of the twelfth transistor M12 receives the third enable signal EN_GC_Z. The third enable signal EN_GC_Z is used to control the twelfth transistor M12 to turn off after the charge pump reverse discharge is started, thereby controlling the first current mirror circuit 31 to stop working.

[0041] In this embodiment, the third enable signal EN_GC_Z and the second enable signal EN_GC_B are two enable signals with opposite logic states. For example, when the third enable signal EN_GC_Z is high, the second enable signal EN_GC_B is low, and when the third enable signal EN_GC_Z is low, the second enable signal EN_GC_B is high.

[0042] In the embodiments of this application, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all NMOS (N-Metal-Oxide-Semiconductor) transistors. In other embodiments, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 may also be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are NMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0043] When the charge pump reverse discharge is initiated, the second enable signal EN_GC_B input to the gate of the eleventh transistor M11 is at a high level. At this time, the second enable signal EN_GC_B controls the eleventh transistor M11 to conduct, thereby controlling the thirteenth transistor M13 and the fourteenth transistor M14 to also conduct. The thirteenth transistor M13 and the fourteenth transistor M14 form a current mirror structure, causing the first current mirror circuit 31 to output a first current. The direction of this first current is from the drain of the fourteenth transistor M14 to its source. The magnitude of the first current is determined by the first current source IA1 and can be adjusted according to different circuit structures. After the charge pump reverse discharge is initiated, the control electrode of the twelfth transistor M12 receives the third enable signal EN_GC_Z. This third enable signal EN_GC_Z controls the twelfth transistor M12 to turn off, thereby controlling the first current mirror circuit 31 to start working.

[0044] Please continue reading Figure 3As shown, the second current mirror circuit 32 in this embodiment includes a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. The second terminal of the fifteenth transistor M15 is used to receive the first supply voltage AVDD. The first terminal of the fifteenth transistor M15 is connected to the first terminal of the fourteenth transistor M14, the control terminal of the fifteenth transistor M15, the first terminal of the sixteenth transistor M16, and the control terminal of the seventeenth transistor M17. The second terminals of the sixteenth transistor M16 and the seventeenth transistor M17 are both used to receive the first supply voltage AVDD. The first terminal of the seventeenth transistor M17 is used to output a second current. The control terminal of the sixteenth transistor M16 is also used to receive the second enable signal EN_GC_B. The second enable signal EN_GC_B is used to control the sixteenth transistor M16 to conduct when the charge pump reverse discharge is started, thereby controlling the second current mirror circuit 32 to start working.

[0045] In the embodiments of this application, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are all PMOS (P-Metal-Oxide-Semiconductor) transistors; in other embodiments, the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 may also be NMOS (N-Metal-Oxide-Semiconductor) transistors. For example, when the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are PMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0046] Specifically, when the charge pump starts reverse discharge, the second enable signal EN_GC_B controls the sixteenth transistor M16 to turn on, thereby pulling up the gate voltages of the fifteenth transistor M15 and the seventeenth transistor M17, causing the fifteenth transistor M15 and the seventeenth transistor M17 to turn off. This allows the second current mirror circuit 32 to start working and output a second current. At this time, the fifteenth transistor M15 and the seventeenth transistor M17 form a current mirror structure, and the second current flows from the source to the drain of the seventeenth transistor M17.

[0047] Please continue reading Figure 3As shown, the current-to-voltage circuit provided in this embodiment includes a first resistor R1 and an eighteenth transistor M18. The first terminal of the first resistor R1 is connected to the first electrode of the seventeenth transistor M17 to receive the second current output by the seventeenth transistor M17. The second terminal of the first resistor R1 is connected to the first electrode and the control electrode of the eighteenth transistor M18, respectively. The second electrode of the eighteenth transistor M18 is grounded. The first terminal of the first resistor R1 is used to output a first clamping voltage. In this embodiment, the voltage at the first terminal of the first resistor R1 is the same as the voltage at point A, therefore the first clamping voltage can be expressed as VA, and the voltage value of the first clamping voltage VA can be expressed as: V A =VGS_M18+I2*R1; where V A VGS_M18 is the voltage value of the first clamping voltage VA, VGS_M18 is the voltage difference between the gate and source of the eighteenth transistor M18, I2 is the current value of the second current, and R1 is the resistance value of the first resistor R1.

[0048] Please continue reading Figure 3 As shown, the first amplifier circuit 34 provided in this embodiment includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, and a twenty-fifth transistor M25. The second terminals of both the nineteenth transistor M19 and the twenty-fifth transistor M25 are used to receive the first supply voltage AVDD. The control terminal of the nineteenth transistor M19 is connected to the gate of the seventeenth transistor M17. The first terminal of the nineteenth transistor M19 is connected to the second terminals of the twentieth transistor M20 and the twenty-first transistor M21, respectively. The control terminal of the twentieth transistor M20 is connected to the first terminal of the first resistor R1 to receive the first power supply voltage AVDD. A clamping voltage VA is provided. The control terminal of the twenty-first transistor M21 is connected to the second terminal of the twenty-fourth transistor M24 and the second terminal of the twenty-fifth transistor M25, respectively. The first terminal of the twentieth transistor M20 is connected to the first terminal of the twenty-second transistor M22, the control terminal of the twenty-second transistor M22, and the control terminal of the twenty-third transistor M23, respectively. The second terminals of the twenty-second transistor M22 and the twenty-third transistor M23 are both grounded. The control terminal of the twenty-fourth transistor M24 is connected to the control terminal of the fourteenth transistor M14, and the second terminal of the twenty-fourth transistor M24 is grounded. The control terminal of the twenty-fifth transistor M25 is connected to the second terminal of the twenty-third transistor M23, and the control terminal of the twenty-fifth transistor M25 is used to output the first voltage clamping control signal.

[0049] In the embodiments of this application, the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21 are all PMOS (P-Metal-Oxide-Semiconductor) transistors. In other embodiments, the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21 may also be NMOS (N-Metal-Oxide-Semiconductor) transistors. For example, when the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21 are PMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0050] In the embodiments of this application, the twenty-second transistor M22, the twenty-third transistor M23, the twenty-fourth transistor M24, and the twenty-fifth transistor M25 are all NMOS (N-Metal-Oxide-Semiconductor) transistors; in other embodiments, the twenty-second transistor M22, the twenty-third transistor M23, the twenty-fourth transistor M24, and the twenty-fifth transistor M25 may also be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when the twenty-second transistor M22, the twenty-third transistor M23, the twenty-fourth transistor M24, and the twenty-fifth transistor M25 are NMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0051] Please continue reading Figure 3As shown, the first driving circuit 35 provided in this embodiment includes a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, and a twenty-ninth transistor M29; wherein, the control electrode of the twenty-fifth transistor M25 is connected to the control electrode of the twenty-sixth transistor M26 and the first electrode of the twenty-seventh transistor M27, respectively; the control electrode of the twenty-sixth transistor M26 is used to receive the first voltage clamping control signal output from the gate of the twenty-fifth transistor M25; the first electrode of the twenty-sixth transistor M26 is connected to the first electrode of the twenty-eighth transistor M28, and the second electrode of the twenty-eighth transistor M28 is used to receive... The first power supply voltage AVDD is received. The control electrode of the twenty-eighth transistor M28 is connected to the control electrode of the twenty-ninth transistor M29. The second electrode of the twenty-sixth transistor M26 is connected to the first electrode of the twenty-ninth transistor M29, and the second electrode of the twenty-ninth transistor M29 is grounded. The second electrode of the twenty-sixth transistor M26 is connected to the control electrode of the second transistor Q2 or the fourth transistor Q4 to output a first drive control signal Q4_GT to the second transistor Q2 or the fourth transistor Q4. This first drive control signal Q4_GT is used to control the conduction level of the fourth transistor Q4, thereby controlling the current value in the first charge-discharge circuit. The second electrode of the twenty-seventh transistor M27 is used to receive the first power supply voltage AVDD. The control electrode of the twenty-seventh transistor M27 is used to receive a first enable signal EN_GC. The first enable signal EN_GC is used to control the seventeenth transistor M17 to conduct when the charge pump reverse discharges, thereby controlling the first drive circuit 35 to start working and output the first drive control signal Q4_GT to the gate of the fourth transistor Q4.

[0052] In the embodiments of this application, both the twenty-seventh transistor M27 and the twenty-eighth transistor M28 are PMOS (P-Metal-Oxide-Semiconductor) transistors; in other embodiments, through modified circuit design, the twenty-seventh transistor M27 and the twenty-eighth transistor M28 in this embodiment can also be NMOS (N-Metal-Oxide-Semiconductor) transistors; for example, when the twenty-seventh transistor M27 and the twenty-eighth transistor M28 are PMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0053] In the embodiments of this application, both the twenty-sixth transistor M26 and the twenty-ninth transistor M29 are NMOS (N-Metal-Oxide-Semiconductor) transistors; in other embodiments, through modified circuit design, the twenty-sixth transistor M26 and the twenty-ninth transistor M29 in this embodiment can also be PMOS (P-Metal-Oxide-Semiconductor) transistors; for example, when the twenty-sixth transistor M26 and the twenty-ninth transistor M29 are NMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0054] Please continue reading Figure 3 As shown in this embodiment, the first current limiting circuit 21 further includes a first inverter 36 and a second inverter 37. The output terminal of the first inverter 36 is connected to the input terminal of the second inverter 37, and the output terminal of the second inverter 37 is connected to the gate of the twenty-seventh transistor M27. The input terminal of the first inverter 36 is used to receive a first enable signal EN_GC. The first inverter 36 is used to invert the first enable signal EN_GC to obtain a third enable signal EN_GC_Z, and inputs the third enable signal EN_GC_Z into the second inverter 37. The second inverter 37 is used to invert the third enable signal EN_GC_Z to obtain a second enable signal EN_GC_B, and outputs the second enable signal EN_GC_B to the gate of the twenty-seventh transistor M27. In this embodiment, the logic states of the first enable signal EN_GC and the second enable signal EN_GC_B are the same, and the logic states of the first enable signal EN_GC and the third enable signal EN_GC_Z are opposite.

[0055] According to the embodiments provided in this example Figure 3 The current limiting circuit shown starts working during the reverse startup phase of the charge pump when the first enable signal EN_GC is high. The first clamping voltage at point A is V. A =VGS_M18+I2*R1. Based on the virtual short and virtual open principle of the first amplifier circuit 34, the voltage at point B and the voltage at point A are made equal. In this embodiment, both the 25th transistor M25 and the 26th transistor M26 are NMOS transistors. When the fourth transistor Q4 is in the conducting state, the 28th transistor M28 is turned on, and the gate voltage of the fourth transistor Q4 is clamped by the 26th transistor M26. Since both the 25th transistor M25 and the 26th transistor M26 are NMOS transistors, at this time, the gate-source voltage of the 25th transistor M25 and the gate voltage of the 26th transistor M26 are approximately equal. Therefore, VQ4_GT=V A=VGS_M18+I2*R1, thus, by adjusting the resistance value of the first resistor R1, the saturation current of the fourth transistor Q4 can be changed. After the charge pump reverse start-up is completed, when the first enable signal EN_GC switches to a low level, the gate of the twenty-sixth transistor M26 is pulled to the first supply voltage AVDD, and no longer clamps the gate voltage of the fourth transistor Q4.

[0056] According to the current limiting circuit provided in the embodiments of this application, the current value of the first charge-discharge branch in the charge pump can be limited by clamping the gate-source voltage of the fourth transistor Q4 in the charge pump. Compared with the method of connecting a smaller second auxiliary transistor Q4S ​​in parallel with the fourth transistor Q4 in the charge pump in related technologies, the space occupied by the charge pump is saved.

[0057] Figure 4 For a schematic diagram of the second current limiting circuit structure provided in the embodiments of this application, please refer to [link / reference]. Figure 4 As shown, the second current limiting circuit 22 includes a second amplifier circuit 41, a third current mirror circuit 42, a second resistor R2, and a second drive circuit 43. The input terminal of the second amplifier circuit 41 is connected to the first terminal of the twenty-third transistor M23. The second amplifier circuit 41 generates a third current I3 based on the reference voltage VCLAMP1 on the first terminal of the twenty-third transistor M23. The third current mirror circuit 42 generates a fourth current I4 based on the third current I3 and outputs the fourth current I4 to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the second terminal of the third transistor Q3. The second drive circuit 43 samples the second clamping voltage VCLAMP2 on the first terminal of the second resistor R2 and generates a second drive control signal Q3_GT based on the second clamping voltage VCLAMP2. The second drive control signal Q3_GT controls the conduction level of either the first transistor Q1 or the third transistor Q3, thereby controlling the current in the second charge / discharge branch to be less than or equal to the second current threshold.

[0058] Please combine Figure 2 and Figure 4 As shown, in this embodiment, the second terminal of the second resistor R2 is connected to the second terminal of the third transistor Q3. That is, based on the voltage on the second terminal of the third transistor Q3, the voltage generated on the second resistor R2 by the fourth current I4 flowing through the second resistor R2 is the sum of the two voltages as the second clamping voltage VCLAMP2. The second clamping voltage VCLAMP2 can be used as the clamping voltage to clamp the third transistor Q3, so as to control the conduction degree of the third transistor Q3, and then to limit the current in the second charge-discharge branch.

[0059] Please continue reading Figure 4As shown, the second amplifier circuit 41 provided in this embodiment includes an amplifier COMP, a thirty-first transistor M31, and a third resistor R3; wherein, the non-inverting input terminal of the amplifier COMP is connected to the first terminal of the twenty-third transistor M23 to sample the reference voltage VCLAMP1 on the first terminal of the twenty-third transistor M23, the inverting input terminal of the amplifier COMP is connected to the first terminal of the third resistor R3 and the second terminal of the thirty-first transistor M31, and the second terminal of the third resistor R3 is grounded; the output terminal of the amplifier COMP is connected to the control terminal of the thirty-first transistor M31.

[0060] In this embodiment, the thirty-first transistor M31 is an NMOS (N-Metal-Oxide-Semiconductor) transistor; in other embodiments, through circuit modification design, the thirty-first transistor M31 in this embodiment can also be a PMOS (P-Metal-Oxide-Semiconductor) transistor; for example, when the thirty-first transistor M31 is an NMOS transistor, its first electrode is the drain, its second electrode is the source, and its control electrode is the gate.

[0061] Understandably, in the second amplifier circuit 41, according to the virtual short and virtual open principle of amplifier COMP, the voltage value of the inverting input terminal of amplifier COMP is equal to the reference voltage VCLAMP1 at the non-inverting input terminal of amplifier COMP, thus making the voltage at the first terminal of the third resistor R3 the reference voltage VCLAMP1.

[0062] In one embodiment of this application, the third current mirror circuit 42 includes a thirty-second transistor M32 and a thirty-third transistor M33. The first terminal and the control terminal of the thirty-second transistor M32 are both connected to the first terminal of the thirty-first transistor M31. The first terminal of the thirty-second transistor M32 is used to receive the second supply voltage CIP. The control terminal of the thirty-second transistor M32 is connected to the control terminal of the thirty-third transistor M33. The second terminal of the thirty-third transistor M33 is also used to receive the second supply voltage CIP. The first terminal of the thirty-third transistor M33 is connected to the first terminal of the second resistor R2.

[0063] In one embodiment of this application, both the thirty-second transistor M32 and the thirty-third transistor M33 are PMOS (P-Metal-Oxide-Semiconductor) transistors. In other embodiments, through circuit modification design, both the thirty-second transistor M32 and the thirty-third transistor M33 in this embodiment can also be NMOS (N-Metal-Oxide-Semiconductor) transistors. For example, when both the thirty-second transistor M32 and the thirty-third transistor M33 are PMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0064] It is understood that, in the embodiments of this application, the gates of the thirty-second transistor M32 and the thirty-third transistor M33 are interconnected to form a current mirror circuit, which converts the current flowing through the thirty-second transistor M32 into the current flowing through the thirty-third transistor M33, and then inputs it to the second resistor R2. The voltage generated on the second resistor R2 by the fourth current I4 flowing through it is the sum of the two voltages as the second clamping voltage VCLAMP2. This second clamping voltage VCLAMP2 can be used as the clamping voltage for clamping the third transistor Q3 to control the conduction level of the third transistor Q3.

[0065] Please continue reading Figure 4 As shown, in one embodiment of this application, the second driving circuit 43 includes a thirty-fourth transistor M34, a thirty-fifth transistor M35, and a thirty-sixth transistor M36; wherein, the second terminal of the thirty-fourth transistor M34 is used to receive the second supply voltage CIP, the first terminal of the thirty-fourth transistor M34 is connected to the first terminal of the thirty-fifth transistor M35, the second terminal of the thirty-fifth transistor M35 is connected to the first terminal of the thirty-sixth transistor M36, the second terminal of the thirty-sixth transistor M36 is grounded, and the control terminal of the thirty-fourth transistor M34 is connected to the control terminal of the thirty-sixth transistor M36; the second terminal of the thirty-fifth transistor M35 is also connected to the control terminal of the first transistor Q1 or the third transistor Q3 to output the second driving control signal Q3_GT to the first transistor Q1 or the third transistor Q3.

[0066] In this embodiment, the thirty-fourth transistor M34 is a PMOS (P-Metal-Oxide-Semiconductor) transistor. In other embodiments, by modifying the circuit design, the thirty-fourth transistor M34 in this embodiment can also be an NMOS (N-Metal-Oxide-Semiconductor) transistor. For example, when the thirty-fourth transistor M34 is a PMOS transistor, its first electrode is the drain, its second electrode is the source, and its control electrode is the gate.

[0067] In one embodiment of this application, both the thirty-fifth transistor M35 and the thirty-sixth transistor M36 can be NMOS (N-Metal-Oxide-Semiconductor) transistors. In other embodiments, through circuit modification design, the thirty-fifth transistor M35 and the thirty-sixth transistor M36 in this embodiment can also be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when both the thirty-fifth transistor M35 and the thirty-sixth transistor M36 are NMOS transistors, their first electrode is the drain, their second electrode is the source, and their control electrode is the gate.

[0068] It is understood that for the low-side transistor (e.g., the fourth transistor Q4) with its source terminal grounded in the charge pump, the embodiments of this application are adopted. Figure 3 The provided first current-limiting circuit can effectively achieve current limiting. For the high-side transistor in the charge pump whose source terminal is not grounded (e.g., the third transistor Q3), it is only necessary to transfer the clamping voltage to the voltage domain corresponding to its drive; the inventive concept is the same for both. For example, the current-limiting circuit for the high-side transistor in the charge pump whose source terminal is not grounded can be found here. Figure 4 As shown, Figure 3 The reference voltage VCLAMP1 generates a fourth current through amplifier COMP and third resistor R3, and then is mirrored by a current mirror composed of the thirty-second transistor M32 and the thirty-third transistor M33 to generate a second clamping voltage VCLAMP2 on the high side across the second resistor R2. This second clamping voltage VCLAMP2 can clamp the gate voltage of the high-side transistor to control the conduction level of the high-side transistor, thereby achieving the purpose of current limiting in the branch where the high-side transistor is located.

[0069] It should be noted that the above embodiments are only illustrated using a charge pump with a voltage conversion ratio of 1:2 as an example. This does not mean that the current limiting circuit provided in this application embodiment can only be applied to the above-mentioned 1:2 charge pump circuit. In fact, the current limiting circuit provided in this embodiment can be applied to charge pump circuits with different structures such as voltage conversion ratios of 1:2, 1:3, 1:4 or 1:6, in order to solve the technical problem that the voltage in the circuit falls on the larger transistor at the moment of reverse start-up.

[0070] Based on the current-limiting circuits for charge pumps provided in the above embodiments, this application also provides a charge pump, which includes the current-limiting circuits for charge pumps as described in any of the above embodiments. According to the charge pump provided in this application, current limiting of the charge pump can be achieved by clamping the gate-source voltage of the transistors in the charge pump. Compared with the related art method of connecting a larger power transistor in parallel with a smaller power transistor in the charge pump, this saves the space occupied by the charge pump.

[0071] Based on the current-limiting circuits for charge pumps provided in the above embodiments, this application also provides a chip that includes the current-limiting circuit for charge pumps as described in any of the above embodiments; or the chip includes the charge pump as described above. According to the chip provided in this application, current limiting of the charge pump can be achieved by clamping the gate-source voltage of the transistors in the charge pump. Compared with the related art method of connecting a larger power transistor in the charge pump in parallel with a smaller power transistor, this saves the space occupied by the chip and reduces hardware costs.

[0072] Based on the current-limiting circuits for charge pumps provided in the above embodiments, this application also provides an electronic device, which includes the current-limiting circuit for charge pumps as described in any of the above embodiments; or the electronic device includes the charge pump or chip as described above. According to the electronic device provided in this application, current limiting of the charge pump can be achieved by clamping the gate-source voltage of the transistor in the charge pump. Compared with the related art method of connecting a larger power transistor in the charge pump with a smaller power transistor in parallel, this saves the space occupied by the chip and reduces hardware costs.

[0073] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A current-limiting circuit for a charge pump, the charge pump comprising a first capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor, the first capacitor, the second transistor, and the fourth transistor forming a first charge-discharge branch, the first capacitor, the first transistor, and the third transistor forming a second charge-discharge branch, the first charge-discharge branch and the second charge-discharge branch being alternately turned on to achieve voltage conversion; characterized in that, The current limiting circuit includes a first current limiting circuit and a second current limiting circuit. The first current limiting circuit is connected to the gate of the second transistor or the fourth transistor in the first charge-discharge branch. The first current limiting circuit is used to clamp the gate voltage of the second transistor or the fourth transistor, thereby controlling the current in the first charge-discharge branch to be less than or equal to the first current threshold. The second current limiting circuit is connected to the control electrode of the first transistor or the third transistor in the second charge-discharge branch. The second current limiting circuit is used to clamp the gate voltage of the first transistor or the third transistor, thereby controlling the current in the second charge-discharge branch to be less than or equal to the second current threshold.

2. The current-limiting circuit for a charge pump according to claim 1, characterized in that, The first current limiting circuit includes a first current mirror circuit, a second current mirror circuit, a current-to-voltage circuit, a first amplifier circuit, and a first driving circuit. The first current mirror circuit is used to generate a first current and output the first current to the second current mirror circuit and the first amplifier circuit, respectively. The second current mirror circuit is used to generate a second current based on the first current, and output the second current to the current-to-voltage circuit and the first amplifier circuit; The current-to-voltage circuit is used to generate a first clamping voltage based on the second current and output the first clamping voltage to the first amplifier circuit. The first amplifier circuit is configured to generate a first voltage clamping control signal based on the first current, the second current, and the first clamping voltage, and output the first voltage clamping control signal to the first driving circuit. The first driving circuit is used to generate a first driving control signal based on the first voltage clamping control signal. The first driving control signal is used to control the conduction degree of the second transistor or the fourth transistor, thereby controlling the current in the first charging and discharging branch to be less than or equal to the first current threshold.

3. The current-limiting circuit for a charge pump according to claim 2, characterized in that, The first current mirror circuit includes a first current source, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The negative terminal of the first current source is connected to the first terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor, the first terminal of the thirteenth transistor, the control terminal of the thirteenth transistor, and the control terminal of the fourteenth transistor, respectively. The second terminals of the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all grounded. The control electrode of the eleventh transistor is used to receive a second enable signal. The second enable signal is used to control the eleventh transistor to turn on when the charge pump reverse discharge is started, thereby controlling the first current mirror circuit to start working. The control electrode of the twelfth transistor is used to receive a third enable signal. The third enable signal is used to control the twelfth transistor to turn off after the charge pump reverse discharge is started, thereby controlling the first current mirror circuit to stop working.

4. The current-limiting circuit for a charge pump according to claim 3, characterized in that, The second current mirror circuit includes a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; The second terminal of the fifteenth transistor is used to receive the first supply voltage. The first terminal of the fifteenth transistor is connected to the first terminal of the fourteenth transistor, the control terminal of the fifteenth transistor, the first terminal of the sixteenth transistor, and the control terminal of the seventeenth transistor. The second terminals of the sixteenth transistor and the seventeenth transistor are both used to receive the first supply voltage. The first terminal of the seventeenth transistor is used to output the second current. The control electrode of the sixteenth transistor is also used to receive the second enable signal. The second enable signal is used to control the sixteenth transistor to turn on when the charge pump reverse discharge is started, thereby controlling the second current mirror circuit to start working.

5. The current-limiting circuit for a charge pump according to claim 4, characterized in that, The current-to-voltage circuit includes a first resistor and an eighteenth transistor; The first end of the first resistor is connected to the first electrode of the seventeenth transistor to receive the second current. The second end of the first resistor is connected to the first electrode of the eighteenth transistor and the control electrode of the eighteenth transistor, respectively. The second electrode of the eighteenth transistor is grounded. The first end of the first resistor is used to output the first clamping voltage.

6. The current-limiting circuit for a charge pump according to claim 5, characterized in that, The first amplifier circuit includes a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor; The second terminals of the nineteenth transistor and the twenty-fifth transistor are both used to receive the first power supply voltage. The control terminal of the nineteenth transistor is connected to the gate of the seventeenth transistor. The first terminal of the nineteenth transistor is connected to the second terminals of the twentyth and twenty-first transistors, respectively. The control terminal of the twentyth transistor is connected to the first terminal of the first resistor R1 to receive the first clamping voltage. The control terminal of the twenty-first transistor is connected to the second terminals of the twenty-fourth and twenty-fifth transistors, respectively. The first terminal of the twentyth transistor is connected to the first terminal of the twenty-second transistor, the control terminal of the twenty-second transistor, and the control terminal of the twenty-third transistor, respectively. The second terminals of the twenty-second and twenty-third transistors are both grounded. The control electrode of the 24th transistor is connected to the control electrode of the 14th transistor, and the second electrode of the 24th transistor is grounded; the control electrode of the 25th transistor is connected to the second electrode of the 23rd transistor, and the control electrode of the 25th transistor is used to output the first voltage clamping control signal.

7. The current-limiting circuit for a charge pump according to claim 6, characterized in that, The first driving circuit includes a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, and a twenty-ninth transistor; The control electrode of the 25th transistor is connected to the control electrode of the 26th transistor and the first electrode of the 27th transistor. The control electrode of the 26th transistor is used to receive the first voltage clamping control signal. The first electrode of the 26th transistor is connected to the first electrode of the 28th transistor. The second electrode of the 28th transistor is used to receive the first supply voltage. The control electrode of the 28th transistor is connected to the control electrode of the 29th transistor. The second electrode of the 26th transistor is connected to the first electrode of the 29th transistor. The second electrode of the 29th transistor is grounded. The second electrode of the 26th transistor is connected to the control electrode of the second transistor or the fourth transistor to output the first drive control signal to the second transistor or the fourth transistor. The second terminal of the 27th transistor is used to receive the first supply voltage, and the control terminal of the 27th transistor is used to receive the first enable signal. The first enable signal is used to control the 17th transistor to conduct when the charge pump reverse discharge is started, thereby controlling the first drive circuit to start working.

8. The current-limiting circuit for a charge pump according to claim 5, characterized in that, The second current limiting circuit includes a second amplifier circuit, a third current mirror circuit, a second resistor, and a second drive circuit; The input terminal of the second amplifier circuit is connected to the first terminal of the twenty-third transistor. The second amplifier circuit is used to generate a third current based on the reference voltage on the first terminal of the twenty-third transistor. The third current mirror circuit is used to generate a fourth current based on the third current and output the fourth current to the first terminal of the second resistor, and the second terminal of the second resistor is connected to the second terminal of the third transistor. The second driving circuit is used to sample the second clamping voltage on the first terminal of the second resistor and generate a second driving control signal based on the second clamping voltage. The second driving control signal is used to control the conduction degree of the first transistor or the third transistor, thereby controlling the current in the second charging and discharging branch to be less than or equal to the second current threshold.

9. The current-limiting circuit for a charge pump according to claim 8, characterized in that, The second amplifier circuit includes an amplifier, a thirty-first transistor, and a third resistor; The non-inverting input of the amplifier is connected to the first terminal of the 23rd transistor to sample the reference voltage on the first terminal of the 23rd transistor. The inverting input of the amplifier is connected to the first terminal of the third resistor and the second terminal of the 31st transistor, and the second terminal of the third resistor is grounded. The output of the amplifier is connected to the control terminal of the 31st transistor.

10. The current-limiting circuit for a charge pump according to claim 9, characterized in that, The third current mirror circuit includes a thirty-second transistor and a thirty-third transistor. The first terminal and the control terminal of the thirty-second transistor are both connected to the first terminal of the thirty-first transistor. The first terminal of the thirty-second transistor is used to receive a second supply voltage. The control terminal of the thirty-second transistor is connected to the control terminal of the thirty-third transistor. The second terminal of the thirty-third transistor is used to receive the second supply voltage. The first terminal of the thirty-third transistor is connected to the first end of the second resistor.

11. The current-limiting circuit for a charge pump according to claim 9, characterized in that, The second driving circuit includes the thirty-fourth transistor, the thirty-fifth transistor, and the thirty-sixth transistor; The second terminal of the thirty-fourth transistor is used to receive the second power supply voltage. The first terminal of the thirty-fourth transistor is connected to the first terminal of the thirty-fifth transistor, the second terminal of the thirty-fifth transistor is connected to the first terminal of the thirty-sixth transistor, the second terminal of the thirty-sixth transistor is grounded, and the control terminal of the thirty-fourth transistor is connected to the control terminal of the thirty-sixth transistor. The second terminal of the thirty-fifth transistor is also connected to the control terminal of the first transistor or the third transistor to output the second drive control signal to the first transistor or the third transistor.

12. A charge pump, characterized in that, The charge pump includes a current-limiting circuit for the charge pump as described in any one of claims 1-11.

13. A chip, characterized in that, The chip includes a current-limiting circuit for a charge pump as described in any one of claims 1-11; or the chip includes a charge pump as described in claim 12.

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