Single-inductor multi-output hybrid switching converter and control method thereof

Abstract

The invention discloses a single-inductor multi-output hybrid switching converter and a control method thereof. The single-inductor multi-output hybrid switching converter converts an input voltage into a first output voltage and a second output voltage. The sub-switching converter is used for converting an input voltage into a relay voltage; the first output switch and the second output switch respectively convert the relay voltage into first output voltage and second output voltage. The sub-switching converter comprises a switching capacitance voltage division circuit which is used for performing switching type capacitance operation and converting the first voltage into two divided voltages with different levels; one end of the inductor is coupled to the switching capacitance voltage division circuit, and the other end of the inductor is coupled to a second voltage. In different configurations, the inductor is coupled to the negative end or the positive end of the first capacitor, so that the first voltage and the reference potential are converted, or the first voltage and the first half of the first voltage are converted. The first voltage and the second voltage respectively correspond to one of the input voltage and the relay voltage and the other of the input voltage and the relay voltage.

Description

Technical Field

[0001] This invention relates to a hybrid switching converter with a single inductor and multiple outputs and its control method, and particularly to a hybrid switching converter with a single inductor and multiple outputs capable of generating multiple output voltages and its control method. Background Technology

[0002] Modern data centers, servers, electric vehicles, and various mobile devices often require power converters with multiple output voltages. With increasingly stringent space and heat dissipation requirements, designing high-power-density and high-efficiency power converters has become a crucial research and development challenge. Traditionally, a common solution is to employ a multi-power converter architecture, which uses multiple independent inductors and switches to support different outputs.

[0003] In existing technologies, such as Figure 1 The multi-output switching converter 10 shown provides multiple outputs through different combinations of switches and inductors. Figure 1 In this circuit, the input voltage Vin is simultaneously coupled to two buck converters. Switches Q1 and Q2, along with inductor L1, form the first buck converter, while switches Q3 and Q4, along with inductor L2, form the second buck converter, corresponding to the first output voltage Vout1 and the second output voltage Vout2, respectively. At the input end, input capacitor Cin1 is coupled to the input of the first buck converter, and input capacitor Cin2 is coupled to the input of the second buck converter to filter out voltage ripple on the input side. At the output end, output capacitor Co1 is coupled to the output of the first buck converter to stabilize its output voltage, and output capacitor Co3 is coupled to the output of the second buck converter to stabilize its output voltage. Simultaneously, output capacitor Co2 is coupled to the first output voltage Vout1, and output capacitor Co4 is coupled to the second output voltage Vout2 to further reduce output noise and stabilize the output voltages. It is worth noting that output switch Q5 is coupled between the first buck converter and the first output voltage Vout1, and is used to convert the output voltage of the first buck converter to the first output voltage Vout1; output switch Q6 is coupled between the second buck converter and the second output voltage Vout2, and is used to convert the output voltage of the second buck converter to the second output voltage Vout2.

[0004] exist Figure 1In the multi-output switching converter 10 shown, the switches Q1-Q4 in each buck converter need to withstand the highest value of the input voltage Vin to ensure stable operation. Since the input voltage Vin can be quite high, the voltage withstand capability requirements for switches Q1-Q4 increase accordingly, which also means that the internal on-resistance of switches Q1-Q4 is high and the conduction loss is large. Furthermore, in order to perform energy conversion at high voltages, conventional buck converters also need to be equipped with large inductors L1 and L2 to cope with the voltage difference between the input voltage Vin and the first output voltage Vout1 and the second output voltage Vout2. The size and cost of inductors L1 and L2 thus increase, making it difficult to further reduce the overall power supply size or increase power density.

[0005] Since each output requires an independent buck converter and inductor, system layout and heat dissipation face greater challenges. In high-temperature environments or when heat dissipation space is limited, ensuring stability and long-term reliability often requires additional heat dissipation designs or higher-specification components, further increasing cost and complexity.

[0006] In multi-output applications, traditional methods require the reuse of multiple power converters. If the system needs to support multiple different voltage outputs simultaneously (such as USB ports, system core voltage, external power supply voltage, etc.), the number of components and wiring complexity increase significantly, making it difficult to integrate into a single chip or module.

[0007] In view of this, in order to solve the above problems and achieve the goals of high density, high efficiency and easy integration at the same time, this invention proposes a hybrid switching converter with single inductor and multiple outputs and its control method, in order to significantly reduce the voltage stress and inductance requirements of the switching elements while maintaining stable output and high efficiency, and thereby improve the integration and reliability of the system. Summary of the Invention

[0008] In one viewpoint, the present invention provides a single-inductor multi-output hybrid switching converter for converting an input voltage into a first output voltage and a second output voltage. The single-inductor multi-output hybrid switching converter includes: a sub-switching converter for converting the input voltage into a relay voltage; a first output switch for conducting during a first inductor cycle according to a first time-division signal to convert the relay voltage into the first output voltage; and a second output switch for conducting during a second inductor cycle according to a second time-division signal to convert the relay voltage into the second output voltage; wherein the sub-switching converter includes: a switching capacitor voltage divider circuit, which, during the first inductor cycle, controls the switching voltage according to a first set of pulse width modulation signals. Multiple switches are configured to perform switched capacitor operation, converting a first voltage into a first voltage group with two different levels. During a second inductor cycle, the multiple switches are controlled according to a second set of pulse width modulation signals to perform switched capacitor operation, converting the first voltage into a second voltage group with two different levels. An inductor has a first terminal coupled to the switched capacitor voltage divider circuit and a second terminal coupled to a second voltage. During the first inductor cycle, according to the first set of pulse width modulation signals, the first terminal of the inductor switches between two different levels of the first voltage group. During the second inductor cycle, according to the second set of pulse width modulation signals, the first terminal of the inductor switches between two different levels of the second voltage group. Between different levels; and a control circuit for generating the first set of pulse width modulation signals, the second set of pulse width modulation signals, the first time-division signal, and the second time-division signal to time-division control the plurality of switches, the first output switch, and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage, and periodically generating the first output voltage and the second output voltage during the first inductor cycle and the second inductor cycle respectively; wherein the first voltage and the second voltage respectively correspond to one and the other of the input voltage and the relay voltage; wherein the control circuit is also used for the first inductor cycle In the first inductor cycle, based on a first feedback signal related to the first output voltage, the first output voltage is adjusted to a first target voltage, and in the second inductor cycle, based on a second feedback signal related to the second output voltage, the second output voltage is adjusted to a second target voltage; wherein, the single-inductor multi-output hybrid switching converter operates in a boundary conduction mode (BCM) or a discontinuous conduction mode (DCM) during the first inductor cycle and the second inductor cycle; wherein, a first configuration of the sub-switching converter refers to the inductor being coupled to the negative terminal of a first capacitor of the switching capacitor voltage divider circuit, and a second configuration of the sub-switching converter refers to the inductor being coupled to the positive terminal of the first capacitor of the switching capacitor voltage divider circuit;In the first configuration, the sub-switching converter converts the first voltage into two different levels: half of the first voltage and a reference potential. In the second configuration, it converts the first voltage into two different levels: the first voltage and half of the first voltage. During a charging phase, the first capacitor of the switching capacitor voltage divider circuit is connected in series with a second capacitor of the same circuit between the first voltage and the reference potential. During a discharging phase, the first capacitor and the second capacitor are connected in parallel with the reference potential.

[0009] In another viewpoint, the present invention provides a control method for a single-inductor multi-output hybrid switching converter, comprising: converting an input voltage into a relay voltage; according to a first time-division signal, during a first inductor cycle, conducting a first output switch to output the relay voltage as a first output voltage; and according to a second time-division signal, during a second inductor cycle, conducting a second output switch to output the relay voltage as a second output voltage; wherein the step of converting the input voltage into the relay voltage includes: during the first inductor cycle, controlling a plurality of switches according to a first set of pulse width modulation signals to perform switched capacitor operation, thereby converting the first voltage into a first group of voltages at two different levels; and during the second inductor cycle, controlling the plurality of switches according to a second set of pulse width modulation signals to perform switched capacitor operation, thereby converting the first voltage into a second group of voltages at two different levels; and during the first inductor cycle, switching a first terminal of an inductor between two different levels of the first group of voltages according to the first set of pulse width modulation signals. During the second inductor cycle, according to the second set of pulse width modulation signals, the first terminal of the inductor is switched between two different levels of the second voltage group; the first terminal of the inductor is controlled to be coupled to the negative terminal of a first capacitor to form a first configuration, and the first voltage is converted into two different levels, half of the first voltage and a reference potential, within the first inductor cycle or the second inductor cycle; the first terminal of the inductor is controlled to be coupled to the positive terminal of the first capacitor to form a second configuration, and the first voltage is converted into two different levels, the first voltage and half of the first voltage, within the first inductor cycle. Or, within the second inductor cycle; during a charging phase, the first capacitor and the second capacitor are connected in series between the first voltage and the reference potential to store charge; during a discharging phase, the first capacitor and the second capacitor are connected in parallel to the reference potential to release charge; the first set of pulse width modulation signals and the second set of pulse width modulation signals are used to time-division control the multiple switches, and periodically, in the first inductor cycle and the second inductor cycle, the same inductor is subjected to excitation and demagnetization operations to perform power conversion between the first voltage and the second voltage; wherein the first voltage and the second voltage respectively correspond to Given one of the input voltage and the other of the relay voltage; using the first time-division signal and the second time-division signal, time-division control is applied to the first output switch and the second output switch, and the first output voltage and the second output voltage are periodically generated correspondingly during the first inductor cycle and the second inductor cycle; and during the first inductor cycle, the first output voltage is adjusted to a first target voltage based on a first feedback signal related to the first output voltage, and during the second inductor cycle, the second output voltage is adjusted to a second target voltage based on a second feedback signal related to the second output voltage;The single-inductor multi-output hybrid switching converter operates in either a boundary conduction mode (BCM) or a discontinuous conduction mode (DCM) during the first inductor cycle and the second inductor cycle.

[0010] In one embodiment, the switching capacitor voltage divider circuit achieves a capacitor balance state in each of the first inductor cycle and each of the second inductor cycle.

[0011] In one embodiment, the control circuit includes: a first error amplifier for amplifying the difference between the first output voltage feedback signal and a first reference signal to generate a first error amplification signal; a second error amplifier for amplifying the difference between the second output voltage feedback signal and a second reference signal to generate a second error amplification signal; and a modulation circuit for generating the first set of pulse width modulation signals according to the first error amplification signal during the first inductor cycle, and generating the second set of pulse width modulation signals according to the second error amplification signal during the second inductor cycle.

[0012] In one embodiment, the control circuit further includes a current sensing circuit to sense the inductor current and generate an inductor current signal, and the modulation circuit further generates the first set of pulse width modulation signals and the second set of pulse width modulation signals based on the inductor current signal.

[0013] In one embodiment, the current sensing circuit further generates a zero-current signal when the inductor current is zero; wherein the control circuit further includes a logic circuit for generating the first time-division signal and the second time-division signal based on the zero-current signal.

[0014] In one embodiment, the control circuit further includes a logic circuit for generating the first time-division signal and the second time-division signal according to a clock signal.

[0015] In one embodiment, the control circuit further includes a logic circuit for generating a time-division switching control signal, the first time-division signal, and the second time-division signal based on the first error amplification signal, the second error amplification signal, and a clock signal or a zero-current signal; wherein the time-division switching control signal, the first time-division signal, and the second time-division signal are all triggered by the clock signal or the zero-current signal, and the first time-division signal and the second time-division signal are out of phase with each other; wherein the logic circuit further determines whether the single-inductor multi-output hybrid switching converter enters a skip mode based on the difference between a first output current and a second output current; wherein in the skip mode, the difference between the number of times the first inductor cycle and the number of times the second inductor cycle are positively correlated with the difference between the first output current and the second output current within a unit cycle.

[0016] In one embodiment, the current sensing circuit includes a sensing resistor and a sensing capacitor, wherein the sensing resistor and the sensing capacitor are connected in series and coupled to the inductor. The inductor current is sensed by the voltage across the sensing capacitor to generate the inductor current signal. A time constant of the sensing resistor and the sensing capacitor is matched with a time constant of the inductor and the DC resistance of the inductor.

[0017] In one embodiment, the power supply between the first voltage and the second voltage is converted into a boost converter or a buck converter.

[0018] In one embodiment, when the switching capacitor voltage divider circuit and the inductor are configured in a buck configuration, the sub-switching converter further includes a boost switch coupled between the second terminal of the inductor and a reference potential, so that the single-inductor multi-output hybrid switching converter can select to operate in a boost conversion or a buck conversion according to the first target voltage or the second target voltage.

[0019] In one embodiment, the first set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the first voltage group, and the second set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the second voltage group.

[0020] In one embodiment, at the end of each first inductor cycle, a starting point of a ramp signal is triggered, and at the end of each second inductor cycle, another starting point of the ramp signal is triggered; wherein the modulation circuit compares the ramp signal with the first error amplification signal in the first inductor cycle to generate the first set of pulse width modulation signals; wherein the modulation circuit compares the ramp signal with the second error amplification signal in the second inductor cycle to generate the second set of pulse width modulation signals; wherein the first inductor cycle and the second inductor cycle are alternately arranged and repeat periodically in sequence.

[0021] This invention offers significant improvements over existing technologies, particularly in reducing system size, increasing efficiency, and enhancing power density. Firstly, compared to traditional methods requiring multiple buck converters (each with its own inductor and switch), the single-inductor configuration proposed in this invention supports multiple output voltage conversions, simplifying circuit design and significantly reducing the number of components required, thereby improving overall system integration and saving space. This innovation not only reduces the physical size of the system but also further improves power density and operating efficiency. Furthermore, since only a single inductor is needed, the inductor size in this system is significantly reduced compared to traditional multi-inductor operation, reducing space requirements and manufacturing costs, thus simplifying design and maintenance. Simultaneously, the switching capacitor voltage divider circuit effectively reduces the voltage stress applied to the inductor, reducing the need for high-voltage switching components and extending the overall system lifespan. Lower-voltage switching components can then be used, further reducing system cost. Finally, compared to the potentially high losses in traditional technologies, this technology helps improve system energy efficiency. In this case, the system's ZCS (Zero Current Switching) operating mode is actively utilized. These high-efficiency soft-switching technologies allow switching elements to switch near zero current, significantly reducing switching losses and electromagnetic interference (EMI), thereby improving overall operating efficiency. This not only optimizes the energy conversion process in existing systems but also demonstrates the energy-saving potential of this solution. Finally, this technology eliminates the need for additional capacitor balancing control circuitry, a challenge often encountered in traditional multi-capacitor systems. The absence of an additional control system to manage voltage balance in the flight capacitors greatly simplifies control circuit design, improves system stability and reliability, and reduces design complexity. In summary, this technology overcomes the limitations of existing technologies, providing a more efficient, compact, and easy-to-use solution.

[0022] Compared to traditional multi-output buck converters that require a separate inductor for each output, this design uses a single inductor to support multiple outputs simultaneously. By integrating inductor resources and a switched capacitor architecture, not only is the amount of bulky inductors reduced, but also the layout space wasted by stacking multiple inductors is avoided. As the overall system component count decreases, mutual interference between components is also reduced, thereby improving overall design efficiency and reliability.

[0023] In terms of power density, by retaining only one inductor and effectively reducing its value, the converter's size can be significantly reduced, contributing to an improvement in overall power density. Furthermore, this design employs a high-efficiency switching capacitor conversion mechanism, which minimizes conduction and switching losses during energy transfer, further enhancing system efficiency. Since high efficiency means less heat generation, it also simplifies the heat dissipation design, improving the overall system reliability and portability.

[0024] In terms of switching element design, hybrid switching converters significantly reduce voltage stress on the switches through boosting or voltage division. On the one hand, switches with lower withstand voltage ratings can be selected, reducing component cost and size; on the other hand, combined with zero-current or zero-voltage switching (ZCS / ZVS) technology, switching losses and electromagnetic interference during switching operation are also relatively reduced, which helps to further improve efficiency and suppress noise.

[0025] Furthermore, this design employs a two-capacitor switching capacitor voltage divider circuit in its system architecture. The switching capacitor's operation automatically achieves dynamic charge balance in each inductor cycle—that is, each inductor magnetization and demagnetization operation—significantly reducing the charge balancing time. Combining these features, this design not only achieves higher power density and efficiency but also reduces system complexity, thus demonstrating superior overall benefits compared to existing technologies in multi-output power supply applications.

[0026] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0027] Figure 1 This is a circuit diagram showing a known switching converter with multiple outputs.

[0028] Figure 2A and Figure 2B This is a circuit block diagram of a hybrid switching converter with a single inductor and multiple outputs according to an embodiment of the present invention.

[0029] Figure 2C and Figure 2D This is a circuit diagram illustrating the switching capacitor voltage divider circuit of a single-inductor multi-output hybrid switching converter during the charging and discharging phases, according to an embodiment of the present invention.

[0030] Figure 3 show Figures 2A-2D A circuit diagram of a more specific embodiment of the hybrid switching converter 20 with single inductor and multiple outputs and the neutron switching converter 21.

[0031] Figure 4 show Figures 2A-2DA circuit diagram of a more specific embodiment of the control circuit 213 in a hybrid switching converter 20 with single inductor and multiple outputs.

[0032] Figure 5 show Figures 2A-2D A circuit diagram of another specific embodiment of the control circuit 213 in the hybrid switching converter 20 with single inductor and multiple outputs.

[0033] Figure 6 This is a circuit diagram of a ramp signal generation circuit for a display control circuit according to an embodiment of the present invention.

[0034] Figure 7 show Figures 2A-2D A circuit diagram of another specific embodiment of the control circuit 213 in the hybrid switching converter 20 with single inductor and multiple outputs.

[0035] Figure 8 This is a circuit diagram of the logic circuit of the display control circuit according to an embodiment of the present invention.

[0036] Figure 9 This is a circuit diagram of the current sensing circuit of the display control circuit according to an embodiment of the present invention.

[0037] Figure 10 This is a schematic diagram of the signal waveforms of a hybrid switching converter with multiple outputs for a single inductor, according to an embodiment of the present invention.

[0038] Figure 11 This is a schematic diagram of the signal waveforms of a hybrid switching converter with multiple outputs for a single inductor, according to an embodiment of the present invention.

[0039] Figure 12 show Figures 2A-2D A circuit diagram of another more specific embodiment of the hybrid switching converter 20 with single inductor and multiple outputs and the neutron switching converter 21.

[0040] Figure 13A This is a schematic diagram of a display logic circuit according to an embodiment of the present invention.

[0041] Figure 13B This is a schematic diagram illustrating the time-sharing switch control signal Sab of a single-inductor multi-output hybrid switching converter operating in normal mode according to an embodiment of the present invention.

[0042] Figure 13C This is a schematic diagram illustrating the time-division switching control signal Sab of a single-inductor multi-output hybrid switching converter operating in skip mode according to an embodiment of the present invention.

[0043] Figure 13DThis is a schematic diagram illustrating the time-division switching control signal Sab of a single-inductor multi-output hybrid switching converter operating in another skip mode according to an embodiment of the present invention.

[0044] Figure 14A and Figure 14B The circuit diagrams for the first and second configurations of the switching capacitor voltage divider circuit are shown respectively.

[0045] Explanation of symbols in the diagram

[0046] 10: Switching converter with multiple outputs

[0047] 20: Single-inductor multi-output hybrid switching converter

[0048] 21: Sub-switching converter

[0049] 211: Switching capacitor voltage divider circuit

[0050] 213: Control Circuit

[0051] 2131: Modulation circuit

[0052] 2132: Current sensing circuit

[0053] 2133: Ramp signal generation circuit

[0054] 21331: Logic Control Circuit

[0055] 21334: Time-sharing control logic circuit

[0056] 21341: First Type D flip-flop

[0057] 21342: Second Type D flip-flop

[0058] C1: First capacitor

[0059] Cin, Cin1, Cin2: Input capacitors

[0060] Ck: Switching clock signal

[0061] Clk: Clock signal

[0062] Co1, Co2, Co3, Co4: Output capacitors

[0063] iL: Inductor current

[0064] Iout1: First output current

[0065] Iout2: Second output current

[0066] Is1, Is2: Current sources

[0067] L1, L2: Inductors

[0068] Co: Output capacitor

[0069] CRP: Reset capacitor

[0070] Cx: Sensing capacitance

[0071] D1, D2: Endpoints

[0072] G: Common endpoint

[0073] Q1, Q2, Q3, Q4: Switches

[0074] Q5, Q6: Output switches

[0075] Rx: Sensing resistance

[0076] S1~S4: Pulse width modulation signals

[0077] S5: First time-sharing control signal

[0078] S6: Second time-sharing control signal

[0079] Sab: Time-sharing switch control signal

[0080] Scom1: First error amplification signal

[0081] Scom2: Second error amplification signal

[0082] SiL: Inductor current signal

[0083] SL: Inductor current signal

[0084] Stg: Trigger signal

[0085] Szc: Zero Current Signal

[0086] Srp: Reset switch

[0087] t0~t8: Time points

[0088] Tsw: Cell period

[0089] V1: First voltage

[0090] V2: Second voltage

[0091] Vin: Input voltage

[0092] Vout1: First output voltage

[0093] Vout2: Second output voltage

[0094] Vref1: First reference signal

[0095] Vref2: Second reference signal

[0096] Vramp: ramp signal

[0097] Vcomp: Error amplification output signal Detailed Implementation

[0098] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0099] Figure 2A and 2B This is a circuit block diagram illustrating a single-inductor, multi-output hybrid switching converter according to an embodiment of the present invention. Figure 2A As shown, the single-inductor multi-output hybrid switching converter 20 of the present invention is used to convert the input voltage Vin into a first output voltage Vout1 and a second output voltage Vout2, and correspondingly generate a first output current Iout1 and a second output current Iout2. The single-inductor multi-output hybrid switching converter 20 includes a sub-switching converter 21, a first output switch Q5, and a second output switch Q6. The sub-switching converter 21 is used to convert the input voltage Vin into a relay voltage Vm. The first output switch Q5 is coupled between the relay voltage Vm and the first output voltage Vout1, and is turned on during a first inductor cycle according to a first time-division signal S5, so as to convert the relay voltage Vm into the first output voltage Vout1. The second output switch Q6 is coupled between the relay voltage Vm and the second output voltage Vout2, and is turned on during a second inductor cycle according to a second time-division signal S6, so as to convert the relay voltage Vm into the second output voltage Vout2.

[0100] Next, please refer to Figure 2B ,like Figure 2BAs shown, the sub-switching converter 21 includes a switching capacitor voltage divider circuit 211, an inductor L1, and a control circuit 213. During the first inductor cycle, the switching capacitor voltage divider circuit 211 controls multiple switches (not shown, but detailed later) according to a first set of pulse width modulation signals PWM1 to perform a switching capacitor operation, converting the first voltage V1 into two different levels of the first voltage group. During the second inductor cycle, it controls multiple switches (not shown, but detailed later) according to a second set of pulse width modulation signals PWM2 to perform a switching capacitor operation, converting the first voltage V1 into two different levels of the second voltage group. The inductor L1 has a first terminal N1 and a second terminal N2. The first terminal N1 is coupled to the switching capacitor voltage divider circuit 211, and the second terminal N2 is coupled to the second voltage V2. During the first inductor cycle, the first terminal N1 of inductor L1 switches between two different levels of the first voltage group according to the duty cycle of the first pulse width modulation signal PWM1; during the second inductor cycle, the first terminal N1 of inductor L1 switches between two different levels of the second voltage group according to the duty cycle of the second pulse width modulation signal PWM2. In other words, the first pulse width modulation signal PWM1 determines the duty cycle of the first terminal N1 of inductor L1 switching between the two different levels of the first voltage group, and the second pulse width modulation signal PWM2 determines the duty cycle of the first terminal N1 of inductor L1 switching between the two different levels of the second voltage group. The control circuit 213 generates a first set of pulse width modulation signals PWM1, a second set of pulse width modulation signals PWM2, a first time-division signal S5, and a second time-division signal S6 to control the switching of multiple switches in the capacitor voltage divider circuit 211, the first output switch Q5, and the second output switch Q6 in a time-division manner. It periodically magnetizes and demagnetizes the same inductor L1 during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage V1 and the second voltage V2, and periodically generates the first output voltage Vout1 and the second output voltage Vout2 during the first inductor cycle and the second inductor cycle, respectively.

[0101] The first voltage V1 and the second voltage V2 correspond to one of the input voltage Vin and the other of the relay voltage Vm, respectively. In one embodiment, the first voltage V1 is the input voltage Vin, and the second voltage V2 is the relay voltage Vm. In this case, the switching capacitor voltage divider circuit 211 and the inductor L1 are configured in a buck configuration, meaning that in some embodiments without additional switches, the relay voltage Vm is lower than the input voltage Vin. In another embodiment, the first voltage V1 is the relay voltage Vm, and the second voltage V2 is the input voltage Vin. In this case, the switching capacitor voltage divider circuit 211 and the inductor L1 are configured in a boost configuration, meaning that Vm is higher than the input voltage Vin.

[0102] The control circuit 213 is also used to adjust the first output voltage Vout1 to a first target voltage based on a first feedback signal Vfb1 related to the first output voltage Vout1 during the first inductor cycle, and to adjust the second output voltage Vout2 to a second target voltage based on a second feedback signal Vfb2 related to the second output voltage Vout2 during the second inductor cycle. The single-inductor multi-output hybrid switching converter 20 operates in boundary conduction mode (BCM) or discontinuous conduction mode (DCM) during the first and second inductor cycles.

[0103] Figure 2C and Figure 2D This is a circuit diagram illustrating the switching capacitor voltage divider circuit of a single-inductor multi-output hybrid switching converter during the charging and discharging phases, according to an embodiment of the present invention. In this embodiment, for ease of understanding, multiple switches in the switching capacitor voltage divider circuit are omitted. These switches, during the charging and discharging phases, electrically connect the first capacitor and the second capacitor as follows: Figure 2C and Figure 2D The circuit.

[0104] like Figure 2C As shown, in the charging phase, the switching capacitor voltage divider circuit 211 connects the first capacitor C1 and the second capacitor C2 in series between the first voltage V1 and the reference potential (ground potential in this specification, the same below). In the discharging phase, as... Figure 2D As shown, after the first capacitor C1 and the second capacitor C2 are connected in parallel, the negative terminals of both the first capacitor C1 and the second capacitor C2 are coupled to the reference potential.

[0105] Furthermore, the first configuration of the sub-switching converter 21 refers to the inductor L1 being coupled to the negative terminal of the first capacitor C1 of the switching capacitor voltage divider circuit 211, that is, as Figure 2C and Figure 2D The single-pole double-throw (SPDT) switch shown is configured to electrically connect the common terminal G and terminal D2; and the second configuration of the sub-switching converter 21 refers to the inductor L1 being coupled to the positive terminal of the first capacitor C1 of the switching capacitor voltage divider circuit 211, that is, as Figure 2C and Figure 2DThe single-pole double-throw switch shown is configured to electrically connect the common terminal G and terminal D1. In the first configuration, the sub-switching converter 21 converts the first voltage V1 at the common terminal G into two different levels: half the first voltage V1 and a reference potential. In other words, in the first configuration, the voltage at the common terminal G switches between these two different levels. In the second configuration, the first voltage V1 at the common terminal G is converted into two different levels: the first voltage V1 and half the first voltage V1. In other words, in the second configuration, the voltage at the common terminal G switches between these two different levels.

[0106] Figure 3 show Figures 2A-2D A circuit diagram of a more specific embodiment of the hybrid switching converter 20 with single inductor and multiple outputs and the neutron switching converter 21. (See diagram for example.) Figure 3 As shown, the sub-switching converter 21 includes a switching capacitor voltage divider circuit 211, an inductor L1, and a control circuit 213. In this embodiment, the first voltage V1 is, for example, the input voltage Vin, and the second voltage V2 is, for example, the relay voltage Vm. The switching capacitor voltage divider circuit 211 and the inductor L1 are configured in a step-down configuration, and the sub-switching converter 21 is in the first configuration (the inductor L1 is coupled to the negative terminal of the first capacitor C1). The switching capacitor voltage divider circuit 211 includes, for example, switches Q1, Q2, Q3, and Q4, the first capacitor C1, and the second capacitor C2. The switching capacitor voltage divider circuit 211 converts the input voltage Vin into two voltage dividers at different levels using a switching capacitor voltage divider method, that is, a voltage divider between half of the input voltage Vin and the ground potential at two different levels. Switches Q1, Q2, Q3, and Q4 are connected in series between the input voltage Vin and the ground potential; and the first capacitor C1 is connected in parallel with the series-connected switches Q2 and Q3, and the second capacitor C2 is electrically connected between the node between switches Q2 and Q3 and the ground potential.

[0107] By properly operating switches Q1-Q4, during the charging phase, the first capacitor C1 is first charged to half the input voltage Vin, so that the voltage at the first terminal N1 of inductor L1 is the output voltage Vin minus half the input voltage Vin, which is half the input voltage Vin. Then, during the subsequent discharging phase, the first terminal N1 of inductor L1 is electrically connected to the ground potential, so as to realize the conversion of the input voltage Vin into a voltage divider between the half input voltage Vin and the ground potential, so that the first terminal N1 of inductor L1 switches between these two different levels (half the input voltage Vin and the ground potential).

[0108] In this embodiment, the first set of pulse width modulation signals PWM1 refers to pulse width modulation signals S1-S4 within the first inductor cycle, and the second set of pulse width modulation signals PWM2 refers to pulse width modulation signals S1-S4 within the second inductor cycle; wherein pulse width modulation signals S1-S4 correspond to control switches Q1-Q4. In this embodiment, the first group of voltages at two different levels is, for example, half of the input voltage Vin and the ground potential; the second group of voltages at two different levels is also, for example, half of the input voltage Vin and the ground potential. That is, within the first inductor cycle, the first set of pulse width modulation signals, for example, converts the input voltage Vin into two different levels: half of the input voltage Vin and the ground potential; and within the second inductor cycle, the second set of pulse width modulation signals, for example, also converts the input voltage Vin into two different levels: half of the input voltage Vin and the ground potential. The operational details will be described in detail later.

[0109] Figure 4 show Figures 2A-2D A circuit diagram of a more specific embodiment of the control circuit 213 in a hybrid switching converter 20 with single inductor and multiple outputs. (See diagram for example.) Figure 4 As shown, the control circuit 213 includes a first error amplifier EA1, a second error amplifier EA2, and a modulation circuit 2131. The first error amplifier EA1 amplifies the difference between the first output voltage feedback signal Vfb1 and the first reference signal Vref1 to generate a first error amplified signal Scom1. The second error amplifier EA2 amplifies the difference between the second output voltage feedback signal Vfb2 and the second reference signal Vref2 to generate a second error amplified signal Scom2. The first reference signal Vref1 is related to the first target voltage of the first output voltage Vout1; the second reference signal Vref2 is related to the second target voltage of the second output voltage Vout2.

[0110] The modulation circuit 2131 is used to generate a first set of pulse width modulation signals PWM1 based on the first error amplification signal Scom1 during the first inductor cycle, and to generate a second set of pulse width modulation signals PWM2 based on the second error amplification signal Scom2 during the second inductor cycle. The first set of pulse width modulation signals PWM1 refers to the pulse width modulation signals S1-S4 within the first inductor cycle, and the second set of pulse width modulation signals PWM2 refers to the pulse width modulation signals S1-S4 within the second inductor cycle.

[0111] Please continue reading. Figure 4In this embodiment, the modulation circuit 2131 includes a time-division switch SWab, a comparator CP, and a PWM signal generation circuit PWMGen. During the first inductor cycle, the time-division switch SWab electrically connects the first error amplifier EA1 to the comparator CP to transmit the first error amplification signal Scom1 to the comparator CP. The first error amplification signal Scom1 is used as the error amplification signal Vcomp and compared with the ramp signal Vramp. During the second inductor cycle, the second error amplifier EA2 is electrically connected to the comparator CP to transmit the second error amplification signal Scom2 to the comparator CP. The second error amplification signal Scom2 is used as the error amplification signal Vcomp and compared with the ramp signal Vramp.

[0112] In this embodiment, during the first inductor cycle, the comparator CP compares the first error amplification signal Scom1 with the ramp signal Vramp. The comparison result is then processed by the PWM signal generation circuit PWMGen to generate pulse width modulation signals S1, S2, S3 and S4 during the first inductor cycle, which serve as the first set of pulse width modulation signals PWM1.

[0113] In this embodiment, during the second inductor cycle, the comparator CP compares the second error amplification signal Scom2 with the ramp signal Vramp. The comparison result is then processed by the PWM signal generation circuit PWMGen to generate pulse width modulation signals S1, S2, S3 and S4 during the second inductor cycle, which serve as the second set of pulse width modulation signals PWM2.

[0114] Figure 5 show Figures 2A-2D A circuit diagram of another more specific embodiment of the control circuit 213 in the single-inductor multi-output hybrid switching converter 20. This embodiment is similar to... Figure 4 The difference in the embodiment shown is that in this embodiment, the control circuit 213 further includes a current sensing circuit 2132 to sense the inductor current iL flowing through the inductor L1 and generate an inductor current signal SiL. The modulation circuit 2131 also generates a first set of pulse width modulation signals PWM1 and a second set of pulse width modulation signals PWM2 based on the inductor current signal SiL.

[0115] For example, comparator CP can superimpose the inductor current signal SiL and the ramp signal Vramp, and then compare the result with the error amplification signal Vcomp to generate pulse width modulation signals S1, S2, S3, and S4. Similarly, comparator CP can superimpose the inductor error amplification signal Vcomp and the inductor current signal SiL, and then compare this result with the ramp signal Vramp to generate pulse width modulation signals S1, S2, S3, and S4. Again, comparator CP can superimpose the inductor current signal SiL with the result of comparing the error amplification signal Vcomp and the ramp signal Vramp to generate pulse width modulation signals S1, S2, S3, and S4.

[0116] Figure 6 This is a circuit diagram of a ramp signal generation circuit for a display control circuit according to an embodiment of the present invention. The control circuit 213 may also include, for example, a ramp signal generation circuit 2133. Figure 6 As shown, the ramp signal generation circuit 2133 includes a logic control circuit 21331, a pulse generator PG, a current source Is, a reset switch Srp, and a capacitor Crup. In boundary conduction mode (BCM) operation, the logic control circuit 21331 generates a switching clock signal Ck based on the zero-current signal Szc. In discontinuous conduction mode (DCM) operation, the logic control circuit 21331 generates a switching clock signal Ck based on the clock signal Clk. In one embodiment, the switching clock signal Ck can be a clock signal Clk with a fixed period, or the switching clock signal Ck can be a signal determined by the zero-current signal Szc and the control loop. The pulse generator PG generates a trigger signal Stg based on the switching clock signal Ck. The current source Is is coupled to the internal voltage Vcc and is powered by the internal power supply in the circuit.

[0117] The reset switch Srp operates according to the trigger signal Stg to control the current source Is to charge and discharge the capacitor Crp, thereby generating a ramp signal Vramp on the capacitor Crp. In one embodiment, after the trigger signal Stg is triggered, when the ramp signal Vramp is lower than the error amplification signal Vcomp, the comparator CP generates a comparison signal Scp to control the PWM signal generation circuit PWMGen, generating pulse width modulation signals S1, S2, S3, and S4.

[0118] Figure 7 show Figures 2A-2D A circuit diagram of another specific embodiment of the control circuit 213 in the single-inductor multi-output hybrid switching converter 20. Compared to Figure 5The control circuit 213 shown in this embodiment, the current sensing circuit 2132, also generates a zero-current signal Szc when the inductor current iL is zero current Izc. The control circuit 213 further includes a logic circuit 2134, which generates a first time-sharing signal S5, a second time-sharing signal S6, and a time-sharing switch control signal Sab based on the zero-current signal Szc. The time-sharing switch control signal Sab controls the time-sharing switch SWab, so that during the first inductor cycle, the time-sharing switch SWab electrically connects the first error amplifier EA1 to the comparator CP, and during the second inductor cycle, the second error amplifier EA2 is electrically connected to the comparator CP.

[0119] Figure 8 This is a circuit diagram of the logic circuit of the display control circuit according to an embodiment of the present invention. Figure 7 In the illustrated embodiment, the control circuit 213 further includes, for example, logic circuit 2134. In this embodiment, as... Figure 8 As shown, the logic circuit 2134 includes, for example, a D-type flip-flop. The input pin D of the D-type flip-flop receives the inverted signal from its output pin Q. When the clock pin of the D-type flip-flop receives a zero-current signal Szc or a clock signal Clk, its internal logic circuit performs state transitions according to preset trigger conditions. Based on the result of its digital logic operation, it generates a first time-sharing signal S5 and a time-sharing switch control signal Sab at the output pin Q, and a second time-sharing signal S6 at the inverted output pin Q'. The first time-sharing signal S5 controls the first output switch Q5, while the time-sharing switch control signal Sab controls the time-sharing switch SWab, and the second time-sharing signal S6 controls the second output switch Q6. In this way, the two time-sharing signals (the first time-sharing signal S5 and the second time-sharing signal S6) can alternately control the first output switch Q5 and the second output switch Q6 in a time-sharing manner, thereby generating the corresponding first output voltage Vout1 and second output voltage Vout2 during the periodic first inductor cycle and the second inductor cycle, respectively. In addition to controlling the first output switch Q5 and the second output switch Q6, the time-sharing switch control signal Sab can be used to operate the time-sharing switch SWab as described above.

[0120] Figure 9 This is a circuit diagram of a current sensing circuit for a display control circuit according to an embodiment of the present invention. Figure 5 In the illustrated embodiment, the control circuit 213 further includes, for example, a current sensing circuit 2132. In this embodiment, as... Figure 9As shown, the current sensing circuit 2132 includes a sensing resistor Rx and a sensing capacitor Cx, wherein the sensing resistor Rx and the sensing capacitor Cx are connected in series and coupled to the inductor L1. The inductor current iL is sensed by the voltage across the sensing capacitor Cx to generate an inductor current signal SiL. The time constant of the sensing resistor Rx and the sensing capacitor Cx is matched with the time constant of the inductor L1 and the DC resistance DCR of the inductor L1.

[0121] Figure 10 This is a schematic diagram of signal waveforms for a single-inductor multi-output hybrid switching converter according to an embodiment of the present invention. The horizontal axis represents time t, and the vertical axis displays the signal waveforms corresponding to each signal. This embodiment uses a periodic first inductor cycle and a second inductor cycle as an example, where time points t0 to t6 represent one unit cycle Tsw, comprising one first inductor cycle and one second inductor cycle. In this embodiment, the single-inductor multi-output hybrid switching converter operates in boundary conduction mode (BCM) during each first inductor cycle and each second inductor cycle. It should be noted that the unit cycle Tsw refers to a complete cycle in the single-inductor multi-output hybrid switching converter that completes the switching operation and energy conversion process of all outputs; this cycle repeats continuously and periodically during the operation of the single-inductor multi-output hybrid switching converter.

[0122] Between time points t0 and t3, the single-inductor multi-output hybrid switching converter is in the first inductor cycle. During this period, the time-sharing switch control signal Sab controls the time-sharing switch SWab to a high level, for example, to electrically connect the first error amplifier EA1 to the comparator CP. The first time-sharing signal S5 turns on the first output switch Q5, and the second time-sharing signal S6 does not turn on the second output switch Q6. Between time points t0 and t1, the first error amplifier signal Scom1 is higher than the ramp signal Vramp, causing the pulse width modulation (PWM) signal S1 to be at a high level, thus turning on switch Q1. Simultaneously, the PWM signal S2 is the inverted signal of PWM signal S1 and is at a low level, therefore switch Q2 is not turned on; the PWM signal S3 is the inverted signal of PWM signal S2 and is therefore at a high level, turning on switch Q3; the PWM signal S4 is the inverted signal of PWM signal S1 and is therefore at a low level, turning off switch Q4. Therefore, from time t0 to time t1, switch Q1 is on, switch Q2 is off, switch Q3 is on, and switch Q4 is off, so that the first capacitor C1 and the second capacitor C2 are connected in series between the input voltage Vin and the ground potential. At this time, the first capacitor C1 is charged, and the voltage at the first terminal N1 of inductor L1 is half of the input voltage Vin (that is, the difference between the input voltage Vin and the voltage across the first capacitor C1: Vin-Vin / 2). Inductor L1 is energized, and the inductor current iL gradually increases, and the first output current Iout1 also gradually increases at the same time.

[0123] During the time interval from time t1 to time t2, the first error amplification signal Scom1 is lower than the ramp signal Vramp, and the PWM signal S1 is at a low level, causing switch Q1 to not conduct. Simultaneously, the PWM signal S2 is the inverted signal of PWM signal S1 and is at a high level, therefore switch Q2 conducts. The PWM signal S3 is the inverted signal of PWM signal S2, therefore the PWM signal S3 is at a low level, and therefore switch Q3 does not conduct. The PWM signal S4 is the inverted signal of PWM signal S1, therefore the PWM signal S4 is at a high level, and therefore switch Q4 conducts. Therefore, from time t1 to time t2, switch Q1 is not conducting, switch Q2 is conducting, switch Q3 is not conducting, and switch Q4 is conducting, causing the first terminal N1 of inductor L1 to be electrically connected to the reference potential (in this embodiment, the reference potential is ground potential). Inductor L1 is demagnetized, and the inductor current iL gradually decreases, and the first output current Iout1 also gradually decreases simultaneously. In other words, during the time interval from time t0 to time t2, the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential.

[0124] At time t2, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches the clock signal Ck according to the zero current signal Szc, and ends the first inductor cycle accordingly. Between time t2 and time t3, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, the second inductor cycle begins at time t3. It should be noted that between time point t0 and time point t3, a complete excitation (from the time point when the inductor current iL is zero current Izc to the time point when the ramp signal Vramp exceeds the first error amplification signal Scom1) and demagnetization (from the time point when the ramp signal Vramp exceeds the first error amplification signal Scom1 to the time point when the inductor current iL is zero current Izc) of the inductor L1 is completed, plus a preset idle time, which is defined as a first inductor cycle.

[0125] Between time points t3 and t6, the single-inductor multi-output hybrid switching converter is in the second inductor cycle. During this period, the time-sharing switch control signal Sab controls the time-sharing switch SWab to, for example, a low level, to electrically connect the second error amplifier EA2 to the comparator CP. The first time-sharing signal S5 does not turn on the first output switch Q5, and the second time-sharing signal S6 turns on the second output switch Q6. Between time points t3 and t4, the second error amplifier signal Scom2 is higher than the ramp signal Vramp, causing the PWM signal S1 to be at a high level, thus turning on switch Q1. Simultaneously, the PWM signal S2 is the inverted signal of PWM signal S1 and is at a low level, therefore switch Q2 is not turned on; the PWM signal S3 is the inverted signal of PWM signal S2, therefore PWM signal S3 is at a high level, and switch Q3 is turned on; the PWM signal S4 is the inverted signal of PWM signal S1, therefore PWM signal S4 is at a low level, and switch Q4 is not turned on. Therefore, from time point t3 to time point t4, switch Q1 is on, switch Q2 is off, switch Q3 is on, and switch Q4 is off, so that the first capacitor C1 and the second capacitor C2 are connected in series between the input voltage Vin and the ground potential. At this time, the first capacitor C1 is charged, and the voltage at the first terminal N1 of inductor L1 is half of the input voltage Vin (that is, the difference between the input voltage and the voltage across the first capacitor C1: Vin-Vin / 2). Inductor L1 is energized, and the inductor current iL gradually increases, and the second output current Iout2 also gradually increases at the same time.

[0126] During the time interval from time t4 to time t5, the second error amplification signal Scom2 is lower than the ramp signal Vramp, and the PWM signal S1 is at a low level, causing switch Q1 to not conduct. Simultaneously, the PWM signal S2 is the inverted signal of PWM signal S1 and is at a high level, therefore switch Q2 conducts. The PWM signal S3 is the inverted signal of PWM signal S2, therefore the PWM signal S3 is at a low level, and therefore switch Q3 does not conduct. The PWM signal S4 is the inverted signal of PWM signal S1, therefore the PWM signal S4 is at a high level, and therefore switch Q4 conducts. Therefore, from time t4 to time t5, switch Q1 is not conducting, switch Q2 is conducting, switch Q3 is not conducting, and switch Q4 is conducting, causing the first terminal N1 of inductor L1 to be electrically connected to the reference potential (in this embodiment, the reference potential is ground potential). Inductor L1 is demagnetized, and the inductor current iL gradually decreases, and the second output current Iout2 also gradually decreases simultaneously. In other words, during the time interval from time t3 to time t5, the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential.

[0127] At time t5, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches the clock signal Ck according to the zero current signal Szc, and ends the second inductor cycle accordingly. Between time t5 and time t6, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, another first inductor cycle begins at time t6. It should be noted that between time t3 and time t6, a complete excitation (from the time when the inductor current iL is zero current Izc to the time when the ramp signal Vramp exceeds the second error amplification signal Scom2) and demagnetization (from the time when the ramp signal Vramp exceeds the second error amplification signal Scom2 to the time when the inductor current iL is zero current Izc), plus the preset dead time, is defined as a second inductor cycle. Subsequently, another first inductor cycle begins at time t6.

[0128] In this embodiment, the first capacitor C1 is charged and discharged in a single first inductor cycle (e.g., from time t0 to time t3), thereby reaching a balanced state and ensuring stable operation. On the other hand, the first capacitor C1 is charged and discharged in a single second inductor cycle (e.g., from time t3 to time t6), thereby reaching a balanced state and ensuring stable operation.

[0129] Furthermore, in this embodiment, the start point of the ramp signal Vramp is triggered at the end of each first inductor cycle and at the end of each second inductor cycle.

[0130] Figure 11 This is a schematic diagram of the signal waveforms of a single-inductor, multi-output hybrid switching converter according to an embodiment of the present invention. This embodiment, for example, takes the periodic repetition of a first inductor cycle and a second inductor cycle as an example, where time points t0 to t8 represent one unit cycle Tsw, comprising one first inductor cycle and one second inductor cycle. In each first inductor cycle, the single-inductor, multi-output hybrid switching converter operates in boundary conduction mode (BCM) operation. This embodiment and... Figure 10 Unlike the illustrated embodiment, in this embodiment, each second inductor cycle operates in discontinuous conduction mode (DCM). The following... Figure 11 and Figure 10 Different parts of the narrative.

[0131] In this embodiment, at time t6, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. However, the logic control circuit 21331 switches the clock signal Ck based on the clock signal Clk instead of the zero current signal Szc, and ends the second inductor cycle accordingly. Therefore, the dead time between time t6 and time t8 is relatively long. Figure 10 In the illustrated embodiment, the preset idle time is long, and this idle time maintains the inductor current iL at zero current Izc. Other parts (i.e., time points t0 to t3, t3 to t5, and t7 to t8) and... Figure 10 The embodiments shown are the same; please refer to [link / reference]. Figure 10 The illustrated examples are as follows.

[0132] Figure 12 show Figures 2A-2D A circuit diagram of another more specific embodiment of the hybrid switching converter 20 with single inductor and multiple outputs and the neutron switching converter 21. This embodiment is similar to... Figure 3 The sub-switching converter 21 in the single-inductor multi-output hybrid switching converter 20 shown differs in that, in this embodiment, the sub-switching converter 21 further includes a boost switch Q7, coupled between the second terminal N2 of the inductor L1 and a reference potential (ground potential in this embodiment), so that the single-inductor multi-output hybrid switching converter 20 can select to operate in boost conversion or buck conversion depending on whether the first target voltage or the second target voltage is higher than the input voltage Vin.

[0133] The boost switch Q7 provides flexibility for the single-inductor, multi-output hybrid switching converter 20 under different target voltage requirements. For example, when the first or second target voltage is higher than the input voltage Vin, the boost switch Q7 switches with either the first output switch Q5 or the second output switch Q6 to achieve boost power conversion. This configures the switching capacitor voltage divider circuit 211, inductor L1, and boost switch Q7 into a boost configuration. In this configuration, the first terminal N1 of inductor L1 can be electrically connected to the input voltage Vin, and the energy of inductor L1 can be stored and released to the output voltage terminal to increase the output voltage Vout1 or Vout2 to the target value.

[0134] On the other hand, when the first target voltage or the second target voltage is lower than the input voltage Vin, the boost switch Q7 is turned off, and the switching capacitor voltage divider circuit 211 and the inductor L1 are directly configured in a buck configuration. In this configuration, the inductor L1, in conjunction with the switching capacitor voltage divider circuit 211, reduces the input voltage Vin, providing a stable first target voltage or second target voltage lower than the input voltage Vin.

[0135] In one embodiment, the first terminal N1 of inductor L1 can be switched to half of the input voltage Vin by switching capacitor conversion. At the same time, it can be switched between the aforementioned boost switch Q7 and the first output switch Q5 or the second output switch Q6 to perform boost power conversion of half of the input voltage Vin.

[0136] Figure 13A This is a schematic diagram of a display logic circuit according to an embodiment of the present invention. Figures 13B-13D This diagram shows the Sab waveform of the time-sharing switch control signal with normal mode and skip mode. (Example) Figure 13A As shown, the logic circuit 2134 of the control circuit 213 is used to generate a time-sharing switch control signal Sab, a first time-sharing signal S5, and a second time-sharing signal S6 based on the first error amplification signal Scom1, the second error amplification signal Scom2, and the clock signal Clk or the zero-current signal Szc. The time-sharing switch control signal Sab, the first time-sharing signal S5, and the second time-sharing signal S6 are all triggered by the clock signal Clk or the zero-current signal Szc, and the first time-sharing signal S5 and the second time-sharing signal S6 are inverted, while the time-sharing switch control signal Sab and the first time-sharing signal S5 are synchronized. Compared to... Figure 8 The embodiment of the logic circuit 2134 shown is as follows: Figure 13AIn the embodiment of the logic circuit 2134 shown, the voltage difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 is used to determine whether the single-inductor multi-output hybrid switching converter 20 enters skip mode. In skip mode, the difference between the number of the first inductor cycles and the number of the second inductor cycles within a unit cycle is positively correlated with the difference between the first output current Iout and the second output current Iout. In one embodiment, particularly in BCM and DCM, the voltage difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 is positively correlated with the difference between the first output current Iout and the second output current Iout.

[0137] Figure 13B This is a schematic diagram illustrating the time-sharing switch control signal Sab of a single-inductor multi-output hybrid switching converter operating in normal mode according to an embodiment of the present invention. In this embodiment, when the single-inductor multi-output hybrid switching converter is in normal mode, the time-sharing switch control signal Sab periodically and sequentially alternates between a logic high level and a logic low level between the first output (the output terminal that generates the first output voltage Vout1) and the second output (the output terminal that generates the second output voltage Vout2), so that the two output terminals sequentially generate stable and continuous waveforms, thereby meeting the requirements of load demand and stable system operation. Figure 13B The time-division switching control signal Sab waveform shown illustrates this, exhibiting the characteristic of alternating high and low levels within a fixed period.

[0138] In one embodiment, when the first output load corresponding to the first output voltage Vout1 and the first output current Iout1, and the second output load corresponding to the second output voltage Vout2 and the second output current Iout2, are both not lightly loaded and the difference is less than a load threshold, for example, when the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 is less than a threshold, the logic circuit 2134 periodically and alternately sets the first time-sharing signal S5 and the second time-sharing signal S6 to the enable level, so that the single-inductor multi-output hybrid switching converter operates in normal mode. For example, Figure 10 The illustrated embodiment illustrates that the process involves periodically repeating two consecutive first inductor cycles followed by two consecutive second inductor cycles.

[0139] Figure 13C This is a schematic diagram illustrating the time-division switching control signal Sab of a single-inductor multi-output hybrid switching converter operating in a skip mode according to an embodiment of the present invention. Figure 13DThis is a schematic diagram illustrating the time-sharing switch control signal Sab of a single-inductor multi-output hybrid switching converter operating in a skip mode according to an embodiment of the present invention. For example, when the single-inductor multi-output hybrid switching converter senses that the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 exceeds a preset first threshold, the logic circuit 2134 will activate the skip mode, such as... Figure 13C The time-sharing switch control signal Sab shown indicates that in each unit cycle Tsw, a high-order quasi-pulse of the second time-sharing signal S6 is skipped. For example, in one embodiment, each unit cycle Tsw skips two sequential second inductor cycles, that is, it periodically repeats four consecutive first inductor cycles followed by two consecutive second inductor cycles.

[0140] When the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 continuously increases and remains above a preset second threshold for a preset period, the logic circuit 2134 dynamically adjusts the high and low level time ratio of the time-sharing switch control signal Sab according to the change in the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2. Specifically, as the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 continuously increases, the duration or proportion of the logic high level in the time-sharing switch control signal Sab will gradually increase, while the proportion of the logic low level will relatively decrease. Figure 13D The time-sharing switch control signal Sab shown indicates that each unit cycle Tsw skips two high-order quasi-pulses of the second time-sharing signal S6. For example, in one embodiment, each unit cycle Tsw skips four second inductor cycles, that is, periodically repeating six consecutive first inductor cycles followed by two consecutive second inductor cycles.

[0141] This adjustment mechanism is called skip mode. Its function is to reduce the number of switching cycles by deliberately skipping some switching cycles when the output load is light, thereby reducing energy loss and electromagnetic interference caused by frequent switching, while still maintaining basic control over the output voltage.

[0142] Of course, when both the first output load and the second output load are lightly loaded, the logic circuit 2134 can also skip at least one high-level pulse of the first time-sharing signal S5 and at least one high-level pulse of the second time-sharing signal S6 in each unit cycle Tsw.

[0143] Figure 14A and Figure 14B The circuit diagrams for the first and second configurations of the switching capacitor voltage divider circuit are shown respectively. Please refer to them. Figure 2C and Figure 2D , Figure 14AThis illustrates a more specific embodiment of the first configuration of the switching capacitor voltage divider circuit, namely... Figure 2C and Figure 2D In the configuration, the common terminal G and terminal D2 are electrically connected. Please refer to the following: Figure 2C and Figure 2D , Figure 14B This illustrates a more specific embodiment of the second configuration of the switching capacitor voltage divider circuit, namely... Figure 2C and Figure 2D In the configuration, the common terminal G is electrically connected to the terminal D1.

[0144] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to enable those skilled in the art to easily understand the content of the invention and is not intended to limit the broadest scope of the invention. The various embodiments described are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can be used to replace corresponding components in another embodiment. For example, Figure 14B The second configuration of the switching capacitor voltage divider circuit shown can be applied to Figures 3-5 , Figure 7 and Figure 12 The single-inductor multi-output hybrid switching converter 20 is described above. Furthermore, within the same spirit of the invention, those skilled in the art will conceive of various equivalent variations and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" as used in this invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art will conceive of various equivalent variations and combinations, many of which are not listed here. Thus, the scope of the invention should cover the above and all other equivalent variations.

Claims

1. A single-inductor multi-output hybrid switching converter for converting an input voltage into a first output voltage and a second output voltage, the single-inductor multi-output hybrid switching converter comprising: A sub-switching converter is used to convert the input voltage into a relay voltage; A first output switch is configured to be turned on during a first inductor cycle according to a first time-division signal, so as to convert the relay voltage into the first output voltage. as well as A second output switch is configured to be turned on during a second inductor cycle according to a second time-division signal, so as to convert the relay voltage into the second output voltage; The sub-switching converter includes: A switching capacitor voltage divider circuit controls multiple switches according to a first set of pulse width modulation signals during a first inductor cycle to perform switching capacitor operation, thereby converting a first voltage into a first group of voltages at two different levels. During a second inductor cycle, the circuit controls the multiple switches according to a second set of pulse width modulation signals to perform switching capacitor operation, thereby converting the first voltage into a second group of voltages at two different levels. An inductor, one first terminal of which is coupled to the switching capacitor voltage divider circuit, and the other second terminal of which is coupled to a second voltage; During the first inductor cycle, the first terminal of the inductor switches between two different voltage levels of the first group according to the first set of pulse width modulation signals; During the second inductor cycle, according to the second set of pulse width modulation signals, the first terminal of the inductor switches between two different levels of the second voltage group; and A control circuit is used to generate the first set of pulse width modulation signals, the second set of pulse width modulation signals, the first time-division signal, and the second time-division signal to control the multiple switches, the first output switch, and the second output switch in a time-division manner. It periodically performs magnetization and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage. It also periodically generates the first output voltage and the second output voltage during the first inductor cycle and the second inductor cycle, respectively. The first voltage and the second voltage respectively correspond to one of the input voltage and the other of the relay voltage; The control circuit is further configured to, during the first inductor cycle, adjust the first output voltage to a first target voltage based on a first feedback signal related to the first output voltage, and during the second inductor cycle, adjust the second output voltage to a second target voltage based on a second feedback signal related to the second output voltage; The single-inductor multi-output hybrid switching converter operates in a boundary conduction mode or a discontinuous conduction mode during the first inductor cycle and the second inductor cycle. Wherein, a first configuration of the sub-switching converter refers to the inductor being coupled to the negative terminal of a first capacitor in the switching capacitor voltage divider circuit, and a second configuration of the sub-switching converter refers to the inductor being coupled to the positive terminal of the first capacitor in the switching capacitor voltage divider circuit. In the first configuration, the sub-switching converter converts the first voltage into two different levels: half of the first voltage and a reference potential. In the second configuration, it converts the first voltage into two different levels: the first voltage and half of the first voltage. In the charging phase, the first capacitor of the switching capacitor voltage divider circuit is connected in series with a second capacitor of the switching capacitor voltage divider circuit between the first voltage and the reference potential, and in the discharging phase, the first capacitor and the second capacitor are connected in parallel with the reference potential.

2. The single-inductor multi-output hybrid switching converter as described in claim 1, wherein, The switching capacitor voltage divider circuit achieves a capacitor balance state in each of the first inductor cycle and each of the second inductor cycle.

3. The hybrid switching converter with single inductor and multiple outputs as described in claim 1, wherein, The control circuit includes: A first error amplifier is used to amplify the difference between the first output voltage feedback signal and a first reference signal to generate a first error amplification signal; A second error amplifier is used to amplify the difference between the second output voltage feedback signal and a second reference signal to generate a second error amplification signal; and A modulation circuit is used to generate the first set of pulse width modulation signals according to the first error amplification signal during the first inductor cycle, and to generate the second set of pulse width modulation signals according to the second error amplification signal during the second inductor cycle.

4. The single-inductor multi-output hybrid switching converter as described in claim 3, wherein, The control circuit also includes a current sensing circuit to sense the inductor current and generate an inductor current signal, and the modulation circuit generates the first set of pulse width modulation signals and the second set of pulse width modulation signals based on the inductor current signal.

5. The single-inductor multi-output hybrid switching converter as described in claim 4, wherein, The current sensing circuit also generates a zero-current signal when the inductor current is zero. The control circuit also includes a logic circuit for generating the first time-division signal and the second time-division signal based on the zero current signal.

6. The single-inductor multi-output hybrid switching converter as described in claim 3, wherein, The control circuit also includes a logic circuit for generating the first time-division signal and the second time-division signal according to a clock signal.

7. The single-inductor multi-output hybrid switching converter as described in claim 3, wherein, The control circuit also includes a logic circuit for generating a time-division switching control signal, the first time-division signal and the second time-division signal based on the first error amplification signal and the second error amplification signal, as well as a clock signal or a zero current signal. The time-sharing switch control signal, the first time-sharing signal, and the second time-sharing signal are all triggered by the clock signal or the zero-current signal, and the first time-sharing signal and the second time-sharing signal are inverses of each other; The logic circuit also determines whether the single-inductor multi-output hybrid switching converter enters a skip mode based on the difference between a first output current and a second output current. In this skip mode, the difference between the number of times the first inductor cycle and the number of times the second inductor cycle are positively correlated with the difference between the first output current and the second output current within a unit cycle.

8. The single-inductor multi-output hybrid switching converter as described in claim 4, wherein, The current sensing circuit includes a sensing resistor and a sensing capacitor, wherein the sensing resistor and the sensing capacitor are connected in series and coupled to the inductor. The inductor current is sensed by the voltage across the sensing capacitor to generate the inductor current signal. The time constant of the sensing resistor and the sensing capacitor is matched with the time constant of the inductor and the DC resistance of the inductor.

9. The single-inductor multi-output hybrid switching converter as described in claim 1, wherein, The power supply between the first voltage and the second voltage is converted into a boost converter or a buck converter.

10. The single-inductor multi-output hybrid switching converter as described in claim 1, wherein, When the switching capacitor voltage divider circuit and the inductor are configured in a buck configuration, the sub-switching converter also includes a boost switch coupled between the second terminal of the inductor and the reference potential, so that the single-inductor multi-output hybrid switching converter can select to operate in a boost conversion or a buck conversion according to the first target voltage or the second target voltage.

11. The single-inductor multi-output hybrid switching converter as described in claim 1, wherein, The first set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the first voltage group, and the second set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the second voltage group.

12. The single-inductor multi-output hybrid switching converter as described in claim 5, wherein, At the end of each first inductor cycle, a ramp signal is triggered at one start point, and at the end of each second inductor cycle, the ramp signal is triggered at another start point. The modulation circuit compares the ramp signal with the first error amplification signal during the first inductor cycle to generate the first set of pulse width modulation signals. The modulation circuit compares the ramp signal with the second error amplification signal during the second inductor cycle to generate the second set of pulse width modulation signals. The first inductor cycle and the second inductor cycle are alternately arranged and repeated periodically in sequence.

13. A control method for a single-inductor, multi-output hybrid switching converter, comprising: Convert an input voltage to a relay voltage; According to a first time-division signal, within a first inductor cycle, a first output switch is turned on to output the relay voltage as a first output voltage; and According to a second time-division signal, within a second inductor cycle, a second output switch is turned on to output the relay voltage as a second output voltage; in, The steps for converting the input voltage to the relay voltage include: During the first inductor cycle, multiple switches are controlled according to a first set of pulse width modulation signals to perform switching capacitor operation, thereby converting a first voltage into a first set of voltages at two different levels. During the second inductor cycle, the multiple switches are controlled according to a second set of pulse width modulation signals to perform switching capacitor operation, thereby converting the first voltage into a second set of voltages at two different levels. During the first inductor cycle, according to the first set of pulse width modulation signals, a first terminal of an inductor is switched between two different voltage levels of the first set of voltage. During the second inductor cycle, the first terminal of the inductor is switched between two different voltage levels of the second group according to the second set of pulse width modulation signals; The first terminal of the inductor is coupled to the negative terminal of a first capacitor to form a first configuration, and the first voltage is converted into two different levels, one half of the first voltage and a reference potential, within the first inductor cycle or the second inductor cycle. The first terminal of the inductor is coupled to the positive terminal of the first capacitor to form a second configuration, and the first voltage is converted into two different levels, the first voltage and half of the first voltage, within the first inductor cycle or the second inductor cycle. During a charging phase, the first capacitor and a second capacitor are connected in series between the first voltage and the reference potential to store charge; During a discharge phase, the first capacitor and the second capacitor are connected in parallel to the reference potential to release the charge; The first set of pulse width modulation signals and the second set of pulse width modulation signals are used to control the multiple switches in a time-division manner, and the same inductor is periodically magnetized and demagnetized during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage. The first voltage and the second voltage respectively correspond to one of the input voltage and the other of the relay voltage; Using the first time-division signal and the second time-division signal, the first output switch and the second output switch are controlled in a time-division manner, and the first output voltage and the second output voltage are generated periodically during the first inductor cycle and the second inductor cycle, respectively; and During the first inductor cycle, the first output voltage is adjusted to a first target voltage based on a first feedback signal related to the first output voltage, and during the second inductor cycle, the second output voltage is adjusted to a second target voltage based on a second feedback signal related to the second output voltage; The single-inductor multi-output hybrid switching converter operates in a boundary conduction mode or a discontinuous conduction mode during the first inductor cycle and the second inductor cycle.

14. The control method for a single-inductor multi-output hybrid switching converter as described in claim 13, wherein, Each of the first inductor cycle and each of the second inductor cycle achieves a capacitor balance state.

15. The control method for a single-inductor, multi-output hybrid switching converter as described in claim 13, wherein, The steps of time-division controlling the multiple switches, the first output switch, and the second output switch, and periodically performing magnetization and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage include: The difference between the first output voltage feedback signal and a first reference signal is amplified to generate a first error amplification signal; Amplify the difference between the second output voltage feedback signal and a second reference signal to generate a second error amplification signal; and During the first inductor cycle, the first set of pulse width modulation signals is generated based on the first error amplification signal, and during the second inductor cycle, the second set of pulse width modulation signals is generated based on the second error amplification signal.

16. The control method for a single-inductor, multi-output hybrid switching converter as described in claim 15, wherein, The step of time-division controlling the multiple switches, the first output switch and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: sensing the inductor current and generating an inductor current signal, and generating the first set of pulse width modulation signals and the second set of pulse width modulation signals based on the inductor current signal.

17. The control method for a single-inductor, multi-output hybrid switching converter as described in claim 16, wherein, The step of time-division controlling the multiple switches, the first output switch, and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: Furthermore, based on the inductor current signal, a zero-current signal is generated when the inductor current is zero; and Based on the zero-current signal, the first time-division signal and the second time-division signal are generated.

18. The control method for a single-inductor multi-output hybrid switching converter as described in claim 15, wherein, The step of time-division control of the multiple switches, the first output switch and the second output switch, and periodically magnetizing and demagnetizing the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: generating the first time-division signal and the second time-division signal according to a clock signal.

19. The control method for a single-inductor, multi-output hybrid switching converter as described in claim 15, wherein, The step of time-division controlling the multiple switches, the first output switch, and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: Based on the first error amplification signal, the second error amplification signal, and a clock signal or a zero-current signal, a time-division switching control signal, the first time-division signal, and the second time-division signal are generated; and Based on a voltage difference between the first error amplification signal and the second error amplification signal, it is determined whether the single-inductor multi-output hybrid switching converter enters a skip mode. The time-sharing switch control signal, the first time-sharing signal, and the second time-sharing signal are all triggered by the clock signal or the zero-current signal, and the first time-sharing signal and the second time-sharing signal are inverses of each other; In this skip mode, the difference between the number of times the first inductor cycle and the number of times the second inductor cycle are positively correlated with the difference between a first output current and a second output current within a unit cycle.

20. The control method for a single-inductor multi-output hybrid switching converter as described in claim 16, wherein, The step of sensing the inductor current and generating an inductor current signal includes: providing a sensing resistor and a sensing capacitor, wherein the sensing resistor and the sensing capacitor are connected in series and coupled to the inductor, and sensing the inductor current through the voltage across the sensing capacitor to generate the inductor current signal, wherein a time constant of the sensing resistor and the sensing capacitor is matched with a time constant of the inductor and the DC resistance of the inductor.

21. The control method for a single-inductor, multi-output hybrid switching converter as described in claim 13, wherein, The power supply between the first voltage and the second voltage is converted into a boost converter or a buck converter.

22. The control method for a single-inductor, multi-output hybrid switching converter as described in claim 13, wherein, The first set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the first voltage group, and the second set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the second voltage group.

23. The control method for a single-inductor multi-output hybrid switching converter as described in claim 17, wherein, At the end of each first inductor cycle, a ramp signal is triggered at one start point, and at the end of each second inductor cycle, the ramp signal is triggered at another start point. The modulation circuit compares the ramp signal with the first error amplification signal during the first inductor cycle to generate the first set of pulse width modulation signals. The modulation circuit compares the ramp signal with the second error amplification signal during the second inductor cycle to generate the second set of pulse width modulation signals. The first inductor cycle and the second inductor cycle are alternately arranged and repeated periodically in sequence.

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