Reconfigurable duplexer and ultra-wideband high-efficiency power amplifier

Abstract

The invention relates to a reconfigurable duplexer and an ultra-wideband high-efficiency power amplifier, and the reconfigurable duplexer comprises a substrate, a first microstrip line, a second microstrip line equivalent to ground capacitance, a third microstrip line equivalent to ground inductance, a fourth microstrip line, a first port, a second port, a third port and a common bonding pad, the first microstrip line, the second microstrip line, the third microstrip line and the fourth microstrip line are integrated on the substrate, the first microstrip line is connected with the first port, the first microstrip line is further connected with the second microstrip line, the second microstrip line is further connected with the common bonding pad, the third microstrip line is connected with the common bonding pad, and the third microstrip line is further connected with the fourth microstrip line. The fourth microstrip line is further connected with the second port, and the common bonding pad is further connected with the third port. According to the low-loss reconfigurable duplexer, due to the novel low-loss reconfigurable duplexer structure, a pit for frequency transition between sub-passbands can be smoothed or slowed down, and good gain flatness and output performance of an ultra-wideband power amplifier system in a working full frequency band are guaranteed.

Description

Technical Field

[0001] This invention relates to the field of radio frequency microwave technology, specifically to a reconfigurable duplexer and an ultrawideband high-efficiency power amplifier. Background Technology

[0002] As wireless communication systems evolve towards higher bandwidth and higher spectral efficiency, higher demands are placed on the operating bandwidth of power amplifiers. Traditional single broadband power amplifiers often face challenges such as decreased efficiency and deteriorated gain flatness while expanding bandwidth.

[0003] An effective ultra-wideband power amplifier design method involves designing two broadband power amplifiers operating in different frequency bands. Then, duplexers covering these two sub-bands are used as input and output networks, connecting the two sub-amplifiers to achieve frequency splicing and reconstruction, thus significantly widening the overall operating bandwidth. This architecture mitigates the challenge of optimal impedance matching for high efficiency over a wide bandwidth caused by violating the Bode-Fano criterion, while maintaining the original performance advantages of the two sub-amplifiers. In this architecture, the duplexer responsible for synthesizing signals from different frequency bands should typically possess characteristics such as low insertion loss, high out-of-band rejection, and good channel isolation to avoid synthesis loss affecting efficiency and to suppress mutual interference and spurious radiation between power amplifiers. While traditional frequency division duplexers can achieve frequency domain separation and synthesis of two signals, the difficulty in achieving ideal square wave switching between the two sub-bands results in a certain transition band between adjacent passbands. This leads to frequency "pits" in overlapping or adjacent regions, causing a sharp drop in the synthesis efficiency of the power amplifier at those frequencies, severely limiting the overall performance of the ultra-wideband power amplifier.

[0004] Therefore, there is an urgent need to find a new type of low-loss duplexer structure that can "smooth out" or mitigate the "pits" in frequency transition between sub-passbands, thereby improving the in-band efficiency and gain flatness of ultra-wideband power amplifiers. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a reconfigurable duplexer and an ultra-wideband high-efficiency power amplifier. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a reconfigurable duplexer, comprising: a substrate, a first microstrip line, a second microstrip line equivalent to a ground capacitance, a third microstrip line equivalent to a ground inductance, a fourth microstrip line, a first port, a second port, a third port, and a common pad, wherein the first microstrip line, the second microstrip line, the third microstrip line, and the fourth microstrip line are integrated on the substrate, wherein: The first microstrip line is connected to the first port, the first microstrip line is also connected to the second microstrip line, the second microstrip line is also connected to the common pad, the third microstrip line is connected to the common pad, the third microstrip line is also connected to the fourth microstrip line, the fourth microstrip line is also connected to the second port, and the common pad is also connected to the third port.

[0006] In one embodiment of the present invention, the reconfigurable duplexer further includes DC blocking capacitor C2, DC blocking capacitor C5, and DC blocking capacitor C6, wherein: The DC blocking capacitor C2 is connected between the first port and the first microstrip line, the DC blocking capacitor C5 is connected between the second port and the fourth microstrip line, and the DC blocking capacitor C6 is connected between the third port and the common pad. In one embodiment of the present invention, the reconfigurable duplexer further includes a series inductor L1, a PIN diode PIN1, a PIN diode PIN2, a first ground microstrip line having several vias, and a second ground microstrip line having several vias, wherein: The series inductor L1 is connected between the second microstrip line and the common pad. The anodes of the PIN diode PIN1 and the PIN diode PIN2 are both connected to the second microstrip line. The cathode of the PIN diode PIN1 is connected to the first ground microstrip line, and the PIN diode PIN1 is grounded through the first ground microstrip line. The cathode of the PIN diode PIN2 is connected to the second ground microstrip line, and the PIN diode PIN2 is grounded through the second ground microstrip line. In one embodiment of the present invention, the reconfigurable duplexer further includes a current-limiting resistor R1 and an RF choke inductor Lb1, wherein: The current-limiting resistor R1 is connected to the bias voltage terminal V1. The current-limiting resistor R1 is also connected to the RF choke inductor Lb1, which is also connected to the first microstrip line, so as to supply power to the PIN diode PIN1 and the PIN diode PIN2 through the bias voltage terminal V1.

[0007] In one embodiment of the present invention, the reconfigurable duplexer further includes a series capacitor C1, a DC blocking capacitor to ground C4, and a third grounded microstrip line having several vias, wherein: The series capacitor C1 is connected between the third microstrip line and the common pad, and the DC blocking capacitor C4 is connected between the third microstrip line and the third ground microstrip line to ground through the third ground microstrip line. In one embodiment of the present invention, the reconfigurable duplexer further includes a PIN diode PIN3 and a fourth grounded microstrip line having several vias, wherein: The anode of the PIN diode PIN3 is connected to the fourth microstrip line, the cathode of the PIN diode PIN3 is connected to the fourth grounded microstrip line, and the PIN diode PIN3 is grounded through the fourth grounded microstrip line. In one embodiment of the present invention, the reconfigurable duplexer further includes a current-limiting resistor R2 and an RF choke inductor Lb2, wherein, The current-limiting resistor R2 is connected to the bias voltage terminal V2. The current-limiting resistor R2 is also connected to the RF choke inductor Lb2. The RF choke inductor Lb2 is also connected to the fourth microstrip line so as to supply power to the PIN diode PIN3 through the bias voltage terminal V2. In one embodiment of the invention, the reconfigurable duplexer further includes an RF-to-ground inductor L2, a DC blocking capacitor C3, pads, and a fifth ground microstrip line having several vias, wherein: The fifth grounding microstrip line, the DC blocking capacitor C3, the pad, the RF-to-ground inductor L2, and the common pad are connected in sequence. In one embodiment of the present invention, the width W2 of the second microstrip line is greater than the width W4 of the fourth microstrip line, the width W1 of the first microstrip line is greater than the width W3 of the third microstrip line, and the length L3 of the third microstrip line is greater than the length L2 of the second microstrip line. Secondly, the present invention also provides an ultra-wideband high-efficiency power amplifier, comprising a first power amplifier operating in different frequency bands, a second power amplifier, and two reconfigurable duplexers as described in any of the above embodiments, wherein... The two outputs of one of the reconfigurable duplexers are respectively connected to the inputs of the first power amplifier and the second power amplifier, and the outputs of the first power amplifier and the second power amplifier are respectively connected to the two inputs of another reconfigurable duplexer.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a reconfigurable duplexer. The reconfigurable duplexer provided by this invention can flexibly adapt to and optimize the passband characteristics of two power amplifiers with different frequency bands by electronically reconfiguring between two filter structures of Π-type low-pass and Π-type high-pass. It effectively avoids the performance "pit" generated at the frequency band boundary of the traditional fixed structure, improves the in-band efficiency and gain flatness of the duplexer broadband or ultra-wideband power amplifier, and ensures good gain flatness and output performance of the ultra-wideband power amplifier system across the entire frequency band.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] Figure 1This is a circuit diagram of a reconfigurable duplexer provided by the present invention; Figure 2 This is a circuit dimension diagram of a reconfigurable duplexer provided by the present invention; Figure 3 This is an architectural diagram of an ultra-wideband high-efficiency power amplifier provided by the present invention; Figure 4 This is a simulation diagram of the S-parameters of the reconfigurable duplexer provided by this invention, operating in both low-frequency and high-frequency paths. Figure 5 These are simulation results of the low-frequency and high-frequency power amplifiers provided by this invention. Figure 6 This is a simulation result of the performance of the ultra-wideband high-efficiency power amplifier with reconfigurable duplexer connection provided by the present invention. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0012] Example 1 Please see Figure 1 , Figure 1 This is a circuit diagram of a reconfigurable duplexer provided by the present invention. The reconfigurable duplexer includes: a substrate, a first microstrip line D1, a second microstrip line D2 (equivalent to a ground capacitance), a third microstrip line D3 (equivalent to a ground inductance), a fourth microstrip line D4, a first port 1, a second port 2, a third port 3, and a common pad D5. The first microstrip line D1, the second microstrip line D2, the third microstrip line D3, and the fourth microstrip line D4 are integrated on the substrate. The first microstrip line D1 is connected to the first port 1. The first microstrip line D1 is also connected to the second microstrip line D2. The second microstrip line D2 is also connected to the common pad D5. The third microstrip line D3 is connected to the common pad D5. The third microstrip line D3 is also connected to the fourth microstrip line D4. The fourth microstrip line D4 is also connected to the second port 2. The common pad D5 is also connected to the third port 3.

[0013] Specifically, this reconfigurable duplexer is implemented using planar microstrip circuitry, with two different frequency bands switched via a switch. The main structure is integrated onto a single dielectric substrate. For example... Figure 1As shown, the core structure of this reconfigurable duplexer includes a first microstrip line D1, a second microstrip line D2, a third microstrip line D3, and a fourth microstrip line D4, which, together with other passive components, constitute the main body for signal gating and filtering. The first microstrip line D1 and the fourth microstrip line D4 are series transmission lines, primarily serving impedance matching and signal transmission purposes. The physical structure of the second microstrip line D2 makes it equivalent to a capacitor to ground, while the third microstrip line D3 is equivalent to an inductor to ground. Port 1, port 2, and port 3 are used to connect the signal source, the low-frequency power amplifier, and the high-frequency power amplifier, respectively.

[0014] Furthermore, such as Figure 2 As shown, the width W2 of the second microstrip line D2 is greater than the width W4 of the fourth microstrip line D4, which is greater than the width W1 of the first microstrip line D1, which is greater than the width W3 of the third microstrip line D3. The length L3 of the third microstrip line D3 is greater than the length L2 of the second microstrip line D2. The lengths of the first microstrip line D1 and the fourth microstrip line D4 can be flexibly adjusted according to the actual longitudinal distance of the connected power amplifier.

[0015] Furthermore, port 1, port 2, and port 3 are standard 50Ω microstrip line input / output ports.

[0016] Furthermore, the common pads are microstrip line structures.

[0017] In an alternative embodiment, such as Figure 1 As shown, the reconfigurable duplexer also includes DC blocking capacitors C2, C5, and C6, wherein: DC blocking capacitor C2 is connected between the first port 1 and the first microstrip line D1, DC blocking capacitor C5 is connected between the second port 2 and the fourth microstrip line D4, and DC blocking capacitor C6 is connected between the third port 3 and the common pad D5.

[0018] In an alternative embodiment, such as Figure 1 As shown, the reconfigurable duplexer also includes a series inductor L1, PIN diodes PIN1 and PIN diodes PIN2, a first ground microstrip line J1 with several vias, and a second ground microstrip line J2 with several vias, wherein: A series inductor L1 is connected between the second microstrip line D2 and the common pad D5. The anodes of both PIN diode PIN1 and PIN diode PIN2 are connected to the second microstrip line D2. The cathode of PIN diode PIN1 is connected to the first ground microstrip line J1, and PIN diode PIN1 is grounded through the first ground microstrip line J1. The cathode of PIN diode PIN2 is connected to the second ground microstrip line J2, and PIN diode PIN2 is grounded through the second ground microstrip line J2.

[0019] In an alternative embodiment, such as Figure 1As shown, the reconfigurable duplexer also includes a current-limiting resistor R1 and an RF choke inductor Lb1, wherein: The current-limiting resistor R1 is connected to the bias voltage terminal V1. The current-limiting resistor R1 is also connected to the RF choke inductor Lb1, which is also connected to the first microstrip line D1, so as to supply power to PIN diodes PIN1 and PIN diode PIN2 through the bias voltage terminal V1.

[0020] In an alternative embodiment, such as Figure 1 As shown, the reconfigurable duplexer also includes a series capacitor C1, a DC blocking capacitor to ground C4, and a third grounded microstrip line J3 with several through-holes, wherein: A series capacitor C1 is connected between the third microstrip line D3 and the common pad D5, and a DC blocking capacitor C4 is connected between the third microstrip line D3 and the third ground microstrip line J3 to ground through the third ground microstrip line J3.

[0021] In an alternative embodiment, such as Figure 1 As shown, the reconfigurable duplexer also includes a PIN diode PIN3 and a fourth grounded microstrip line J4 with several vias, wherein: The anode of PIN diode PIN3 is connected to the fourth microstrip line D4, the cathode of PIN diode PIN3 is connected to the fourth ground microstrip line J4, and PIN diode PIN3 is grounded through the fourth ground microstrip line J4.

[0022] In an alternative embodiment, such as Figure 1 As shown, the reconfigurable duplexer also includes a current-limiting resistor R2 and an RF choke inductor Lb2, wherein, The current-limiting resistor R2 is connected to the bias voltage terminal V2. The current-limiting resistor R2 is also connected to the RF choke inductor Lb2. The RF choke inductor Lb2 is also connected to the fourth microstrip line D4, so as to power the PIN diode PIN3 through the bias voltage terminal V2.

[0023] In an alternative embodiment, such as Figure 1 As shown, the reconfigurable duplexer also includes an RF-to-ground inductor L2, a DC blocking capacitor C3, a pad D6, and a fifth ground microstrip line J5 with several vias, wherein: The fifth ground microstrip line J5, DC blocking capacitor C3, pad D6, RF-to-ground inductor L2, and common pad D5 are connected in sequence.

[0024] Furthermore, pad D6 is a microstrip line structure.

[0025] Preferably, all microstrip lines in this embodiment are made of a stacked structure of copper, nickel, and gold from bottom to top.

[0026] To achieve electronic reconfiguration of the circuit path, this embodiment integrates PIN diode switches and their bias circuits at key locations in the reconfigurable duplexer. Specifically, an external bias voltage terminal V1 is provided on the first microstrip line D1. This bias voltage provides operating bias for PIN diodes PIN1 and PIN2 through a current-limiting resistor R1 and an RF choke inductor Lb1. The cathodes of PIN diodes PIN1 and PIN2 are connected to the ground plane through a metallized via (the second ground microstrip line), while their anodes are connected to the corresponding nodes on the second microstrip line D2. Simultaneously, a series inductor L1 is loaded on the second microstrip line D2, with one end connected to the common pad D5. A DC blocking capacitor C4 and a series capacitor C1 are loaded on the third microstrip line D3. The DC blocking capacitor C4 is connected to ground through a metallized via (the third ground microstrip line J3), and the other end of the series capacitor C1 is also connected to the common pad D5. A PIN diode PIN3 is mounted on the fourth microstrip line D4. Its cathode is connected to ground through a metallized via (fourth ground microstrip line J4), while its anode is connected to the external bias voltage terminal V2 via a current-limiting resistor R2 and an RF choke inductor Lb2 to power the PIN diode PIN3. Additionally, an RF-to-ground inductor L2 is connected to the common pad D5 and grounded via a DC blocking capacitor C3. The DC blocking capacitor C3 blocks DC power to the low-frequency path diode, ensuring effective isolation between the PIN diode bias path and the RF main path, preventing RF signal leakage to the DC power supply. DC blocking capacitors C2, C5, and C6 are connected in series at the front ends of the first port 1, second port 2, and third port 3, respectively, also for blocking DC components.

[0027] The working principle of this invention is as follows: By controlling the bias voltages of bias voltage terminals V1 and V2, the ON or OFF states of PIN diodes PIN1, PIN2, and PIN3 are changed. When a specific bias combination is applied, the different states of the PIN diodes will change the current path of the RF signal, thereby allowing the entire circuit to switch between two preset filter topologies. Low-frequency path: When PIN diodes PIN1 and PIN2 are off and PIN diode PIN3 is on, the second microstrip line D2, series inductor L1, RF-to-ground inductor L2, and series capacitor C1 together form a Π-type low-pass network. The second microstrip line D2 is equivalent to the ground capacitor. The series capacitor C1, through PIN diode PIN3 to ground, together with RF-to-ground L2, forms a resonant network, which effectively improves the insertion loss of the low-frequency path.

[0028] High-frequency path: When PIN diodes PIN1 and PIN2 are turned on and PIN diode PIN3 is turned off, the third microstrip line D3, series capacitor C1 and series inductor L1 together form a Π-type high-pass network. The third microstrip line D3 is equivalent to the inductor to ground, and the series inductor L1 is connected to ground through PIN diodes PIN1 and PIN2.

[0029] Through the above-mentioned reconfiguration mechanism, a single reconfigurable duplexer can dynamically adapt to two power amplifiers with different operating frequency bands, realizing the frequency band switching function of the ultra-wideband power amplifier system.

[0030] This invention achieves electronic reconfiguration between two filter structures, Π-type low-pass and Π-type high-pass, by controlling the switching state of the PIN diode. It can flexibly adapt to and optimize the passband characteristics of two power amplifiers in different frequency bands, effectively avoiding the performance "pit" generated at the frequency band boundary of the traditional fixed structure, and ensuring good gain flatness and output performance of the ultra-wideband power amplifier system across the entire frequency band.

[0031] This invention benefits from its reconfigurable filter structure, which can effectively suppress the low-frequency inherent gain and high-order harmonic signals of the selected power amplifier during operation, thereby improving the stability of the power amplifier and enhancing the isolation between the two power amplifier channels to avoid mutual interference.

[0032] The overall structure of this invention is based on planar microstrip circuits, which has the advantages of compact structure and easy integration with existing microwave PCB processes. At the same time, the external bias and control circuits are simple and easy to implement in system-in-package.

[0033] Example 2 Please see Figure 3 , Figure 3 This is an architectural diagram of an ultra-wideband high-efficiency power amplifier provided by the present invention. Based on Embodiment 1, the present invention further provides an ultra-wideband high-efficiency power amplifier, which includes a first power amplifier PA1 operating in different frequency bands, a second power amplifier PA2, and two reconfigurable duplexers as described in Embodiment 1. The two outputs of a reconfigurable duplexer are connected to the inputs of a first power amplifier PA1 and a second power amplifier PA2, respectively. This reconfigurable duplexer serves as an input network. The outputs of the first power amplifier PA1 and the second power amplifier PA2 are connected to the two inputs of another reconfigurable duplexer, which serves as an output network.

[0034] Specifically, this embodiment utilizes the reconfiguration mechanism of a reconfigurable duplexer, whereby a single reconfigurable duplexer can dynamically adapt to two power amplifiers operating in different frequency bands, thereby achieving the frequency band switching function of the ultra-wideband power amplifier system. For example... Figure 3As shown, in the ultra-wideband power amplifier system architecture, the third port 3 of the reconfigurable duplexer is connected to the pre-amplifier or signal source and the power amplifier, while the first port 1 and the second port 2 are connected to two independent power amplifier modules optimized for low and high frequencies, respectively. The system can expand the overall output bandwidth by controlling the operating state of the duplexer.

[0035] like Figure 4 As shown, Figure 4 The simulation S-parameter results of the reconfigurable duplexer of this embodiment under two operating states are shown. It exhibits low insertion loss (<0.4dB) in the passband and good suppression characteristics in the stopband. Figure 5 As shown, Figure 5 The simulation results of the low-frequency power amplifier and the high-frequency power amplifier, which are connected separately, are shown. For example... Figure 6 As shown, Figure 6 This demonstrates the performance simulation results of the ultra-wideband power amplifier within the overall extended frequency band after integrating this reconfigurable duplexer, verifying its effectiveness in achieving broadband coverage while maintaining the performance advantages of each sub-amplifier.

[0036] In a preferred embodiment of the present invention, the dielectric substrate is a Rogers RO4350B with a thickness of 0.762 mm. The PIN diode is an SMP1345-079LF, the DC blocking capacitor and filter capacitor are surface-mount capacitors, the inductor is a high-Q inductor, and the resistor is a surface-mount resistor with a 0402 package. Through optimization... Figure 3 The microstrip line size parameters (W1, W2, W3, W4, L2, L3, etc.) and the values ​​of series capacitor C1, series inductor L1 and RF-to-ground inductor L2 shown can precisely tune the cutoff frequency, insertion loss and out-of-band rejection level of the filter to meet the performance requirements of a specific ultra-wideband power amplifier system.

[0037] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0039] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A reconfigurable duplexer, characterized in that, include: The substrate, a first microstrip line, a second microstrip line equivalent to a ground capacitance, a third microstrip line equivalent to a ground inductance, a fourth microstrip line, a first port, a second port, a third port, and a common pad are integrated on the substrate. The first microstrip line, the second microstrip line, the third microstrip line, and the fourth microstrip line are integrated on the substrate. The first microstrip line is connected to the first port, the first microstrip line is also connected to the second microstrip line, the second microstrip line is also connected to the common pad, the third microstrip line is connected to the common pad, the third microstrip line is also connected to the fourth microstrip line, the fourth microstrip line is also connected to the second port, and the common pad is also connected to the third port.

2. The reconfigurable duplexer according to claim 1, characterized in that, It also includes DC blocking capacitors C2, C5, and C6, where: The DC blocking capacitor C2 is connected between the first port and the first microstrip line, the DC blocking capacitor C5 is connected between the second port and the fourth microstrip line, and the DC blocking capacitor C6 is connected between the third port and the common pad.

3. The reconfigurable duplexer according to claim 1, characterized in that, It also includes a series inductor L1, PIN diode PIN1, PIN diode PIN2, a first ground microstrip line with several through-holes, and a second ground microstrip line with several through-holes, wherein: The series inductor L1 is connected between the second microstrip line and the common pad. The anodes of the PIN diode PIN1 and the PIN diode PIN2 are both connected to the second microstrip line. The cathode of the PIN diode PIN1 is connected to the first ground microstrip line, and the PIN diode PIN1 is grounded through the first ground microstrip line. The cathode of the PIN diode PIN2 is connected to the second ground microstrip line, and the PIN diode PIN2 is grounded through the second ground microstrip line.

4. The reconfigurable duplexer according to claim 3, characterized in that, It also includes a current-limiting resistor R1 and an RF choke inductor Lb1, wherein: The current-limiting resistor R1 is connected to the bias voltage terminal V1. The current-limiting resistor R1 is also connected to the RF choke inductor Lb1, which is also connected to the first microstrip line, so as to supply power to the PIN diode PIN1 and the PIN diode PIN2 through the bias voltage terminal V1.

5. The reconfigurable duplexer according to claim 1, characterized in that, It also includes a series capacitor C1, a DC blocking capacitor to ground C4, and a third grounding microstrip line with several through-holes, wherein: The series capacitor C1 is connected between the third microstrip line and the common pad, and the DC blocking capacitor C4 is connected between the third microstrip line and the third ground microstrip line to ground through the third ground microstrip line.

6. The reconfigurable duplexer according to claim 1, characterized in that, It also includes a PIN diode PIN3 and a fourth grounded microstrip line with several through-holes, wherein: The anode of the PIN diode PIN3 is connected to the fourth microstrip line, the cathode of the PIN diode PIN3 is connected to the fourth grounded microstrip line, and the PIN diode PIN3 is grounded through the fourth grounded microstrip line.

7. The reconfigurable duplexer according to claim 6, characterized in that, It also includes a current-limiting resistor R2 and an RF choke inductor Lb2, wherein, The current-limiting resistor R2 is connected to the bias voltage terminal V2. The current-limiting resistor R2 is also connected to the RF choke inductor Lb2. The RF choke inductor Lb2 is also connected to the fourth microstrip line so as to supply power to the PIN diode PIN3 through the bias voltage terminal V2.

8. The reconfigurable duplexer according to claim 1, characterized in that, It also includes an RF-to-ground inductor L2, a DC blocking capacitor C3, pads, and a fifth ground microstrip line with several vias, wherein: The fifth grounding microstrip line, the DC blocking capacitor C3, the pad, the RF-to-ground inductor L2, and the common pad are connected in sequence.

9. The reconfigurable duplexer according to claim 1, characterized in that, The width W2 of the second microstrip line is greater than the width W4 of the fourth microstrip line, which is greater than the width W1 of the first microstrip line and the width W3 of the third microstrip line. The length L3 of the third microstrip line is greater than the length L2 of the second microstrip line.

10. An ultra-wideband high-efficiency power amplifier, characterized in that, Includes a first power amplifier operating in different frequency bands, a second power amplifier, and two reconfigurable duplexers as described in any one of claims 1 to 9, wherein, The two outputs of one of the reconfigurable duplexers are respectively connected to the inputs of the first power amplifier and the second power amplifier, and the outputs of the first power amplifier and the second power amplifier are respectively connected to the two inputs of another reconfigurable duplexer.

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