Ramp voltage generator, chip system and electronic equipment

Abstract

The invention relates to a ramp voltage generator, a chip system and electronic equipment, and relates to the technical field of chips. The ramp voltage generator comprises M + N voltage generation circuits, a first control circuit and N second control circuits, the first output end of the first control circuit is coupled with the control ends of the M first voltage generation circuits; the first control circuit is used for controlling the on-off of the M first voltage generation circuits; the first output ends of the N second control circuits are coupled with the control ends of the N second voltage generation circuits in a one-to-one correspondence manner; the N second control circuits are used for controlling the on-off of the N second voltage generation circuits in a one-to-one correspondence manner; the output ends of the M + N voltage generation circuits are coupled with the output end of the ramp voltage generator, and the ramp voltage generator is used for regulating and controlling the ramp voltage value output by the ramp voltage generator according to the on-off of the M + N voltage generation circuits. In this way, the time of ramping down or ramping up of the ramp voltage can be reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more particularly to a ramp voltage generator, chip system, and electronic device. Background Technology

[0002] In the field of complementary metal-oxide-semiconductor (CIS) image sensors, improving frame rate is crucial. The readout time (Tline) of a line of pixels in an image affects the frame rate. In CIS, a ramp (RAMP) voltage can be used as a reference level to quantize the level generated by CIS sensing. Within a Tline cycle, the ramp fall time (or ramp rise time) is the main factor limiting Tline. Currently, the ramp fall time or ramp rise time is relatively long. To optimize Tline, it is necessary to reduce the ramp fall time or ramp rise time. Summary of the Invention

[0003] This application provides a ramp voltage generator, chip system, and electronic device, which solves the problem of long ramp descent or ramp ascent times in the prior art.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] Firstly, a ramp voltage generator is provided, comprising: M+N voltage generation circuits. The M+N voltage generation circuits include M first voltage generation circuits and N second voltage generation circuits. M > 1, N ≥ 1, and both M and N are integers. A first control circuit is provided. The first output terminal of the first control circuit is coupled to the control terminals of the M first voltage generation circuits. The first control circuit is used to control the on / off state of the M first voltage generation circuits. N second control circuits are provided, with their first output terminals coupled to the control terminals of the N second voltage generation circuits in a one-to-one correspondence. The N second control circuits are used to control the on / off state of the N second voltage generation circuits in a one-to-one correspondence. The output terminals of the M+N voltage generation circuits are all coupled to the output terminal of the ramp voltage generator, and the ramp voltage generator is used to adjust the ramp voltage value output by the ramp voltage generator according to the on / off state of the M+N voltage generation circuits.

[0006] In the above technical solution, M first voltage generation circuits share a single first control circuit. These M first voltage generation circuits can be turned off simultaneously, thus causing a significant drop in the ramp voltage at that moment. N second voltage generation circuits correspond one-to-one with N second control circuits. The turn-off times of the N second voltage generation circuits can differ, resulting in a stepped decrease in the ramp voltage. This reduces the ramp voltage's descent time. Similarly, it also reduces the ramp voltage's ascent time. On one hand, this reduces the time to read out one line of pixels (Tline) of the image, improving the frame rate. On the other hand, it does not require changing the clock signal period, thus not increasing the power consumption of the electronic device. Furthermore, it does not require changing the ramp voltage slope, maintaining compatibility with existing circuits and reducing costs. Finally, the number of control circuits is reduced, making the circuit simpler.

[0007] In one possible implementation of the first aspect, the first control circuit includes a first inverter. The input terminal of the first inverter is coupled to the first input terminal of the first control circuit, and the output terminal of the first inverter is coupled to the first output terminal of the first control circuit. In the above possible implementations, the first control circuit may include an inverter, which has a small area and can further simplify the circuit.

[0008] In one possible implementation of the first aspect, the first input terminal of the first control circuit is coupled to the first input terminals of N second control circuits. The second control circuit includes a latch. The reset terminal of the latch is coupled to the first input terminal of the second control circuit. The input terminal of the latch is coupled to the second input terminal of the second control circuit. The first output terminal of the latch is coupled to the first output terminal of the second control circuit. In the above possible implementation, the second control circuit can reuse the existing latch, resulting in lower cost. The inverter can share the reset signal with the latch, using the existing reset signal as its input signal. Therefore, no new interfaces or signals are required, resulting in lower circuit cost.

[0009] In one possible implementation of the first aspect, the ramp voltage generator further includes: P logic switches and P second control circuits. The first output terminal of the first control circuit is coupled to the first input terminals of all P logic switches. The first output terminals of the P second control circuits are coupled one-to-one to the second input terminals of the P logic switches. The output terminals of the P logic switches are coupled one-to-one to the control terminals of P of the M first voltage generation circuits. 1 ≤ P ≤ M, and P is an integer. In the above possible implementation, by setting the first logic switch, a voltage generation circuit can selectively perform one of two functions: simultaneously turn off with other voltage generation circuits, or turn off sequentially. Furthermore, only the first logic switch and the first control circuit need to be added to the existing second control circuit. This requires minimal circuit modification and has a low cost.

[0010] In one possible implementation of the first aspect, the logic switch includes: a first AND gate and a first OR gate. The first input terminal of the logic switch is coupled to the first input terminal of the first AND gate. The second input terminal of the first AND gate is coupled to the control terminal of the logic switch. The output terminal of the first AND gate is coupled to the first input terminal of the first OR gate. The second input terminal of the first OR gate is coupled to the second input terminal of the logic switch. The output terminal of the first OR gate is coupled to the output terminal of the logic switch. In the above possible implementations, the first logic switch can be implemented using one AND gate and one OR gate, resulting in a simple circuit structure and low cost. Furthermore, only a constant high-level or constant low-level signal needs to be added as the control signal for each first logic switch. The added signal is very simple, and the circuit design cost is low. Moreover, the existing interface in the ramp voltage generator can be easily reused to obtain this added signal, saving circuit costs.

[0011] In one possible implementation of the first aspect, the first control circuit includes: a first multiplexer and a first inverter. The first input terminal of the first multiplexer is coupled to the first input terminal of the first control circuit. The second input terminal of the first multiplexer is coupled to the second input terminal of the first control circuit. The selection terminal of the first multiplexer is coupled to the third input terminal of the first control circuit. The output terminal of the first multiplexer is coupled to the input terminal of the first inverter. The output terminal of the first inverter is coupled to the first output terminal of the first control circuit. In the above possible implementations, by setting the first multiplexer, the scheme of simultaneously turning off multiple voltage generation circuits in the ramp voltage generator can be controlled as a whole. Furthermore, the first multiplexer has a simple structure and low circuit cost. The selection signal of the first multiplexer can reuse the enable signal, further reducing cost.

[0012] In one possible implementation of the first aspect, the first control circuit further includes: a second AND gate, a first multiplexer, and a first inverter. The first input terminal of the second AND gate is coupled to the first input terminal of the first control circuit. The second input terminals of the second AND gate and the multiplexer are both coupled to the second input terminal of the first control circuit. The output terminal of the second AND gate is coupled to the first input terminal of the multiplexer. The selection terminal of the first multiplexer is coupled to the third input terminal of the first control circuit. The output terminal of the first multiplexer is coupled to the input terminal of the first inverter. The output terminal of the first inverter is coupled to the first output terminal of the first control circuit. In the above possible implementations, by setting the second AND gate, the first control circuit can also activate the control function via an enable signal. The circuit structure is relatively simple.

[0013] In one possible implementation of the first aspect, each of the M+N voltage generation circuits includes a current source, a ramp switch, and a first resistor. The first resistors in all M+N voltage generation circuits are the same. The current sources in the M+N voltage generation circuits are coupled one-to-one with the first terminals of the ramp switches in each of the M+N voltage generation circuits. The second terminals of the ramp switches and the first terminals of the first resistors are both coupled to the output terminals of the M+N voltage generation circuits. The control terminal of the ramp switch is the control terminal of the voltage generation circuit. The second terminal of the first resistor is grounded. In the above possible implementation, the M+N voltage generation circuits can output voltage using a shunt method, can reuse the original circuitry, and have a lower cost.

[0014] In one possible implementation of the first aspect, the ramp voltage generator further includes: M+N auxiliary switches. The first terminals of the M+N auxiliary switches are coupled one-to-one with the current sources in the M+N voltage generation circuits. The M+N auxiliary switches include M first auxiliary switches and N second auxiliary switches. A second resistor. The first terminal of the second resistor is coupled to the second terminals of all M+N auxiliary switches. The second terminal of the second resistor is grounded. A third control circuit. The first output terminal of the third control circuit is coupled to the control terminals of all M first auxiliary switches. N fourth control circuits. The first output terminals of the N fourth control circuits are coupled one-to-one with the control terminals of the N second auxiliary switches. In the above possible implementation, the current source coupled to the ramp switch is also coupled to the second resistor through an auxiliary switch. When the ramp switch is turned off, the auxiliary switch can be turned on to discharge the current of the current source. The M first auxiliary switches can be controlled by a common third control circuit, and the N second auxiliary switches can be controlled by N independent fourth control circuits respectively. Thus, they can work in conjunction with the ramp switch.

[0015] Secondly, a ramp voltage generator is provided, which is used to: output a reset voltage in a first time period; and output a ramp voltage in a second time period. The second time period follows the first time period, and the first and second time periods are continuous. The ramp voltage has a slope less than 0, meaning the ramp voltage output at the beginning of the second time period is less than the reset voltage output at the end of the first time period. Alternatively, the ramp voltage has a slope greater than 0, meaning the ramp voltage output at the beginning of the second time period is greater than the reset voltage output at the end of the first time period. In this technical solution, the ramp voltage drops significantly or rises sharply between the end of the previous time period and the beginning of the current time period. Therefore, the ramp voltage can reach the required voltage value more quickly. Consequently, the ramp voltage's descent time or rise time can be reduced.

[0016] Thirdly, a ramp voltage generator is provided, which is used to: output a first ramp voltage in a first sub-time period; and output a second ramp voltage in a second sub-time period. The second sub-time period is located after the first sub-time period, and the first and second sub-time periods are continuous. Specifically, the slopes of both the first and second ramp voltages are less than 0, and the second ramp voltage output at the beginning of the second sub-time period is less than the first ramp voltage output at the end of the first sub-time period. Alternatively, the slopes of both the first and second ramp voltages are greater than 0, and the second ramp voltage output at the beginning of the second sub-time period is greater than the first ramp voltage output at the end of the first sub-time period. In the above technical solution, the ramp voltage drops significantly or rises sharply at the end of the previous time period and the beginning of the current time period. Therefore, the ramp voltage can reach the required voltage value more quickly. Thus, the ramp drop time or ramp rise time can be reduced.

[0017] Fourthly, a chip system is provided, comprising an analog-to-digital converter circuit and a ramp voltage generator provided in the first aspect, any possible implementation of the first aspect, the second aspect, or the third aspect. The analog-to-digital converter circuit is coupled to the ramp voltage generator.

[0018] Fifthly, an electronic device is provided, comprising a circuit board and the chip system provided in the fourth aspect. The chip system is disposed on the circuit board.

[0019] In one possible implementation of the fifth aspect, the electronic device also includes a pixel array. The pixel array is coupled to the chip system.

[0020] Understandably, any of the chip systems or electronic devices provided above utilize the corresponding ramp voltage generators provided. Therefore, the beneficial effects they can achieve can be referred to in the beneficial effects of the corresponding ramp voltage generators provided above, and will not be repeated here. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0022] Figure 2 A schematic diagram of a ramp voltage generator provided in this application embodiment. Figure 1 ;

[0023] Figure 3 A schematic diagram of a voltage provided for an embodiment of this application. Figure 1 ;

[0024] Figure 4 A schematic diagram of a voltage provided for an embodiment of this application. Figure 2 ;

[0025] Figure 5 A schematic diagram of a voltage provided for an embodiment of this application. Figure 3 ;

[0026] Figure 6 A schematic diagram of a second control circuit provided in an embodiment of this application;

[0027] Figure 7 Timing of an electrical signal provided in an embodiment of this application Figure 1 ;

[0028] Figure 8 A schematic diagram of a voltage provided for an embodiment of this application. Figure 4 ;

[0029] Figure 9 A schematic diagram of a first control circuit and a second control circuit provided in the embodiments of this application. Figure 1 ;

[0030] Figure 10 A schematic diagram of a first control circuit and a second control circuit provided in the embodiments of this application. Figure 2 ;

[0031] Figure 11 Timing of an electrical signal provided in an embodiment of this application Figure 2 ;

[0032] Figure 12 A schematic diagram of a first logic switch provided in an embodiment of this application. Figure 1 ;

[0033] Figure 13 A schematic diagram of a first logic switch provided in an embodiment of this application. Figure 2 ;

[0034] Figure 14 Timing of an electrical signal provided in an embodiment of this application Figure 3 ;

[0035] Figure 15 A schematic diagram of a first control circuit provided in an embodiment of this application. Figure 1 ;

[0036] Figure 16 Timing of an electrical signal provided in an embodiment of this application Figure 4 ;

[0037] Figure 17 A schematic diagram of a first control circuit provided in an embodiment of this application. Figure 2 ;

[0038] Figure 18A schematic diagram of a ramp voltage generator provided in this application embodiment. Figure 2 ;

[0039] Figure 19 A schematic diagram of a third control circuit and a fourth control circuit provided in the embodiments of this application. Figure 1 ;

[0040] Figure 20 A schematic diagram of a second logic switch provided in an embodiment of this application;

[0041] Figure 21 A schematic diagram of a third control circuit and a fourth control circuit provided in the embodiments of this application. Figure 2 ;

[0042] Figure 22 A schematic diagram of a voltage provided for an embodiment of this application. Figure 5 ;

[0043] Figure 23 A schematic diagram of a voltage provided for an embodiment of this application. Figure 6 . Detailed Implementation

[0044] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0045] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0046] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0047] First, the application scenarios of the embodiments of this application will be introduced. The embodiments of this application can be applied to electronic devices. The electronic device can be an image sensor, such as a complementary metal oxide semiconductor image sensor (CIS). The electronic device can also be a mobile phone, tablet computer, computer, laptop computer, camera, wearable device, in-vehicle device, or terminal device, etc. The embodiments of this application do not limit the type of electronic device.

[0048] In some possible implementations, such as Figure 1 As shown, taking a CIS (Computer Integrated System) device 1000 as an example, the device 1000 may include: a pixel array 100, a line decoder 210, a ramp (RAMP) voltage generator 300, and an analog-to-digital converter (ADC) circuit 220. Both the line decoder 210 and the ADC circuit 220 are coupled to the pixel array 100. The ramp voltage generator 300 is coupled to the ADC circuit 220.

[0049] The pixel array 100 may include multiple pixels arranged in multiple rows and columns. Each pixel may include a photodiode. Each pixel can output a pixel signal based on sensed light. The row decoder 210 can select one row of pixels from the pixel array 100 at a time and control the operation of that row. Under the multiple controls of the row decoder 210, the pixel array 100 can output pixel signals to the analog-to-digital converter (ADC) circuit 220. The ramp voltage generator 300 can generate a ramp voltage Vr. The ramp voltage Vr can be a voltage used for the analog-to-digital conversion operation of the ADC circuit 220. The ramp voltage Vr can be a linearly decreasing voltage or a linearly increasing voltage. The ADC circuit 220 can perform an analog-to-digital conversion operation on the pixel signal output from the pixel array 100 based on the ramp voltage Vr. For example, the ADC circuit 220 can use the ramp voltage Vr as a reference level to quantize the level sensed by the pixel array 100. The analog-to-digital converter (ADC) 220 performs an analog-to-digital conversion (ADC) operation by starting to count the digital code from the moment the ramp voltage Vr begins to decrease, and stopping the counting when the ramp voltage Vr and the pixel signal voltage reach the same level. The ADC 220 can perform ADC operations on multiple columns of pixel signals in parallel. The ADC 220 can output the result of converting the pixel signals into digital signals as an image.

[0050] Additionally, the ramp voltage generator 300 can be integrated onto a single chip system, or the ramp voltage generator 300 and the analog-to-digital converter circuit 220 can be integrated onto a single chip system, or the ramp voltage generator 300, the analog-to-digital converter circuit 220, and the line decoder 210 can be integrated onto a single chip system. The electronic device 1000 may also include a circuit board (…). Figure 1 (Not shown in the image), the chip system can be mounted on a circuit board.

[0051] In some examples, such as Figure 2 As shown, the ramp voltage generator 300 may include a ramp control circuit 310, a ramp output circuit 320, and a filter 330. The ramp control circuit 310 can be used to control the ramp output circuit 320 to output a voltage to the filter 330. The filter 330 is used to output a ramp voltage Vr according to the voltage. The filter 330 can be used to smooth, remove, or reduce high-frequency noise or other rapidly changing fluctuations in the input signal, making it a smooth DC component or a low-frequency signal.

[0052] For example, the ramp output circuit 320 can output a voltage that decreases in a stepped manner or increases in a stepped manner by voltage division.

[0053] As another example, the ramp output circuit 320 can output a voltage that decreases in a stepped manner or increases in a stepped manner by means of shunting.

[0054] like Figure 2 As shown, the ramp output circuit 320 includes: multiple current sources, such as A1 to A4; multiple ramp switches, such as K1 to K4; and a first resistor, such as R1. The ramp voltage generator 300 also includes a ramp control circuit 310 and a filter 330. The output terminals of the multiple current sources are coupled one-to-one with the first terminals of the multiple ramp switches. The second terminals of the multiple ramp switches and the first terminal of the first resistor are both coupled to the output terminal of the ramp output circuit 320. The second terminal of the first resistor is grounded. The input terminal of the filter 330 is coupled to the output terminal of the ramp output circuit 320. The ramp control circuit 310 is used to control the on / off state of the multiple ramp switches. For example, the ramp control circuit 310 outputs control signals OP1 to OP4 to K1 to K4, thereby controlling the on / off state of K1 to K4. In practice, the number of current sources and ramp switches can be greater, and this embodiment does not limit this.

[0055] like Figure 3As shown, the vertical axis represents voltage, and the horizontal axis represents time. Taking a ramp voltage Vr, which includes a linearly decreasing voltage, as an example: When multiple switches are all on, the output of the ramp output circuit 320 is used to output a reset voltage. When the number of on switches decreases, the output of the ramp output circuit 320 is used to output voltage Vr', which can decrease in a stepped manner. Filter 330 is used to input the stepped voltage Vr' and converts it into a ramp voltage Vr through filtering. The output of filter 330 is used to output the ramp voltage Vr.

[0056] In some possible implementations, such as Figure 4 As shown, the period of Vr's step-like decrease is the period of the clock signal (clock, CLK), and Tclk takes the value Tz.

[0057] In some examples, at time T1, the first ramp switch is turned off, and the current source coupled to the first ramp switch no longer outputs current to the first resistor. The current flowing through the first resistor decreases, and the voltage Vr' at the first terminal of the first resistor drops. At time Tz, after time T1, the second ramp switch is turned off, and the current source coupled to the second ramp switch no longer outputs current to the first resistor. The current flowing through the first resistor decreases again, and the voltage Vr' at the first terminal of the first resistor drops again. This continues until the voltage Vr' at the first terminal of the first resistor reaches the desired voltage value. Figure 4 In this scenario, it takes 8 Tz of time for the first ramp switch to be turned off until the ninth ramp switch is turned off. If the total number of ramp switches is Q, the time for Vr' to descend in a stepwise manner is (Q-1)*Tz. For example, Tclk = 1 / 1.08 GHz, Q = 2048.

[0058] In this embodiment, the time for the slope voltage Vr to descend (or ascend) is relatively long.

[0059] In other possible implementations, such as Figure 5 As shown, the slope descent time of the ramp voltage Vr can be reduced by decreasing the value of Tclk. For example, Tclk can be set to 1 / 2Tz.

[0060] In some examples, the dashed, stepped voltage drop Vr' is Figure 4Let Vr' be the solid line representing the stepped decrease in voltage Vr' in this example. In this example, at time T1, the first ramp switch is turned off, and the voltage Vr' at the first terminal of the first resistor decreases. 1 / 2Tz time after time T1, the second ramp switch is turned off, and the voltage Vr' at the first terminal of the first resistor decreases again. This continues until the voltage Vr' at the first terminal of the first resistor reaches the desired value. From the time the first ramp switch is turned off to the time it takes for the ninth ramp switch to be turned off, 4Tz time is required. If the total number of ramp switches is Q, the time for the stepped decrease in Vr' is (Q-1)*(1 / 2)*Tz.

[0061] In this embodiment, by reducing the period of the clock signal, the speed at which each switch is turned off is accelerated, thereby reducing the slope descent time of the ramp voltage Vr. Similarly, the slope rise time of the ramp voltage Vr can also be reduced. However, reducing the period of the clock signal increases the power consumption of the electronic device 1000. Moreover, in this embodiment, the slope of the ramp voltage Vr will change, and the original circuit cannot be compatible with the ramp voltage Vr after the slope change. Modification of the original circuit is required, resulting in higher costs.

[0062] Next Figure 4 and Figure 5 The Vr' scheme shown uses a ramp voltage generator 300 as an example. The ramp control circuit 310 of the ramp voltage generator 300 includes multiple second control circuits. The output terminals of the multiple second control circuits are coupled one-to-one with the control terminals of multiple ramp switches. The multiple second control circuits are used to control the on / off state of the multiple ramp switches one-to-one. Since the off time of each ramp switch is different and the control signal of each ramp switch is different, a corresponding second control circuit needs to be set for each ramp switch.

[0063] For example, since the number of ramp switches is relatively large, the embodiments of this application use... Figure 2 Taking K1 to K4 as examples, the structure of the second control circuit will be illustrated.

[0064] like Figure 6As shown, the second control circuit 311 includes a first latch 31. The reset terminal of the first latch 31 is coupled to the first input terminal of the second control circuit 311 (for inputting a reset signal RST). The input terminal of the first latch 31 is coupled to the second input terminal of the second control circuit 311 (for inputting a step signal, such as IN1, IN2, IN3, or IN4). The enable terminal of the first latch 31 is coupled to the third input terminal of the second control circuit 311 (for inputting a latch enable signal LEN). The first output terminal of the first latch 31 is coupled to the first output terminal of the second control circuit 311 (for outputting a latch signal, such as SL1, SL2, SL3, or SL4). The latch signal output by each first latch 31 (e.g., SL1) is the control signal (e.g., OP1) of the ramp switch corresponding to that first latch 31. The reset terminals of multiple first latches 31 are coupled, and multiple first latches 31 share the reset signal RST. The latch enable terminals of multiple first latches 31 are coupled, and the multiple first latches 31 share the latch enable signal LEN.

[0065] like Figure 7 As shown, when a low level is applied to the control terminals of ramp switches K1 to K4, ramp switches K1 to K4 are turned on; when a high level is applied to the control terminals of ramp switches K1 to K4, ramp switches K1 to K4 are turned off. The ramp switches can be P-channel metal-oxide-semiconductor (PMOS) transistors. In practice, ramp switches can also be turned on at a high level and turned off at a low level; this embodiment does not impose such limitations. The changes in each signal occur at the rising edge of the clock signal CLK. This scheme is activated when the latch enable signal LEN is high.

[0066] When the reset signal RST is high, multiple first latches 31 are reset, and the latch signals SL1~SL4 (that is, control signals OP1~OP4) output by multiple first latches 31 are all low, and ramp switches K1~K4 are turned on.

[0067] When the reset signal RST is low, the latch signals SL1 to SL4 output by the multiple first latches 31 are the step signals (IN1 to IN4) input to the input terminals of the first latches 31, respectively. Figure 7 It can be seen that the step signals input to the multiple first latches 31 are different, resulting in different latch signals output by the multiple first latches 31. Therefore, the control signals OP1 to OP4 are different, and the turn-off times of ramp switches K1 to K4 are different. Ramp switches K1 to K4 are turned off sequentially according to the cycle of Tclk.

[0068] In some other possible implementations, such as Figure 8As shown, by simultaneously turning off multiple ramp switches, the ramp voltage Vr drops significantly at time T1, thereby reducing the ramp descent time of Vr. For example, Tclk is set to Tz.

[0069] In some examples, the dashed, stepped voltage drop Vr' is Figure 4 The solid line represents the stepped decrease in voltage Vr' in this example. In this example, at time T1, the first to fifth ramp switches are all turned off, and the voltage Vr' at the first terminal of the first resistor drops significantly. At time Tz, after time T1, the sixth ramp switch is turned off, and the voltage Vr' at the first terminal of the first resistor drops again. This continues until the voltage Vr' at the first terminal of the first resistor reaches the desired value. It takes 4 Tz times from the time the first ramp switch is turned off to the time when the ninth ramp switch is turned off.

[0070] In this embodiment, by simultaneously turning off multiple ramp switches, the ramp voltage Vr drops significantly at that moment. This reduces the ramp-down time of Vr. Similarly, the ramp-up time of Vr can also be reduced. On one hand, this reduces the readout time (Tline) of one pixel in the image, increasing the frame rate. On the other hand, it does not require changing the clock signal period, thus not increasing the power consumption of the electronic device 1000. Furthermore, it does not require changing the slope of the ramp voltage Vr, maintaining compatibility with existing circuitry and reducing costs.

[0071] Next Figure 8 The Vr' scheme shown uses a ramp voltage generator 300 as an example for illustration. For example... Figure 9 As shown, the ramp output circuit 320 of the ramp voltage generator 300 includes M+N voltage generation circuits. The M+N voltage generation circuits include M first voltage generation circuits 321 and N second voltage generation circuits 322. M > 1, N ≥ 1, and both M and N are integers. The ramp control circuit 310 of the ramp voltage generator 300 includes a first control circuit 312 and N second control circuits 311. The first output terminal of the first control circuit 312 is coupled to the control terminals of all M first voltage generation circuits 321. The first control circuit 312 is used to control the on / off state of the M first voltage generation circuits 321. The first output terminals of the N second control circuits 311 are coupled one-to-one to the control terminals of the N second voltage generation circuits 322. The N second control circuits 311 are used to control the on / off state of the N second voltage generation circuits 322. The output terminals of all M+N voltage generation circuits are coupled to the output terminal of the ramp output circuit 320. The ramp voltage generator 300 is used to regulate the ramp voltage value output by the ramp voltage generator 300 according to the on / off state of M+N voltage generation circuits.

[0072] For example, the outputs of the M+N voltage generation circuits are all coupled to the output of the ramp voltage generator 300 through the filter 330.

[0073] For example, each of the M+N voltage generation circuits includes a current source, a ramp switch, and a first resistor. The structure of the M+N voltage generation circuits can be referenced. Figure 2 The first resistor in each of the M+N voltage generation circuits is the same. The current sources in each of the M+N voltage generation circuits are coupled one-to-one with the first terminals of the ramp switches in each of the M+N voltage generation circuits. The second terminals of the ramp switches and the first terminals of the first resistors are both coupled to the output terminals of the M+N voltage generation circuits. The control terminal of the ramp switches is the control terminal of the voltage generation circuits. The second terminal of the first resistor is grounded.

[0074] For example, if M first voltage generation circuits 321 are simultaneously turned off, the ramp fall time of the ramp voltage can be reduced by (M-1)*Tclk, for example, M=128. The analog-to-digital converter circuit 220 can be an M+N bit current-mode analog-to-digital converter circuit 220. The first control circuit 312 can control the M-bit current-mode analog-to-digital converter circuit 220 to accelerate. The numbers M and N are used to determine the ramp step size and amplitude range of the ramp voltage.

[0075] In this embodiment, M first voltage generation circuits 321 share a single first control circuit 312. The M first voltage generation circuits 321 can be turned off simultaneously, thus causing a significant drop in the ramp voltage at that moment. N second voltage generation circuits 322 correspond one-to-one with N second control circuits 311. The turn-off times of the N second voltage generation circuits 322 can differ, resulting in a stepped drop in the ramp voltage. This reduces the ramp-down time of the ramp voltage Vr. Similarly, it also reduces the ramp-up time of the ramp voltage Vr. On one hand, this reduces the readout time (Tline) of one pixel in the image, increasing the frame rate. On the other hand, it does not require changing the clock signal period, thus not increasing the power consumption of the electronic device 1000. Furthermore, it does not require changing the slope of the ramp voltage Vr, maintaining compatibility with existing circuitry and reducing costs. Moreover, the number of control circuits is reduced, simplifying the circuitry.

[0076] In this implementation, the M+N voltage generation circuits can output Vr' in a shunt manner, which can reuse the original circuits and reduce costs.

[0077] In some possible implementations, the structure consists of M+N voltage generation circuits. Figure 2 Taking the structure shown as an example, the structure of the first control circuit 312 and the structure of the second control circuit 311 will be illustrated.

[0078] like Figure 10 As shown, ramp switches K1 and K4 are located in two first voltage generation circuits 321, respectively. Ramp switches K2 and K3 are located in two second voltage generation circuits 322, respectively.

[0079] The first control circuit 312 includes a first inverter 32. The input terminal of the first inverter 32 is coupled to the first input terminal of the first control circuit 312 (used for inputting the reset signal RST), and the output terminal of the first inverter 32 is coupled to the first output terminal of the first control circuit 312 (used for outputting the common signal SWN). The common signal SWN output by the first inverter 32 is the control signal for the M ramp switches coupled to the first inverter 32.

[0080] The second control circuit 311 includes: a first latch 31. The reset terminal of the first latch 31 is coupled to the first input terminal of the second control circuit 311 (for inputting a reset signal RST). The input terminal of the first latch 31 is coupled to the second input terminal of the second control circuit 311 (for inputting a step signal, such as IN2 or IN3). The enable terminal of the first latch 31 is coupled to the third input terminal of the second control circuit 311 (for inputting a latch enable signal LEN). The first output terminal of the first latch 31 is coupled to the first output terminal of the second control circuit 311 (for outputting a latch signal, such as SL2 or SL3). The latch signal (e.g., SL2 or SL3) output by the first latch 31 serves as the signal output by the second control circuit 311. If the ramp switch is controlled only by the second control circuit 311, then the latch signal (e.g., SL2 or SL3) of the first latch 31 coupled to the ramp switch serves as the control signal for the ramp switch.

[0081] The first input terminal of the first control circuit 312 is coupled to the first input terminals of N second control circuits 311. The N second control circuits 311 and the first control circuit 312 share a reset signal RST. The latch enable terminals of the N first latches 31 are coupled, and the N first latches 31 share a latch enable signal LEN.

[0082] like Figure 11As shown, when a low level is applied to the control terminals of ramp switches K1-K4, ramp switches K1-K4 are turned on; when a high level is applied to the control terminals of ramp switches K1-K4, ramp switches K1-K4 are turned off. The ramp switches can be P-channel metal-oxide-semiconductor (PMOS) transistors. In practice, ramp switches can also be turned on at a high level and turned off at a low level; this embodiment does not limit this. The changes in each signal occur at the rising edge of the clock signal CLK. This scheme is activated when the latch enable signal LEN is high. The ramp voltage Vr (shown by the dashed line) is... Figure 7 In this embodiment, Vr is the slope voltage Vr represented by the solid line.

[0083] For ramp switches K1 and K4: the SWN output by the first inverter 32 is the control signal OP1 for ramp switch K1 and the control signal OP4 for ramp switch K4.

[0084] For ramp switches K2 and K3: When the reset signal RST is high, both first latches 31 are reset, and the latch signals SL2 and SL3 (i.e., control signals OP2 and OP3) output by the two first latches 31 are low, turning on ramp switches K2 and K3. When the reset signal RST is low, the latch signals SL2 and SL3 output by the two first latches 31 are the step signals (IN2 and IN3) input to the input terminals of the first latches 31, respectively. Figure 11 It can be seen that the step signals input to the two first latches 31 coupled to K2 and K3 are different, resulting in different latch signals output by these two first latches 31. Therefore, the control signals OP2 and OP3 are different, and the turn-off times of ramp switches K2 and K3 are different. Ramp switches K2 and K3 are turned off sequentially according to the cycle of Tclk.

[0085] In this embodiment, the first control circuit 312 may include an inverter. The inverter has a small area, which further simplifies the circuit. Furthermore, the second control circuit 311 can reuse the existing latch, resulting in lower cost. The inverter can share the reset signal with the latch, using the existing reset signal as its input. Therefore, no new interfaces or signals are required, leading to lower circuit cost.

[0086] In some possible implementations, the first voltage generation circuit 321 can be selectively controlled by either the first control circuit 312 or the second control circuit 311. Some of the M first voltage generation circuits 321 can be turned off simultaneously, causing the ramp voltage Vr to drop significantly at that moment. Alternatively, the other part of the M first voltage generation circuits 321 can be turned off at different times, causing the ramp voltage Vr to decrease in a stepwise manner.

[0087] In some examples, such as Figure 12 As shown, the ramp voltage generator 300 further includes: P first logic switches 313 and P second control circuits 311. The first output terminal of each of the first control circuits 312 is coupled to the first input terminals of all P first logic switches 313. The first output terminals of each of the P second control circuits 311 are coupled to the second input terminals of each of the P first logic switches 313. The output terminals of each of the P first logic switches 313 are coupled to the control terminals of each of the P first voltage generation circuits 321 in the M first voltage generation circuits 321. 1 ≤ P ≤ M, and P is an integer.

[0088] In this embodiment, by setting the first logic switch 313, a voltage generation circuit can selectively perform one of two functions: simultaneously shutting down with other voltage generation circuits, or sequentially shutting down. Furthermore, it only requires adding the first logic switch 313 and the first control circuit 312 to the existing second control circuit 311. This involves minimal circuit modification and low cost.

[0089] In some possible implementations, the structure consists of M+N voltage generation circuits. Figure 2 Taking the structure shown as an example, the structure of the first logic switch 313 will be illustrated.

[0090] like Figure 13 As shown, ramp switch K4 is located in P first voltage generation circuits 321.

[0091] The first logic switch 313 includes a first AND gate 33 and a first OR gate 34. The first input terminal of the first logic switch 313 is coupled to the first input terminal of the first AND gate 33. The second input terminal of the first AND gate 33 is coupled to the control terminal of the first logic switch 313 (used to output an independent selection signal SVP). The output terminal of the first AND gate 33 is coupled to the first input terminal of the first OR gate 34. The second input terminal of the first OR gate 34 is coupled to the second input terminal of the first logic switch 313. The output terminal of the first OR gate 34 is coupled to the output terminal of the first logic switch 313 (used to output a common signal SWN or a latch signal, such as SL4).

[0092] like Figure 14As shown, when the ramp switch K4 needs to be simultaneously turned off, the control independent selection signal SVP is high. The first AND gate 33 outputs a common signal SWN to the first OR gate 34. The first OR gate 34 takes the common signal SWN and the latch signal SL4 as inputs and outputs the common signal SWN as the control signal for the ramp switch K4.

[0093] When the ramp switch K4 is not required to be simultaneously turned off, the independent control selection signal SVP is low. The first AND gate 33 outputs a low level to the first OR gate 34. The first OR gate 34 receives a low level and a latch signal SL4 as input, and outputs a latch signal SL4 as the control signal for the ramp switch K4. (The timing of the latch signal SL4 at this time is the same as...) Figure 14 The timing of the latch signal SL4 differs because the number of ramp switches involved in simultaneous shutdown is reduced, and the reset time is shifted later. The timing of the latch signal SL4 in this case can be referenced... Figure 7 The timing of the latch signal SL4 in the middle.

[0094] In this embodiment, the first logic switch 313 can be implemented using an AND gate and an OR gate, resulting in a simple circuit structure and low cost. Furthermore, only a constant high-level or constant low-level signal needs to be added as the control signal for each first logic switch 313. The added signal is very simple, and the circuit design cost is low. Moreover, the existing interface in the ramp voltage generator 300 can be easily reused to obtain this added signal, saving circuit costs.

[0095] In some possible implementations, a selection switch may be provided inside the first control circuit 312. The first control circuit 312 can select not to output a valid signal through the internal selection switch, so that all first voltage generation circuits 321 can be controlled by the second control circuit 311.

[0096] In some examples, such as Figure 15 As shown, ramp switch K4 is located in P first voltage generation circuits 321.

[0097] The first control circuit 312 includes a first multiplexer 35 and a first inverter 32. The first input terminal of the first multiplexer 35 is coupled to the first input terminal of the first control circuit 312 (for inputting a reset signal RST). The second input terminal of the first multiplexer 35 is coupled to the second input terminal of the first control circuit 312 (for inputting a general enable signal SWEN). The selection terminal of the first multiplexer 35 is coupled to the third input terminal of the first control circuit 312 (for inputting a general selection signal SWSEL). The output terminal of the first multiplexer 35 is coupled to the input terminal of the first inverter 32. The output terminal of the first inverter 32 is coupled to the first output terminal of the first control circuit 312 (for outputting a common signal SWN or a low level).

[0098] like Figure 16 As shown, when a ramp switch is required to simultaneously turn off, the control general selection signal SWSEL is low. The first multiplexer 35 selects the output reset signal RST. The first inverter 32 takes the reset signal RST as input and outputs the common signal SWN. Subsequent processes can be found in [reference needed]. Figure 14 The relevant descriptions in the embodiments of this application will not be repeated here.

[0099] When all ramp switches do not need to be simultaneously turned off, the control master selection signal SWSEL is high. The first multiplexer 35 selects the output master enable signal SWEN, which is high. The first inverter 32 receives a high input and outputs a low output. The first AND gate 33 outputs a low level to the first OR gate 34. Subsequent processes can be found in [reference needed]. Figure 14 The relevant descriptions in the embodiments of this application will not be repeated here.

[0100] In this embodiment, by providing a first multiplexer 35, the scheme of simultaneously shutting down multiple voltage generation circuits can be controlled as a whole by the ramp voltage generator 300. Furthermore, the first multiplexer 35 has a simple structure and low circuit cost. The selection signal of the first multiplexer 35 can be multiplexed with an enable signal, further reducing cost.

[0101] In some possible implementations, the first control circuit 312 can also activate the control function via an enable signal.

[0102] In some examples, such as Figure 17 As shown, ramp switch K4 is located in P first voltage generation circuits 321.

[0103] The first control circuit 312 further includes a second AND gate 36, a first multiplexer 35, and a first inverter 32. The first input terminal of the second AND gate 36 is coupled to the first input terminal of the first control circuit 312 (for inputting the reset signal RST). The second input terminals of both the second AND gate 36 and the first multiplexer 35 are coupled to the second input terminals of the first control circuit 312 (for inputting the total enable signal SWEN). The output terminal of the second AND gate 36 is coupled to the first input terminal of the first multiplexer 35. The selection terminal of the first multiplexer 35 is coupled to the third input terminal of the first control circuit 312 (for inputting the total selection signal SWSEL). The output terminal of the first multiplexer 35 is coupled to the input terminal of the first inverter 32. The output terminal of the first inverter 32 is coupled to the first output terminal of the first control circuit 312 (for outputting the common signal SWN or a low level).

[0104] The timing diagram for this example can be referenced. Figure 16The scheme is activated when the SWEN enable signal is high.

[0105] In this embodiment, by providing a second AND gate 36, the first control circuit 312 can also activate the control function via an enable signal. The circuit structure is relatively simple.

[0106] In some possible implementations, the ramp voltage generator 300 may further include a fifth control circuit and L third voltage generation circuits, with the first output terminal of the fifth control circuit coupled to the control terminals of the L third voltage generation circuits. The structure of the third voltage generation circuit can refer to the structure of the first voltage generation circuit 321, and will not be repeated here. During the output of the ramp voltage, the ramp voltage generator 300 can control the M first voltage generation circuits 321 to be turned off simultaneously through the first control circuit 312, causing the ramp voltage Vr to drop significantly at the first falling moment. The ramp voltage generator 300 can also control the N second voltage generation circuits 322 to be turned off sequentially through the N second control circuits 311, causing the ramp voltage Vr to drop linearly. The ramp voltage generator 300 can also control the L third voltage generation circuits to be turned off simultaneously through the fifth control circuit, causing the ramp voltage Vr to drop significantly at the second falling moment. The ramp voltage generator can also be equipped with more common control circuits to achieve more moments when the ramp voltage Vr drops significantly, and this application does not limit this. A common control circuit refers to a control circuit that controls multiple voltage generating circuits, such as the first control circuit 312 and the fifth control circuit. In contrast to a common control circuit is an independent control circuit. An independent control circuit refers to a control circuit that controls only one voltage generating circuit, such as the second control circuit 311.

[0107] In some possible implementations, the second voltage generation circuit 322 can also be coupled to the first control circuit 312 and the second control circuit 311 via the first logic switch 313. That is, the control circuit for all voltage generation circuits can be... Figure 13 , Figure 15 or Figure 17 The structure is shown. The ramp voltage generator 300 can use the first multiplexer 35 to select whether any voltage generation circuit participates in the simultaneous shutdown among all voltage generation circuits. The ramp voltage generator 300 can also use the first logic switch 313 to select a specific voltage generation circuit from all voltage generation circuits to participate in the simultaneous shutdown.

[0108] In some possible implementations, when the ramp switch is turned off, the current source coupled to the ramp switch can be shut off.

[0109] In some other possible implementations, when the ramp switch is turned off, the current source coupled to the ramp switch may not be turned off. The current from the current source can be discharged through a second resistor coupled to the current source.

[0110] In some examples, such as Figure 18 As shown, the ramp output circuit 320 of the ramp voltage generator 300 further includes M+N auxiliary switches, such as S1 to S4. The first terminals of the M+N auxiliary switches are coupled one-to-one with the current sources (e.g., A1 to A4) in the M+N voltage generation circuits. The M+N auxiliary switches include M first auxiliary switches (e.g., S1 and S4) and N second auxiliary switches (e.g., S2 and S3). The ramp output circuit 320 of the ramp voltage generator 300 also includes a second resistor, such as R2. The first terminal of the second resistor is coupled to the second terminals of all M+N auxiliary switches. The second terminal of the second resistor is grounded. The ramp control circuit 310 can output control signals OP1' to OP4' to the auxiliary switches S1 to S4, thereby controlling the on / off state of the auxiliary switches S1 to S4.

[0111] For example, when K1 is on, S1 is off; when K1 is off, S1 is on. This discharges the current from current source A1.

[0112] In some examples, such as Figure 19 As shown, the ramp control circuit 310 of the ramp voltage generator 300 further includes a third control circuit 314. The first output terminal of the third control circuit 314 is coupled to the control terminals of the M first auxiliary switches. For example, the third control circuit 314 outputs OP1' (OP1' and OP4' are the same) to the first auxiliary switches S1 and S4, thereby controlling the on / off state of the first auxiliary switches S1 and S4.

[0113] The ramp control circuit 310 of the ramp voltage generator 300 also includes N fourth control circuits 315. The first output terminal SF of the N fourth control circuits 315 is coupled one-to-one with the control terminals of the N second auxiliary switches. For example, two fourth control circuits 315 output OP2' and OP3' to the second auxiliary switch S2 and the second auxiliary switch S3 respectively, thereby controlling the on / off state of the second auxiliary switch S2 and the second auxiliary switch S3.

[0114] In some examples, such as Figure 20As shown, the ramp voltage generator 300 further includes: P second logic switches 316 and P fourth control circuits 315. The first output terminal of the third control circuit 314 is coupled to the first input terminals of all P second logic switches 316. The first output terminals of the P fourth control circuits 315 are coupled one-to-one to the second input terminals of the P second logic switches 316. The output terminals of the P second logic switches 316 are coupled one-to-one to the control terminals of P of the M first auxiliary switches. 1 ≤ P ≤ M, and P is an integer.

[0115] In this embodiment, the current source coupled by the ramp switch is also coupled to a second resistor through an auxiliary switch. When the ramp switch is turned off, the auxiliary switch can be turned on to discharge the current from the current source. The M first auxiliary switches can be controlled by a common third control circuit 314, and the N second auxiliary switches can be controlled by N independent fourth control circuits 315 respectively. Thus, they can work in conjunction with the ramp switch.

[0116] In some possible implementations, the structure of the third control circuit 314 can refer to the structure of the first control circuit 312. The structure of the fourth control circuit 315 can refer to the structure of the second control circuit 311. The structure of the second logic switch 316 can refer to the structure of the first logic switch 313.

[0117] In some examples, such as Figure 21 As shown, the third control circuit 314 may include: a third AND gate 37 and a second multiplexer 38. The first input of the third AND gate 37 is coupled to the first input of the third control circuit 314 (for inputting the reset signal RST). The output of the third AND gate 37 is coupled to the first input of the second multiplexer 38. The second inputs of both the third AND gate 37 and the second multiplexer 38 are coupled to the second input of the third control circuit 314 (for inputting the total enable signal SWEN). The selection terminal of the second multiplexer 38 is coupled to the third input of the third control circuit 314 (for inputting the total selection signal SWSEL). The output of the second multiplexer 38 is coupled to the first output of the third control circuit 314 (for outputting a common inverted signal SWP or a high level).

[0118] It can be seen that the signal input to the third control circuit 314 is the same as the signal input to the first control circuit 312, and the signal output by the third control circuit 314 is opposite to the signal output by the first control circuit 312. The control principle of the third control circuit 314 can refer to the control principle of the first control circuit 312. For example, the third control circuit 314 can be integrated with the first control circuit 312, or the third control circuit 314 can reuse part of the circuitry of the first control circuit 312. For instance, the third AND gate 37 and the second multiplexer 38 of the third control circuit 314 can be the second AND gate 36 and the first multiplexer 35 of the first control circuit 312, respectively. That is, the signal output by the first multiplexer 35 of the first control circuit 312 is used as the signal output by the third control circuit 314 and is applied to the control terminal of the auxiliary switch S4 when needed.

[0119] In some examples, such as Figure 21 As shown, the fourth control circuit 315 may include a second latch 39. The reset terminal of the second latch 39 is coupled to the first input terminal of the fourth control circuit 315 (for inputting a reset signal RST). The input terminal of the second latch 39 is coupled to the second input terminal of the fourth control circuit 315 (for inputting a step signal, such as IN1, IN2, IN3, or IN4). Figure 21 Only IN4 is shown as the coupling. The enable terminal of the second latch 39 is coupled to the third input terminal of the fourth control circuit 315 (used to input the latch enable signal LEN). The first output terminal of the second latch 39 is coupled to the first output terminal of the fourth control circuit 315 (used to output the latch inverse signal, such as SF1, SF2, SF3, or SF4). Figure 21 Only SF4 is shown as a coupling. The latching inverse signal (e.g., SF1, SF2, SF3, or SF4) output by the first latch 31 serves as the signal output by the second control circuit 311. If the ramp switch is controlled only by the second control circuit 311, then the latching inverse signal (e.g., SF2 or SF3) of the first latch 31 coupled to the ramp switch serves as the control signal for the ramp switch. The first input terminal of the first control circuit 312 is coupled to the first input terminals of N fourth control circuits 315. The N fourth control circuits 315 and the third control circuit 314 share the reset signal RST. The latching enable terminals of the N second latches 39 are coupled, and the N second latches 39 share the latching enable signal LEN.

[0120] It can be seen that the input signal of the fourth control circuit 315 is the same as the input signal of the second control circuit 311, and the output signal of the fourth control circuit 315 is opposite to the output signal of the second control circuit 311. The control principle of the fourth control circuit 315 can refer to the control principle of the second control circuit 311. For example, the fourth control circuit 315 can be integrated with the second control circuit 311, or the fourth control circuit 315 can reuse part of the circuitry of the second control circuit 311. For example, the second latch 39 of the fourth control circuit 315 can be the first latch 31 of the second control circuit 311. The first latch 31 of the second control circuit 311 outputs two opposite signals (e.g., SL4 and SF4). The latched signal (e.g., SL4) is the output signal of the second control circuit 311 and is applied to the control terminal of the ramp switch K4 when needed. The latched inverse signal (e.g., SF4) is the output signal of the fourth control circuit 315 and is applied to the control terminal of the auxiliary switch S4 when needed.

[0121] In some examples, such as Figure 21 As shown, the second logic switch 316 may include a second OR gate 40 and a fourth AND gate 41. The second input terminal of the second logic switch 316 is coupled to the first input terminal of the second OR gate 40. The second input terminal of the second OR gate 40 is coupled to the control terminal of the second logic switch 316 (used to output an independently selectable inverted signal SVN). The first input terminal of the second logic switch 316 is coupled to the first input terminal of the fourth AND gate 41. The output terminal of the second OR gate 40 is coupled to the second input terminal of the fourth AND gate 41. The output terminal of the fourth AND gate 41 is coupled to the output terminal of the second logic switch 316 (used to output a common inverted signal SWP or a latched inverted signal, such as SF4).

[0122] The control principle of the second logic switch 316 can be referred to the control principle of the first logic switch 313. The embodiments of this application will not be described in detail here.

[0123] In some other possible implementations, the third control circuit 314 may be the same control circuit as the first control circuit 312. The fourth control circuit 315 may be the same control circuit as the second control circuit 311. The output terminal of the first control circuit 312 may be coupled to the second inverter, and the output terminal of the second inverter may be coupled to the control terminals of M first auxiliary switches. The output terminal of the second control circuit 311 may be coupled to the third inverter, and the output terminal of the third inverter may be coupled to the control terminals of N second auxiliary switches.

[0124] based on Figure 1 , Figure 2 , Figure 9 , Figure 10 , Figure 12 , Figure 13, Figure 15 , Figures 17-21 The ramp voltage generator 300 shown can be used to: output a reset voltage in a first time period; and output a ramp voltage in a second time period. The second time period follows the first time period, and the first and second time periods are continuous.

[0125] In some examples, the slope of the ramp voltage is less than 0, and the ramp voltage output at the beginning of the second time period is less than the reset voltage output at the end of the first time period.

[0126] For example, the first time period is the period when the reset signal RST is at a high level, and the second time period is the period when the reset signal RST is at a low level.

[0127] At the end of the first time period and the beginning of the second time period, the voltage drops significantly. This causes the ramp voltage output at the beginning of the second time period to be lower than the reset voltage output at the end of the first time period. The significant voltage drop is because multiple voltage generation circuits are simultaneously turned off at the beginning of the second time period.

[0128] If the voltage generation circuit is low-level conducting, the initial time of the second time period is: the control signal output by the common control circuit corresponding to the multiple voltage generation circuits (e.g., Figure 11 The rising edge of the SWN in the voltage generation circuit arrives at the time. If the ramp switch in the voltage generation circuit is high-level and conducting, the initial time of the second time period is the falling edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits.

[0129] For example, such as Figure 22 As shown in Figure (a), the first time period can be the time period between time T2 and time T3. The second time period can be the time period between time T3 and time T5.

[0130] In other examples, the slope of the ramp voltage is greater than 0, and the ramp voltage output at the beginning of the second time period is greater than the reset voltage output at the end of the first time period.

[0131] For example, at the end of the first time period and the beginning of the second time period, the voltage rises significantly. This causes the ramp voltage output at the beginning of the second time period to be greater than the reset voltage output at the end of the first time period. The significant voltage rise is because multiple voltage generation circuits are simultaneously turned on at the beginning of the second time period.

[0132] If the voltage generation circuit is low-level conducting, the initial time of the second time period is the arrival time of the falling edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits. If the ramp switch in the voltage generation circuit is high-level conducting, the initial time of the second time period is the arrival time of the rising edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits.

[0133] For example, such as Figure 23 As shown in Figure (a), the first time period can be the time period between time T6 and time T7. The second time period can be the time period between time T7 and time T9.

[0134] In some possible implementations, the ramp voltage generator 300 can be used to: output a first ramp voltage in a first sub-time period within a second time period; and output a second ramp voltage in a second sub-time period within the second time period. The second sub-time period follows the first sub-time period, and the first and second sub-time periods are consecutive.

[0135] In some examples, the slopes of the first and second ramp voltages are both less than 0, and the second ramp voltage output at the beginning of the second sub-time period is less than the first ramp voltage output at the end of the first sub-time period.

[0136] For example, the slopes of the first and second ramp voltages may be equal or unequal.

[0137] For example, at the end of the first sub-time period and the beginning of the second sub-time period, the ramp voltage drops significantly. This causes the second ramp voltage output at the beginning of the second sub-time period to be lower than the first ramp voltage output at the end of the first sub-time period. The significant drop in ramp voltage is because multiple voltage generation circuits are simultaneously turned off at the beginning of the second sub-time period.

[0138] If the voltage generation circuit is low-level conducting, the initial time of the second time period is the arrival time of the rising edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits. If the ramp switch in the voltage generation circuit is high-level conducting, the initial time of the second time period is the arrival time of the falling edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits.

[0139] For example, such as Figure 22 As shown in Figure (b), the first sub-time period can be the time period between time T3 and time T4. The second sub-time period can be the time period between time T4 and time T5.

[0140] In other examples, the slopes of the first and second ramp voltages are both greater than 0, and the second ramp voltage output at the beginning of the second sub-time period is greater than the first ramp voltage output at the end of the first sub-time period.

[0141] For example, the slopes of the first and second ramp voltages may be equal or unequal.

[0142] For example, at the end of the first sub-time period and the beginning of the second sub-time period, the ramp voltage increases significantly. This causes the second ramp voltage output at the beginning of the second sub-time period to be greater than the first ramp voltage output at the end of the first sub-time period. The significant increase in ramp voltage is because multiple voltage generation circuits are simultaneously turned on at the beginning of the second sub-time period.

[0143] If the voltage generation circuit is low-level conducting, the initial time of the second time period is the arrival time of the falling edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits. If the ramp switch in the voltage generation circuit is high-level conducting, the initial time of the second time period is the arrival time of the rising edge of the control signal output by the common control circuit corresponding to the multiple voltage generation circuits.

[0144] For example, such as Figure 23 As shown in Figure (b), the first sub-time period can be the time period between time T7 and time T8. The second sub-time period can be the time period between time T8 and time T9.

[0145] In this embodiment, the ramp voltage drops significantly at the end of the previous time period and rises sharply at the beginning of the current time period. This allows the ramp voltage to reach the required voltage value more quickly. Therefore, the ramp voltage's descent time or ramp-up time can be reduced.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0147] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0149] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ramp voltage generator, characterized in that, The ramp voltage generator includes: M+N voltage generation circuits; the M+N voltage generation circuits include M first voltage generation circuits and N second voltage generation circuits; M>1, N≥1, and M and N are both integers; A first control circuit; the first output terminal of the first control circuit is coupled to the control terminals of the M first voltage generating circuits; the first control circuit is used to control the on / off state of the M first voltage generating circuits; N second control circuits, wherein the first output terminals of the N second control circuits are coupled one-to-one with the control terminals of the N second voltage generation circuits; the N second control circuits are used to control the on / off state of the N second voltage generation circuits one-to-one. The output terminals of the M+N voltage generation circuits are all coupled to the output terminal of the ramp voltage generator. The ramp voltage generator is used to adjust the ramp voltage value output by the ramp voltage generator according to the on / off state of the M+N voltage generation circuits.

2. The ramp voltage generator according to claim 1, characterized in that, The first control circuit includes: The first inverter; the input terminal of the first inverter is coupled to the first input terminal of the first control circuit, and the output terminal of the first inverter is coupled to the first output terminal of the first control circuit.

3. The ramp voltage generator according to claim 2, characterized in that, The first input terminal of the first control circuit is coupled to the first input terminals of the N second control circuits; The second control circuit includes: A latch; the reset terminal of the latch is coupled to the first input terminal of the second control circuit; the input terminal of the latch is coupled to the second input terminal of the second control circuit; the first output terminal of the latch is coupled to the first output terminal of the second control circuit.

4. The ramp voltage generator according to any one of claims 1-3, characterized in that, The ramp voltage generator also includes: P logic switches and P second control circuits; the first output terminal of the first control circuit is coupled to the first input terminal of each of the P logic switches; the first output terminal of each of the P second control circuits is coupled to the second input terminal of each of the P logic switches; the output terminal of each of the P logic switches is coupled to the control terminal of each of the P first voltage generation circuits in the M first voltage generation circuits; 1≤P≤M, and P is an integer.

5. The ramp voltage generator according to claim 4, characterized in that, The logic switch includes: A first AND gate and a first OR gate; the first input terminal of the logic switch is coupled to the first input terminal of the first AND gate; the second input terminal of the first AND gate is coupled to the control terminal of the logic switch; the output terminal of the first AND gate is coupled to the first input terminal of the first OR gate; the second input terminal of the first OR gate is coupled to the second input terminal of the logic switch; the output terminal of the first OR gate is coupled to the output terminal of the logic switch.

6. The ramp voltage generator according to claim 4 or 5, characterized in that, The first control circuit includes: A first multiplexer and a first inverter; the first input terminal of the first multiplexer is coupled to the first input terminal of the first control circuit; the second input terminal of the first multiplexer is coupled to the second input terminal of the first control circuit; the selection terminal of the first multiplexer is coupled to the third input terminal of the first control circuit; the output terminal of the first multiplexer is coupled to the input terminal of the first inverter; the output terminal of the first inverter is coupled to the first output terminal of the first control circuit.

7. The ramp voltage generator according to claim 4 or 5, characterized in that, The first control circuit further includes: A second AND gate, a first multiplexer, and a first inverter; the first input of the second AND gate is coupled to the first input of the first control circuit; the second input of the second AND gate and the second input of the multiplexer are both coupled to the second input of the first control circuit; the output of the second AND gate is coupled to the first input of the multiplexer; the selection terminal of the first multiplexer is coupled to the third input of the first control circuit; the output of the first multiplexer is coupled to the input of the first inverter; the output of the first inverter is coupled to the first output of the first control circuit.

8. The ramp voltage generator according to any one of claims 1-7, characterized in that, Each of the M+N voltage generation circuits includes: a current source, a ramp switch, and a first resistor; The first resistor in each of the M+N voltage generation circuits is the same first resistor; The current sources in the M+N voltage generation circuits are coupled one-to-one with the first terminals of the ramp switches in the M+N voltage generation circuits; the second terminals of the ramp switches in the M+N voltage generation circuits and the first terminals of the first resistors are both coupled to the output terminals of the M+N voltage generation circuits; the control terminal of the ramp switches is the control terminal of the voltage generation circuits; the second terminal of the first resistor is grounded.

9. The ramp voltage generator according to claim 8, characterized in that, The ramp voltage generator also includes: M+N auxiliary switches; the first terminals of the M+N auxiliary switches are coupled one-to-one with the current sources in the M+N voltage generation circuits; the M+N auxiliary switches include M first auxiliary switches and N second auxiliary switches; The second resistor; the first end of the second resistor is coupled to the second ends of all M+N auxiliary switches; the second end of the second resistor is grounded; A third control circuit; the first output terminal of the third control circuit is coupled to the control terminals of the M first auxiliary switches; N fourth control circuits; the first output terminals of the N fourth control circuits are coupled one-to-one with the control terminals of the N second auxiliary switches.

10. A ramp voltage generator, characterized in that, The ramp voltage generator is used for: Output the reset voltage during the first time period; In the second time period, the ramp voltage is output; the second time period is after the first time period, and the first time period and the second time period are continuous. Wherein, the slope of the ramp voltage is less than 0, and the ramp voltage output at the initial moment of the second time period is less than the reset voltage output at the end moment of the first time period; or, the slope of the ramp voltage is greater than 0, and the ramp voltage output at the initial moment of the second time period is greater than the reset voltage output at the end moment of the first time period.

11. A ramp voltage generator, characterized in that, The ramp voltage generator is used for: In the first sub-time period, output the first ramp voltage; In the second sub-time period, the second ramp voltage is output; the second sub-time period is located after the first sub-time period, and the first sub-time period and the second sub-time period are continuous; Wherein, the slopes of the first and second slope voltages are both less than 0, and the second slope voltage output at the beginning of the second sub-time period is less than the first slope voltage output at the end of the first sub-time period; or, the slopes of the first and second slope voltages are both greater than 0, and the second slope voltage output at the beginning of the second sub-time period is greater than the first slope voltage output at the end of the first sub-time period.

12. A chip system, characterized in that, The chip system includes an analog-to-digital conversion circuit and a ramp voltage generator as described in any one of claims 1-11; The analog-to-digital converter circuit is coupled to the ramp voltage generator.

13. An electronic device, characterized in that, The electronic device includes a circuit board and the chip system as described in claim 12; The chip system is mounted on the circuit board.

14. The electronic device according to claim 13, characterized in that, The electronic device also includes a pixel array; The pixel array is coupled to the chip system.

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