Multiplex terminal resistor module, simplex interface chip and electronic equipment
By reusing terminating resistor modules and logic circuits to provide matching impedance for simplex interface chips, the problems of increased area and power consumption in existing technologies are solved, and signal integrity and power consumption optimization are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPONE TECHNOLOGY (BEIJING) CO LTD
- Filing Date
- 2026-01-21
- Publication Date
- 2026-05-15
AI Technical Summary
Existing simplex interface chips require two RDACs to achieve a 50Ω matching impedance, which increases chip area, calibration time, and power consumption. Furthermore, power consumption cannot be reduced by adjusting the impedance value at the TX terminal during low-speed signal transmission.
By employing a multiplexed terminating resistor module, a digital-to-analog converter is multiplexed using selection logic circuitry and multiplication logic circuitry to provide matched impedance for the receiving and transmitting ports. The impedance value at the TX end is multiplied by a configurable multiplication factor adjustment code during low-speed signal transmission.
This reduces the area and calibration time of the simplex interface chip, ensures signal transmission integrity, and lowers chip power consumption.
Smart Images
Figure CN122052768A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a multiplexed terminating resistor module, a simplex interface chip, and an electronic device. Background Technology
[0002] In traditional wired simplex interface chips, the transmission line typically has a 50Ω characteristic impedance. If the transmitter (TX) and receiver (RX) ports lack a 50Ω matching impedance, signal attenuation and reflection will occur at the TX and RX ports. When the signal transmission rate exceeds 1.5Gbps, this significantly impairs signal integrity. Therefore, a terminating resistor circuit (i.e., a resistive digital-to-analog converter, RDAC) is usually set up for both TX and RX. Thus, a simplex interface chip requires two RDACs, necessitating two RDAC calibration times to achieve the 50Ω matching impedance. This increases the chip area and the calibration time using Automatic Test Equipment (ATE). Furthermore, it has been found that when the signal transmission rate is less than 1.5Gbps, increasing the impedance value at the TX end can reduce TX power consumption without affecting signal integrity. However, after ATE calibration of the RDAC at the TX end, the impedance value generated by the RDAC at the TX end is fixed, making it impossible to reduce power consumption by increasing the TX impedance value, thus increasing the chip's power consumption. In summary, the existing simplex interface chips that use two RDACs to provide matching impedances for TX and RX increase chip area, calibration time, and power consumption. Summary of the Invention
[0003] In view of this, this disclosure proposes a multiplexed terminating resistor module, simplex interface chip, and electronic device that can reduce the area, calibration time, and power consumption of the simplex interface chip.
[0004] According to one aspect of this disclosure, a multiplexed terminating resistor module is provided, comprising: a selection logic circuit, a multiplying logic circuit, and a digital-to-analog converter (DAC); wherein the output terminal of the selection logic circuit is connected to the input terminal of the multiplying logic circuit, the output terminal of the multiplying logic circuit is connected to the DAC, and the DAC is connected to the input / output ports of a simplex interface chip, the input / output ports including a receiving port and a transmitting port; wherein the selection logic circuit is used to determine the current operating mode of the simplex interface chip and output a terminating resistor adjustment code and a multiplying factor adjustment code corresponding to the current operating mode, wherein the terminating resistor adjustment code represents the reference impedance value required by the input / output port, and the multiplying factor adjustment code represents the amplification factor of the reference impedance value; the multiplying logic circuit is used to output a digital control code according to the terminating resistor adjustment code and the multiplying factor adjustment code, the digital control code representing the target impedance value required by the receiving port or the transmitting port in the current operating mode; the DAC is used to convert the digital control code into the corresponding target impedance value to provide the corresponding target impedance value to the receiving port or the transmitting port.
[0005] In one possible implementation, determining the current operating mode of the simplex interface chip and outputting the termination resistor adjustment code and multiplier factor adjustment code corresponding to the current operating mode includes: determining the current operating mode of the simplex interface chip based on the externally input transmit mode enable setting and receive mode enable setting; the operating mode includes a transmit mode using the transmit port or a receive mode using the receive port; based on the current operating mode of the simplex interface chip, processing the externally input termination resistor adjustment setting and multiplier factor adjustment setting into a termination resistor adjustment code and multiplier factor adjustment code corresponding to the current operating mode; wherein, the multiplier factor adjustment code in the transmit mode represents an amplification factor greater than or equal to 1, and the multiplier factor adjustment code in the receive mode represents an amplification factor of 1.
[0006] In one possible implementation, when the transmit mode enable setting is 1 and the receive mode enable setting is 0, the simplex interface chip operates in transmit mode; when the receive mode enable setting is 1, the simplex interface chip operates in receive mode; the operating mode also includes a high-impedance mode when neither the transmit port nor the receive port is used, and when both the transmit mode enable setting and the receive mode enable setting are 0, the simplex interface chip operates in high-impedance mode.
[0007] In one possible implementation, the selection logic circuit includes: a first NOT gate, a second NOT gate, a first NAND gate, a second NAND gate, an AND gate, an OR gate, and a decoder; wherein, the input of the first NOT gate is input to the transmit mode enable position, and the output of the first NOT gate is connected to the first input of the first NAND gate; the input of the second NOT gate is input to the receive mode enable position, the output of the second NOT gate is connected to the second input of the first NAND gate and the first input of the second NAND gate, and the second output of the second NAND gate is input to the transmit mode enable position; the output of the first NAND gate is connected to the first input of the AND gate, the second input of the AND gate is input to the termination resistor adjustment position, and the output of the AND gate is connected to the input of the multiplication logic circuit; the output of the second NAND gate is connected to the first input of the OR gate, the second input of the OR gate is input to the multiplication factor adjustment position, the output of the OR gate is connected to the input of the decoder, and the output of the decoder is connected to the input of the multiplication logic circuit; the decoder is used to convert the output value of the OR gate into the multiplication factor adjustment code.
[0008] In one possible implementation, the digital-to-analog converter employs an N-bit resistor switch array with a single-ended or differential structure. The digital control code is an N-bit binary code, where the nth binary bit is used to control the switching state of the nth resistor in the digital-to-analog converter. N is a positive integer, and 0 ≤ n < N.
[0009] In one possible implementation, the terminal resistor adjustment code is an N-bit binary code; the multiplier adjustment code is a K-bit binary code; one bit of the multiplier adjustment code is 1, and the remaining bits are 0; different amplification factors correspond to different multiplier adjustment codes, K=N-1; wherein, the multiplier logic circuit uses N parallel K-to-1 shift multipliers, and the nth K-to-1 shift multiplier is used to select one bit from the K-bit binary number shifted into the terminal resistor adjustment code based on the multiplier adjustment code to obtain the nth binary number in the digital control code; wherein, the K-bit binary numbers input to different K-to-1 shift multipliers are different.
[0010] In one possible implementation, the reference impedance value depends on the transmission line impedance, and each resistance value of the N-bit resistor switch array depends on the reference impedance value, wherein the redundant bit resistance value is equal to the least significant bit resistance value, and the most significant bit resistance value is 1 / M of the least significant bit resistance value. (N-2) M is a positive integer.
[0011] In one possible implementation, during the calibration phase of the multiplexed terminating resistor module, the operating mode is controlled to receive mode to obtain the terminating resistor adjustment code corresponding to the reference impedance value, and based on the terminating resistor adjustment code corresponding to the reference impedance value, the multiplication factor adjustment code under different amplification factors is determined.
[0012] According to another aspect of this disclosure, a simplex interface chip is provided, including input / output ports, and further including: the aforementioned multiplexed terminating resistor module.
[0013] According to another aspect of this disclosure, an electronic device is provided including the aforementioned simplex interface chip.
[0014] According to various aspects of this disclosure, by utilizing selection logic circuits and multiplication logic circuits, the receive port and transmit port in a simplex interface chip can reuse a single digital-to-analog converter (such as an RDAC) to provide impedance values matching the transmission line impedance. This requires only one digital-to-analog converter and one digital-to-analog converter calibration time, thereby reducing chip area and calibration time using ATE. Furthermore, the selection logic circuits and multiplication logic circuits can provide accurate reference impedance values for the receive port and transmit port, ensuring signal transmission integrity. Additionally, the impedance value of the transmit port TX can be amplified by multiplying the reference impedance value using a configurable multiplication factor adjustment code. This not only ensures the integrity of the transmit port TX signal transmission but also reduces chip power consumption. In other words, the impedance value of the transmit port TX can be multiplied by the multiplication logic circuit, not limited by the impedance fixation after ATE calibration. Thus, when the signal transmission rate is less than 1.5Gbps, the impedance value at the TX end can be multiplied, thereby reducing power consumption at the TX end. In summary, the multiplexed terminating resistor module using embodiments of this disclosure can effectively reduce the area, calibration time, and power consumption of a simplex interface chip.
[0015] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0016] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0017] Figure 1 A block diagram of a multiplexed terminating resistor module according to an embodiment of the present disclosure is shown.
[0018] Figure 2 A schematic diagram of a multiplexed terminating resistor module according to an embodiment of the present disclosure is shown.
[0019] Figure Labels
[0020] exist Figure 1 and Figure 2 In the diagram, 10 represents a selection logic circuit, 11 represents a multiplication logic circuit, 12 represents a digital-to-analog converter, 101 represents the first NOT gate, 102 represents the second NOT gate, 103 represents the first NAND gate, 104 represents the second NAND gate, 105 represents an AND gate, 106 represents an OR gate, and 107 represents a decoder. Detailed Implementation
[0021] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0022] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0023] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0024] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0025] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0026] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0027] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.
[0028] Figure 1 A block diagram of a multiplexed terminating resistor module according to an embodiment of the present disclosure is shown. Figure 1 As shown, the multiplexing terminating resistor module includes: a selection logic circuit 10, a multiplication logic circuit 11, and a digital-to-analog converter 12; wherein, the output terminal of the selection logic circuit 10 is connected to the input terminal of the multiplication logic circuit 11, the output terminal of the multiplication logic circuit 11 is connected to the digital-to-analog converter 12, and the digital-to-analog converter 12 is connected to the input-output (IO) port of the simplex interface chip, and the input-output (IO) port includes a receive port TX and a transmit port RX;
[0029] Among them, the selection logic circuit 10 is used to determine the current working mode of the simplex interface chip and output the termination resistance adjustment code and multiplication factor adjustment code corresponding to the current working mode. The termination resistance adjustment code represents the reference impedance value required by the input and output ports, and the multiplication factor adjustment code represents the amplification factor of the reference impedance value.
[0030] The multiplication logic circuit 11 is used to output a digital control code based on the terminal resistance adjustment code and the multiplication factor adjustment code. The digital control code represents the target impedance value required by the receiving port or the transmitting port in the current working mode.
[0031] The digital-to-analog converter 12 is used to convert digital control codes into corresponding target impedance values to provide the corresponding target impedance values to the receiving port or the transmitting port.
[0032] According to the multiplexing terminating resistor module of this disclosure, by utilizing selection logic circuitry and multiplication logic circuitry, the receiving port and transmitting port of the simplex interface chip can multiplex a single digital-to-analog converter (such as an RDAC) to provide impedance values matching the transmission line impedance. This requires only one digital-to-analog converter and one digital-to-analog converter calibration time, thereby reducing chip area and calibration time using ATE. Furthermore, the selection logic circuitry and multiplication logic circuitry can provide accurate reference impedance values for the receiving port and transmitting port, thereby ensuring the integrity of signal transmission. Additionally, the impedance value of the transmitting port TX can be amplified by multiplying the reference impedance value using a configurable multiplication factor adjustment code. This not only ensures the integrity of the TX signal transmission at the transmitting port but also reduces chip power consumption. In other words, the impedance value of the transmitting port TX can be multiplied by the multiplication logic circuitry, not limited by the impedance fixation after ATE calibration. Thus, when the signal transmission rate is less than 1.5Gbps, the impedance value at the TX end can be multiplied, thereby reducing power consumption at the TX end. In summary, the multiplexing terminating resistor module of this disclosure can effectively reduce the area, calibration time, and power consumption of the simplex interface chip.
[0033] In some embodiments, the current operating mode of the simplex interface chip is determined, and the terminating resistor adjustment code and multiplication factor adjustment code corresponding to the current operating mode are output, including:
[0034] Based on the external input transmit mode enable setting and receive mode enable setting, determine the current operating mode of the simplex interface chip. The operating mode includes transmit mode using the transmit port or receive mode using the receive port.
[0035] Based on the current operating mode of the simplex interface chip, the externally input terminating resistor adjustment range and multiplier factor adjustment range are processed into terminating resistor adjustment codes and multiplier factor adjustment codes corresponding to the current operating mode.
[0036] In this method, the multiplier adjustment code in transmit mode represents an amplification factor greater than or equal to 1, while the multiplier adjustment code in receive mode represents an amplification factor of 1. This allows for the provision of a precise reference impedance value to the receive port RX in receive mode, and the multiplier adjustment code in transmit mode amplifies the impedance value provided to the transmit port TX by multiples, thereby ensuring signal transmission integrity while reducing power consumption at the receive port.
[0037] In practical applications, the transmit mode enable position, receive mode enable position, termination resistor adjustment position, and multiplier factor adjustment position can be obtained from the register of the external digital processing circuit. The external digital processing circuit can determine the specific values of the transmit mode enable position, receive mode enable position, termination resistor adjustment position, and multiplier factor adjustment position input to the selection logic circuit based on information such as the working timing of the simplex interface chip and the data transmission rate. This disclosure does not limit this aspect.
[0038] In some embodiments, the transmit mode enable position and receive mode enable position can be represented by a single binary number, the terminal resistor adjustment position can be represented by an N-bit binary number, and the multiplier factor adjustment position can be represented by a two-bit binary number. This disclosure does not limit the scope of the embodiments.
[0039] In some embodiments, as shown in Table 1, the operating modes FUNCTION (MODE) under different transmit mode enable levels EN_TX and receive mode enable levels EN_RX are as follows: when the transmit mode enable level is 1 and the receive mode enable level is 0, the simplex interface chip operates in transmit mode TX; when the receive mode enable level is 1, the simplex interface chip operates in receive mode RX. The operating modes also include a high-impedance mode HZ when neither the transmit nor receive port is used. When both the transmit and receive modes are 0, the simplex interface chip operates in high-impedance mode. High-impedance mode can be understood as the port in the chip not working (i.e., not transmitting signals). Therefore, in this mode, the switch states corresponding to each resistor in the digital-to-analog converter 12 can all be open.
[0040] Table 1
[0041]
[0042] It should be understood that the terminating resistor adjustment range determines the terminating resistor adjustment code. The terminating resistor adjustment code represents the required reference impedance value for the input / output port. This reference impedance value depends on the transmission line impedance. Therefore, if the transmission line impedance is constant (e.g., 50Ω), the reference impedance value is also constant (e.g., 50Ω), resulting in a constant terminating resistor adjustment code and corresponding terminating resistor adjustment range. If the transmission line impedance changes, the corresponding terminating resistor adjustment code and range also change. Therefore, the corresponding terminating resistor adjustment code can be determined based on the reference impedance value, thus yielding the corresponding terminating resistor adjustment range. Similarly, the multiplier factor adjustment range determines the multiplier factor adjustment code. Therefore, the corresponding multiplier factor adjustment code can be determined based on different amplification factors, thus yielding the multiplier factor adjustment range for different amplification factors.
[0043] In practical applications, during the calibration phase of the multiplexed terminating resistor module, the operating mode can be controlled to receive mode to obtain the terminating resistor adjustment code corresponding to the reference impedance value. Based on the terminating resistor adjustment code corresponding to the reference impedance value, the multiplication factor adjustment code for different amplification factors can be determined. Specifically, during the calibration phase of the multiplexed terminating resistor module, the operating mode can be controlled to receive mode by setting the transmit mode enable and receive mode enable positions (which is equivalent to keeping the amplification factor represented by the multiplication factor adjustment code at 1). The terminating resistor adjustment code corresponding to the reference impedance value can be obtained using ATE (for example, the resistance value of the digital-to-analog converter 12 can be measured by ATE, and the corresponding terminating resistor adjustment code can be continuously adjusted to obtain the terminating resistor adjustment code when the resistance value of the digital-to-analog converter 12 is the reference impedance value), thus obtaining the corresponding terminating resistor adjustment position. Furthermore, based on the terminating resistor adjustment code corresponding to the reference impedance value (that is, keeping the terminating resistor adjustment code as the terminating resistor adjustment code corresponding to the reference impedance value), the multiplication factor adjustment code under different amplification factors can be determined by ATE. For example, the resistance value of the digital-to-analog converter 12 can be measured by ATE, and the corresponding multiplication factor adjustment code can be continuously adjusted to obtain the multiplication factor adjustment code when the resistance value of the digital-to-analog converter 12 is M times the reference impedance value. For example, if the reference impedance value is 50Ω, the multiplication factor adjustment codes corresponding to the resistance values of the digital-to-analog converter 12 of 100Ω (that is, 2 times the reference impedance value), 200Ω (that is, 4 times the reference impedance value), and 400Ω (that is, 8 times the reference impedance value) can be tested and obtained respectively.
[0044] Therefore, by knowing the terminating resistor adjustment code corresponding to the known reference impedance value and the multiplier adjustment code corresponding to different amplification factors, a mapping relationship is established between the terminating resistor adjustment code and the reference impedance value, as well as a mapping relationship between different amplification factors and the multiplier adjustment code. Thus, in some embodiments, a mapping relationship can be further established between the terminating resistor adjustment code and the terminating resistor adjustment level, and a mapping relationship between the multiplier adjustment code for different amplification factors and the multiplier adjustment level. For example, both the terminating resistor adjustment code and the terminating resistor adjustment level can be represented as N-bit binary codes, in which case the terminating resistor adjustment code is directly equal to the terminating resistor adjustment level. Of course, the terminating resistor adjustment level and the terminating resistor adjustment code can also use different numbers of bits or different bases, as long as the terminating resistor adjustment level can be mapped to the corresponding terminating resistor adjustment code (for example, a decoder can be added to the selection logic circuit 10 to achieve the above mapping). This disclosure does not limit this aspect. For example, the multiplier adjustment code can be represented as a K-bit binary code, where K=N-1, and the multiplier adjustment level can be represented as a two-bit binary code. A mapping relationship between the K-bit multiplier adjustment code and the two-bit multiplier adjustment level with the same amplification factor can be established in advance. A decoder can be added to the selection logic circuit 10 to realize this mapping relationship, so that the multiplier adjustment level can be mapped to the corresponding multiplier adjustment code. Of course, the multiplier adjustment code and the multiplier adjustment level can both be represented as K-bit binary codes, in which case the multiplier adjustment code is directly equal to the multiplier adjustment level. Alternatively, the multiplier adjustment code and the multiplier adjustment level can also be represented in different bases (such as decimal). This embodiment of the present disclosure does not limit this.
[0045] In some embodiments, the selection logic circuit 10 can be implemented using combinational logic to determine whether the RDAC is used as the TX port impedance or the RX port impedance, such as... Figure 2As shown, the selection logic circuit 10 may specifically include: a first NOT gate 101, a second NOT gate 102, a first NAND gate 103, a second NAND gate 104, an AND gate 105, an OR gate 106, and a decoder 107; wherein, the input terminal of the first NOT gate 101 is set to the transmit mode enable position EN_TX, and the output terminal of the first NOT gate 101 is connected to the first input terminal of the first NAND gate 103; the input terminal of the second NOT gate 103 is set to the receive mode enable position EN_RX, the output terminal of the second NOT gate 102 is connected to the second input terminal of the first NAND gate 103 and the first input terminal of the second NAND gate 104, and the second output terminal of the second NAND gate 104 is set to the transmit mode enable position EN_TX; the first NAND gate 102... The output of gate 103 is connected to the first input of AND gate 105. The second input of AND gate 105 is connected to the terminal resistor adjustment range TRIM_TERM<4:0>. The output of AND gate 105 is connected to the input of multiplier logic circuit 11 to output the terminal resistor adjustment code TRIM<4:0>. The output of second NAND gate 104 is connected to the first input of OR gate 106. The second input of OR gate 106 is connected to the multiplier factor adjustment range SEL_MULT<1:0>. The output of OR gate 106 is connected to the input of decoder 107. The output of decoder 107 is connected to the input of multiplier logic circuit 11. Decoder 107 is used to convert the output value of OR gate 106 into a multiplier factor adjustment code. This selection logic circuit 10 can achieve its desired function through simple combinational logic. This selection logic circuit 10 uses simple combinational logic to achieve the selection of operating mode and the conversion of input information, with a simple structure, small area, and low power consumption.
[0046] For example, taking the resolution N=5bit of the RDAC as an example, the termination resistor adjustment range TRIM_TERM<4:0> and the termination resistor adjustment code TRIM<4:0> can be 5-bit binary codes. The decoder 107 can be a DEC2T4 (2-bit to 4-bit decoder), which can convert the two-bit binary value output by the OR gate 106 into a 4-bit binary multiplication factor adjustment code MULT<3:0>, that is, convert the two-bit binary multiplication factor adjustment code into a 4-bit binary multiplication factor adjustment code.
[0047] In some embodiments, the digital-to-analog converter 12 can employ an N-bit resistor switch array with a single-ended structure (i.e., a resistor connected between the I / O and the power supply / ground) or a differential structure (i.e., a resistor connected between two differential I / Os). Thus, the digital-to-analog converter 12 can be a resistive digital-to-analog converter, wherein the digital control code is an N-bit binary code, and the nth binary bit in the digital control code is used to control the switching state corresponding to the nth resistor in the digital-to-analog converter 12, where N is a positive integer, 0 ≤ n < N. For example, as... Figure 2The illustrated digital-to-analog converter 12 employs a single-ended 5-bit resistor switch array (i.e., the RDAC resolution N=5 bits). As mentioned above, the reference impedance value depends on the transmission line impedance, and the resistance values of each bit in the N-bit resistor switch array depend on the reference impedance value. Specifically, the resistance value of the redundant bit is equal to the Least Significant Bit (LSB) resistance value, and the resistance value of the Most Significant Bit (MSB) is 1 / M of the LSB resistance value. (N-2) M is a positive integer (M can be understood as a multiplier factor between different bit resistor values in the RDAC). It should be understood that M can be set by the user and corresponds to the amplification factor of the reference impedance value mentioned above.
[0048] For example, such as Figure 2 In the RDAC shown, M=2, N=5, the LSB bit resistance value and the redundant bit resistance value are R, the LSB-1 bit resistance value is R / 2, the LSB-2 bit resistance value is R / 4, and the MSB resistance value is R / 8. In practical applications, the LSB bit resistance value R can be obtained by setting the terminal resistance adjustment code to the middle number of the N-bit binary code (such as binary 10000), and the total impedance generated by the digital-to-analog converter 12 to the reference impedance value (such as 50Ω). Other bit resistance values (such as R / 2, R / 4, R / 8, etc.) can then be calculated. This embodiment of the present disclosure does not limit this.
[0049] In some embodiments, the multiplication logic circuit 11 can be implemented using a K-to-one shifter-based multiplier to execute a digital output that varies in multiples when the RDAC provides the impedance value of the TX port. For example, Table 2 shows the impedance values FUNCTION (afterATE) generated by the digital-to-analog converter 12 under different operating modes MODE and different multiplication factor adjustment levels SEL_MULT<1:0>, where TRIM_TERM<4:0> represents the terminal resistor adjustment level.
[0050] Table 2
[0051]
[0052] As shown in Table 2, the impedance value is 0 in high-impedance mode; in receive mode, the impedance value follows the terminal resistor adjustment level, which is equal to the reference impedance value; in transmit mode, different multiplication factor adjustment levels correspond to different impedance values.
[0053] As described above, the terminal resistor adjustment code is an N-bit binary code; the multiplier adjustment code is a K-bit binary code, where K = N-1; wherein, one bit of the multiplier adjustment code is 1 and the rest are 0. For example, when the amplification factor corresponding to the multiplier adjustment code is 1, the multiplier adjustment code can be 1000; different amplification factors correspond to different multiplier adjustment codes; thus, in some embodiments, the multiplier logic circuit 12 can specifically adopt N parallel K-to-1 shift multipliers. The nth K-to-1 shift multiplier is used to select one bit from the K-bit binary number shifted into the terminal resistor adjustment code based on the multiplier adjustment code to obtain the nth binary number in the digital control code; wherein, the K-bit binary numbers input to different K-to-1 shift multipliers are different.
[0054] For example, with Figure 2 Taking the multiplication logic circuit 12 shown in the figure as an example, as Figure 2As shown, the terminating resistor adjustment code TRIM<4:0> is a 5-bit binary code, and the multiplier factor adjustment code MULT<3:0> is a 4-bit binary code. The multiplier logic circuit 12 can use five parallel 4-to-1 shift multipliers (MUX4T1). The multiplier factor adjustment code also acts as a selection signal, instructing MUX4T1 to select one bit from the input 4-bit binary number. Specifically, the fourth 4-to-1 shift multiplier is used to shift the input 4-bit binary number (i.e., TRIM) from the terminating resistor adjustment code based on the multiplier factor adjustment code. <4> Select one bit (i.e., the bit indicated by "1" in the multiplication factor adjustment code) to obtain the 4th binary bit SW in the digital control code. <4> Among them, TRIM <4> This represents the 4th bit in the termination resistance adjustment code TRIM<4:0>. The fourth 4-to-1 shift multiplier is used to shift the 4-bit binary number (i.e., TRIM) from the termination resistance adjustment code based on the multiplication factor adjustment code. <3> TRIM <4> Select one bit (,0,0) to obtain the third binary bit SW in the digital control code. <3> Among them, TRIM <3> This represents the 3rd bit in the terminating resistance adjustment code TRIM<4:0>, and so on. The 0th 4-to-1 shift multiplier is used to shift the 4-bit binary number (i.e., TRIM) from the terminating resistance adjustment code based on the multiplication factor adjustment code. <0> TRIM <1> TRIM <2> TRIM <3> Select one bit to obtain the 0th binary bit SW in the digital control code. <0> Among them, TRIM <2> This represents the second bit of the TRIM<4:0> terminal resistance adjustment code, TRIM. <1> This represents the first bit of the termination resistance adjustment code TRIM<4:0>, TRIM <0> This represents bit 0 of the TRIM<4:0> terminal resistance adjustment code, SW <1> SW is the first binary digit in the digital control code. <2> This is the second binary digit in the digital control code, from which we can obtain the 5-bit digital control code SW<4:0>=(SW <4> SW <3> SW <2> SW <1> SW <0> ), then SW <4> Can be controlled Figure 2 The switching state SW corresponds to the 4th resistor R / 8 of the intermediate digital-to-analog converter 12. <3> Can be controlled Figure 2 The switching state corresponding to the third resistor R / 4 of the intermediate digital-to-analog converter 12, and so on, SW <0> Can be controlled Figure 2The switching state corresponding to the 0th resistor R in the digital-to-analog converter 12, for example, when the amplification factor corresponding to the multiplication factor adjustment code is 1, the multiplication factor adjustment code is 1000, and the terminal resistor adjustment code is 10000. Then, through the aforementioned five parallel 4-to-1 shift multipliers, a 5-bit digital control code of 10000 is obtained. It should be understood that by controlling the switching states of each resistor in the digital-to-analog converter 12, the total impedance generated by the entire digital-to-analog converter can be adjusted, thus converting the digital control code into the corresponding target impedance value. This target impedance value may be a reference impedance value, or it may be an impedance value amplified from the reference impedance value.
[0055] It should be understood that since the N parallel K-to-1 shift multipliers have the same multiplication factor adjustment code but different inputs and use a shift input method, the entire multiplication logic circuit 10 can be equivalent to using a simple multiplexer to form a shift multiplier to achieve the multiplication of the terminal resistor adjustment code based on the multiplication factor adjustment code, thus realizing the amplification of the reference impedance value. Moreover, the multiplication logic circuit 10 has a simple structure, a large area, and low power consumption.
[0056] It should be noted that the above Figure 2 The structures of each circuit in the multiplexed terminating resistor module shown are some possible implementations provided by the embodiments of this disclosure. In fact, those skilled in the art can customize the resistor switch structure used in the digital-to-analog converter 12 under the guidance of the embodiments of this disclosure. For example, they can use a resistor switch array with more or fewer bits (N=6 bits, 4 bits, etc.). The corresponding multiplication logic circuit 11 can use a corresponding number of K-to-1 shift multipliers and use the multiplication factor adjustment code and terminating resistor adjustment code corresponding to the binary number. The embodiments of this disclosure do not limit this.
[0057] Based on the multiplexing terminating resistor module proposed in the above embodiments of this disclosure, this disclosure also provides a simplex interface chip, including input / output ports, and further including the aforementioned multiplexing terminating resistor module. In this way, in the simplex interface chip, TX and RX can reuse the same multiplexing terminating resistor module, thus requiring only one RDAC and one RDAC calibration time, reducing the chip area and ATE time; when the signal transmission rate is less than 1.5Gbps, it is not limited by impedance fixing after ATE, and the impedance value at the TX end can be increased by a factor of several, reducing TX power consumption, that is, reducing chip power consumption.
[0058] It should be understood that the simplex interface chip described above may include other required functional modules. This disclosure does not limit the specific circuit structure of the simplex interface chip. In particular, the connection method between the input / output ports of the simplex interface chip and the digital-to-analog converter 12 in the multiplexing terminating resistor module can refer to the connection of the RDAC in the input / output ports of the existing simplex interface chip. This disclosure does not limit this aspect.
[0059] Based on the aforementioned simplex interface chip, this disclosure also provides an electronic device including the simplex interface chip. This allows for unidirectional signal transmission, whereby a receiving port receives a signal transmitted from a transmission line, and the transmitting port then transmits it to the next node.
[0060] It should be understood that the above-mentioned electronic device can be any device that requires the use of a simplex interface chip to realize unidirectional signal transmission, such as sensor signal transmission, etc., and the embodiments disclosed herein do not limit this.
[0061] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of modules according to various embodiments of this disclosure. In this regard, each block in the block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0062] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A multiplexed terminating resistor module, characterized in that, include: The selection logic circuit, the multiplication logic circuit, and the digital-to-analog converter are configured to be connected. The output of the selection logic circuit is connected to the input of the multiplication logic circuit, the output of the multiplication logic circuit is connected to the digital-to-analog converter, and the digital-to-analog converter is connected to the input / output port of the simplex interface chip, wherein the input / output port includes a receiving port and a transmitting port. The selection logic circuit is used to determine the current operating mode of the simplex interface chip and output the termination resistance adjustment code and multiplication factor adjustment code corresponding to the current operating mode. The termination resistance adjustment code represents the reference impedance value required by the input / output port, and the multiplication factor adjustment code represents the amplification factor of the reference impedance value. The multiplication logic circuit is used to output a digital control code according to the terminal resistance adjustment code and the multiplication factor adjustment code, wherein the digital control code represents the target impedance value required by the receiving port or the transmitting port in the current working mode. The digital-to-analog converter is used to convert the digital control code into a corresponding target impedance value, so as to provide the corresponding target impedance value to the receiving port or the transmitting port.
2. The module according to claim 1, characterized in that, The step of determining the current operating mode of the simplex interface chip and outputting the termination resistor adjustment code and multiplication factor adjustment code corresponding to the current operating mode includes: The current operating mode of the simplex interface chip is determined based on the external input transmit mode enable setting and receive mode enable setting; the operating mode includes transmit mode using the transmit port or receive mode using the receive port. Based on the current working mode of the simplex interface chip, the externally input terminal resistor adjustment level and multiplier factor adjustment level are processed into terminal resistor adjustment code and multiplier factor adjustment code corresponding to the current working mode. In the transmitting mode, the multiplier adjustment code represents an amplification factor greater than or equal to 1, while in the receiving mode, the multiplier adjustment code represents an amplification factor of 1.
3. The module according to claim 2, characterized in that, When the transmit mode enable setting is 1 and the receive mode enable setting is 0, the simplex interface chip operates in transmit mode. When the receive mode enable setting is 1, the simplex interface chip operates in receive mode. The operating mode also includes a high-impedance mode when neither the transmitting port nor the receiving port is used. When the transmitting mode enable setting is 0 and the receiving mode enable setting is 0, the simplex interface chip operates in a high-impedance mode.
4. The module according to claim 2 or 3, characterized in that, The selection logic circuit includes: a first NOT gate, a second NOT gate, a first NAND gate, a second NAND gate, an AND gate, an OR gate, and a decoder; wherein, the input terminal of the first NOT gate is input to the transmit mode enable position, and the output terminal of the first NOT gate is connected to the first input terminal of the first NAND gate; the input terminal of the second NOT gate is input to the receive mode enable position, the output terminal of the second NOT gate is connected to the second input terminal of the first NAND gate and the first input terminal of the second NAND gate, and the second output terminal of the second NAND gate is input to the transmit mode enable position; The output of the first NAND gate is connected to the first input of the AND gate, the second input of the AND gate is used to input the terminal resistor adjustment level, and the output of the AND gate is connected to the input of the multiplication logic circuit. The output of the second NAND gate is connected to the first input of the OR gate, the second input of the OR gate is input to the multiplication factor adjustment level, the output of the OR gate is connected to the input of the decoder, the output of the decoder is connected to the input of the multiplication logic circuit, and the decoder is used to convert the output value of the OR gate into the multiplication factor adjustment code.
5. The module according to claim 1, characterized in that, The digital-to-analog converter adopts an N-bit resistor switch array with a single-ended or differential structure. The digital control code is an N-bit binary code. The nth binary bit in the digital control code is used to control the switching state of the nth resistor in the digital-to-analog converter. N is a positive integer, 0 ≤ n < N.
6. The module according to claim 5, characterized in that, The terminal resistor adjustment code is an N-bit binary code; the multiplier adjustment code is a K-bit binary code; one bit of the multiplier adjustment code is 1, and the rest are 0; different amplification factors correspond to different multiplier adjustment codes, K=N-1; The multiplication logic circuit employs N parallel K-to-1 shift multipliers. The nth K-to-1 shift multiplier is used to select one bit from the K-bit binary number shifted into the terminal resistor adjustment code based on the multiplication factor adjustment code, thereby obtaining the nth binary number in the digital control code. The K-bit binary numbers input to different K-to-1 shift multipliers are different.
7. The module according to claim 5 or 6, characterized in that, The reference impedance value depends on the transmission line impedance, and the resistance value of each bit in the N-bit resistor switch array depends on the reference impedance value. The redundant bit resistance value is equal to the least significant bit resistance value, and the most significant bit resistance value is 1 / M of the least significant bit resistance value. (N-2) M is a positive integer.
8. The module according to any one of claims 1 to 3, characterized in that, During the calibration phase of the multiplexed terminating resistor module, by controlling the operating mode to receive mode, the terminating resistor adjustment code corresponding to the reference impedance value is obtained, and based on the terminating resistor adjustment code corresponding to the reference impedance value, the multiplication factor adjustment code under different amplification factors is determined.
9. A simplex interface chip, comprising input and output ports, characterized in that, Also includes: The multiplexed terminating resistor module as described in any one of claims 1 to 8.
10. An electronic device, characterized in that, Includes the simplex interface chip as described in claim 9.