Orthogonal time-frequency-space transceiver suitable for satellite-ground scene

Abstract

The invention discloses an orthogonal time-frequency-space transceiver suitable for a satellite-ground scene, and relates to the technical field of satellite communication, in particular to the orthogonal time-frequency-space transceiver suitable for the satellite-ground scene. The invention aims to solve the problem that the bit error rate is too high. The method comprises the following steps of: 1, enabling transmission data to sequentially pass through a convolutional coding module, an interleaving module, a scrambling module, a QAM (Quadrature Amplitude Modulation) module, an OTFS (Over the Top File System) module and a CP (Content Program) adding module, and inserting DMRS (Demodulation Reference Signal) into output data of the 2, framing a data symbol, an information symbol and a leader sequence; 3, the framed data sequentially pass through a DAC and an antenna to enter a time-frequency double-selection channel, an antenna on the other FPGA receives a signal, then the signal passes through an ADC to reach a frame synchronization module, output data are sequentially input into CFO frequency offset estimation and correction, symbol synchronization, CP removal, FFT, channel estimation and equalization, inverse two-dimensional Fourier transform, information symbol solution, QAM demodulation, descrambling, de-interleaving and de-convolution coding modules, and then the output data are sent to a frame synchronization module. And the received 01 sequence is obtained.

Description

Technical Field

[0001] This invention relates to the field of satellite communication technology, and more specifically to an orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios. Background Technology

[0002] The mobile speed supported by 6G has increased from 500km / h in 5G to 1000km / h. As terminal mobility continues to increase, the wireless signal transmission environment becomes more complex, undoubtedly placing higher demands on physical layer transmission technology. As a key technology of fourth-generation mobile communication, OFDM can flexibly allocate resources and effectively combat multipath fading. However, with the increase in mobile speed, the impact of Doppler shift also increases, which precisely disrupts the orthogonality between OFDM subcarriers. In certain 6G scenarios, OFDM may no longer have a performance advantage, and there is an urgent need to find a new modulation and demodulation method to solve this problem. It is at this time that Orthogonal Time Frequency Space (OTFS) technology, which has superior performance in high-speed mobile environments, has come into view and become one of the alternative waveforms for 6G.

[0003] OTFS is a recently proposed multi-carrier modulation technique with many advantages that OFDM lacks. OTFS effectively resists multipath fading, which, in high-speed mobile environments, causes time-varying and frequency-selective fading. OFDM is highly sensitive to multipath fading, requiring complex equalization and channel estimation algorithms. OTFS, however, utilizes joint time-frequency processing, providing better resistance to multipath fading and reducing signal distortion and interference. Because of this joint processing, OTFS achieves lower latency in high-speed environments and is less affected by Doppler shift. In contrast, OFDM is prone to increased latency and performance degradation in high-speed environments. OTFS achieves higher spectral efficiency by simultaneously utilizing resources in both time and frequency dimensions. Compared to OFDM, OTFS can achieve higher data transmission rates and capacity with the same spectral resources. Due to its joint time-frequency characteristics, OTFS has lower requirements for channel estimation and equalization. OTFS reduces signal processing complexity and simplifies the design of channel estimation and equalization algorithms.

[0004] One of the key application scenarios for 6G is the construction of a unified satellite internet. Satellite internet enables deep integration of space-based and airborne networks with terrestrial mobile communication networks, achieving three-dimensional coverage through integrated consideration of systems, protocols, networks, services, and terminals. Because satellite internet can achieve all-weather, all-area coverage of the Earth's surface and three-dimensional space, users can access the internet on demand anytime, anywhere. However, due to the complex and variable channel environment, limited resources, and large transmission delays, communication performance is affected during satellite internet information transmission. Therefore, how to transmit signals with high quality and efficiency has become a major research hotspot in satellite communication. Compared with terrestrial wireless communication, LEO satellite motion has the characteristics of large spatiotemporal dynamics between satellite and ground, and is therefore more affected by the high Doppler shift caused by high-speed satellite motion. Although the Doppler shift of satellites can be estimated and canceled, the high Doppler shift caused by high-speed moving user terminals on the ground cannot be predicted or canceled. As mentioned earlier, OFDM is very sensitive to Doppler shift. To address this issue, frequency compensation methods are commonly used. However, achieving high accuracy requires fixing the location of the ground terminal. Furthermore, residual Doppler frequency shift can still disrupt the orthogonality between subcarriers. Summary of the Invention

[0005] The purpose of this invention is to solve the problem that due to the high speed of ground user terminals, even with pre-compensation, satellite-to-ground communication still has a large Doppler frequency offset, resulting in an excessively high bit error rate. Therefore, this invention proposes an orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios.

[0006] The specific process of an orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios is as follows:

[0007] Step 1: The transmitted data sequentially passes through the convolutional coding module, interleaving module, scrambling module, QAM modulation module, OTFS modulation module, and CP module. The CP module outputs data, and DMRS is inserted into the CP module output data to obtain the transmitter data symbols.

[0008] Step 2: Frame the data symbols, information symbols, and preamble sequence to obtain the framed data;

[0009] Step 3: The framed data is sequentially fed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes through the ADC to reach the frame synchronization module. The output data of the frame synchronization module is sequentially input into the CFO frequency offset estimation and correction module, symbol synchronization module, CP removal module, FFT module, channel estimation and equalization module, inverse two-dimensional Fourier transform module, information symbol decryption module, QAM demodulation module, descrambling module, deinterleaving module, and deconvolution coding module to obtain the received 01 sequence.

[0010] The beneficial effects of this invention are as follows:

[0011] This invention achieves a low bit error rate in satellite-to-ground communication scenarios where ground terminals are moving at high speeds, meeting current communication performance requirements. This invention addresses the problem of high bit error rates in existing satellite-to-ground communication systems where high-speed movement of ground user terminals, even with pre-compensation, still results in residual Doppler frequency offset. The transmitted data is processed through a convolutional coding module, an interleaving module, a scrambling module, a QAM modulation module, an OTFS modulation module, and a CP addition module to obtain data symbols. DMRS is inserted into the generated data symbols, which are then framed with information symbols and a preamble sequence to form transmitter symbols. These symbols are then transmitted to the real channel via a DAC and antenna. The transmitted signal passes through a receiver antenna, ADC, frame synchronization module, CFO frequency offset estimation and correction module, symbol synchronization module, CP removal module, FFT module, channel estimation and equalization module, inverse two-dimensional Fourier transform module, information symbol decryption module, QAM demodulation module, descrambling module, deinterleaving module, and Viterbi decoding module to obtain the received 0 / 1 sequence.

[0012] The present invention has the following beneficial effects:

[0013] 1. This invention eliminates the need for the two-dimensional Fourier transform followed by IFFT in the traditional OTFS modulation module by directly performing N-point IFFT on the M rows, thus greatly reducing the on-chip latency of the FPGA.

[0014] 2. The synchronization algorithm used in this invention can still achieve good synchronization results in complex channel environments;

[0015] 3. This invention selects to perform channel estimation and equalization processing in the time-frequency domain at the receiver, which is highly compatible with OFDM systems. It can realize OTFS communication systems with minimal changes to existing equipment, greatly reducing the replacement cost for enterprises and lowering the bit error rate. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating the data processing of the OTFS communication system implemented in this invention.

[0017] Figure 2 This is a simplified schematic diagram of OTFS modulation according to the present invention;

[0018] Figure 3 This is a waveform diagram of the output signal of the information symbol generation module of the present invention;

[0019] Figure 4 This is a block diagram of the hardware implementation of channel estimation and equalization in this invention;

[0020] Figure 5This is a schematic diagram of the 16QAM demodulation bit quantization hard decision method of the present invention; Detailed Implementation

[0021] Specific Implementation Method 1: The specific process of this implementation method for an orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios is as follows:

[0022] Step 1: The transmitted data sequentially passes through the convolutional coding module, interleaving module, scrambling module, QAM modulation module, OTFS modulation module, and CP module. The CP module outputs data, and DMRS is inserted into the CP module output data to obtain the transmitter data symbols.

[0023] Step 2: Frame the data symbols, information symbols, and preamble sequence to obtain the framed data;

[0024] Step 3: The framed data is sequentially fed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes through the ADC to reach the frame synchronization module. The output data of the frame synchronization module is sequentially input into the CFO frequency offset estimation and correction module, symbol synchronization module, CP removal module, FFT module, channel estimation and equalization module, inverse two-dimensional Fourier transform module, information symbol decryption module, QAM demodulation module, descrambling module, deinterleaving module, and deconvolution coding module to obtain the received 01 sequence.

[0025] Specific Implementation Method Two: This implementation method differs from Specific Implementation Method One in that: in step one, the transmitted data sequentially passes through a convolutional coding module, an interleaving module, a scrambling module, a QAM modulation module, an OTFS modulation module, and a CP addition module. The CP addition module outputs data, and DMRS is inserted into the output data of the CP addition module to obtain the transmitter data symbols; the specific process is as follows:

[0026] Step 11: Transmit data to the convolutional coding module, and the convolutional coding module outputs data A; the specific process is as follows:

[0027] Design a convolutional coding module with a bit rate of 1 / 2 to perform convolutional coding on the transmitted data. The generator polynomial of the convolutional coding is set as follows: and ;

[0028] in, This represents 133 in octal. This represents 171 in octal. , Represents the generator polynomial;

[0029] Convolutional coding module: Channel coding is a type of anti-interference technique used to ensure the reliability of communication system transmission. It improves transmission reliability by adding redundant information to the data; common examples include convolutional codes, LDPC, and Turbo codes. This invention uses a convolutional coding module as the channel coding method at the physical layer. A convolutional coding module with a code rate of 1 / 2 is designed at the transmitter to encode the transmitted data. The generator polynomial of the convolutional coding is set as follows: and Inside the FPGA chip, the convolutional encoder consists of six serial shift registers. For each input bit, two outputs are calculated using XOR gate logic and ultimately merged into continuous encoded data. During digital signal processing, the scrambled serial bitstream data is input to the encoding module for encoding. After one bit is input, the convolutional encoder outputs two bits of encoded data in parallel. These two parallel bits are then input into the serial-to-serial buffer unit for a parallel-to-serial conversion, and the output serial data clock is doubled to maintain the timing interval between data symbols. For address transformation in subsequent interleaving operations, an internal counter counts the serial encoded data, outputting data labels synchronously with the output encoded data.

[0030] Steps 1 and 2: Input the output data A from the convolutional coding module into the interleaving module, and the interleaving module outputs data B; the specific process is as follows:

[0031] Each symbol contains 48 subcarriers carrying data, each subcarrier uses 16-QAM modulation, and the interleaving depth is set to 192 bits; the interleaving process of the output data A (bit stream) of the convolutional coding module is divided into two stages;

[0032] In the first stage of interleaving, the input data A is written into a 12-row, 16-column matrix, and then the bits are read out column by column.

[0033] In the second-level interleaving process, the input data A is based on 24-bit units. The positions of the first 12 bits remain unchanged, while the last 12 bits are permuted by alternating the positions of adjacent two bits.

[0034] The first-level interleaving and the second-level interleaving processes use a ping-pong operation.

[0035] Interleaving Module: Interleaving is commonly used in wireless communication systems to handle burst errors during data transmission. Wireless channels are susceptible to external interference, leading to consecutive bit errors. Convolutional coding excels at correcting randomly distributed errors. The interleaver shuffles the input data stream, causing consecutive errors during transmission to disperse and become random errors after deinterleaving at the receiver, thus improving the efficiency of error correction coding. The interleaving depth is equal to the number of data segments carried by a single symbol. In this design, each symbol carries data via 48 subcarriers, and each subcarrier uses 16-QAM modulation; therefore, the interleaving depth in the system is set to 192 bits. The interleaving process of the convolutional coding input bitstream can be divided into two levels. The first level of interleaving writes the input bitstream row-by-row into a 12x16 matrix, and then reads out the bits column by column. In the second level of interleaving, data is processed in 24-bit units. The first 12 bits remain unchanged, while the last 12 bits are permuted using an alternating rule of adjacent bits. The reason for the second level of interleaving involves the mapping of constellation points, which avoids the low reliability of the lower 12 bits over a long period. Specifically, if all points fall into secondary positions, this operation can map some of them to important positions. Important positions are the four points closest to the origin, while secondary positions are the points on the edges, which are more affected by noise and fading.

[0036] In the hardware implementation, the RAM resources of the FPGA chip are used as the core component of the interleaving module. The interleaving process is achieved by writing the bit data stream in ascending address order and then reading it out in adjusted address order. Since the RAM cannot write data for the next symbol while reading out interleaved data, the module cannot process continuous symbol data streams. To solve this problem, a ping-pong operation is adopted in the design. The storage depth of the generated RAM is doubled, and the write and read addresses are also widened by one bit. The highest bit of the widened address is used as a transition flag. Adjacent symbol data sequentially use the front and back halves of the RAM's storage space. This way, while the previous set of data is being read out, the next set of data can still be written to the corresponding half of the storage space, thus preventing timing conflicts that could lead to errors in the output bit stream.

[0037] Step 13: Input the data B output from the interleaving module into the scrambling module, and the scrambling module outputs data C; the specific process is as follows:

[0038] The initial value of the feedback shift register is set to 1011101;

[0039] Setting the generator polynomial of the feedback shift register is ;

[0040] The output data B of the interleaving module is input into the feedback shift register. The scrambling sequence generated by the feedback shift register is XORed with the output data B of the interleaving module to obtain the scrambled data C.

[0041] in, This indicates the 7th stage of the feedback shift register. This indicates the 4th stage of the feedback shift register. This represents the generator polynomial of the feedback shift register. Indicates a feedback shift register;

[0042] The purpose of scrambling at the transmitting end is to avoid long sequences of 0s or 1s in digital communication and to prevent interference with symbol synchronization at the receiving end. In this invention, a feedback shift register is used to scramble the output data B of the interleaving module, which can disrupt the sequence order without increasing redundant bits. The initial value of the feedback shift register is 1011101, and the generator polynomial of the feedback shift register is... After XORing the scrambling sequence generated by the feedback shift register with the output data B of the interleaving module, the scrambled output data can be obtained.

[0043] Step 14: Input the scrambling module output data C into the QAM modulation module, and the QAM modulation module outputs data D; the specific process is as follows:

[0044] It adopts 16-QAM modulation;

[0045] Set the data width to 8 bits and the scaling factor to [value missing]. ;

[0046] QAM Modulation Module: The data after scrambling enters the QAM modulation module. The data symbol generation module of this invention uses 16-QAM modulation, dividing the serial data stream into groups of 4 bits. To ensure that all mapping methods have the same average power, the complex symbol components obtained after mapping also need to be normalized. Since 16-QAM normalization involves... Its value is approximately 0.316228, but FPGA cannot represent this decimal well, or in other words, floating-point operations consume too many resources.

[0047] Here we convert floating-point numbers to fixed-point numbers. The process is as follows: set the data width to 8 bits, and set the scaling factor to... ,so It then became 20.

[0048] Based on the 16-QAM modulation principle, the modulation process is relatively simple to implement internally in an FPGA. The 16-QAM modulation module pre-stores the normalized in-direction and quadrature component data of 16 constellation points. After grouping the serial encoded data stream into 4-bit groups, the position of the mapped constellation point can be obtained by judging the values ​​of the two high bits and the low bits. Finally, the corresponding complex symbol data is output.

[0049] Step 15: Input the output data D from the QAM modulation module into the OTFS modulation module. The OTFS modulation module outputs a time-domain transmission signal. ;

[0050] Step 16: Input the time-domain transmit signal output from the OTFS modulation module into the CP module. The CP module outputs the CP-added time-domain transmit signal (added before the time-domain transmit signal output from the OTFS modulation module). The specific process is as follows:

[0051] The CP length is one-quarter of the length of the time-domain transmitted signal output by the OTFS modulation module.

[0052] Step 17: The time-domain transmit signal after CP addition from the CP module is input to the DMRS insertion module, and the DMRS insertion module outputs data symbols; the specific process is as follows:

[0053] Insert a CP and a DMRS for every OTFS symbol.

[0054] DMRS generation reads 64 data points pre-inserted with 0s from the ROM (set up before all other steps).

[0055] The other steps and parameters are the same as in Specific Implementation Method 1.

[0056] Specific Implementation Method Three: This implementation method differs from Specific Implementation Method One or Two in that: in step one-five, the output data D of the QAM modulation module is input into the OTFS modulation module, and the OTFS modulation module outputs a time-domain transmission signal. The specific process is as follows:

[0057] Step 151: The output data D of the QAM modulation module is transformed to the time-frequency domain using ISFFT; it is represented as:

[0058]

[0059] in, Represents data signals in the time-frequency domain. express Fourier transform matrix of order 1, express Fourier inverse transform matrix; This represents the output data D of the QAM modulation module (a two-dimensional information symbol to be transmitted in the time-delay-Doppler domain).

[0060] The ISFFT transform is manifested by first multiplying the output data D of the QAM modulation module on the left by a Fourier transform matrix, and then multiplying it on the right by an inverse Fourier transform matrix.

[0061] Step 152: Data signal in the time-frequency domain The signal is transformed to the time domain using the Heisenberg transform; it is represented as:

[0062]

[0063] In the formula, Send signals in the time domain; for A diagonal matrix of order 1 represents the discrete pulse shaping window function matrix; for The inverse Fourier transform matrix of order 1;

[0064] In matrix operations, the Heisenberg transform is manifested by first left-multiplying the time-frequency domain data by an inverse Fourier transform matrix, and then left-multiplying it by a discrete pulse shaping window function matrix. When the pulse shaping window function is a rectangular window, the diagonal matrix... It's just one Unit matrix of order ;

[0065] Step 153: Combined Formation Japanese style , obtain time-domain transmitted signal A concise representation:

[0066]

[0067] Step 154: Send signal to the time domain concise representation Perform the operation.

[0068] Other steps and parameters are the same as in specific implementation method one or two.

[0069] Specific Implementation Method Four: This implementation method differs from Specific Implementation Methods One to Three in that: in step 154, the signal is sent in the time domain. concise representation Perform the operation; the specific process is as follows:

[0070] Step 1541: Send signal in the time domain The input column-row transformation module rearranges the data, changing the original column-arranged data into row-arranged data. The specific process is as follows:

[0071] Time-domain transmission signal Each group contains 48 numbers, reducing the total data from 56 groups to 48 groups of 56 numbers each. Eight zeros are inserted between the 56 numbers in each group (resulting in 28 numbers, 8 zeros, 28 numbers in total). The time-domain signal is then transmitted in column-ordered fashion. Transformed into a row-arranged time-domain transmitted signal ;

[0072] Step 1542: Send signals to the time domain of the row-by-row input. Perform IFFT operations (the general IFFT / FFT processing module controls the time-domain signal transmission) The last byte is set to 0), and the time-domain transmission signal arranged in rows after the IFFT operation is obtained;

[0073] Step 1543: Transform the row-arranged time-domain transmission signal obtained in Step 1542 into a column-arranged signal, resulting in 64 groups, each with 48 numbers. Insert a zero at the beginning and 15 zeros in the middle of these 48 numbers (i.e., 1 zero followed by 24 numbers, then 15 zeros followed by 24 numbers), thus obtaining the time-domain transmission signal. .

[0074] OTFS modulation module: Data from the QAM modulation module enters the OTFS modulation module. The matrix representation of OTFS is analyzed first, assuming a rectangular window function in the time-frequency domain.

[0075] make This represents a two-dimensional information symbol to be transmitted in the time-delay-Doppler domain, which is obtained by serial-to-parallel conversion of the serial signal to be transmitted. The time-delay-Doppler domain data is then transformed to the time-frequency domain using ISFFT, i.e., first... each row Inverse Fourier transform of the point, then... Each column The Fourier transform of a point, the matrix representation of this process is as follows:

[0076]

[0077] In the above formula For data signals in the time-frequency domain, for Fourier transform matrix of order 1, for The ISFFT transform is a matrix of order-1 inverse Fourier transform. Therefore, in matrix representation, the ISFFT transform is manifested as multiplying the two-dimensional time-delay-Doppler domain data first on the left by a Fourier transform matrix, and then on the right by an inverse Fourier transform matrix.

[0078] Then, the time-frequency domain data is transformed into a time-domain transmitted signal through the Heisenberg transform. In the matrix representation, this is done by first... Each column Inverse Fourier transform of the point, then Adding the same discrete pulse shaping window function to each column, the matrix representation of this process is as follows:

[0079]

[0080] In the above formula The signal to be transmitted in the time domain. for A diagonal matrix of order 1 represents the effect of the pulse shaping window function. for The Heisenberg transform is a matrix of inverse Fourier transform. Therefore, in matrix operations, the Heisenberg transform is manifested by first left-multiplying the time-frequency domain data by an inverse Fourier transform matrix, and then left-multiplying it by a pulse shaping window function matrix. When the transmitted pulse shaping window function is a rectangular window, the diagonal matrix... It's just one Unit matrix of order .

[0081] Then, by combining the two equations, we can obtain the data to be transmitted by the transmitter. A concise representation:

[0082]

[0083] In other words, in actual hardware implementation, it's not necessary to perform a two-dimensional Fourier transform followed by a Heisenberg transform; it only requires... Figure 2 Like the dashed box, you can directly (only need to work on OTFS resource blocks) process each row. Simply use the IFFT function.

[0084] Therefore, the OTFS modulation module actually only needs to be divided into three modules: a column-to-row transformation module, an IFFT module, and a row-to-column transformation module, which will be introduced one by one below.

[0085] The main function of the column-row transformation module is to rearrange the data order, changing the input from column-based to row-based. From a data flow perspective, the original 56 groups of 48 numbers each are transformed into 48 groups of 56 numbers each. Furthermore, four zeros are inserted into each group of 56 numbers to facilitate subsequent IFFT operations. (The row-column transformation module then reverses the IFFT-ordered row-based data back into column-based data.) The part in parentheses is for emphasis; it's not needed in the main body of the text.

[0086] General IFFT / FFT processing module:

[0087] Since IFFT / FFT is frequently invoked in the design of the system baseband transceiver, this invention designs a general-purpose IFFT / FFT processing module based on the Xilinx FFT IP core. This module includes an AXI bus interface for interacting with the FFT IP core and control logic to guide its operations. Users only need to focus on the module's external interface and input data stream format to implement IFFT / FFT operations. Xilinx FPGA chips offer four different architecture types for their FFT soft cores to meet the needs of various design scenarios: pipelined, radix-4 burst, radix-2 burst, and radix-2 Lite burst. To ensure continuous data processing at the transceiver, this project selects a pipelined FFT IP core as the kernel of the IFFT / FFT processing module.

[0088] All channels of the FFT IP core use the AXI interface, mainly including control word channels, input data channels, and output data channels. Each individual channel is controlled using the AXI interface. The AXI interface requires that the current data is valid only when both the valid and ready signals are high simultaneously. The last signal typically indicates the last bit of a data set. After the general IFFT / FFT module is enabled, the FFT IP core must first be configured via external control logic. Only after successful configuration can data be transmitted to it for processing. The last bit of the control byte represents the FFT direction; setting it to 0 indicates an IFFT transform, and setting it to 1 indicates an FFT transform. Once the FFT IP is configured, it will send a high ready signal, and data will begin to be fed into the module for computation.

[0089] The 48 sets of numbers, each with 64 numbers, output from the row and column transformation module are sent as input data to the general IFFT / FFT processing module. By changing the control byte to set the module's calculation direction to IFFT operation and setting the data format to 8-bit fixed-point numbers, the output data is obtained and then sent to the row and column transformation module for the next step of operation.

[0090] The row-column transformation module transforms the data arranged in rows after IFFT back into arranged in columns, resulting in 64 groups of numbers, each group containing 48 numbers. These 48 numbers are then inserted with leading zeros and 15 zeros in the middle before being sent to subsequent modules.

[0091] The other steps and parameters are the same as those in one of the specific implementation methods one to three.

[0092] Specific Implementation Method Five: This implementation method differs from Specific Implementation Methods One to Four in that: in step two, data symbols, information symbols, and preamble sequences are framed to obtain framed data; the specific process is as follows:

[0093] Step 21: Transmit data input to the information symbol generation module; the information symbol generation module generates information symbols; the specific process is as follows:

[0094] The generation of information symbols is similar to that of data symbols, except that the modulation method is BPSK and it does not include a DMRS insertion module;

[0095] This is to ensure its reliability as much as possible. The relationship between the four-bit encoded bits of the information symbol input and the modulation scheme and code rate is shown in Table 1.

[0096] Table 1. Correspondence between modulation scheme, coding scheme and coded bits

[0097] Encoded bits Coding efficiency Modulation method 1101 1 / 2 BPSK 1111 3 / 4 BPSK 0101 1 / 2 QPSK 0111 3 / 4 QPSK 1001 3 / 4 16QAM 1011 1 / 2 16QAM 0001 2 / 3 64QAM 0011 3 / 4 64QAM

[0098] The output waveform of the information symbol generation module is shown below. Figure 3 The input RATA is 1011, indicating that the modulation scheme used for the data symbol is 16-QAM and the coding rate is 1 / 2. The input LENGTH indicates the frame length of the data symbol. These two values ​​provide important information for the receiver to decode the data symbol. DPI_RE is the result of the input data after convolutional coding, interleaving, BPSK modulation, PTRS insertion, and zero padding, which will then be sent to the IFFT module.

[0099] Step 22: Preamble Sequence Generation Module: Preamble sequence generation only requires reading the pre-stored sequence value from the ROM;

[0100] Steps two and three: Frame the data symbols, information symbols, and preamble sequence to obtain the framed data; the specific process is as follows:

[0101] The symbols are combined in the order of the preamble, information symbols, and data symbols.

[0102] A preamble sequence is used for frame and symbol synchronization, followed by an information symbol. This information symbol carries the control information for the frame and is crucial during frame transmission. To ensure correct transmission and reception of information bits, this symbol consistently uses a combination of 1 / 2-rate convolutional coding and BPSK modulation. The modulated information contains a total of 24 bits, including a coded bit field, a length bit field, and a cyclic redundancy check (CRC) field. The coded bit field determines the coding rate and modulation scheme used in the frame. In the system designed in this invention, the transmitter determines the coded bit information to use based on current communication requirements, while the receiver determines the demodulation method for the frame data based on the received coded bits. The length bit field is 12 bits long and represents the length of the data symbols carried in the current frame. The physical layer uses this parameter to determine the total number of bytes transmitted between the physical layer and the MAC layer. To ensure the correctness of the first two fields, the information symbol also includes an 8-bit CRC check field. An 8-bit CRC checksum is obtained by calculating the data in these two fields and is transmitted along with the first two fields. After extracting information symbols at the receiving end, the CRC checksum obtained using the same calculation method is compared with the received CRC checksum. If they differ, the frame is discarded. The DMRS in the data symbols is used for channel estimation and equalization.

[0103] The other steps and parameters are the same as those in one of the specific implementation methods one to four.

[0104] Specific Implementation Method Six: This implementation method differs from Specific Implementation Methods One through Five in that: in step three, the framed data is sequentially passed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. Another antenna on the FPGA receives the signal after passing through the time-frequency dual-selection channel, which then passes through the ADC and reaches the frame synchronization module. The frame synchronization module outputs data sequentially into the CFO frequency offset estimation and correction module, symbol synchronization module, CP removal module, FFT module, channel estimation and equalization module, inverse two-dimensional Fourier transform module, information symbol de-symbol module, QAM demodulation module, descrambling module, deinterleaving module, and deconvolution coding module to obtain the received 01 sequence. The specific process is as follows:

[0105] Step 31: The framed data is sequentially passed through the DAC on the FPGA, the antenna on the FPGA, and then into the time-frequency dual-selection channel. Another antenna on the FPGA receives the signal after passing through the time-frequency dual-selection channel, which is then passed through the ADC and reaches the frame synchronization module. The frame synchronization module outputs the data. The specific process is as follows:

[0106] Step 311: The framed data is sequentially passed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes it through the ADC. The ADC outputs the data.

[0107] Step 312: The ADC output data passes through the frame synchronization module, and the frame synchronization module outputs data; the specific process is as follows:

[0108] Approximation of amplitude calculation ;

[0109] in, Indicates the delay correlation value The real part, Indicates the delay correlation value The imaginary part;

[0110] A frame is considered to have arrived when the value of the decision variable is greater than the threshold for 32 consecutive clock cycles.

[0111] When the value of the decision variable is less than or equal to the threshold for 32 consecutive clock cycles, it represents the end of the frame and the frame synchronization is completed.

[0112] Frame synchronization module: Frame synchronization is the acquisition process that detects the arrival of data frames. Its core function is to identify the arrival time of burst data frames in the channel in real time. The accuracy of frame synchronization directly affects the demodulation performance of the receiver. This paper utilizes the periodicity of the preamble sequence and employs a delay correlation algorithm to detect and synchronize burst frames in the channel.

[0113] Set the window length related to delay. The length of a single cycle of the preceding sequence is equal to that of the preceding sequence. The data within the window is calculated in relation to the preceding sequence. Delay correlation value of each sampling point and autocorrelation value The decision variables of the delay correlation algorithm are obtained. Among them, delay-related The calculated value is

[0114]

[0115] Autocorrelation value of data received within the window for

[0116]

[0117] The final decision variables obtained by the delay correlation algorithm for

[0118]

[0119] In the formula The amplitude needs to be obtained by squaring the real and imaginary parts separately and then adding them together. Performing square root operations within the FPGA consumes significant hardware resources. Since the subsequent threshold decision module does not require the exact signal amplitude, a simplified algorithm can be used to approximate the signal amplitude. Let's assume the calculated amplitude is... Then the signal amplitude can be approximated as The approximate simplified estimate is larger than the actual value, but it has little impact on the subsequent threshold decision module; only a slight adjustment of the threshold value is needed. That's all.

[0120] Ideally, when the received signal contains only noise, the cross-correlation coefficient of the noise sampling data is 0, therefore the obtained delay correlation value is... The value is 0, therefore the decision variable is... The amplitude is relatively low; when a burst data frame arrives, the delay correlation value is determined based on the periodicity of the frame header preamble sequence. Theoretically, it becomes the cross-correlation coefficient of the preceding sequence, the decision variable. Significantly increased; due to the presence of 10 leader sequences within the leader symbol, the decision variable... It maintains a flat trend for 9 leader sequence symbols before significantly decreasing. The threshold value is set in this module design. The value is set to 0.5. This eliminates the need for a divider. It is only necessary to determine whether the following condition is true.

[0121]

[0122] Delay-related algorithm decision variables This is the accumulated value of the correlation calculations within the delay window length, which is set to 16. The correlation accumulation module is used to buffer the output data of the autocorrelation calculation module and the delay correlation calculation module and perform the accumulation operation. In its hardware implementation, this module uses a 16-depth FIFO to buffer the input data, achieving synchronous output of the current data input and the data from the previous 16 clock cycles. Then, it adds the current data input to the accumulated value, and subtracts the data from the previous 16 clock cycles from the accumulated value. The final output of the correlation accumulation module is the sum of the correlation values ​​over 16 clock cycles. The delay correlation values ​​obtained after passing through the correlation accumulation module are shown below. and autocorrelation value The decision variables are sent to the threshold decision module for calculation. Used with threshold A comparison is performed. To ensure the accuracy of the frame synchronization algorithm and reduce the probability of misjudgment, a setting is made during the implementation process for the decision variable. The value exceeds the threshold for 32 consecutive clock cycles. At that time, the frame synchronization module pulls the data frame arrival signal high. After the data buffer module receives the data frame arrival signal and pulls it high, it makes multiple decisions, and when the decision variable... The value is below the threshold for 32 consecutive clock cycles. At this time, the data frame arrival signal is pulled low to complete the frame synchronization process.

[0123] Step 32: The frame synchronization module outputs data into the CFO frequency offset estimation and correction module, and the CFO frequency offset estimation and correction module outputs the corrected data; the specific process is as follows:

[0124] Four sets of delay correlation calculations were performed using five repeated leading symbols to obtain the 16-point length sum of the four correlation calculations.

[0125] The sum of the 16-point lengths from the four related calculations is used to perform inverse trigonometric function operations to obtain four angle deviation estimates. Then, the average of the four angle deviation estimates is calculated to obtain the corrected data.

[0126] CFO frequency offset estimation and correction module: This invention utilizes the repetitive periodicity of the preamble symbol and employs a maximum likelihood estimation algorithm for carrier synchronization processing. Assuming the ideal received signal is... In normalized carrier frequency deviation The received signal under the influence of:

[0127]

[0128] Let the period of the preamble symbol be , then the delay-related variable can be expressed as:

[0129]

[0130] Using the maximum likelihood estimation algorithm, the carrier frequency deviation can be obtained by averaging multiple estimates:

[0131]

[0132] After obtaining the frequency deviation, frequency compensation is performed on the received data:

[0133]

[0134] Design selection First, four sets of time-delay correlation calculations are performed using five repeated leading symbols to obtain the 16-point length summation results of the four correlation calculations. Then, the four summation results are subjected to inverse trigonometric function operations to obtain four angle deviation estimates. Finally, the average of the four angle deviation estimates is calculated to obtain the corrected data.

[0135] Step 33: The CFO frequency offset estimation and correction module outputs the corrected data, which is then input into the symbol synchronization module. The symbol synchronization module outputs the data. The specific process is as follows:

[0136] The corrected data output from the CFO frequency offset estimation and correction module is matched with the leader sequence in real time using a sliding window cross-correlation algorithm. The termination boundary of the leader sequence is determined based on the calculated cross-correlation peak position.

[0137] Symbol synchronization module: Symbol synchronization precisely times the grouping of data symbols, thereby determining the accurate start and end positions of each data symbol. This process is crucial for the subsequent demodulation work of the receiver. In this invention, the waveform characteristics of the physical layer preamble structure are pre-stored by the transmitter and receiver, and their deterministic characteristics provide a key benchmark for the receiver's symbol synchronization algorithm. The receiver uses a sliding window cross-correlation algorithm to match the corrected data output from the CFO frequency offset estimation and correction module with the preamble sequence in real time. By calculating the cross-correlation peak position, the termination boundary of the preamble sequence is accurately determined. The receiver calculates the cross-correlation between the pre-stored preamble sequence and the data output from the frame synchronization module using the following formula:

[0138]

[0139] In the formula The length for calculating the cross-correlation coefficient is set to 16 in the simulation experiment, consistent with the length of the leader sequence. It is the conjugate of the preamble sequence known locally at the receiver.

[0140] Due to the good correlation properties of the leader sequence, the cross-correlation coefficients calculated cumulatively within the window are incremented at the end of each leader symbol. A peak will appear. When the last peak appears, it can be marked as the end of the preamble symbol. According to the specified frame format, the receiver can deduce the start point of the data symbol and complete the symbol synchronization process.

[0141] The implementation of the symbol synchronization internal functional module can follow the design method of the frame synchronization internal correlation module described above. In this design, a complex multiplier is used to calculate the cross-correlation between the local preamble sequence and the input data. The local preamble sequence can be pre-stored in the FPGA's on-chip memory using a .coe format file, and then input to the cross-correlation calculation module in sync with the input data. The data buffer module prevents incomplete output data frames due to excessively long clock cycles required for symbol synchronization calculations; it also uses a FIFO memory internally. The core function of the peak detection module is to calculate the cumulative cross-correlation between the local preamble sequence and the received signal, and extract the extreme points of its amplitude spectrum. Internally, a counter counts the peak values. Since the first set of short training sequences output by the frame synchronization module is incomplete, this module detects the 9th peak as the end point of the preamble symbol, at which point the feedback signal is pulled high.

[0142] Steps 3 and 4: The symbol synchronization module outputs data into the CP module, and then outputs data to the CP module;

[0143] Step 35: Input the data output from the CP module into the FFT module, and the FFT module outputs the data;

[0144] Step 36: The FFT module outputs data into the channel estimation and equalization module, and the channel estimation and equalization module outputs data.

[0145] Step 37: The output data of the channel estimation and equalization module is input into the inverse two-dimensional Fourier transform module, and the inverse two-dimensional Fourier transform module outputs the data.

[0146] Step 38: The output data of the inverse two-dimensional Fourier transform module is input into the solution information symbol generation module, and the solution information symbol generation module outputs the data.

[0147] The specific process of solving the information symbol generation module is the reverse process (reverse order process) of the information symbol generation module.

[0148] The information symbol generation module: After the input data passes through the channel estimation and equalization module, it is sent to the information symbol generation module. By buffering the data with symbol=3, the signal field symbol after channel estimation and equalization is obtained. Then, after zero removal, BPSK deinterleaving, deinterleaving, and Viterbi decoding, RATA and LENGTH are obtained. RATA is then sent to the QAM demodulation module and Viterbi decoding module to indicate the modulation and coding scheme used by the transmitter. LENGTH is sent to the decoding module to indicate the end of data transmission.

[0149] Step 39: The data output from the information symbol decoding module is input into the QAM demodulation module, and the QAM demodulation module outputs the data.

[0150] The specific process of the QAM demodulation module is the reverse process of the QAM modulation module;

[0151] QAM Demodulation Module: The implementation of the 16-QAM demodulation module is relatively simple, mainly relying on the constellation mapping relationship used during symbol modulation to recover the encoded data carried by the symbols. The design employs a hard-decision method with bit quantization. Figure 5 This is a schematic diagram of the hard decision method for bit quantization. When the constellation point of the received complex signal falls within the corresponding rectangular area, it is determined to be the corresponding symbol. Figure 5 middle This represents the decision threshold for the data component. Since the complex data components of QAM modulation have already been normalized at the transmitter, and the normalization coefficient of 16-QAM is... Therefore, the decision threshold in the implementation process Set as It is worth noting that, because the preceding channel estimation and equalization modules, in order to avoid a division structure, only corrected the phase rotation caused by the channel, but did not compensate for its amplitude. Therefore, it is necessary to... It is added to the decision threshold, hence the decision threshold is:

[0152]

[0153] When the OTFS data sign arrives, the module internally determines the values ​​of the in-phase and quadrature components of the complex data simultaneously. First, it uses the sign bit of the most significant bit to determine the sign, and then compares it with the decision threshold. The values ​​are compared to determine which rectangular region the mapped point of the received data symbol falls within on the constellation diagram, and the corresponding encoded data is demodulated. At the hardware implementation level, the FPGA data in this design uses 8-bit signed fixed-point numbers to represent the data, with negative numbers represented in two's complement form. When comparing two positive numbers, the decimal places are compared bit by bit from left to right; in the first different bit, the value of 1 corresponds to a larger value. When comparing two negative numbers, since a larger binary value in the two's complement of a negative number corresponds to a larger actual value, the last 7 bits of the sign bit are directly compared.

[0154] Step 30: The QAM demodulation module outputs data into the descrambling module, and the descrambling module outputs data.

[0155] The specific process of the descrambling module is the reverse process of the scrambling module;

[0156] Step 31: The descrambling module outputs data into the deinterleaving module, and the deinterleaving module outputs data.

[0157] The specific process of the deinterleaving module is the reverse process of the interleaving module;

[0158] Step 32: The data output from the deinterleaving module is input into the deconvolution coding module, and the deconvolution coding module outputs the data.

[0159] The specific process of deconvolutional coding module is the inverse process of convolutional coding module;

[0160] Decoding module (descrambling, deinterleaving, deconvolutional coding):

[0161] The decoding operation at the baseband receiver can be viewed as the inverse process of the encoding operation at the transmitter. In this design, the decoding process at the baseband receiver mainly includes three modules: deinterleaving, deconvolution coding, and descrambling. The implementation principles and design methods of the deinterleaving and descrambling modules are the same as those of the interleaving and scrambling modules at the transmitter. Only minor modifications are needed to these two modules during the FPGA design process.

[0162] Deconvolutional coding is a high-efficiency decoding algorithm based on dynamic programming, mainly used to process digital signals distorted by noise interference. Its core idea is to compare the cumulative metrics of different paths state-by-state to select the globally optimal solution from all possible decoding paths, thereby achieving high-precision error correction for convolutionally coded signals. Since the input data width of the Viterbi decoding IP core is 2 bits, the deinterleaved bit data stream must first undergo serial-to-parallel conversion, and then be converted into an AXI data stream via an interface before being sent to the IP core for demodulation.

[0163] Key parameters for the deconvolutional coding IP core include constraint length, code rate, and backtracking depth. In this design, referencing the convolutional coding parameters used at the transmitter, the constraint length is set to 7, the code rate to 1 / 2, and the backtracking depth to 42. The decoder's generator polynomial remains consistent with the transmitter's and is set to... and Finally, the 0-1 sequence obtained after Viterbi decoding is transmitted back to the MAC layer.

[0164] The other steps and parameters are the same as those in any of the specific implementation methods one to five.

[0165] Specific Implementation Method Seven: This implementation method differs from Specific Implementation Methods One through Six in that: in steps three and four, the symbol synchronization module outputs data to the de-CP module, and the de-CP module outputs data; the specific process is as follows:

[0166] The CP removal function can be completed by deleting the first fifth of the output data of the symbol synchronization module;

[0167] Remove CP module: Based on the CP length mentioned above, delete the first one-fifth of the data address to complete the CP removal function.

[0168] The other steps and parameters are the same as those in one of the specific implementation methods one to six.

[0169] Specific Implementation Method Eight: This implementation method differs from Specific Implementation Methods One through Seven in that: in step three and five, the data output from the CP module is input into the FFT module, and the FFT module outputs data; the specific process is as follows:

[0170] The output data from the CP module is input to the FFT module (the last bit of the control byte in the general IFFT / FFT processing module is set to 1), and the last bit of the control data byte in the FFT module is set to 1.

[0171] FFT module: As mentioned above, the last bit of the control byte represents the direction of the FFT. Setting it to 1 will enable the FFT transformation.

[0172] The other steps and parameters are the same as those in any of the specific implementation methods one to seven.

[0173] Specific Implementation Method Nine: This implementation method differs from Specific Implementation Methods One through Eight in that: in step three and six, the FFT module outputs data into the channel estimation and equalization module, and the channel estimation and equalization module outputs data; the specific process is as follows:

[0174] Channel estimation and channel equalization are performed in the time-frequency domain. Least squares estimation (LS) is used for channel estimation, and zero-forcing equalization (ZF) is used for channel equalization.

[0175] Channel estimation and equalization module: The channel estimation and equalization method based on DMRS is as follows:

[0176] First, the average of the first and second received DMRS is taken. The sum of the two independently statistical noise samples is divided by 2, and the change is equivalent to half the change of a single noise sample.

[0177]

[0178] Channel estimation uses the LS estimation method:

[0179]

[0180] The above formula requires a complex complex division structure, which is not easy to implement in hardware circuits. The formula is further simplified as follows:

[0181]

[0182] Furthermore, since the DMRS data value is 1 or -1, the algorithm can be further simplified to:

[0183]

[0184] Channel equalization uses ZF equalization, and the equalized channel is then... for:

[0185]

[0186] make Further simplification yields:

[0187] Based on the above analysis, the hardware implementation structure of the channel estimation and equalization module is as follows: Figure 4 As shown, it can be divided into four parts: DMRS extraction, energy calculation, channel estimation, and channel equalization.

[0188] The other steps and parameters are the same as those in one of the specific implementation methods one to eight.

[0189] Specific Implementation Method Ten: This implementation method differs from Specific Implementation Methods One through Nine in that: in step three-seven, the output data of the channel estimation and equalization module is input to the inverse two-dimensional Fourier transform module, and the inverse two-dimensional Fourier transform module outputs data; the specific process is as follows:

[0190] Perform an N-point FFT on each row of the resource block of the output data from the channel estimation and equalization module, and then perform an M-point IFFT on each column.

[0191] The inverse 2D Fourier transform module performs an N-point FFT on each row of the OTFS resource block, and then performs an M-point IFFT on each column.

[0192] The other steps and parameters are the same as those in any of the specific implementation methods one to nine.

[0193] This invention may have other embodiments. Without departing from the spirit and essence of this invention, those skilled in the art can make various corresponding changes and modifications according to this invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios, characterized in that: The specific process of the transceiver is as follows: Step 1: The transmitted data sequentially passes through the convolutional coding module, interleaving module, scrambling module, QAM modulation module, OTFS modulation module, and CP module. The CP module outputs data, and DMRS is inserted into the CP module output data to obtain the transmitter data symbols. Step 2: Frame the data symbols, information symbols, and preamble sequence to obtain the framed data; Step 3: The framed data is sequentially fed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes through the ADC to reach the frame synchronization module. The output data of the frame synchronization module is sequentially input into the CFO frequency offset estimation and correction module, symbol synchronization module, CP removal module, FFT module, channel estimation and equalization module, inverse two-dimensional Fourier transform module, information symbol decryption module, QAM demodulation module, descrambling module, deinterleaving module, and deconvolution coding module to obtain the received 01 sequence.

2. The orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 1, characterized in that: In step one, the transmitted data sequentially passes through the convolutional coding module, interleaving module, scrambling module, QAM modulation module, OTFS modulation module, and CP module. The CP module outputs data, and DMRS is inserted into the CP module output data to obtain the transmitter data symbol. The specific process is as follows: Step 11: Transmit data to the convolutional coding module, and the convolutional coding module outputs data A; the specific process is as follows: Design a convolutional coding module with a bit rate of 1 / 2 to perform convolutional coding on the transmitted data. The generator polynomial of the convolutional coding is set as follows: and ; in, This represents 133 in octal. This represents 171 in octal. , Represents the generator polynomial; Steps 1 and 2: Input the output data A from the convolutional coding module into the interleaving module, and the interleaving module outputs data B; the specific process is as follows: Each symbol contains 48 subcarriers carrying data, each subcarrier uses 16-QAM modulation, and the interleaving depth is set to 192 bits; the interleaving process of the output data A of the convolutional coding module is divided into two stages; In the first stage of interleaving, the input data A is written into a 12-row, 16-column matrix, and then the bits are read out column by column. In the second-level interleaving process, the input data A is based on 24-bit units. The positions of the first 12 bits remain unchanged, while the last 12 bits are permuted by alternating the positions of adjacent two bits. The first-level interleaving and the second-level interleaving processes use a ping-pong operation. Step 13: Input the data B output from the interleaving module into the scrambling module, and the scrambling module outputs data C; the specific process is as follows: The initial value of the feedback shift register is set to 1011101; Setting the generator polynomial of the feedback shift register is ; The output data B of the interleaving module is input into the feedback shift register. The scrambling sequence generated by the feedback shift register is XORed with the output data B of the interleaving module to obtain the scrambled data C. in, This indicates the 7th stage of the feedback shift register. This indicates the 4th stage of the feedback shift register. This represents the generator polynomial of the feedback shift register. Indicates a feedback shift register; Step 14: Input the scrambling module output data C into the QAM modulation module, and the QAM modulation module outputs data D; the specific process is as follows: It adopts 16-QAM modulation; Set the data width to 8 bits and the scaling factor to [value missing]. ; Step 15: Input the output data D from the QAM modulation module into the OTFS modulation module. The OTFS modulation module outputs a time-domain transmission signal. ; Step 16: Input the time-domain transmit signal output from the OTFS modulation module into the CP module, and the CP module outputs the CP-added time-domain transmit signal; the specific process is as follows: The CP length is one-quarter of the length of the time-domain transmitted signal output by the OTFS modulation module; Step 17: The time-domain transmit signal after CP addition from the CP module is input to the DMRS insertion module, and the DMRS insertion module outputs data symbols; the specific process is as follows: Insert a CP and a DMRS for every OTFS symbol.

3. The orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 2, characterized in that: In step one five, the output data D of the QAM modulation module is input into the OTFS modulation module, and the OTFS modulation module outputs a time-domain transmission signal. ; The specific process is as follows: Step 151: The output data D of the QAM modulation module is transformed to the time-frequency domain using ISFFT; it is represented as: in, Represents data signals in the time-frequency domain. express Fourier transform matrix of order 1, express Fourier inverse transform matrix; This indicates the output data D of the QAM modulation module; The ISFFT transform is manifested by first multiplying the output data D of the QAM modulation module on the left by a Fourier transform matrix, and then multiplying it on the right by an inverse Fourier transform matrix. Step 152: Data signal in the time-frequency domain The signal is transformed to the time domain using the Heisenberg transform; it is represented as: In the formula, Send signals in the time domain; for A diagonal matrix of order 1 represents the discrete pulse shaping window function matrix; for The inverse Fourier transform matrix of order 1; In matrix operations, the Heisenberg transform is manifested by first left-multiplying the time-frequency domain data by an inverse Fourier transform matrix, and then left-multiplying it by a discrete pulse shaping window function matrix. When the pulse shaping window function is a rectangular window, the diagonal matrix... It's just one Unit matrix of order ; Step 153: Combined Formation Japanese style , obtain time-domain transmitted signal A concise representation: Step 154: Send signal to the time domain concise representation Perform the operation.

4. The orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 3, characterized in that: In step 154, a signal is sent in the time domain. concise representation Perform the operation; The specific process is as follows: Step 1541: Send signal in the time domain The input column-row transformation module rearranges the data, changing the original column-arranged data into row-arranged data. The specific process is as follows: Time-domain transmission signal Each group contains 48 numbers, and a total of 56 groups of data are reduced to 48 groups of data, with 56 numbers in each group; Insert eight zeros between the 56 numbers in each group, and then send the time-domain signal arranged in columns. Transformed into a row-arranged time-domain transmitted signal ; Step 1542: Send signals to the time domain of the row-by-row input. Perform an IFFT operation to obtain the time-domain transmit signal arranged in rows after the IFFT operation; Step 1543: Transform the row-arranged time-domain transmission signal obtained in Step 1542 into a column-arranged signal, resulting in 64 groups, each with 48 numbers. Insert zeros at the beginning and 15 zeros in the middle of these 48 numbers to obtain the time-domain transmission signal. for.

5. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 4, characterized in that: In step two, the data symbols, information symbols, and preamble sequence are framed to obtain framed data. The specific process is as follows: Step 21: Transmit data input to the information symbol generation module; the information symbol generation module generates information symbols; the specific process is as follows: The generation of information symbols is similar to that of data symbols, except that the modulation method is BPSK and it does not include a DMRS insertion module; Step 22: Generating the preamble sequence simply requires reading the pre-stored sequence value from the ROM; Steps two and three: Frame the data symbols, information symbols, and preamble sequence to obtain the framed data; the specific process is as follows: The symbols are combined in the order of the preamble, information symbols, and data symbols.

6. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 5, characterized in that: In step three, the framed data is sequentially passed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes through the ADC to reach the frame synchronization module. The output data of the frame synchronization module is sequentially input into the CFO frequency offset estimation and correction module, symbol synchronization module, CP removal module, FFT module, channel estimation and equalization module, inverse two-dimensional Fourier transform module, information symbol decryption module, QAM demodulation module, descrambling module, deinterleaving module and deconvolution coding module to obtain the received 01 sequence. The specific process is as follows: Step 31: The framed data is sequentially passed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes through the ADC to reach the frame synchronization module. The frame synchronization module outputs the data. The specific process is as follows: Step 311: The framed data is sequentially passed through the DAC on the FPGA and the antenna on the FPGA into the time-frequency dual-selection channel. The antenna on another FPGA receives the signal after passing through the time-frequency dual-selection channel, and then passes it through the ADC. The ADC outputs the data. Step 312: The ADC output data passes through the frame synchronization module, and the frame synchronization module outputs data. The specific process is as follows: Approximation of amplitude calculation ; in, Indicates the delay correlation value The real part, Indicates the delay correlation value The imaginary part; A frame is considered to have arrived when the value of the decision variable is greater than the threshold for 32 consecutive clock cycles. When the value of the decision variable is less than or equal to the threshold for 32 consecutive clock cycles, it represents the end of the frame and the frame synchronization is completed. Step 32: The frame synchronization module outputs data into the CFO frequency offset estimation and correction module, and the CFO frequency offset estimation and correction module outputs the corrected data; the specific process is as follows: Four sets of delay correlation calculations were performed using five repeated leading symbols to obtain the 16-point length sum of the four correlation calculations. The sum of the 16-point lengths from the four related calculations is used to perform inverse trigonometric function operations to obtain four angle deviation estimates. Then, the average of the four angle deviation estimates is calculated to obtain the corrected data. Step 33: The CFO frequency offset estimation and correction module outputs the corrected data, which is then input into the symbol synchronization module. The symbol synchronization module outputs the data. The specific process is as follows: The corrected data output from the CFO frequency offset estimation and correction module is matched with the leader sequence in real time using a sliding window cross-correlation algorithm. The termination boundary of the leader sequence is determined based on the calculated cross-correlation peak position. Steps 3 and 4: The symbol synchronization module outputs data into the CP module, and then outputs data to the CP module; Step 35: Input the data output from the CP module into the FFT module, and the FFT module outputs the data; Step 36: The FFT module outputs data into the channel estimation and equalization module, and the channel estimation and equalization module outputs data. Step 37: The output data of the channel estimation and equalization module is input into the inverse two-dimensional Fourier transform module, and the inverse two-dimensional Fourier transform module outputs the data. Step 38: The output data of the inverse two-dimensional Fourier transform module is input into the solution information symbol generation module, and the solution information symbol generation module outputs the data. The specific process of solving the information symbol generation module is the reverse process of the information symbol generation module; Step 39: The data output from the information symbol decoding module is input into the QAM demodulation module, and the QAM demodulation module outputs the data. The specific process of the QAM demodulation module is the reverse process of the QAM modulation module; Step 30: The QAM demodulation module outputs data into the descrambling module, and the descrambling module outputs data. The specific process of the descrambling module is the reverse process of the scrambling module; Step 31: The descrambling module outputs data into the deinterleaving module, and the deinterleaving module outputs data. The specific process of the deinterleaving module is the reverse process of the interleaving module; Step 32: The data output from the deinterleaving module is input into the deconvolution coding module, and the deconvolution coding module outputs the data. The specific process of deconvolutional coding module is the inverse process of convolutional coding module.

7. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 6, characterized in that: In steps three and four, the symbol synchronization module outputs data and inputs it into the CP module, and the CP module outputs data. The specific process is as follows: The CP removal function can be completed by deleting the first fifth of the output data of the symbol synchronization module.

8. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 7, characterized in that: In step three, the data output from the CP module is input into the FFT module, and the FFT module outputs the data. The specific process is as follows: The CP module outputs data to the FFT module, which then controls the last bit of the data byte to be set to 1.

9. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 8, characterized in that: In step three and six, the FFT module outputs data into the channel estimation and equalization module, and the channel estimation and equalization module outputs data. The specific process is as follows: Channel estimation and channel equalization are performed in the time-frequency domain. The channel estimation adopts least squares estimation (LS), and the channel equalization adopts zero-forcing equalization (ZF).

10. An orthogonal time-frequency space transceiver suitable for satellite-to-ground scenarios according to claim 9, characterized in that: In step 37, the output data of the channel estimation and equalization module is input into the inverse two-dimensional Fourier transform module, and the inverse two-dimensional Fourier transform module outputs data. The specific process is as follows: Perform an N-point FFT on each row of the resource block output data from the channel estimation and equalization module, and then perform an M-point IFFT on each column.

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