Main station-terminal module distributed clock synchronization method based on PID closed-loop control

Abstract

The invention discloses a master station-terminal module distributed clock synchronization method based on PID closed-loop control, and belongs to the technical field of industrial automatic control clock synchronization. Comprising the following steps: S1, synchronizing clocks of a master station and a slave station by measuring and compensating network transmission delay and node crystal oscillator deviation, and establishing a system time reference; s2, the slave station periodically sends a data frame with a timestamp T1 to the terminal module through a bus by taking the Sync0 signal as a reference; s3, the terminal module records local time T2 while receiving the data frame, compares the local time T2 with the timestamp T1 in the frame, and calculates clock skew; s4, the terminal module selects PID parameters according to the deviation, and a local clock is adjusted in a closed-loop mode to enable the clock deviation to approach zero; and S5, repeating the process in each communication period, and keeping all the terminal modules consistent with the master station for a long time through continuous iteration. And a Sync0 signal is used as a time reference and extends to an RS485 bus, and microsecond-level clock synchronization of a terminal module and a master station is realized through a three-level synchronization architecture, so that the requirements of scenes such as multi-axis servo control and high-speed data acquisition on high-precision time consistency are met.

Description

Technical Field

[0001] This invention belongs to the field of clock synchronization technology for industrial automation control, and particularly relates to a distributed clock synchronization method for master station-terminal modules based on PID closed-loop control. Background Technology

[0002] With the deepening of industrialization and intelligent manufacturing, industrial automation systems are placing increasingly higher demands on the time coordination accuracy between equipment. In scenarios such as precision motion control, distributed data acquisition, and multi-axis synchronous control, the clock consistency between each actuator and sensor directly determines the control accuracy and data reliability of the system.

[0003] The EtherCAT protocol's distributed clock (DC) technology enables microsecond-level synchronization between master and slave stations. However, its synchronization capability cannot directly cover terminal modules that rely on the RS485 bus. In existing technologies, the RS485 bus is only used for transmitting service data, and there is a lack of an effective synchronization mechanism between the terminal module's clock and the EtherCAT master station. When multiple RS485 modules need to work collaboratively (such as multi-axis pulse output or multi-point synchronous sampling), clock deviations can lead to problems such as asynchronous instruction execution and inconsistent data acquisition times, severely impacting system performance. Taking multi-axis servo control as an example, if the clocks of each axis pulse transceiver module have a deviation of tens of microseconds, it will directly cause motion trajectory errors, failing to meet the requirements of precision machining.

[0004] For example, a time synchronization method and related device in an SRB network is disclosed in a Chinese patent document [CN119342574B]. By determining the master station and slave station in the SRB network, the information transmission time between the master station and the slave station is calculated, a macro period is generated, and a synchronization time packet is sent periodically within the macro period, so that the slave station can perform local time synchronization based on the millisecond time information in the synchronization time packet and the real-time data packet.

[0005] While the above technical solutions can effectively reduce time synchronization errors and improve the time consistency and stability of the system, they can only transmit information and cannot correct the local clock frequency, thus failing to fundamentally solve the clock drift problem. Summary of the Invention

[0006] The purpose of this invention is to address the synchronization accuracy problem by providing a distributed clock synchronization method for master station-terminal modules based on PID closed-loop control, which ensures synchronization accuracy from the Ethercat link to the RS485 terminal module.

[0007] To achieve the above objectives, the present invention adopts the following technical solutions: This distributed clock synchronization method for master station-terminal modules based on PID closed-loop control includes: S1. By measuring and compensating for network transmission delay and node crystal oscillator deviation, the clocks of the master station and slave station are synchronized, and a system time reference is established; S2. The slave station uses the Sync0 signal as a reference and periodically sends data frames with timestamp T1 to the terminal module via the bus; S3. The terminal module records the local time T2 while receiving the data frame, and compares it with the timestamp T1 in the frame to calculate the clock deviation; S4. The terminal module selects PID parameters based on the magnitude of the deviation and adjusts the local clock in a closed loop to bring the clock deviation close to zero. S5. Repeat the above process in each communication cycle. Through continuous iteration, all terminal modules and the main station maintain long-term consistency.

[0008] In the aforementioned distributed clock synchronization method for master-terminal modules based on PID closed-loop control, The master station is an EtherCAT master station, and the slave station is an EtherCAT coupler. The master station is connected to the EtherCAT coupler through a standard network cable to establish an EtherCAT communication network, and the master station sends synchronization messages to the slave station.

[0009] In the aforementioned distributed clock synchronization method for master-terminal modules based on PID closed-loop control, the slave station receives synchronization messages and records its local time, synchronizing with the master station's microsecond-level clock via a distributed clock. After synchronization is complete, the system enters operation mode, preparing to send data to downstream modules.

[0010] In the above-mentioned distributed clock synchronization method of master station-terminal module based on PID closed-loop control, in step 2, the slave station generates a Sync0 synchronization signal as the time base of the entire bus, and sends or broadcasts data frames to all connected terminal modules through the bus at a fixed period.

[0011] In the aforementioned distributed clock synchronization method for master-terminal modules based on PID closed-loop control, the data frame contains a timestamp field, which records the time when the slave station sends the frame as T1.

[0012] In the aforementioned distributed clock synchronization method of master station-terminal module based on PID closed-loop control, the terminal module is either a pulse transceiver module or an analog signal acquisition module.

[0013] In the above-mentioned distributed clock synchronization method of master station-terminal module based on PID closed-loop control, in S3, the terminal module records the local clock time of the current module as T2 when it receives the data frame. The terminal module parses the time T1 sent by the slave station from the data frame and calculates the time deviation value diff.

[0014] In the aforementioned distributed clock synchronization method for master-terminal modules based on PID closed-loop control, in S4, each terminal module has a built-in dual-mode adaptive PID controller to adjust the local clock frequency so that diff approaches 0. The adjustment calculation formula is as follows:

[0015] In the aforementioned distributed clock synchronization method for master-terminal modules based on PID closed-loop control, When the time deviation value is greater than the threshold, increase the proportional coefficient and decrease the integral coefficient; When the time deviation is less than the threshold, decrease the proportional coefficient and increase the derivative coefficient.

[0016] In the aforementioned distributed clock synchronization method for master station-terminal modules based on PID closed-loop control, the terminal module adjusts the frequency of the local clock crystal or the counter compensation value according to the PID output result to achieve closed-loop control.

[0017] Compared with existing technologies, the advantages of this invention are: The Sync0 signal serves as a time reference, extending to the RS485 bus. Through a three-level synchronization architecture, the terminal module and the master station achieve microsecond-level clock synchronization, meeting the high-precision time consistency requirements of scenarios such as multi-axis servo control and high-speed data acquisition.

[0018] Employing a dual-mode adaptive PID controller with coarse and fine adjustment, the system automatically switches parameters based on the magnitude of the time deviation. Coarse adjustment quickly converges to large deviations, while fine adjustment suppresses steady-state jitter. Compared to the open-loop time update of existing technologies, this invention achieves closed-loop feedback control, continuously compensating for crystal oscillator drift and ensuring that the clocks of all modules are highly stable and the synchronization error continuously approaches zero during long-term operation.

[0019] Without modifying existing RS485 hardware, the high-precision synchronization capability of EtherCAT can be extended to traditional RS485 terminals simply by optimizing the communication mechanism and algorithm of slave and terminal modules, thus achieving heterogeneous network integration at extremely low cost. Attached Figure Description

[0020] Figure 1 This is a flowchart of the clock synchronization method provided by the present invention.

[0021] Figure 2 This is the dual-mode PID control flowchart provided by the present invention. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0023] This distributed clock synchronization method for master-terminal modules based on PID closed-loop control is applied to industrial automation control systems. For example... Figure 1 As shown, the system includes an EtherCAT master station, an EtherCAT coupler, and multiple mounted RS485 terminal modules. The EtherCAT master station, located at the control end, acts as a primary node, typically an industrial PC, PLC, or embedded controller, responsible for initiating and scheduling EtherCAT messages. The EtherCAT coupler, acting as a secondary node, connects to the master station via a standard network cable to establish an EtherCAT communication network. The terminal modules, designed based on an MCU+RS485 chip, serve as tertiary nodes. In this implementation, pulse transceiver modules and analog signal acquisition modules are specifically used. Multiple terminal modules are mounted below the coupler via an RS485 bus, with terminating resistors configured on the RS485 bus segments to ensure signal quality.

[0024] By measuring and compensating for network transmission delays and node crystal oscillator deviations, the clocks of the master station and slave stations are synchronized, establishing a system time base. Specifically, the EtherCAT master station uses distributed clock (DC) technology to send synchronization messages to the EtherCAT coupler. The EtherCAT coupler receives the synchronization messages and records its local time, achieving microsecond-level clock synchronization with the master station through the DC mechanism. After synchronization is complete, the system enters the operating mode, ready to send data to downstream modules.

[0025] A high-precision time base is established for the overall synchronization link to ensure that the clock of the EtherCAT coupler is highly consistent with that of the master station. By utilizing the inherent distributed clock capability of the EtherCAT protocol, microsecond-level synchronization between the EtherCAT master station and the EtherCAT coupler is achieved at extremely low cost, providing a reliable time base for subsequent RS485 module synchronization.

[0026] Furthermore, the slave station, i.e., the EtherCAT coupler, generates a Sync0 synchronization signal, which serves as the time base for the entire RS485 bus. It then sends data frames to all connected terminal modules via the RS485 bus at fixed intervals, transmitting EtherCAT's synchronization capability to the terminal modules through the RS485 bus. In this step, the periodic time base frames generated by the Sync0 signal enable the RS485 bus to transmit high-precision time information without requiring modifications to existing RS485 hardware, thus maintaining the system's low-cost advantage.

[0027] In this embodiment, the fixed period is set to 1ms, and each data frame contains a timestamp field that records the time when the EtherCAT coupler sends the data frame, denoted as T1.

[0028] Furthermore, while receiving data frames, the terminal module records the local time T2 and compares it with the timestamp T1 in the frame to calculate the clock deviation and quantify the deviation between the local clock of the terminal module and the reference clock of the EtherCAT coupler.

[0029] If the calculation result is positive, it indicates that the local clock of the terminal module is faster than the reference clock; if it is negative, it indicates that the local clock of the terminal module is slower than the reference clock.

[0030] In this embodiment, both the pulse transceiver module and the analog signal acquisition module have built-in high-precision timers, enabling microsecond-level timestamp capture and quantifying the deviation between the terminal module's local clock and the EtherCAT coupler's reference clock. By comparing the local timestamp with the intra-frame timestamp, the clock deviation of each module is accurately obtained, providing accuracy feedback input for subsequent closed-loop adjustment.

[0031] Preferably, the terminal module selects PID parameters based on the magnitude of the deviation and uses closed-loop adjustment of the local clock to bring the clock deviation close to zero.

[0032] After each RS485 terminal module is powered on, system initialization is performed first. The dual-mode PID controller integrated inside the RS485 terminal module needs to be pre-configured with two different sets of control parameters, one for coarse-tuning mode and one for fine-tuning mode. Compared with fine-tuning mode, coarse-tuning mode uses a larger proportional coefficient, a smaller integral coefficient, and a larger derivative coefficient. This is to achieve rapid convergence of deviation in coarse-tuning mode and reduce steady-state error and suppress clock jitter in fine-tuning mode.

[0033] Meanwhile, the module sets the threshold conditions for mode switching. In this embodiment, taking a communication period of 1ms as an example, the cumulative error of fifty consecutive times being less than 20% of the communication period, i.e. 200μm, is used as the criterion for switching from coarse adjustment mode to fine adjustment mode. During the initialization phase, the cumulative error counter and integral term also need to be cleared to ensure that the system starts operating from the known state.

[0034] The current cycle clock deviation value diff is used as the input signal for PID control.

[0035] The module evaluates its own synchronization status to determine which control mode to adopt. The terminal maintains a sliding window to record the absolute difference of the last fifty communication cycles and calculates the cumulative sum. After each cycle of deviation acquisition is completed, the module adds the absolute deviation value of that cycle to the cumulative sum and updates the window count.

[0036] In this embodiment, the absolute deviation value is used to avoid the problem of positive and negative deviations canceling each other out. When the module clock fluctuates around the reference value, the algebraic summation result approaches zero, which can create the illusion of "zero error". However, the summation of the absolute deviation value accurately reflects the actual deviation of 100μs in each cycle, ensuring that the statistical results are true and reliable.

[0037] When the window count reaches fifty, the module counts the average absolute deviation within the window and compares it with the preset mode switching threshold. If the average absolute deviation is less than 200μm, it indicates that the system has entered a relatively stable synchronization state, and the module sets the current mode to fine-tuning mode. Otherwise, it indicates that the system is still in a state of large deviation, and the module switches to coarse-tuning mode to ensure rapid convergence.

[0038] To ensure smooth mode switching, the module adopts a sliding window mechanism. After each new cycle of statistics is completed, a deviation value is removed from the window. The data is accumulated and kept with the clock for fifty cycles to ensure that the mode judgment can reflect the latest status of the system in real time and avoid judgment lag due to outdated historical data.

[0039] Furthermore, based on the currently determined control mode, the module selects the corresponding PID parameter set to calculate the control quantity, and the adjustment formula is as follows:

[0040] Where Δf(k) is the control output, which is the adjustment amount that needs to be applied to the controlled object in the Kth cycle, e(k) is the clock deviation value of the current cycle, which is the difference between the controlled quantity and the target value in the Kth cycle, and e(k-1) is the deviation of the previous cycle, which is the difference between the controlled quantity and the target value in the (K-1)th cycle. As a proportional control, the control quantity is proportional to the current deviation. Based on the size of the clock deviation in the current cycle, an adjustment quantity proportional to it is applied. The larger the deviation, the stronger the adjustment capability, causing the clock to quickly return to the reference direction. As an integral term, the control quantity is proportional to the cumulative sum of historical deviations. It accumulates and compensates for long-standing minor deviations, eliminating steady-state errors that cannot be eliminated by proportional shift. The derivative term is proportional to the rate of change of the deviation and makes predictive adjustments based on the trend of clock deviation changes. If the deviation is increasing rapidly, the derivative term applies reverse adjustment in advance to suppress overshoot and oscillation.

[0041] The inputs to a PID controller include the deviation value of the current cycle, the integral of the historical deviations, and the difference between the current deviation and the deviation of the previous cycle, i.e., the derivative term. The output of the PID controller is the amount of time that needs to be compensated for in each cycle.

[0042] To prevent excessive control input from causing system oscillation, the output of the PID controller is limited. Based on the cycle length, the maximum single adjustment is set and limited to within 200μm to ensure that the system adjustment process is stable and controllable.

[0043] Those skilled in the art can also adopt an integral separation strategy, whereby when the absolute value of the deviation in the current period exceeds a certain threshold, the accumulation of the integral term is temporarily stopped, and the proportional and differential terms are used for adjustment to prevent excessive accumulation of the integral term during the large deviation stage and to avoid overshoot in the subsequent adjustment process.

[0044] Furthermore, the PID controller automatically switches parameter modes based on the magnitude of the deviation: when the time deviation is large (in this embodiment, the cumulative error after 50 consecutive cycles is greater than 20% of the communication cycle), the system adopts a coarse-tuning mode, increasing the proportional coefficient Kp and decreasing the integral coefficient Ki to achieve rapid convergence of the deviation; when the time deviation is small (i.e., the cumulative error after 50 consecutive cycles is less than 20% of the communication cycle), the system switches to a fine-tuning mode, decreasing the proportional coefficient Kp and increasing the derivative coefficient Kd to suppress steady-state jitter and clock fluctuations. The module adjusts the frequency of the local clock crystal or the counter compensation value based on the PID output to achieve closed-loop control. This balances the two conflicting goals of rapid convergence and steady-state accuracy; the closed-loop feedback mechanism continuously compensates for crystal drift, ensuring that the module clock remains highly consistent with the master station reference; compared to the open-loop time update of existing technologies, this solution has stronger dynamic adaptability and robustness.

[0045] The output calculated by the PID controller is ultimately converted into actual clock adjustments through hardware means. In this embodiment, the clock frequency is fine-tuned by adjusting the period count value of the timer.

[0046] Specifically, each terminal module has an internal reference timer for generating local clock cycles. Without synchronization adjustments, the timer's period is fixed. When clock adjustment is needed, the terminal module calculates the corresponding cycle compensation value based on the PID output and adds it to the reference count value in each timer cycle. If the module clock is too fast (positive deviation), the cycle count value needs to be increased, and the clock frequency decreased. Conversely, the cycle count value decreases. The terminal module's local clock frequency is gradually corrected to match the reference clock, achieving closed-loop elimination of clock deviation. This approach offers advantages such as high precision, continuous adjustment, and no jumps, making it suitable for motion control scenarios with high clock continuity requirements.

[0047] Preferably, to ensure the long-term reliability of the system, the module has a built-in status monitoring and anomaly handling mechanism. The terminal module continuously monitors the deviation value of the current period and calculates the average absolute deviation within the sliding window. If the indicator continues to deteriorate and exceeds the warning threshold, it will report a synchronization quality warning message to the host computer, indicating that there may be a hardware failure or interference.

[0048] If the module fails to receive Sync0 data frames for several consecutive cycles, it pauses PID adjustment and maintains the current clock frequency in a free-running state. The local clock is maintained by its own crystal oscillator. Simultaneously, it continuously monitors the bus, and immediately resumes the synchronization adjustment process upon communication recovery.

[0049] The above process is repeated in each communication cycle, and continuous iteration ensures that all terminal modules remain consistent with the master station over a long period. The system clock maintains closed-loop control to ensure rapid response to changes in clock deviation. This allows the synchronization error to continuously converge and stabilize within an acceptable range. Even if changes in ambient temperature cause crystal oscillator drift, the system can automatically compensate, achieving long-term high-precision synchronization.

[0050] In this embodiment, an RS485 bus is used. Those skilled in the art can also replace it with other fieldbuses, and the synchronization principle of the present invention will still apply. By replacing the Sync0 signal with other periodic signals, the transmission of the time reference can still be achieved.

[0051] The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains may make various modifications or compensations to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

[0052] Although this document uses terms such as clock synchronization, master station, slave station, Sync0 signal, terminal module, clock skew, and PID frequently, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of this invention; interpreting them as any additional limitation would contradict the spirit of this invention.

Claims

1. A distributed clock synchronization method for master station-terminal modules based on PID closed-loop control, characterized in that, The method includes: S1. By measuring and compensating for network transmission delay and node crystal oscillator deviation, the clocks of the master station and slave station are synchronized, and a system time reference is established; S2. The slave station uses the Sync0 signal as a reference and periodically sends data frames with timestamp T1 to the terminal module via the bus; S3. The terminal module records the local time T2 while receiving the data frame, and compares it with the timestamp T1 in the frame to calculate the clock deviation; S4. The terminal module selects PID parameters based on the magnitude of the deviation and adjusts the local clock in a closed loop to bring the clock deviation close to zero. S5. Repeat the above process in each communication cycle, and keep all terminal modules consistent with the main station in the long term through continuous iteration.

2. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 1, characterized in that, In step 1, the master station is an EtherCAT master station, and the slave station is an EtherCAT coupler. The master station is connected to the EtherCAT coupler through a standard network cable to establish an EtherCAT communication network, and the master station sends synchronization messages to the slave station.

3. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 2, characterized in that, The slave station receives the synchronization message and records the local time. It then synchronizes with the master station's microsecond-level clock using a distributed clock. Once synchronization is complete, the system enters operation mode and prepares to send data to downstream modules.

4. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 1, characterized in that, In step 2, a Sync0 synchronization signal is generated inside the station as the time base for the entire bus, and data frames are sent or broadcast to all connected terminal modules through the bus at fixed intervals.

5. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 4, characterized in that, The data frame contains a timestamp field, which records the time when the slave station sent the frame as T1.

6. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 4, characterized in that, The terminal module is one of the pulse transceiver modules or analog signal acquisition modules.

7. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 1, characterized in that, In S3, while receiving a data frame, the terminal module records the local clock time of the current module, denoted as T2. The terminal module parses the time T1 sent by the slave station from the data frame and calculates the time deviation value diff.

8. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 1, characterized in that, In S4, each terminal module has a built-in dual-mode adaptive PID controller to adjust the local clock frequency so that diff approaches 0. The adjustment calculation formula is as follows:

9. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 8, characterized in that, When the time deviation value is greater than the threshold, increase the proportional coefficient and decrease the integral coefficient; When the time deviation is less than the threshold, decrease the proportional coefficient and increase the derivative coefficient.

10. The distributed clock synchronization method for master station-terminal modules based on PID closed-loop control according to claim 1, characterized in that, The terminal module adjusts the frequency of the local clock crystal or the counter compensation value based on the PID output to achieve closed-loop control.

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