Communication device for extending flexray bus by ARM (Advanced RISC Machines)

Abstract

A communication device for extending a flexray bus by an ARM (Advanced RISC Machines) mainly comprises an ARM processor and a flexray communication controller, and the flexray communication controller is connected to an external bus of the ARM processor through a preset external bus interface; a register and a message buffer area of the FlexRay communication controller are mapped to a unified memory address space of the ARM processor; and the FlexRay communication controller is connected to the FlexRay physical bus through the FlexRay bus driver. According to the device, a cooperative communication system of an ARM main processor and a FlexRay communication controller is constructed, high-performance, high-reliability and low-delay FlexRay communication is realized on a general ARM processor through a layered software architecture, and meanwhile, the simplicity of hardware design and the portability of software are kept.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a communication device for an ARM extended flexray bus. Background Technology

[0002] As automotive electronic architecture evolves towards domain controllers and central computing platforms, ARM architecture processors have become the preferred choice for main control chips due to their high performance, low power consumption, and rich ecosystem. Meanwhile, the FlexRay bus, with its high determinism, high bandwidth, and high reliability, still holds an important position in safety-critical areas such as chassis control and powertrain. However, most commercial ARM processors do not integrate a native FlexRay controller, limiting their application in scenarios requiring FlexRay communication.

[0003] In existing technologies, the following methods are typically used: Using a dedicated MCU with an integrated FlexRay controller: This approach limits the flexibility of processor selection and may not meet the needs of high-performance computing; Implementing the FlexRay IP core via FPGA is challenging due to its high development difficulty, long development cycle, high cost, and complex verification process.

[0004] Therefore, there is an urgent need for a communication method that can efficiently and reliably connect a general-purpose ARM processor to the FlexRay bus. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this disclosure provides a communication method for extending the ARM FlexRay bus, which aims to achieve high-performance, high-reliability, and low-latency FlexRay communication on a general-purpose ARM processor through a standard external bus interface, while maintaining the simplicity of hardware design and the portability of software.

[0006] The present disclosure provides a communication device for an ARM extended FlexRay bus, the core of which is to build a collaborative communication system of "ARM main processor + FlexRay communication controller" and to manage it efficiently through a layered software architecture.

[0007] The device mainly includes: an ARM processor, a FlexRay communication controller, and a FlexRay bus driver, among which: The FlexRay communication controller is connected to the external bus of the ARM processor through a preset external bus interface; wherein the external bus interface is a parallel memory bus, or a high-speed SPI serial bus or a PCIe interface. The registers and message buffers of the FlexRay communication controller are mapped to the unified memory address space of the ARM processor; The FlexRay communication controller connects to the FlexRay physical bus via the FlexRay bus driver.

[0008] Furthermore, the initialization configuration method of the communication controller includes: The driver on the ARM processor initializes and configures the external bus interface; Perform a reset operation on the FlexRay communication controller and configure its global communication parameters, including one or more of the following: communication cycle length, static segment and dynamic segment duration, bit timing parameters, node ID, and cluster loop length; Configure the message buffers of the FlexRay communication controller, specifying the working mode (send or receive), the corresponding frame ID (slot number), the valid cycle mask, the data length, and the channel to which each buffer belongs.

[0009] Furthermore, the data transmission method of this device is as follows: The application passes the data to be sent and the target slot number to the driver; The driver locates the corresponding send message buffer based on the target slot number; Write the data to be sent into the data area of ​​the buffer and set the "send request" flag of the buffer; The FlexRay communication controller automatically encapsulates the data in the buffer into FlexRay frames and sends them to the FlexRay bus when the predetermined communication cycle and static / dynamic segment slots arrive, and updates the buffer status after the transmission is completed.

[0010] Furthermore, the data receiving method of this device is as follows: After receiving a valid frame on the FlexRay bus, the FlexRay communication controller automatically stores it into a preset receive message buffer according to its slot number, and generates a receive interrupt or sets a status flag. The ARM processor driver detects the event via interrupt or polling. In an interrupt service routine or polling task, the driver reads complete FlexRay frame data from the receive buffer, including data payload and status information, and passes it to the upper-layer application through a callback function or message queue mechanism.

[0011] Furthermore, the ARM processor driver monitors the status register of the FlexRay communication controller in real time to manage communication errors, synchronization status, and wake-up events.

[0012] Furthermore, the ARM processor provides a network management interface for enabling synchronous startup and sleep / wake-up of multiple FlexRay bus nodes.

[0013] Furthermore, the FlexRay communication controller connects two parallel FlexRay physical buses via two parallel FlexRay bus drivers.

[0014] Compared with the prior art, the beneficial effects of this disclosure are: ① It enables high-performance, high-reliability, and low-latency FlexRay communication on a general-purpose ARM processor through a standard external bus interface; ② It maintains the simplicity of hardware design and the portability of software; ③ It effectively expands the application of ARM processors in scenarios requiring FlexRay communication; ④ It can expand multiple FlexRay buses with different channels according to different usage scenarios. Attached Figure Description

[0015] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments of this disclosure taken in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0016] Figure 1 This is a system block diagram of an ARM extended flexray bus according to an exemplary embodiment of the present disclosure; Figure 2 The operation process for ARM to control the FlexRay bus. Detailed Implementation

[0017] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0018] This disclosure provides a communication device for an ARM extended Flexray bus. In one exemplary embodiment, the device is designed as follows: 1. Hardware Architecture The FlexRay communication controller connects to the external bus of the ARM processor via a pre-defined external bus interface.

[0019] The external bus interface is preferably a parallel memory bus, which maps the registers and message buffers of the FlexRay communication controller to the unified memory address space of the ARM processor; or it can be a high-speed SPI serial bus or a PCIe interface.

[0020] The FlexRay communication controller is connected to the FlexRay physical bus via a FlexRay bus driver.

[0021] 2. Communication controller initialization and configuration The driver on the ARM processor initializes and configures the external bus interface.

[0022] Perform a reset operation on the FlexRay communication controller and configure its global communication parameters, including but not limited to: communication cycle length, static segment and dynamic segment duration, bit timing parameters, node ID, and cluster loop length.

[0023] Configure the message buffers (mailboxes) of the FlexRay communication controller, specifying the working mode (send or receive), the corresponding frame ID (slot number), the valid cycle mask, the data length, and the channel to which each buffer belongs.

[0024] 3. Data transmission process The application passes the data to be sent and the target slot number to the driver.

[0025] The driver locates the corresponding send message buffer based on the target slot number.

[0026] Write the data to be sent into the data area of ​​the buffer and set the "send request" flag of the buffer.

[0027] The FlexRay communication controller automatically encapsulates the data in the buffer into FlexRay frames and sends them to the bus when the predetermined communication cycle and static / dynamic segment slots arrive, and updates the buffer state after the transmission is completed.

[0028] 4. Data Receiving Process After receiving a valid frame on the bus, the FlexRay communication controller automatically stores it in the preset receive message buffer according to its slot number, and generates a receive interrupt or sets a status flag.

[0029] The ARM processor driver detects the event via interrupt or polling.

[0030] In an interrupt service routine or polling task, the driver reads the complete FlexRay frame data (including data payload and status information) from the receive buffer and passes it to the upper-layer application through a callback function or message queue mechanism.

[0031] 5. System Management and Error Handling The driver monitors the status register of the FlexRay communication controller in real time, enabling the management of communication errors, synchronization status, and wake-up events.

[0032] Provides a network management interface to support the synchronous startup and sleep / wake-up process of FlexRay nodes. Application Examples The device will be further described in detail with reference to the accompanying drawings and a specific hardware platform example. In this example, Rockchip's 8-core processing chip RK3588J is connected to an FPGA chip via a PCIe 2.0 interface, and then connected to an SM4310 FlexRay communication controller via an asynchronous interface extended from the FPGA chip.

[0033] 1. Figure 1 System block diagram for extending the FlexRay bus for ARM.

[0034] Core chip selection: ARM processor: RK3588 (with powerful computing capabilities and an external memory interface); FPGA chip: XC7A50T (equipped with a PCIe hard core, capable of communicating with ARM, and featuring rich I / O interfaces for expansion). FlexRay communication controller: Guowei Electronics SM4310MP; Bus driver: Guowei Electronics SM1080ATSMP.

[0035] 2. The operation procedure of ARM controlling the FlexRay bus is shown in the attached diagram. Figure 2 As shown.

[0036] The ARM and FPGA coordinate their operations on FlexRay via PCIe and interrupt mechanisms, as follows: ① AMI Write Operation: The ARM writes the target AMI device address and the data to be sent to the specified address on the FPGA via a PCIe PIO write operation. After receiving the data, the FPGA immediately sends it through the AMI interface.

[0037] ② AMI Read Operation: The ARM first writes the address of the AMI device to be read to the FPGA via a PCIe PIO write operation. The FPGA then initiates a read request to the AMI device and temporarily stores the acquired data. Subsequently, the FPGA sends a PCIe interrupt to the ARM. Upon receiving the interrupt, the ARM reads the cached AMI data from the FPGA's specified address via a PCIe PIO read operation.

[0038] ③ FlexRay Interrupt Handling: When FlexRay generates a pin interrupt, the FPGA sends a PCIe interrupt to the ARM. Upon receiving this interrupt, the ARM enters the interrupt service routine.

[0039] ④ Interrupt type identification: In order to distinguish different interrupt sources (such as AMI read completion or FlexRay pin interrupt mentioned above), the ARM reads and writes the specified status register address of the FPGA through PCIe PIO in the interrupt service routine, thereby querying and determining the specific interrupt type and performing corresponding processing.

[0040] The above technical solutions are merely exemplary embodiments of the present invention. For those skilled in the art, based on the application methods and principles disclosed in the present invention, it is easy to make various types of improvements or modifications, and not limited to the methods described in the specific embodiments of the present invention. Therefore, the methods described above are merely preferred and not restrictive.

Claims

1. A communication device for extending the ARM FlexRay bus, characterized in that, include: ARM processor, FlexRay communication controller, FlexRay bus driver, wherein: The FlexRay communication controller is connected to the external bus of the ARM processor through a preset external bus interface; wherein the external bus interface is a parallel memory bus, or a high-speed SPI serial bus or a PCIe interface. The registers and message buffers of the FlexRay communication controller are mapped to the unified memory address space of the ARM processor; The FlexRay communication controller connects to the FlexRay physical bus via the FlexRay bus driver.

2. The apparatus according to claim 1, characterized in that, The initialization configuration method of the communication controller includes: The driver on the ARM processor initializes and configures the external bus interface; Perform a reset operation on the FlexRay communication controller and configure its global communication parameters, including one or more of the following: communication cycle length, static segment and dynamic segment duration, bit timing parameters, node ID, and cluster loop length; Configure the message buffers of the FlexRay communication controller, specifying the working mode (send or receive), the corresponding frame ID (slot number), the valid cycle mask, the data length, and the channel to which each buffer belongs.

3. The apparatus according to claim 2, characterized in that, The data transmission method of this device is as follows: The application passes the data to be sent and the target slot number to the driver; The driver locates the corresponding send message buffer based on the target slot number; Write the data to be sent into the data area of ​​the buffer and set the "send request" flag of the buffer; The FlexRay communication controller automatically encapsulates the data in the buffer into FlexRay frames and sends them to the FlexRay bus when the predetermined communication cycle and static / dynamic segment slots arrive, and updates the buffer status after the transmission is completed.

4. The apparatus according to claim 2, characterized in that, The data receiving method of this device is as follows: After receiving a valid frame on the FlexRay bus, the FlexRay communication controller automatically stores it into a preset receive message buffer according to its slot number, and generates a receive interrupt or sets a status flag. The ARM processor driver detects the event via interrupt or polling. In an interrupt service routine or polling task, the driver reads complete FlexRay frame data from the receive buffer, including data payload and status information, and passes it to the upper-layer application through a callback function or message queue mechanism.

5. The apparatus according to claim 1, characterized in that, The ARM processor driver monitors the status register of the FlexRay communication controller in real time, enabling the management of communication errors, synchronization status, and wake-up events.

6. The apparatus according to claim 1, characterized in that, The ARM processor provides a network management interface for synchronous startup and sleep / wake-up of multiple FlexRay bus nodes.

7. The apparatus according to any one of claims 1-6, characterized in that, The FlexRay communication controller connects two parallel FlexRay physical buses through two parallel FlexRay bus drivers.

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