A signal processing method and apparatus, electronic device, medium, and product

Abstract

The application relates to the technical field of large-scale multiple-input multiple-output, and provides a signal processing method and device, electronic equipment, a medium and a product.The method comprises the following steps: determining a Gram matrix of a channel matrix of a multiple-input multiple-output (MIMO) system according to the channel matrix and a conjugate transpose of the channel matrix; decomposing an augmented matrix determined according to the conjugate transpose of the channel matrix and the Gram matrix to obtain a decomposed augmented matrix, wherein the Gram matrix is eliminated as an upper triangular matrix in the decomposed augmented matrix, and a lower triangular matrix corresponding to the upper triangular matrix is determined according to an elimination factor recorded in an elimination process; and performing back substitution calculation on the decomposed augmented matrix to obtain a weighting matrix, wherein the weighting matrix is used for zero-forcing detection of a received signal.The adaptability of a real-time signal detection method is improved, and the problem that an existing method is difficult to cope with various service scenarios is effectively solved.

Description

Technical Field

[0001] This application relates to the field of massive multiple-input multiple-output (MIMO) technology, and more particularly to a signal processing method, apparatus, electronic device, medium, and product. Background Technology

[0002] Zero forcing (ZF) is a linear technique used for signal detection or equalization in MIMO communication systems. Currently, real-time signal detection requirements for Massive MIMO systems mainly include two approaches: solutions based on Central Processing Unit (CPU) servers and solutions based on dedicated hardware accelerators. CPU-server-based solutions utilize the parallel processing of general-purpose servers and multi-core CPUs, along with Single Instruction Multiple Data (SIMD) instructions for baseband computation, offering good flexibility and programmability. However, scaling up requires increasing the number of servers, resulting in high total cost of ownership, large physical space requirements, and difficulty in meeting the space requirements of base station infrastructure. Dedicated hardware accelerator-based solutions typically employ application-specific integrated circuits (ASICs), digital signal processors (DSPs), or field-programmable gate arrays (FPGAs) to embed the algorithm into hardware logic, pursuing maximum energy efficiency. However, this approach lacks reconfigurability, struggles to adapt to dynamically changing network configurations and user traffic, and suffers from severely insufficient maintainability and system update flexibility.

[0003] It is evident that existing real-time signal detection methods have poor adaptability in the face of complex and ever-changing business scenarios in wireless communication. Summary of the Invention

[0004] This application provides a signal processing method, apparatus, electronic device, medium, and product, aiming to solve the problem of poor adaptability of existing real-time signal detection methods.

[0005] In a first aspect, embodiments of this application provide a signal processing method applied to a graphics processing unit (GPU), the method comprising:

[0006] Based on the channel matrix of the multiple-input multiple-output (MIMO) system and its conjugate transpose, the Gram matrix of the channel matrix is ​​determined, wherein the channel matrix is ​​an N×K dimension matrix, N is the number of antennas, K is the number of user equipment, and N is greater than K, and both N and K are positive integers; the Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix.

[0007] The augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix is ​​decomposed to obtain the decomposed augmented matrix. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded in the elimination process.

[0008] The augmented matrix after decomposition is back-substituted to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

[0009] Optionally, determining the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix includes:

[0010] The channel matrix is ​​divided into blocks to obtain L row blocks and T column blocks. The L row blocks are obtained by dividing the channel matrix equally along the row dimension, and the T column blocks are obtained by dividing the channel matrix equally along the column dimension. L is a positive integer less than N, and T is a positive integer less than K.

[0011] Each row block is loaded into GPU shared memory in parallel using GPU thread blocks. Each row block includes T column blocks. Each thread block corresponds to one row block. Each thread block includes multiple thread bundles. The thread bundles are used to calculate the product of the conjugate transpose of each column block in the row block loaded in the corresponding thread block and the column block.

[0012] The product of the blocks located in the upper triangular region in the matrix corresponding to the L row blocks and T column blocks is calculated in parallel using thread bundles.

[0013] The lower triangular region is filled with a complex conjugate by multiplying the blocks of the upper triangular region to obtain the Gram matrix, wherein the lower triangular region is conjugate symmetric with the upper triangular region.

[0014] Optionally, the step of parallelly calculating the product of the blocks located in the upper triangular region of the matrices corresponding to the L row blocks and T column blocks using thread bundles includes:

[0015] According to the preset register size, the T column blocks in each row block are split into T' register-level blocks in each row block, where T' is greater than T;

[0016] The threads within the thread bundle load the register-level blocks from the GPU shared memory into the preset register. Each thread performs a local inner product multiplication and addition operation on the register-level blocks in the corresponding preset register to obtain a local accumulation result.

[0017] Using GPU atomic accumulation instructions, the local accumulation results of all threads are synchronously written back to the blocks located in the upper triangular region of the matrix corresponding to the L row blocks and T column blocks.

[0018] Optionally, the step of decomposing the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix includes:

[0019] The conjugate transpose of the channel matrix is ​​concatenated with the Gram matrix to obtain the augmented matrix;

[0020] Based on the dimension of the augmented matrix and the total number of GPU threads, a static mapping between global threads and the rows and columns of the augmented matrix is ​​established, and the remaining rows in the augmented matrix that have not been decomposed are divided into several row segments. In the static mapping, each GPU thread corresponds to a unique column index and initial row offset. In each round of the inner loop, all GPU threads process one row segment in parallel.

[0021] Based on the elimination operation performed on the elements within the row segment by each GPU thread, the diagonal element values ​​of the augmented matrix are calculated and stored in the diagonal array, and the elimination factor generated during the elimination process of each row is recorded.

[0022] Divide the augmented matrix by the diagonal element values ​​in the diagonal array to make the diagonal elements of the upper triangular matrix after the elimination of the Gram matrix equal to 1, and perform a linear transformation based on the diagonal matrix and the lower triangular matrix on the conjugate transpose of the channel matrix.

[0023] According to the column index allocated by the static mapping and the initial row offset, the elimination factors recorded in each round of row segment processing are written back in batches to iteratively update the lower triangular matrix until the Gram matrix in the augmented matrix is ​​completely eliminated to the upper triangular matrix, thus obtaining the decomposed augmented matrix.

[0024] Optionally, the back-substitution calculation of the decomposed augmented matrix to obtain the weighted matrix includes:

[0025] The conjugate transpose of the upper triangular matrix and the updated channel matrix is ​​loaded into the GPU shared memory. A column mapping relationship between global threads and the upper triangular matrix is ​​established based on the total number of GPU threads. The conjugate transpose of the updated channel matrix is ​​obtained by performing diagonal matrix scaling and lower triangular matrix inverse transformation on the conjugate transpose of the channel matrix in the augmented matrix. Each GPU thread corresponds to a unique column of the upper triangular matrix.

[0026] Based on the column mapping relationship, a bottom-up solution order is adopted to perform back-substitution calculations row by row from the last row of the upper triangular matrix to obtain the solution values ​​corresponding to each column;

[0027] The solution values ​​corresponding to each column are combined in row and column order to obtain the weighted matrix.

[0028] Secondly, embodiments of this application provide a signal processing apparatus applied to a graphics processing unit (GPU), the apparatus comprising:

[0029] The determination module is used to determine the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix, wherein the channel matrix is ​​an N×K dimension matrix, N is the number of antennas, K is the number of user equipment, and N is greater than K, and N and K are both positive integers; the Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix.

[0030] The decomposition module is used to decompose the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded in the elimination process.

[0031] The calculation module is used to perform back-substitution calculation on the decomposed augmented matrix to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

[0032] Thirdly, embodiments of this application provide an electronic device, including: a processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, it implements the steps of the signal processing method as described in the first aspect.

[0033] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the signal processing method as described in the first aspect.

[0034] Fifthly, embodiments of this application provide a computer program product including computer instructions that, when executed by a processor, implement the steps of the signal processing method as described in the first aspect.

[0035] In this embodiment, a GPU-based parallel architecture is used to construct the channel matrix. The computational load is reduced by leveraging GPU block parallelism and the symmetry of Hermitian matrices, efficiently constructing the Gram matrix and overcoming the bottleneck of high-dimensional computation. Then, the augmented matrix, determined by the conjugate transpose of the channel matrix and the Gram matrix, is decomposed to obtain the decomposed augmented matrix, avoiding the high overhead of explicit inversion. It also supports row-segment batch processing, adapting to dynamic changes in the number of users. Back-substitution calculation is performed on the decomposed augmented matrix to solve for the weighted matrix, balancing computational efficiency and result accuracy. The weighted matrix is ​​used for zero-forcing detection of the received signal, quickly canceling inter-user interference. This improves the adaptability of the real-time signal detection method and effectively solves the problem that existing methods struggle to cope with changing business scenarios. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a flowchart of a signal processing method provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of a Massive MIMO system provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of Gram matrix calculation provided in an embodiment of this application;

[0040] Figure 4 This is a schematic diagram of the structure of a signal processing device provided in an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] See Figure 1 , Figure 1 This is a flowchart of a signal processing method provided in an embodiment of this application. The signal processing method is applied to a graphics processing unit (GPU). Figure 1 As shown, the method includes the following steps:

[0044] Step 101: Determine the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix. The channel matrix is ​​an N×K dimension matrix, where N is the number of antennas, K is the number of user equipment, and N is greater than K. Both N and K are positive integers. The Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix.

[0045] In this step, the base station in a Massive MIMO system is equipped with a large number of antennas (i.e., N antennas, where N can range from 256 to 1024), and the number of antennas is much larger than the number of user equipment (i.e., K user equipment, where K can range from 16 to 128). Figure 2 As shown, when N / K approaches infinity, the column vectors of the channel matrix tend to be orthogonal, resulting in channel hardening. This causes linear precoding / detection algorithms such as ZF and Minimum Mean Square Error (MMSE) to approach optimal performance in Massive MIMO scenarios. In this embodiment, the channel matrix of the Massive MIMO system can be obtained through channel estimation techniques. H Channel matrix H It can directly reflect the signal transmission link characteristics between the base station and each user.

[0046] After obtaining the channel matrix, the Gram matrix of the channel matrix is ​​determined based on the channel matrix and its conjugate transpose. The Gram matrix is ​​a K×K dimension Hermitian positive definite matrix.

[0047] Specifically, based on the uplink model in related technologies, the corresponding weighting matrix can be obtained. .therefore, W It can be represented as:

[0048]

[0049] in, H Let N be the channel matrix (N×K dimensions) of a Massive MIMO system. H H for H The conjugate transpose of . Construct the channel matrix. H Gram matrix ,and G It is a positive Hermitian definite matrix, which is symmetric in the complex field and has positive eigenvalues.

[0050] For example, the channel matrix can be divided into row and column levels, and GPU threads can load these blocks into shared memory in parallel, reducing global memory access latency. Furthermore, leveraging the Hermitian conjugate symmetry, only the upper triangular region of the Gram matrix needs to be calculated, while the lower triangular region is filled with complex conjugates, directly halving the computational load. Simultaneously, threads can compute the inner product of sub-blocks in parallel, avoiding memory conflicts through atomic accumulation instructions, ensuring efficient and synchronized computation. In this way, the... The complex channel matrix multiplication operation is transformed into a low-dimensional (K×K) matrix operation, which reduces the amount of computation by utilizing the properties of positive definite matrices and is adapted to the parallel architecture of GPUs.

[0051] Step 102: Decompose the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded during the elimination process.

[0052] In this step, considering the high complexity of directly solving the inverse of the Gram matrix, this embodiment employs the method of constructing an augmented matrix and eliminating variables to achieve a one-time calculation of the weighted matrix for zero-forcing detection, thus making the computation more efficient. W .

[0053] For example, in order to calculate simultaneously G -1 Sum weighted matrix First, an augmented matrix is ​​constructed based on the conjugate transpose of the channel matrix and the Gram matrix, thus completing the integration of the augmented matrix:

[0054]

[0055] in, AThe matrix is ​​an augmented matrix with dimensions K×(K+N). A Static Mapping LDL (SM-LDL) algorithm can be used to decompose the augmented matrix using a GPU-based parallel architecture. A Decomposition is performed as follows: Before the kernel function starts, a static mapping is completed between the global threads and the rows and columns of the augmented matrix. Each thread is assigned a unique column index and an initial row offset to avoid the overhead of dynamic index calculation. The remaining undecomposed rows are divided into segments of a preset length. In each round of the inner loop, all threads process one row segment in parallel, solving the problems of row-level serial processing and thread idleness in traditional LDL decomposition. The threads perform elimination operations in registers, and the Gram matrix is ​​decomposed. G Elimination results in an upper triangular matrix L H Simultaneously record the elimination factors to form a unit lower triangular matrix. L Augmented matrix A Middle left H H Synchronized update to F = D -1 L -1 H H ,in, D It is a diagonal matrix, formed by the diagonal elements of the elimination process; after elimination, we have: L H [ W ]=[ F The elimination results are written back to the GPU global memory in batches to ensure data consistency.

[0056] Thus, matrix factorization replaces direct inversion. G -1 ,reduce The computational bottleneck of complexity is addressed, and key matrix blocks are updated synchronously to provide data support for subsequent back-substitution calculations.

[0057] Step 103: Perform back-substitution calculation on the decomposed augmented matrix to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

[0058] In this step, a GPU-based parallel architecture performs back-substitution calculations on the decomposed augmented matrix to obtain the weighted matrix for zero-forcing detection. W The decomposed upper triangular matrix L H And the updated D -1 L -1 H HLoaded into GPU shared memory, a mapping relationship between threads and matrix columns is established based on the total number of threads, with each thread responsible for calculating one column. A bottom-up solution order is adopted to ensure that the solutions for subsequent rows are ready when the solution for the current row is being calculated. Thread synchronization within the same column is achieved through GPU synchronization functions to avoid calculation deviations caused by unprepared data. The solution values ​​of all columns are combined in row and column order to directly obtain:

[0059] .

[0060] by The complexity of solving the weighted matrix is ​​reduced, and combined with the GPU parallel architecture, the computational throughput is significantly improved.

[0061] Thus, when performing zero-forcing detection, the weighting matrix can be... W The received signal is loaded into the GPU's shared memory, and threads are started to perform multiply-accumulate operations in parallel. The weighting matrix is ​​transformed by the inverse channel matrix to cancel the superposition interference of signals from different users on the same time-frequency resource. The estimated value of the user's transmitted signal obtained by the multiply-accumulate operation, i.e., the zero-forcing detection result, is written back to global memory in batches from the shared memory and then output. This completes the restoration from the received signal to the user's original signal, realizing high-spectrum-efficiency communication in the Massive MIMO system.

[0062] In this embodiment, a GPU-based parallel architecture is used to construct the channel matrix. The computational load is reduced by leveraging GPU block parallelism and the symmetry of Hermitian matrices, efficiently constructing the Gram matrix and overcoming the bottleneck of high-dimensional computation. Then, the augmented matrix, determined by the conjugate transpose of the channel matrix and the Gram matrix, is decomposed to obtain the decomposed augmented matrix, avoiding the high overhead of explicit inversion. It also supports row-segment batch processing, adapting to dynamic changes in the number of users. Back-substitution calculation is performed on the decomposed augmented matrix to solve for the weighted matrix, balancing computational efficiency and result accuracy. The weighted matrix is ​​used for zero-forcing detection of the received signal, quickly canceling inter-user interference. This improves the adaptability of the real-time signal detection method and effectively solves the problem that existing methods struggle to cope with changing business scenarios.

[0063] Optionally, step 101, determining the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix, includes:

[0064] The channel matrix is ​​divided into blocks to obtain L row blocks and T column blocks. The L row blocks are obtained by dividing the channel matrix equally along the row dimension, and the T column blocks are obtained by dividing the channel matrix equally along the column dimension. L is a positive integer less than N, and T is a positive integer less than K.

[0065] Each row block is loaded into GPU shared memory in parallel using GPU thread blocks. Each row block includes T column blocks. Each thread block corresponds to one row block. Each thread block includes multiple thread bundles. The thread bundles are used to calculate the product of the conjugate transpose of each column block in the row block loaded in the corresponding thread block and the column block.

[0066] The product of the blocks located in the upper triangular region in the matrix corresponding to the L row blocks and T column blocks is calculated in parallel using thread bundles.

[0067] The lower triangular region is filled with a complex conjugate by multiplying the blocks of the upper triangular region to obtain the Gram matrix, wherein the lower triangular region is conjugate symmetric with the upper triangular region.

[0068] In this embodiment, the calculation of the Gram matrix is ​​essentially the product of the conjugate transpose of the channel matrix and the channel matrix itself. First, assume the channel matrix has the following form:

[0069]

[0070] A Gram matrix can be represented as:

[0071]

[0072] Among them, the child elements of G g i,j for:

[0073]

[0074] In calculating the Gram matrix G At that time, only the channel matrix needs to be... H As an input parameter, compared to the traditional GPU parallel matrix multiplication method that requires passing in two matrices, it significantly reduces data transmission overhead (e.g., Figure 3 As shown, Figure 3 (Diagram illustrating Gram matrix calculation). In the task partitioning based on the GPU thread block architecture, each thread block is responsible for the calculation. G A block. By utilizing the properties of the Hermitian matrix ( j ≥ i In the GPU, each thread beam focuses on the upper triangular elements. G [ i,j The calculation of ].

[0075] Specifically, each thread calculates a partial inner product between the H column vectors and atomically accumulates it to global memory. G [ i,j This avoids memory conflicts. Because... GThe Hermitian property allows the lower triangular part to be directly obtained from the complex conjugate symmetry of the upper triangular elements, reducing computation and storage requirements by half. Further, combining multi-level cache block optimization techniques, a Parallel Hermitian Block Gram Matrix Multiplication (PHBGMM) algorithm is proposed. Through the synergistic optimization of matrix symmetry and GPU parallel architecture, efficient Gram matrix computation is achieved. Constructing the Gram matrix mainly involves three stages:

[0076] Chunked loading: H Load into shared memory in chunks;

[0077] Sub-block product: Parallel computation of sub-block products;

[0078] Symmetrical filling: Fill the lower triangle based on Hermitian properties.

[0079] During the block loading process, the channel matrix H To perform block processing, it can first be divided into L equal row blocks along its row dimension (N-dimensional), with each row block having a height of [missing information]. b N ,Right now:

[0080]

[0081] Gram matrices can be written in blocks as follows:

[0082]

[0083] In further computation, the GPU only needs to repeatedly load each submatrix (i.e., row-blocks). Then complete the corresponding inner product and accumulate it to the global product. G In the middle. Each line is divided into blocks. Continue dividing the column dimension (K dimensions) into T equal columns, with each column block having a height of [missing information]. b K .make:

[0084]

[0085] in, The first of the T columns is the first... t Divide into columns into blocks, t It is a positive integer less than or equal to T. Thus, the Gram matrix can also be viewed as being divided into [N / b N ]×[K / b K [Number] blocks.

[0086] During the sub-block multiplication process, each row sub-block can be loaded into the GPU shared memory in parallel by GPU thread blocks, and the product of the sub-blocks in the upper triangular region of the matrix corresponding to the L row sub-blocks and the T column sub-blocks can be calculated in parallel by warps.

[0087] After the sub-block multiplication process, symmetric padding is performed. The sub-blocks in the lower triangular region are filled with the complex conjugate of the product of the sub-blocks in the upper triangular region to obtain the Gram matrix, that is:

[0088]

[0089] where

[0090]

[0091] For the elements within the block , it can be expressed as:

[0092]

[0093] where 1 ≤ r , s ≤ b K . It is a diagonal block when t = t', and the upper triangular part when t < t'. To further reuse data, in the GPU kernel, each also needs to be loaded from the global memory to the shared memory and then loaded into the register in small chunks for multiplication and addition. The specific process can be seen in the following description:

[0094] Optionally, the parallel calculation of the product of the sub-blocks in the upper triangular region of the matrix corresponding to the L row sub-blocks and the T column sub-blocks by warps includes:

[0095] According to the size of the preset register, the T column sub-blocks in each row sub-block are split to obtain T' register-level sub-blocks of each row sub-block, where T' > T;

[0096] Threads within a warp load the register-level sub-blocks from the GPU shared memory to the preset register, and each thread completes the local inner product multiplication and addition operation of the register-level sub-block in the corresponding preset register to obtain a local accumulation result;

[0097] Through the GPU atomic accumulation instruction, the local accumulation results of all threads are synchronously written back to the sub-blocks in the upper triangular region of the matrix corresponding to the L row sub-blocks and the T column sub-blocks.

[0098] In this example, it can be set that:

[0099]

[0100] where This represents a small block after the shared memory is partitioned, and can be the size of a predefined register block. Based on this, for a block... and In degree d Within each register tile, the local accumulation can be calculated as follows:

[0101]

[0102] in, Q d Indicates the first d A subset of row indices corresponding to each register block (totaling ) r N Okay, if the whole piece has b N If so, then D× r N = b N ). Traverse all d Then, a block was obtained. Complete cumulative result:

[0103]

[0104] In GPU kernel functions, each thread and thread bundle can retrieve data from shared memory according to a block-based strategy. The multiplication and addition are performed in the register. The accumulated result is then written directly back to the corresponding global memory using an atomic addition instruction. Position. Finally, for the lower triangle part:

[0105]

[0106] In this embodiment, the PHBGMM algorithm is proposed to calculate only the upper triangle and then fill the lower triangle in one go using conjugate symmetry, directly reducing the computational cost by half. Secondly, a two-level block partitioning method is used, first... H The algorithm divides the data into large blocks along the row direction and then into smaller blocks along the column direction to ensure that the thread bundle is always fully loaded. Finally, it uses shared memory and registers for block partitioning, moving large blocks into shared memory first and smaller blocks into registers to reduce global memory access; after multiplication and addition within a block, atomic accumulation is used to write the data back. This reduces floating-point operations by half and lowers global memory access.

[0107] Optionally, step 102, decomposing the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix, includes:

[0108] The conjugate transpose of the channel matrix is ​​concatenated with the Gram matrix to obtain the augmented matrix, which is expressed as follows: A =[ HH | G ], where A is the augmented matrix, H H This is the conjugate transpose of the channel matrix. G Let be the Gram matrix, and let the dimension of the augmented matrix be K×(K+N);

[0109] Based on the dimension of the augmented matrix and the total number of GPU threads, a static mapping between global threads and the rows and columns of the augmented matrix is ​​established. In the static mapping, each GPU thread corresponds to a unique column index and an initial row offset. The column index is used to represent the column number of the augmented matrix corresponding to the GPU thread, and the initial row offset is used to represent the starting row number of the augmented matrix corresponding to the GPU thread.

[0110] The remaining rows in the augmented matrix that have not been decomposed are divided into several rows according to a preset segment length. In each round of the inner loop, all GPU threads process one row in parallel.

[0111] Each GPU thread performs elimination operations on the elements within a row segment, calculating the update values ​​of the off-diagonal elements and the diagonal elements of the augmented matrix, storing the diagonal element values ​​in a diagonal array, and recording the elimination factors generated during the elimination process in each row. The update values ​​of the off-diagonal elements are the iterative results of the elimination operations on the elements at the non-main diagonal positions within the current row segment of the augmented matrix, and the diagonal element values ​​are the iterative results of the elimination operations on the elements at the main diagonal positions within the current row segment of the augmented matrix.

[0112] Divide the augmented matrix by the diagonal elements of the diagonal array to make the diagonal elements of the upper triangular matrix obtained after eliminating the Gram matrix equal to 1, and simultaneously adjust the values ​​of the diagonal elements in the augmented matrix. H H Updated to D −1 L −1 H H , D The diagonal matrix determined based on the diagonal array. L It is a lower triangular matrix;

[0113] Based on the elimination factors recorded during each round of row segment processing, and according to the column index and initial row offset allocated by the static mapping, the elimination factors are written back in batches to the corresponding row and column positions of the lower triangular matrix, completing the iterative update of the lower triangular matrix until the Gram matrix in the augmented matrix is ​​completely eliminated into an upper triangular matrix. L H This yields the augmented matrix after decomposition.

[0114] In this embodiment, the augmented matrix is ​​represented as: A =[ H H | G In the Gram matrix G Elimination results in an upper triangular matrix L H Simultaneously record the elimination factors to form a unit lower triangular matrix. L Augmented matrix A Middle left H H Synchronized update to F = D -1 L -1 H H For LDL decomposition, in order to obtain the augmented matrix during iterative computation... F Matrices can be calculated L H The upper triangular part and the diagonal elements D Partial. Because at the numerical level, if only the matrix is ​​considered... L H It can be applied only to the augmented matrix. A Simply perform a proper downward triangle elimination. To obtain... A -1 The partial information is then applied to the augmented matrix. A =[ H H | G This makes the operation more convenient. Therefore, the LDL decomposition logic is transformed into the reverse process. First, the diagonal elements are initialized, and then the calculation is performed row by row in reverse.

[0115] For example, for First calculate the first k Non-diagonal elements of a row:

[0116]

[0117] Then calculate the first... k diagonal elements of a row:

[0118]

[0119] Store it in an array d In the middle. The augmented matrix [ H H | G Divide by d jj This makes the diagonal elements all equal to 1. A corresponding scaling is also applied to the augmented matrix. Thus, in the final upper triangle, all diagonal elements are 1, conforming to the form of an upper triangular matrix. When all pivot rows... After processing, the right side of the augmented matrix will show an upper triangle, i.e. L H The lower triangle stores the data needed for the elimination operation. Left side H H Then update to D -1 L -1 H H Thus, we have:

[0120]

[0121] Where A=LDL H .

[0122] Furthermore, considering that in GPU parallel computing, each outer loop only processes the Gaussian elimination operation of the current pivot row, while the update of the lower triangular part is often run serially, the parallelism of each update round is limited by the number of rows, resulting in most threads in the GPU thread block being idle and wasting resources. Therefore, this embodiment proposes an LDL decomposition algorithm based on static mapping. The goal is to ensure that each thread computes a unique block of the matrix (…). i,j The system considers the augmented matrix's dimensions and the total number of GPU threads, ensuring that each thread has a computational task and avoiding multiple threads processing the same element. Before the outer loop begins, a static mapping is established between global threads and the rows and columns of the augmented matrix, based on the augmented matrix's dimensions and the total number of GPU threads.

[0123] For example, for an n-dimensional square matrix, let the total number of GPU threads be T. In each iteration, each thread needs to be mapped to a submatrix. A position within this. Therefore, the column and row indices in the static mapping are defined as follows:

[0124]

[0125]

[0126] Where tid is the global index number of the thread within the entire thread block, determined by the following formula:

[0127]

[0128] Here, `colIdx` and `rowOffset` represent the column index and initial row offset that the thread will process in the entire matrix, respectively. To ensure that all threads can cover the complete row dimension of the submatrix, the entire matrix needs to be divided into several segments, with each segment containing the following number of rows:

[0129]

[0130] Therefore, the number of iterations required for each round of submatrix processing is:

[0131]

[0132] In the i In the inner loop, the actual row index of the matrix handled by the thread is given by the following formula:

[0133]

[0134] This approach uses static thread mapping, where each thread is responsible for a specific row / column before startup, avoiding repeated index calculations and global synchronization during iteration. Then, row-level batch processing is performed, segmenting the remaining rows so that all threads can work in each loop iteration, resolving the issues of row-level serial processing and thread idleness in traditional decomposition. Finally, register-based local updates are used, with row-level elimination performed only in registers and written back in a single operation, significantly reducing the number of global synchronization operations.

[0135] Optionally, step 103, performing back-substitution calculation on the decomposed augmented matrix to obtain a weighted matrix, includes:

[0136] The conjugate transpose of the upper triangular matrix and the updated channel matrix is ​​loaded into the GPU shared memory. A column mapping relationship between global threads and the upper triangular matrix is ​​established based on the total number of GPU threads. The upper triangular matrix is ​​obtained by decomposing and eliminating Gram matrices in the augmented matrix. The conjugate transpose of the updated channel matrix is ​​obtained by performing diagonal matrix scaling and lower triangular matrix inverse transformation on the conjugate transpose of the channel matrix in the augmented matrix. Each GPU thread corresponds to a unique column of the upper triangular matrix.

[0137] A bottom-up solution order is adopted, starting from the last row of the upper triangular matrix, and back-substitution calculation is performed row by row upward. Each GPU thread calculates the solution value of the current row based on the solution results of the subsequent rows in the corresponding column and the element values ​​of the upper triangular matrix. The element values ​​are the final iterative update values ​​of the Gram matrix after elimination operation and diagonal scaling.

[0138] Within the same column, thread synchronization is performed using GPU synchronization functions, ensuring that the solution values ​​for all subsequent rows corresponding to the current row have been calculated and stored.

[0139] After all row solutions for the current column have been calculated, the column solutions for each GPU thread are written back to the GPU global memory in batches. The solutions for all columns are then combined in row and column order to obtain the weighted matrix for zero-forcing detection.

[0140] In this embodiment, in order to solve the subsequent system of linear equations of the form Ux=b, where U is a n×n An upper triangular matrix. Such a matrix has all elements below the diagonal equal to 0, and takes the following form:

[0141]

[0142] The right side of the equation b It can be a vector or a matrix. The key step in solving this type of system of equations is to start from the last row and calculate the unknowns row by row upwards. x i :

[0143]

[0144] if b If the matrix has multiple columns, repeat this process for each column. This bottom-up back-substitution method is used because in the upper triangular matrix U, the rows... i elements on exist j j>i The time is 0. Therefore, the solution for each row is 0. x i The solution depends on the subsequent steps. x i+1 arrive x i-1 Starting from the bottom row ensures that the calculation... x i All that is needed x j middle Figure 4 All have been solved. In the back-substitution algorithm, although the calculation of each row depends on the results of all the rows above, there is parallelism when processing columns of different matrices. The core parallel strategy of the parallel back-substitution algorithm given in this embodiment is column-by-column parallelism. Each calculation result needs to use a synchronization function to ensure that all threads have completed the back-substitution calculation.

[0145] In this way, by adopting a bottom-up order to substitute back from the last row of the matrix, each thread combines the solved results of the subsequent rows in its responsible column with the eliminated and scaled element values ​​of the upper triangular matrix to calculate the solution value of the current row. Within the same column, the GPU synchronization function ensures that the solution values ​​of the subsequent rows are ready, avoiding calculation errors. After all the solution values ​​of each column have been calculated, the thread writes the column solution values ​​back to the GPU global memory in batches. All the column solution values ​​are combined in row and column order to obtain the weighted matrix for zero-forcing detection, which improves the efficiency of parallel processing.

[0146] See Figure 4 , Figure 4 This is a schematic diagram of a signal processing device provided in an embodiment of this application. The signal processing device is applied to a graphics processing unit (GPU), such as... Figure 5As shown, the signal processing device 400 includes:

[0147] The determining module 401 is used to determine the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix, wherein the channel matrix is ​​an N×K dimension matrix, N is the number of antennas, K is the number of user equipment, and N is greater than K, and N and K are both positive integers; the Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix.

[0148] The decomposition module 402 is used to decompose the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded in the elimination process.

[0149] The calculation module 403 is used to perform back-substitution calculation on the decomposed augmented matrix to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

[0150] Optionally, module 401 is specifically used for:

[0151] The channel matrix is ​​divided into blocks to obtain L row blocks and T column blocks. The L row blocks are obtained by dividing the channel matrix equally along the row dimension, and the T column blocks are obtained by dividing the channel matrix equally along the column dimension. L is a positive integer less than N, and T is a positive integer less than K.

[0152] Each row block is loaded into GPU shared memory in parallel using GPU thread blocks. Each row block includes T column blocks. Each thread block corresponds to one row block. Each thread block includes multiple thread bundles. The thread bundles are used to calculate the product of the conjugate transpose of each column block in the row block loaded in the corresponding thread block and the column block.

[0153] The product of the blocks located in the upper triangular region in the matrix corresponding to the L row blocks and T column blocks is calculated in parallel using thread bundles.

[0154] The lower triangular region is filled with a complex conjugate by multiplying the blocks of the upper triangular region to obtain the Gram matrix, wherein the lower triangular region is conjugate symmetric with the upper triangular region.

[0155] Optionally, the step of parallelly calculating the product of the blocks located in the upper triangular region of the matrices corresponding to the L row blocks and T column blocks using thread bundles includes:

[0156] According to the preset register size, the T column blocks in each row block are split into T' register-level blocks in each row block, where T' is greater than T;

[0157] The threads within the thread bundle load the register-level blocks from the GPU shared memory into the preset register. Each thread performs a local inner product multiplication and addition operation on the register-level blocks in the corresponding preset register to obtain a local accumulation result.

[0158] Using GPU atomic accumulation instructions, the local accumulation results of all threads are synchronously written back to the blocks located in the upper triangular region of the matrix corresponding to the L row blocks and T column blocks.

[0159] Optionally, the decomposition module 402 is specifically used for:

[0160] The conjugate transpose of the channel matrix is ​​concatenated with the Gram matrix to obtain the augmented matrix;

[0161] Based on the dimension of the augmented matrix and the total number of GPU threads, a static mapping between global threads and the rows and columns of the augmented matrix is ​​established, and the remaining rows in the augmented matrix that have not been decomposed are divided into several row segments. In the static mapping, each GPU thread corresponds to a unique column index and initial row offset. In each round of the inner loop, all GPU threads process one row segment in parallel.

[0162] Based on the elimination operation performed on the elements within the row segment by each GPU thread, the diagonal element values ​​of the augmented matrix are calculated and stored in the diagonal array, and the elimination factor generated during the elimination process of each row is recorded.

[0163] Divide the augmented matrix by the diagonal element values ​​in the diagonal array to make the diagonal elements of the upper triangular matrix after the elimination of the Gram matrix equal to 1, and perform a linear transformation based on the diagonal matrix and the lower triangular matrix on the conjugate transpose of the channel matrix.

[0164] According to the column index allocated by the static mapping and the initial row offset, the elimination factors recorded in each round of row segment processing are written back in batches to iteratively update the lower triangular matrix until the Gram matrix in the augmented matrix is ​​completely eliminated to the upper triangular matrix, thus obtaining the decomposed augmented matrix.

[0165] Optionally, the calculation module 403 is specifically used for:

[0166] The conjugate transpose of the upper triangular matrix and the updated channel matrix is ​​loaded into the GPU shared memory. A column mapping relationship between global threads and the upper triangular matrix is ​​established based on the total number of GPU threads. The conjugate transpose of the updated channel matrix is ​​obtained by performing diagonal matrix scaling and lower triangular matrix inverse transformation on the conjugate transpose of the channel matrix in the augmented matrix. Each GPU thread corresponds to a unique column of the upper triangular matrix.

[0167] Based on the column mapping relationship, a bottom-up solution order is adopted to perform back-substitution calculations row by row from the last row of the upper triangular matrix to obtain the solution values ​​corresponding to each column;

[0168] The solution values ​​corresponding to each column are combined in row and column order to obtain the weighted matrix.

[0169] The signal processing apparatus 400 is designed to implement the various processes described in the embodiments of the signal processing method, with each technical feature corresponding to the others and achieving the same technical effect. To avoid repetition, these details will not be repeated here.

[0170] This application also provides an electronic device, including: a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the various processes of the above-described signal processing method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0171] For details, see Figure 5 This application also provides an electronic device, including a bus 501, a transceiver 502, an antenna 503, a bus interface 504, a processor 505, and a memory 506.

[0172] The processor 505 is configured to perform the following steps:

[0173] Based on the channel matrix of the multiple-input multiple-output (MIMO) system and its conjugate transpose, the Gram matrix of the channel matrix is ​​determined, wherein the channel matrix is ​​an N×K dimension matrix, N is the number of antennas, K is the number of user equipment, and N is greater than K, and both N and K are positive integers; the Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix.

[0174] The augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix is ​​decomposed to obtain the decomposed augmented matrix. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded in the elimination process.

[0175] The augmented matrix after decomposition is back-substituted to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

[0176] exist ​ In this document, a bus architecture (represented by bus 501) is used. Bus 501 can include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 505 and memory represented by memory 506. Bus 501 can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 504 provides an interface between bus 501 and transceiver 502. Transceiver 502 can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 505 is transmitted over a wireless medium via antenna 503, which further receives data and transmits it to processor 505.

[0177] Processor 505 manages bus 501 and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 506 can be used to store data used by processor 505 during operation.

[0178] This application also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the various processes of the above-described signal processing method embodiments and achieves the same technical effects. To avoid repetition, it will not be described again here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0179] This application also provides a computer program product, including computer instructions. When executed by a processor, these computer instructions implement the various processes of the above-described signal processing method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0180] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0181] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0182] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A signal processing method, characterized in that, Applied to a graphics processing unit (GPU), the method includes: Based on the channel matrix of the multiple-input multiple-output (MIMO) system and its conjugate transpose, the Gram matrix of the channel matrix is ​​determined, wherein the channel matrix is ​​an N×K dimension matrix, N is the number of antennas, K is the number of user equipment, and N is greater than K, and both N and K are positive integers; the Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix. The augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix is ​​decomposed to obtain the decomposed augmented matrix. In the process of decomposing the augmented matrix, the remaining rows that have not yet been decomposed are divided into several row segments. In each round of the inner loop, one row segment is processed in parallel by all GPU threads. In the static mapping constructed based on the dimension of the augmented matrix and the total number of GPU threads, each GPU thread corresponds to a unique column index and initial row offset. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded in the elimination process. The augmented matrix after decomposition is back-substituted to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

2. The method according to claim 1, characterized in that, Determining the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix includes: The channel matrix is ​​divided into blocks to obtain L row blocks and T column blocks. The L row blocks are obtained by dividing the channel matrix equally along the row dimension, and the T column blocks are obtained by dividing the channel matrix equally along the column dimension. L is a positive integer less than N, and T is a positive integer less than K. Each row block is loaded into GPU shared memory in parallel using GPU thread blocks. Each row block includes T column blocks. Each thread block corresponds to one row block. Each thread block includes multiple thread bundles. The thread bundles are used to calculate the product of the conjugate transpose of each column block in the row block loaded in the corresponding thread block and the column block. The product of the blocks located in the upper triangular region in the matrix corresponding to the L row blocks and T column blocks is calculated in parallel using thread bundles. The lower triangular region is filled with a complex conjugate by multiplying the blocks of the upper triangular region to obtain the Gram matrix, wherein the lower triangular region is conjugate symmetric with the upper triangular region.

3. The method according to claim 2, characterized in that, The step of parallelly calculating the product of the blocks located in the upper triangular region of the matrix corresponding to the L row blocks and T column blocks using thread bundles includes: According to the preset register size, the T column blocks in each row block are split into T' register-level blocks in each row block, where T' is greater than T; The threads within the thread bundle load the register-level blocks from the GPU shared memory into the preset register. Each thread performs a local inner product multiplication and addition operation on the register-level blocks in the corresponding preset register to obtain a local accumulation result. Using GPU atomic accumulation instructions, the local accumulation results of all threads are synchronously written back to the blocks located in the upper triangular region of the matrix corresponding to the L row blocks and T column blocks.

4. The method according to claim 1, characterized in that, The step of decomposing the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix includes: The conjugate transpose of the channel matrix is ​​concatenated with the Gram matrix to obtain the augmented matrix; Based on the dimension of the augmented matrix and the total number of GPU threads, a static mapping between global threads and the rows and columns of the augmented matrix is ​​established, and the remaining rows in the augmented matrix that have not been decomposed are divided into several row segments. In the static mapping, each GPU thread corresponds to a unique column index and initial row offset. In each round of the inner loop, all GPU threads process one row segment in parallel. Based on the elimination operation performed on the elements within the row segment by each GPU thread, the diagonal element values ​​of the augmented matrix are calculated and stored in the diagonal array, and the elimination factor generated during the elimination process of each row is recorded. Divide the augmented matrix by the diagonal element values ​​in the diagonal array to make the diagonal elements of the upper triangular matrix after the elimination of the Gram matrix equal to 1, and perform a linear transformation based on the diagonal matrix and the lower triangular matrix on the conjugate transpose of the channel matrix. According to the column index allocated by the static mapping and the initial row offset, the elimination factors recorded in each round of row segment processing are written back in batches to iteratively update the lower triangular matrix until the Gram matrix in the augmented matrix is ​​completely eliminated to the upper triangular matrix, thus obtaining the decomposed augmented matrix.

5. The method according to claim 1, characterized in that, The back-substitution calculation of the decomposed augmented matrix to obtain the weighted matrix includes: The conjugate transpose of the upper triangular matrix and the updated channel matrix is ​​loaded into the GPU shared memory. A column mapping relationship between global threads and the upper triangular matrix is ​​established based on the total number of GPU threads. The conjugate transpose of the updated channel matrix is ​​obtained by performing diagonal matrix scaling and lower triangular matrix inverse transformation on the conjugate transpose of the channel matrix in the augmented matrix. Each GPU thread corresponds to a unique column of the upper triangular matrix. Based on the column mapping relationship, a bottom-up solution order is adopted to perform back-substitution calculations row by row from the last row of the upper triangular matrix to obtain the solution values ​​corresponding to each column; The solution values ​​corresponding to each column are combined in row and column order to obtain the weighted matrix.

6. A signal processing apparatus, characterized in that, The device, applied to a graphics processing unit (GPU), includes: The determination module is used to determine the Gram matrix of the channel matrix based on the channel matrix of the multiple-input multiple-output (MIMO) system and the conjugate transpose of the channel matrix, wherein the channel matrix is ​​an N×K dimension matrix, N is the number of antennas, K is the number of user equipment, and N is greater than K, and N and K are both positive integers; the Gram matrix is ​​the product of the conjugate transpose of the channel matrix and the channel matrix, and the Gram matrix is ​​a K×K dimension Hermitian positive definite matrix. The decomposition module is used to decompose the augmented matrix determined by the conjugate transpose of the channel matrix and the Gram matrix to obtain the decomposed augmented matrix. In the process of decomposing the augmented matrix, the remaining rows that have not yet been decomposed are divided into several row segments. In each round of the inner loop, one row segment is processed in parallel by all GPU threads. In the static mapping constructed based on the dimension of the augmented matrix and the total number of GPU threads, each GPU thread corresponds to a unique column index and initial row offset. In the decomposed augmented matrix, the Gram matrix is ​​eliminated to an upper triangular matrix, and the lower triangular matrix corresponding to the upper triangular matrix is ​​determined according to the elimination factor recorded in the elimination process. The calculation module is used to perform back-substitution calculation on the decomposed augmented matrix to obtain a weighted matrix, which is used for zero-forcing detection of the received signal.

7. The apparatus according to claim 6, characterized in that, The determining module is specifically used for: The channel matrix is ​​divided into blocks to obtain L row blocks and T column blocks. The L row blocks are obtained by dividing the channel matrix equally along the row dimension, and the T column blocks are obtained by dividing the channel matrix equally along the column dimension. L is a positive integer less than N, and T is a positive integer less than K. Each row block is loaded into GPU shared memory in parallel using GPU thread blocks. Each row block includes T column blocks. Each thread block corresponds to one row block. Each thread block includes multiple thread bundles. The thread bundles are used to calculate the product of the conjugate transpose of each column block in the row block loaded in the corresponding thread block and the column block. The product of the blocks located in the upper triangular region in the matrix corresponding to the L row blocks and T column blocks is calculated in parallel using thread bundles. The lower triangular region is filled with a complex conjugate by multiplying the blocks of the upper triangular region to obtain the Gram matrix, wherein the lower triangular region is conjugate symmetric with the upper triangular region.

8. An electronic device, characterized in that, include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the method as described in any one of claims 1 to 5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 5.

10. A computer program product, characterized in that, Includes computer instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 5.

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