Phased array integrated printed circuit board laminated structure and board manufacturing method

Abstract

The invention relates to a phased array integrated printed circuit board laminated structure and a board manufacturing method, and belongs to the technical field of satellite communication equipment. The stacked structure comprises an antenna array panel which comprises an antenna patch layer, a gap layer, a coupling feeder line layer, a feeder line reference ground layer and a common reference ground layer which are stacked from top to bottom; the multifunctional board is located below the antenna array panel, and the multifunctional board and the antenna array panel are integrally pressed to form a single PCB; the multifunctional board comprises a power supply network layer, a control network layer, a multi-beam network layer and a T component SIP layer which are stacked from top to bottom; the multi-beam network layer comprises at least two reference ground layers and at least two multi-beam network sub-layers which are alternately stacked; the public reference ground layer and the power supply network layer are directly adjacent up and down; the T assembly SIP layer comprises a fifth reference ground layer and a bottom device layer located below the fifth reference ground layer, and the bottom device layer is the bottom surface of the PCB. The size and the weight of equipment are greatly reduced, and the high-frequency performance and the whole machine stability are improved.

Description

Technical Field

[0001] This invention relates to the field of satellite communication equipment technology, and in particular to a phased array integrated printed circuit board stack-up structure and manufacturing method. Background Technology

[0002] In the field of wireless communication equipment, phased array antennas are widely used in various long-distance signal transmission scenarios due to their flexible beam pointing capabilities. Currently, such devices are typically implemented using a discrete architecture design, where the antenna array panel required for signal radiation and the multi-functional board for signal processing and power amplification are separate printed circuit boards. The two boards are interconnected via RF connectors, power connectors, and digital connectors to achieve signal and energy exchange. While this discrete design can meet basic functional requirements, it has significant shortcomings in high-frequency signal transmission scenarios: Firstly, the presence of connectors introduces additional signal loss and parasitic parameters, especially at high frequencies, where signal integrity is easily affected, and the reliability of connector contacts also reduces the overall stability of the device; secondly, assembling the two separate circuit boards requires additional structural space, increasing not only the size and weight of the device but also the assembly complexity and cost.

[0003] To address these issues, the industry has gradually developed integrated architectures, integrating antenna arrays and some functional circuits onto a single printed circuit board (PCB), reducing the use of connectors. However, while some existing integrated solutions achieve integration, they employ multi-batch lamination processes. Excessive lamination steps significantly reduce PCB manufacturing yield, increasing production cycles and costs. Other solutions, to ensure high-frequency performance, utilize special interlayer interconnect structures, requiring customized production equipment and becoming incompatible with traditional PCB production lines, leading to significant mass production difficulties and high manufacturing costs. Furthermore, the layer stack design of existing integrated solutions fails to adequately consider the shielding requirements of high-frequency signals, leaving interlayer crosstalk and electromagnetic interference issues prominent, impacting equipment performance stability. Summary of the Invention

[0004] Therefore, it is necessary to provide a phased array integrated printed circuit board stack-up structure and manufacturing method that can achieve a high degree of integration between the antenna array and functional circuits and stable high-frequency performance, in response to the above-mentioned technical problems.

[0005] A phased array integrated printed circuit board stack-up structure includes:

[0006] An antenna array panel, the antenna array panel comprising, from top to bottom, an antenna patch layer, a slot layer, a coupling feed line layer, a feed line reference ground layer and a common reference ground layer; A multi-functional board is located below the antenna array panel, and the two are integrally pressed together to form a single PCB. The multi-functional board includes a power network layer, a control network layer, a multi-beam network layer, and a T-component SIP layer stacked from top to bottom; The multibeam network layer includes at least two reference ground layers and at least two multibeam network sublayers that are alternately stacked. The common reference ground layer and the power network layer are directly adjacent to each other vertically. The T-component SIP layer includes a fifth reference ground layer and a bottom device layer located below it, the bottom device layer being the bottom surface of the PCB.

[0007] On the other hand, a method for making a plate is also provided, the method comprising: The coupling feed layer, feed reference ground layer and common reference ground layer in the antenna array panel are first pressed together to form the first antenna sub-assembly; at the same time, the multi-beam network layer in the multi-function board is first pressed together to form the first multi-function sub-assembly. The antenna patch layer and the slot layer are pressed together with the first antenna sub-assembly for a second time to form an antenna array panel prefabricated board; at the same time, the power network layer, the control network layer, the T component SIP layer are pressed together with the first multifunctional sub-assembly for a second time to form a multifunctional board prefabricated board. A vertical conductive structure is formed between the common reference ground layer of the antenna array panel prefabricated plate and the power network layer of the multifunctional panel prefabricated plate to achieve electrical connection between the two. The antenna array panel prefabricated board and the multi-functional board prefabricated board are aligned and stacked, and then pressed together for the third time to form a single PCB.

[0008] Compared with existing technologies, the phased array integrated printed circuit board stack-up structure and manufacturing method provided by this invention have the following advantages: 1. By integrating the antenna array panel and the multi-functional board into a single PCB, with the common reference ground layer and the power network layer directly adjacent to each other, the traditional discrete architecture that requires RF connectors, power connectors, and digital connectors for interconnection is completely eliminated. This structural design avoids insertion loss, parasitic capacitance, and parasitic inductance caused by connectors, making it particularly suitable for high-frequency scenarios such as the KA band, significantly improving signal transmission integrity. Simultaneously, it eliminates reliability issues caused by poor connector contact, enhancing the long-term stability of the equipment under harsh environments such as vibration and temperature cycling.

[0009] 2. By integrating the antenna array panel and the multi-functional board into a single PCB, with the bottom component layer directly serving as the bottom surface of the PCB, there is no need for an additional independent substrate or shell for the multi-functional board, resulting in a more compact structure. Compared to the traditional solution of two separate circuit boards plus connectors, this invention effectively reduces the module's longitudinal dimensions and overall projected area, lightens the weight, and simplifies the assembly process. It eliminates the need for alignment, locking, and connector soldering between the two boards, thereby reducing manufacturing costs and production cycle.

[0010] 3. The multi-beam network layer comprises at least two alternately stacked reference ground layers and at least two multi-beam network sublayers. This alternating "ground, signal, ground, signal" structure ensures that each multi-beam network sublayer is surrounded by upper and lower reference ground layers, forming a natural electromagnetic shielding cavity. This significantly reduces crosstalk between different beam signals and the coupling of external interference. Simultaneously, the common reference ground layer and the power network layer are directly adjacent, providing a low-impedance return path for the power network and further suppressing power supply noise interference with RF signals. These design features collectively ensure the purity of high-frequency signal transmission within the multilayer board, resolving the prominent inter-layer interference problem in existing integration solutions.

[0011] In the 4.T component SIP layer, the bottom device layer serves as the external interface and heat dissipation interface. On the one hand, this shortens the interconnection path between the chip and the antenna, further reducing transmission loss. On the other hand, the bottom device layer is directly exposed on the bottom surface of the PCB, making it easy to attach to the heat sink and improving the heat dissipation performance of the high-power transmitting component. At the same time, compared with the AIP architecture that completely embeds the chip in the inner layer, the bottom device layer of this invention has an accessible design, making chip-level repair and testing more convenient, and improving testability and maintainability.

[0012] 5. The stacked structure designed in this invention has clear layers and well-defined functional zones. This structure does not require the introduction of overly complex irregular layers or special materials, and can be achieved using conventional high-frequency boards and FR4 mixed-pressing processes. Furthermore, through reasonable layer sequence design, the total number of pressing operations can be controlled within a small range, thus making it compatible with traditional printed circuit board production lines. It does not require customized equipment, significantly improving manufacturing yield and reducing mass production thresholds and production costs. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention, and those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0014] Figure 1 This is a simplified schematic diagram of the integrated printed circuit board stack-up structure of the phased array in Example 1; Figure 2 This is a detailed schematic diagram of the integrated phased array printed circuit board stack-up structure and lamination in Example 1; Figure 3 This is a flowchart illustrating the board-making method in Example 2.

[0015] Explanation of reference numerals in the attached figures: Antenna array panel 100, antenna patch layer 110, slot layer 120, coupling feed layer 130, feed reference ground layer 140, common reference ground layer 150, multifunction board 200, power network layer 210, control network layer 220, multi-beam network layer 230, first reference ground layer 231, first multi-beam network sublayer 232, second reference ground layer 233, second multi-beam network sublayer 234, third reference ground layer 235, third multi-beam network sublayer 236, Fourth Reference Ground Layer 237, Fourth Multibeam Network Sublayer 238, T-Component SIP Layer 240, Fifth Reference Ground Layer 241, Bottom Device Layer 242, First Blind Via S1, Second Blind Via S2, Buried Via S3, First Through Via S4, Second Through Via S5, Third Through Via S6, First Back Drilled Hole S7-1, Second Back Drilled Hole S7-2, Third Back Drilled Hole S7-3, Fourth Back Drilled Hole S7-4, Fifth Back Drilled Hole S7-5, Copper Paste Sintered Structure S8.

[0016] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0019] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0020] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection, an electrical connection, a physical connection, or a wireless communication connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two elements or the interaction between two elements, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] It is understood that the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] Example 1 like Figure 1 and Figure 2 As shown, this embodiment provides an integrated phased array printed circuit board stack-up structure, including: an antenna array panel 100 and a multi-functional board 200 located below the antenna array panel 100, which are integrally pressed together to form a single PCB.

[0024] Specifically, the antenna array panel 100 includes, from top to bottom, an antenna patch layer 110, a slot layer 120, a coupling feed line layer 130, a feed line reference ground layer 140, and a common reference ground layer 150. The antenna patch layer 110 is the top layer (TOP layer) of the PCB board, on which the antenna array is mounted for radiating or receiving KA-band radio frequency signals. The slot layer 120 and the coupling feed line layer 130 together form an electromagnetic coupling structure, enabling effective signal excitation from the feed line to the patch. The feed line reference ground layer 140 provides a precise impedance reference for the coupling feed line. The common reference ground layer 150 serves as the bottom reference of the antenna array panel 100 and is also a key interface connecting to the underlying multi-function board 200.

[0025] The multi-function board 200 includes, from top to bottom, a power network layer 210, a control network layer 220, a multi-beam network layer 230, and a T-component SIP layer 240. The power network layer 210 provides a stable DC power distribution for the entire PCB. The control network layer 220 is responsible for transmitting digital logic signals such as beam control and status monitoring.

[0026] The multibeam network layer 230 includes at least two alternately stacked reference ground layers and at least two multibeam network sublayers. In this embodiment, as... Figure 2 As shown, the multi-beam network layer 230 specifically includes, from top to bottom, a first reference ground layer 231, a first multi-beam network sublayer 232, a second reference ground layer 233, a second multi-beam network sublayer 234, a third reference ground layer 235, a third multi-beam network sublayer 236, a fourth reference ground layer 237, and a fourth multi-beam network sublayer 238. This alternating stacking structure of "ground, signal, ground, signal" ensures that each multi-beam network sublayer is tightly surrounded by the upper and lower reference ground layers, forming a natural stripline-like structure. This provides an excellent electromagnetic shielding environment for multi-beam signals and effectively suppresses inter-layer crosstalk. Specifically, the first multi-beam network sublayer 232, the second multi-beam network sublayer 234, the third multi-beam network sublayer 236, and the fourth multi-beam network sublayer 238 are used to transmit four different beam signals, realizing the four-beam phased array function.

[0027] The common reference ground plane 150 and the power network plane 210 are directly adjacent to each other. This design provides the shortest and lowest impedance return path for the power network. At high frequencies, power integrity issues directly affect RF signal quality. The close proximity of the common reference ground plane and the power plane creates a strong coupling capacitance, greatly suppressing power noise and providing an extremely stable reference plane for the underlying RF circuitry.

[0028] The T-component SIP layer 240 includes a fifth reference ground layer 241 and a bottom device layer 242 located below it, the bottom device layer 242 being the bottom surface of the PCB. The fifth reference ground layer 241 provides shielding for the bottom of the multi-beam network layer 230 and serves as a reference for the bottom device layer 242. The bottom device layer 242 (i.e., the BOTTOM layer of the PCB) houses at least one of the following: a multi-function chip, a power amplifier chip, a power chip, passive components, connectors, multi-beam network signal lines, digital signal lines, and power signal lines. This "sandwich" layout of top antenna and bottom device results in extremely short interconnection paths between the chip and the antenna, while the bottom device can be directly mounted on a heat sink, achieving excellent heat dissipation performance. Compared to the AIP architecture where the chip is completely embedded, the bottom devices in this structure are all accessible, greatly improving testability and maintainability. To achieve electrical interconnection between layers, this stack-up structure also integrates various types of via structures.

[0029] In terms of vertical interconnection, the antenna array panel 100 also includes a first blind via S1. The first blind via S1 penetrates the dielectric layer between the feed reference ground layer 140 and the common reference ground layer 150 to conduct power between the feed reference ground layer 140 and the common reference ground layer 150. The first blind via S1 is used to transmit multi-beam feed signals, and its aperture size is obtained through simulation optimization, taking into account both high-frequency performance and conventional process capabilities. It is preferably made using a PCB industry-standard 8-mil drilling aperture.

[0030] The antenna array panel 100 also includes a second blind aperture S2. The second blind aperture S2 penetrates the coupling feed layer 130, the feed reference ground layer 140, and the common reference ground layer 150 to conduct power through them. As a shielding ground hole for the multi-beam feed signal, the second blind aperture S2 is a key design element for ensuring the performance of the multi-beam feed signal and suppressing electromagnetic interference. During the design process, the aperture spacing, layout position, physical dimensions, and integrity must be strictly controlled. It works in conjunction with the first blind aperture S1 to form a near-coaxial structure, ensuring signal integrity. The thickness-to-aperture ratio of the second blind aperture S2 must be strictly controlled to within 6:1 to ensure process reliability. Furthermore, to ensure that the signal lines in each multi-beam network sublayer can be completely grounded, these multi-beam signal lines need to be routed overlapping in each layer in the vertical projection direction.

[0031] The multi-functional board 200 also includes buried vias S3. The buried vias S3 penetrate at least two reference ground layers and at least two multi-beam network sub-layers in the multi-beam network layer 230. In this embodiment, the buried vias S3 penetrate from the first reference ground layer 231 to the fourth multi-beam network sub-layer 238, serving as accompanying ground vias for the multi-beam network signals. This ensures that each layer of multi-beam signal lines is completely surrounded by ground vias in the vertical direction, achieving three-dimensional grounding shielding. A 10 mil borehole diameter is preferably used.

[0032] In terms of interconnection, the antenna array panel 100 also includes a first through-hole S4 and a first back-drilled hole S7-1. The first through-hole S4 penetrates the antenna patch layer 110, the slot layer 120, the coupling feed layer 130, the feed reference ground layer 140, and the common reference ground layer 150, serving as a shielding ground hole for the antenna array. The first back-drilled hole S7-1 is formed by back-drilling from below the common reference ground layer 150 based on the first through-hole S4, used to remove the remnant of the first through-hole S4 extending downward from the common reference ground layer 150. It can be understood that the first through-hole S4 is a shielding ground hole for the antenna array, ensuring that the board thickness to hole diameter ratio is 6:1. The shielding ground holes of the antenna array are a key design for ensuring antenna performance and suppressing electromagnetic interference. During the design process, the hole spacing, layout position, physical dimensions, and integrity all need to be strictly controlled.

[0033] It is understandable that this residual segment would create unnecessary parasitic capacitance and inductance. The drilled size of the via is closely related to the parasitic capacitance and inductance introduced by the via. Therefore, removing them through back-drilling can effectively reduce the impact on the performance of the high-frequency antenna. The size of the first back-drilled hole S7-1 was optimized based on the parasitic parameter simulation formula: parasitic capacitance C = 1.41T. D1 / (D2-D1), where ε is the dielectric constant of the substrate material, T1 is the thickness of the PCB board, D1 is the diameter of the PCB via pad, and D2 is the diameter of the solder mask opening on the PCB via layer. From the formula, it can be seen that the parasitic capacitance of PCB vias mainly affects the circuit by prolonging the signal rise time and reducing the circuit speed, especially in high-frequency circuits where the impact is more severe.

[0034] The parasitic inductance L = 5.05H [In(4H / d) + 1], where H is the length of the PCB via and d is the diameter of the center hole. From the formula, it can be seen that the PCB via pads have a relatively small impact on the parasitic inductance, while the length of the PCB via has a significant impact.

[0035] As shown in the formula above, the size of the drill hole directly changes the parasitic parameters, thus affecting circuit performance. The first back-drilled hole S7-1 preferably uses a 12-mil drill hole diameter.

[0036] The multi-function board 200 also includes a second through-hole S5, a second back-drilled hole S7-2, a third back-drilled hole S7-3, a fourth back-drilled hole S7-4, and a fifth back-drilled hole S7-5. The second through-hole S5 penetrates the power network layer 210, the control network layer 220, the multi-beam network layer 230, and the T-component SIP layer 240, and is used to connect the power network, the digital signal network, and provide a common ground. The second back-drilled hole S7-2 conducts the first multi-beam network sublayer 232 to the bottom device layer 242; the third back-drilled hole S7-3 conducts the second multi-beam network sublayer 234 to the bottom device layer 242; the fourth back-drilled hole S7-4 conducts the third multi-beam network sublayer 236 to the bottom device layer 242; and the fifth back-drilled hole S7-5 conducts the fourth multi-beam network sublayer 238 to the bottom device layer 242. This series of stepped back-drilled vias (S7-2 to S7-5) vertically guides signals from multi-beam network sublayers at different depths to the bottom device layer 242, while eliminating the residual segments generated by vias at unnecessary connections between layers, ensuring low-loss, high-fidelity transmission of multi-beam signals from the inner layer to the bottom chip. Preferably, the second via S5, the second back-drilled via S7-2, the third back-drilled via S7-3, the fourth back-drilled via S7-4, the fifth back-drilled via S7-5, and the second via S5 use a 12 mil drilling diameter to meet the board thickness to hole diameter ratio of 6:1, and are used to connect the power supply network, the digital signal network, and the shielding ground via; the second back-drilled via S7-2, the third back-drilled via S7-3, the fourth back-drilled via S7-4, and the fifth back-drilled via S7-5 all use a 12 mil drilling diameter, and the drilling design dimensions are calculated in the same way as the first back-drilled via S7-1.

[0037] In terms of overall interconnection, the stack-up structure also includes a third via S6. The third via S6 penetrates all layers from the antenna patch layer 110 to the bottom device layer 242, serving to connect the antenna patch layer 110, slot layer 120, coupling feed layer 130, feed reference ground layer 140, common reference ground layer 150, power network layer 210, control network layer 220, first reference ground layer 231, first multi-beam network sub-layer 232, second reference ground layer 233, second multi-beam network sub-layer 234, third reference ground layer 235, third multi-beam network sub-layer 236, fourth reference ground layer 237, fourth multi-beam network sub-layer 238, fifth reference ground layer 241, and bottom device layer 242, thus connecting the common ground network of the entire PCB and providing a unified, low-impedance ground potential reference for all circuits. Preferably, the third via S6 uses a 20 mil drill hole diameter.

[0038] Finally, regarding interlayer connections: the common reference ground layer 150 and the power network layer 210 are electrically connected via a copper paste sintering structure S8. Specifically, copper paste is screen-printed onto the area to be connected in the common reference ground layer 150, pre-cured, and aligned with the power network layer 210. Pressure sintering is then performed under high temperature (above 300°C) and inert gas protection. After the paste has initially cured, the power network layer 210 and the common reference ground layer 150 are aligned and stacked, then press-fitted for pressure sintering. Under heat and pressure, the copper paste and pads fuse and diffuse to form dense, pure copper connection points. Compared to traditional mechanical drilling or conductive adhesive, this sintering connection has lower contact resistance and higher current carrying capacity, ensuring reliable power and ground connectivity between the antenna array panel and the multi-functional board.

[0039] This invention, through the aforementioned integrated layered structure and accompanying via design, completely eliminates the RF connectors and power connectors between the antenna panel and the multi-function board in traditional phased array antennas, thus eliminating insertion loss, parasitic effects, and reliability risks associated with connectors. Simultaneously, through an alternating "ground, signal, ground, signal" beam network layer structure, tightly coupled power and ground planes, and stepped back-drilling technology, it effectively solves the problems of electromagnetic interference, signal crosstalk, and signal integrity at high frequencies. Furthermore, the bottom component layer design makes heat dissipation and maintainability far superior to AIP architectures. Overall, this structure achieves high performance, high integration, high reliability, and manufacturability for KA-band phased array antennas.

[0040] Example 2 Based on the integrated printed circuit board stack-up structure of phased array in Embodiment 1, this embodiment discloses a board manufacturing method, such as... Figure 3 As shown, the board-making method includes the following steps: Step 1: The coupling feeder layer, feeder reference ground layer and common reference ground layer in the antenna array panel are first pressed together to form the first antenna sub-assembly; at the same time, the multi-beam network layer in the multi-function board is first pressed together to form the first multi-function sub-assembly.

[0041] It is understandable that this step involves pre-pressing the core RF multilayer structure of the antenna array panel and the multi-function board separately. The antenna section first presses the bottom three layers, namely the coupling feed layer and below; the multi-beam network section first presses all eight sublayers, as well as the first reference ground layer to the fourth multi-beam network sublayer.

[0042] In the specific implementation of step 1, firstly, the core boards and prepregs required for each layer are prepared. For the antenna subassembly, a first blind via with a diameter of 8 mil is drilled at the designed position on the core board of the feed reference ground layer and the common reference ground layer, and the via is filled with electroplating to achieve conductivity. Then, the coupling feed layer, the feed reference ground layer, and the common reference ground layer are stacked and subjected to the first pressing under high temperature and high pressure. After pressing, a second blind via with a diameter of 10 mil is drilled from the surface of the coupling feed layer to ensure that the board thickness-to-diameter ratio meets 6:1, and the three layers are electroplated to conduction. At the same time, for the multi-functional subassembly, eight layers from the first reference ground layer to the fourth multi-beam network subassembly are stacked, pressed, and buried vias with a diameter of 10 mil are drilled, the board thickness-to-diameter ratio is 6:1, and all these inner layers are electroplated to conduction.

[0043] This step, by dividing the complex multi-layer structure into two independent sub-components for pre-pressing, allows for controllable pressing layers in each sub-component, reducing the complexity of a single pressing process. In particular, the introduction of buried vias (S3) enables fully shielded vertical interconnection within the multi-beam network layer, laying the foundation for subsequent high-density wiring.

[0044] Step 2: The antenna patch layer, the slot layer and the first antenna sub-assembly are pressed together for the second time to form the antenna array panel prefabricated board; at the same time, the power network layer, the control network layer, the T component SIP layer and the first multi-functional sub-assembly are pressed together for the second time to form the multi-functional board prefabricated board.

[0045] As can be understood, this step involves adding the remaining layers to each of the two sub-components to complete the prefabrication of the full structure of their respective panels. An upper radiating element layer is added to the antenna side, while an upper power control layer and a lower T-component layer are added to the multi-function board side.

[0046] In the specific implementation of step 2, for the antenna array panel, the antenna patch layer, the slot layer, and the first antenna sub-assembly formed in step 1 are accurately stacked and then pressed together a second time. After pressing, the first through-hole and the first back-drill hole are drilled. The through-hole is drilled first to connect all antenna layers, and then back-drilling is performed from the lower surface of the common reference ground layer, with precise control of the back-drilling depth to remove the remaining sections of the through-hole below the common reference ground layer. For the multi-function board, the power network layer, the control network layer, the T-component SIP layer, and the first multi-function sub-assembly formed in step 1 are stacked and then pressed together a second time. After pressing, the second through-hole and the second to fifth back-drill holes are drilled. The through-hole is drilled first to penetrate the entire multi-function board prefabrication plate, and then, according to the different depths of each multi-beam sub-layer, a stepped back-drilling is performed from the bottom device layer side to remove the remaining sections of the through-hole after reaching each target layer. For example, the back-drilling depth of the second back-drill hole ends at the first multi-beam network sub-layer, and so on until all are completed.

[0047] This step, through the uniform through-hole and stepped back-drilling after the second lamination, not only ensures reliable connections between layers but also completely eliminates the parasitic effects caused by high-frequency signal via fragments through precise back-drilling technology. This is a key process for ensuring KA-band signal quality. The shielding ground hole array of the antenna array and the stepped exit holes of the multi-beam network are both completed in this step.

[0048] Step 3: A vertical conductive structure is formed between the common reference ground layer of the antenna array panel prefabricated plate and the power network layer of the multi-functional panel prefabricated plate to achieve electrical connection between the two.

[0049] This step involves joining two separate prefabricated panels together using a special conductive bonding process, rather than the traditional pressing and drilling method. The copper paste sintering process used achieves a reliable connection with low resistance and a high melting point.

[0050] In the specific implementation of step 3, the lower surface of the common reference ground layer of the antenna array panel prefabricated board and the upper surface of the power network layer of the multi-functional board prefabricated board are first surface-treated to remove the oxide layer, such as through micro-etching. Then, a layer of special copper paste is coated in the predetermined connection area of ​​the common reference ground layer using a screen printing process. The prefabricated board coated with copper paste is placed in a reflow oven under inert gas protection for preheating, allowing the solvent in the copper paste to evaporate and the resin to initially cure. Next, the two prefabricated boards are aligned and stacked, and placed in a vacuum press, where a certain pressure is applied at a high temperature above 300°C for sintering. Under the combined action of heat and pressure, the copper particles in the copper paste diffuse and fuse with the copper pads on both sides, ultimately forming a dense, pure copper vertical conductive structure.

[0051] This step differs from the traditional mechanical drilling and electroplating process; instead, it employs a copper paste sintering process to achieve a vertical connection between two thick plates. This not only avoids a series of technological challenges associated with drilling deep holes in two already patterned and perforated thick plates, such as alignment accuracy, hole wall roughness, and electroplating depth, but also results in a pure copper connection point with extremely low resistance and excellent thermal conductivity, providing a high-quality through path for power and ground. The completion of this step signifies the initial electrical integration of the antenna array panel and the multi-functional board.

[0052] Step 4: Align and stack the antenna array panel prefabricated board and the multi-functional board prefabricated board, and perform a third pressing to form a single PCB.

[0053] It is understandable that this step is the final overall bonding step, which permanently solidifies the two prefabricated boards that have been connected by sintering points into a complete PCB.

[0054] In step 4, a high-flow-rate prepreg is filled between the antenna array panel prefabricated board and the multi-functional board prefabricated board, which have been initially aligned and connected through copper paste sintering, to ensure that the gap is filled and firmly bonded during lamination. Then, the entire stack is placed in a large press for the third and final lamination. After lamination, a third through-hole with a diameter of 20 mil is drilled from the top layer of the entire board, i.e., the antenna patch layer. This through-hole penetrates all layers and is then electroplated. This third through-hole serves as the common ground hole for the entire board, connecting the common ground network of the entire PCB to form a complete, low-impedance ground plane. Finally, conventional PCB post-processing steps such as outer layer patterning, solder masking, and surface treatment are performed. Components such as the multi-functional chip and power amplifier chip are then assembled on the bottom component layer, ultimately resulting in a complete phased array integrated PCB.

[0055] This step, by strictly controlling the total number of laminations to no more than three, significantly reduces reliability risks such as layer misalignment, voids, and delamination caused by multiple high-temperature and high-pressure processes, compared to complex integration solutions requiring four to six or even more laminations. This significantly improves manufacturing yield. Simultaneously, the final drilled third through-hole ensures the integrity of the entire board. The entire board manufacturing method is based entirely on traditional mainstream PCB processes, requiring no special or customized expensive equipment, and offers excellent mass production economics and process compatibility.

[0056] It should be understood that, although this embodiment Figure 3 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A phased array integrated printed circuit board stack-up structure, characterized in that, include: The antenna array panel (100) includes an antenna patch layer (110), a slot layer (120), a coupling feed layer (130), a feed reference ground layer (140), and a common reference ground layer (150) stacked from top to bottom. A multi-functional board (200) is located below the antenna array panel (100), and the two are integrally pressed together to form a single PCB. The multifunctional board (200) includes a power network layer (210), a control network layer (220), a multi-beam network layer (230), and a T-component SIP layer (240) stacked from top to bottom. The multibeam network layer (230) includes at least two reference ground layers and at least two multibeam network sublayers that are alternately stacked; The common reference ground layer (150) and the power network layer (210) are directly adjacent to each other vertically; The T component SIP layer (240) includes a fifth reference ground layer (241) and a bottom device layer (242) located below it, the bottom device layer (242) being the bottom surface of the PCB.

2. The integrated phased array printed circuit board stack-up structure according to claim 1, characterized in that, The multibeam network layer (230) includes, from top to bottom, a first reference ground layer (231), a first multibeam network sublayer (232), a second reference ground layer (233), a second multibeam network sublayer (234), a third reference ground layer (235), a third multibeam network sublayer (236), a fourth reference ground layer (237), and a fourth multibeam network sublayer (238); The fifth reference stratum (241) is located below the fourth multibeam network sublayer (238).

3. The integrated phased array printed circuit board stack-up structure according to claim 2, characterized in that, The first multi-beam network sublayer (232), the second multi-beam network sublayer (234), the third multi-beam network sublayer (236), and the fourth multi-beam network sublayer (238) are used to transmit four different beam signals, respectively.

4. The integrated phased array printed circuit board stack-up structure according to claim 1, characterized in that, The common reference ground layer (150) and the power network layer (210) are electrically connected through a copper paste sintering structure (S8).

5. The phased array integrated printed circuit board stack-up structure according to any one of claims 1 to 4, characterized in that, The antenna array panel (100) further includes a first blind hole (S1) that penetrates the dielectric layer between the feed reference ground layer (140) and the common reference ground layer (150) to conduct the feed reference ground layer (140) and the common reference ground layer (150).

6. The phased array integrated printed circuit board stack-up structure according to claim 5, characterized in that, The antenna array panel (100) further includes a second blind hole (S2) that penetrates the coupling feed layer (130), the feed reference ground layer (140), and the common reference ground layer (150) to conduct the coupling feed layer (130), the feed reference ground layer (140), and the common reference ground layer (150).

7. The integrated printed circuit board stack-up structure of phased array according to claim 6, characterized in that, The antenna array panel (100) also includes a first through hole (S4) and a first back drill hole (S7-1). The first via (S4) penetrates the antenna patch layer (110), the slot layer (120), the coupling feed layer (130), the feed reference ground layer (140), and the common reference ground layer (150). The first back-drilled hole (S7-1) is formed by back-drilling from below the common reference formation (150) based on the first through hole (S4), and is used to remove the remnant of the first through hole (S4) extending downward from the common reference formation (150).

8. The phased array integrated printed circuit board stack-up structure according to claim 2 or 3, characterized in that, The multifunctional board (200) also includes a buried via (S3) that penetrates at least two reference ground layers and at least two multibeam network sublayers in the multibeam network layer (230).

9. The phased array integrated printed circuit board stack-up structure according to claim 8, characterized in that, The multifunctional board (200) also includes a second through hole (S5), a second back drill hole (S7-2), a third back drill hole (S7-3), a fourth back drill hole (S7-4), and a fifth back drill hole (S7-5). The second via (S5) penetrates the power network layer (210), control network layer (220), multibeam network layer (230) and T component SIP layer (240). The first multi-beam network sublayer (232) is connected to the bottom device layer (242) through the second back-drilled hole (S7-2). The second multi-beam network sublayer (234) is connected to the bottom device layer (242) through the third back-drilled hole (S7-3). The third multi-beam network sublayer (236) is connected to the bottom device layer (242) through the fourth back-drilled hole (S7-4). The fourth multi-beam network sublayer (238) is connected to the bottom device layer (242) through the fifth back-drilled hole (S7-5).

10. A method for making a plate, characterized in that, The method includes: The coupling feed layer, feed reference ground layer and common reference ground layer in the antenna array panel are first pressed together to form the first antenna sub-assembly; at the same time, the multi-beam network layer in the multi-function board is first pressed together to form the first multi-function sub-assembly. The antenna patch layer and the slot layer are pressed together with the first antenna sub-assembly for a second time to form an antenna array panel prefabricated board; at the same time, the power network layer, the control network layer, the T component SIP layer are pressed together with the first multifunctional sub-assembly for a second time to form a multifunctional board prefabricated board. A vertical conductive structure is formed between the common reference ground layer of the antenna array panel prefabricated plate and the power network layer of the multifunctional panel prefabricated plate to achieve electrical connection between the two. The antenna array panel prefabricated board and the multi-functional board prefabricated board are aligned and stacked, and then pressed together for the third time to form a single PCB.

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