Semiconductor power device and forming method thereof

Abstract

The invention provides a semiconductor power device and a forming method thereof, and the semiconductor power device comprises a nucleating layer which is formed on a substrate; a buffer layer formed on the nucleating layer; the dislocation regulation and control layer is formed on the buffer layer, the dislocation regulation and control layer comprises at least two stacked high-resistance layers and lattice mismatch layers formed between the two adjacent high-resistance layers, and the lattice mismatch layers and the high-resistance layers located on the lattice mismatch layers both have blade type dislocation. As the lattice mismatch layer and the high-resistance layer located on the lattice mismatch layer both have edge-type dislocation, continuously distributed hole traps can be induced to be formed around the lattice mismatch layer and coupled with original traps in the buffer layer, a channel for hole transmission can be formed, hole redistribution can be realized through the channel, and the hole transmission efficiency is improved. The electron accumulation in the buffer layer can be effectively relieved, so that the dynamic performance degradation of the device is inhibited.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor power device and a method for forming the same. Background Technology

[0002] Dynamic on-resistance is a key parameter for evaluating the performance of gallium nitride (GaN) power devices in practical power supply applications. An increase in its value directly leads to additional conduction losses, thus affecting the conversion efficiency, temperature rise control, and long-term operational reliability of the entire power system. When the device is in high-frequency switching operation, the degradation of dynamic on-resistance is mainly due to the charge trapping effect in the epitaxial layer. Specifically, numerous defects in the device structure (including surface states, interface states, and the buffer layer) trap or release charge carriers during switching, creating dynamic electrostatic modulation of the channel, causing the on-resistance to increase with the number of switching cycles or stress time. Therefore, it is necessary to reduce the degradation of dynamic on-resistance to effectively suppress the dynamic performance degradation of the device. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor power device and a method for forming the same, so as to suppress the dynamic performance degradation of the device.

[0004] To achieve the above objectives, the present invention provides a semiconductor power device, comprising:

[0005] Substrate;

[0006] A nucleation layer is formed on the substrate;

[0007] A buffer layer is formed on the nucleation layer;

[0008] A dislocation control layer is formed on the buffer layer. The dislocation control layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer have edge dislocations.

[0009] Optionally, in the semiconductor power device, the material of the lattice mismatch layer is Al. x Ga 1-x N or In x Ga 1-x N, where 0.1 <x≤1。

[0010] Optionally, in the semiconductor power device, in the dislocation control layer, the number of high-resistivity layers is n, and the number of lattice mismatch layers is n-1, where 2≤n≤6, and n is an integer.

[0011] Optionally, in the semiconductor power device, the high-resistivity layer is made of carbon-doped gallium nitride.

[0012] Optionally, in the semiconductor power device, the semiconductor power device further includes:

[0013] A channel layer is formed on the dislocation control layer;

[0014] A barrier layer is formed on the channel layer;

[0015] A cap layer is formed on the barrier layer.

[0016] Based on the same inventive concept, the present invention also provides a method for forming a semiconductor power device, comprising:

[0017] Provide substrate;

[0018] A nucleation layer is formed on the substrate;

[0019] A buffer layer is formed on the nucleation layer;

[0020] A dislocation control layer is formed on the buffer layer. The dislocation control layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer have edge dislocations.

[0021] Optionally, in the method for forming the semiconductor power device, the material of the lattice mismatch layer is Al. x Ga 1-x N or In x Ga 1-x N, where 0.1 <x≤1。

[0022] Optionally, in the method for forming the semiconductor power device, in the dislocation control layer, the number of high-resistivity layers is n, and the number of lattice mismatch layers is n-1, where 2≤n≤6, and n is an integer.

[0023] Optionally, in the method for forming the semiconductor power device, the lattice mismatch layer is formed at a temperature of 600°C-900°C.

[0024] Optionally, in the method for forming the semiconductor power device, after forming the dislocation modulation layer, the method further includes:

[0025] A channel layer is formed on the dislocation control layer;

[0026] A barrier layer is formed on the channel layer;

[0027] A cap layer is formed on the barrier layer.

[0028] In the semiconductor power device and its formation method provided by the present invention, the semiconductor power device includes: a nucleation layer formed on a substrate; a buffer layer formed on the nucleation layer; and a dislocation modulation layer formed on the buffer layer. The dislocation modulation layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer contain edge dislocations. Since both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer contain edge dislocations, continuously distributed hole traps can be induced around them and coupled with the original traps in the buffer layer to form a channel for hole transport (i.e., a hole channel). Through this channel, hole redistribution can be achieved, effectively alleviating electron accumulation in the buffer layer and thus suppressing the dynamic performance degradation of the device. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of a semiconductor power device provided in an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of the structure of a semiconductor power device provided in another embodiment of the present invention.

[0031] Figure 3 This is a schematic flowchart of a method for forming a semiconductor power device provided in an embodiment of the present invention.

[0032] Figures 4 to 6 This is a schematic diagram of the structure formed in the method for forming a semiconductor power device provided in an embodiment of the present invention.

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 100 - Substrate; 110 - Nucleation layer; 120 - Buffer layer; 130 - Dislocation control layer; 131 - First high-resistivity layer; 132 - First lattice mismatch layer; 133 - Second high-resistivity layer; 134 - Second lattice mismatch layer; 135 - Third high-resistivity layer; 140 - Channel layer; 150 - Barrier layer; 160 - Cap layer. Detailed Implementation

[0035] The semiconductor power device and its formation method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may have different emphases and sometimes use different scales.

[0036] Figure 1 is a schematic structural diagram of a semiconductor power device provided by an embodiment of the present invention. As Figure 1 shown, the semiconductor power device provided in this embodiment includes a substrate 100, and a nucleation layer 110, a buffer layer 120, and a dislocation control layer 130 sequentially formed on the substrate 100.

[0037] In this embodiment, the substrate 100 may be a silicon substrate 100, and the crystal orientation of the substrate 100 is <111>.

[0038] As Figure 1 shown, the nucleation layer 110 is formed on the substrate 100. The material of the nucleation layer 110 may be aluminum nitride (AlN), which can act as a wetting layer and provide pre-compressive stress. Among them, the thickness of the nucleation layer 110 may be 100 nm to 250 nm.

[0039] As Figure 1 shown, the buffer layer 120 is formed on the nucleation layer 110, and the buffer layer 120 may cover the top surface of the nucleation layer 110. Among them, the buffer layer 120 is used to store compressive stress to compensate for the tensile stress suffered by the dislocation control layer 130 during the cooling process of the device.

[0040] In some embodiments, the material of the buffer layer 120 may include AlN and / or AlGaN.

[0041] In some embodiments, the buffer layer 120 may be a superlattice structure in which Al(Ga)N layers and AlGaN layers are alternately stacked.

[0042] In a further solution, the buffer layer 120 includes a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer stacked in sequence from bottom to top to store compressive stress, so as to better compensate for the tensile stress suffered by the dislocation control layer 130 during the cooling process of the device. Specifically, the material of the first buffer layer may be Al x Ga 1-x N, where 0.6 < x < 0.8; the material of the second buffer layer may be Al x Ga 1-x N, where 0.4 < x < 0.6; the material of the third buffer layer may be Al x Ga 1-x N, where 0.2 < x < 0.4; the material of the fourth buffer layer may be Al x Ga 1-xN, where 0.1 < x < 0.3. The thickness of the first buffer layer can be 100 nm to 300 nm; the thickness of the second buffer layer can be 100 nm to 600 nm; the thickness of the third buffer layer can be 100 nm to 800 nm; the thickness of the fourth buffer layer can be 100 nm to 12000 nm.

[0043] In this embodiment, the thickness of the buffer layer 120 can be set according to the breakdown voltage level of the device. For example, the thickness of the buffer layer 120 can be 500 nm to 2 μm.

[0044] In this embodiment, as Figure 1 shown, the dislocation control layer 130 is formed on the buffer layer 120. The dislocation control layer 130 includes at least two stacked high-resistance layers and a lattice mismatch layer formed between two adjacent high-resistance layers. That is to say, in the dislocation control layer 130, the high-resistance layers and the lattice mismatch layer are alternately stacked in sequence, and both the starting layer and the ending layer in the dislocation control layer 130 are high-resistance layers. Among them, both the lattice mismatch layer and the high-resistance layer located on the lattice mismatch layer have edge dislocations; further, both the lattice mismatch layer and the high-resistance layer located on the lattice mismatch layer have edge dislocations induced by lattice mismatch.

[0045] It has been found through research that edge dislocations in the GaN epitaxial layer can act as independent transport paths for holes. Edge dislocations induce the formation of continuously distributed hole traps around them, and these traps are coupled with the C N type defects in the carbon-doped buffer layer to form a "hole channel". The hole redistribution assisted by edge dislocations helps to alleviate the electron accumulation in the buffer layer, thereby reducing the dynamic performance degradation. In this embodiment, since both the lattice mismatch layer and the high-resistance layer located on the lattice mismatch layer have edge dislocations, continuously distributed hole traps can be induced around them and coupled with the original traps in the buffer layer, capable of forming a channel for hole transport (i.e., a hole channel). Through this channel, hole redistribution can be achieved, effectively alleviating the electron accumulation in the buffer layer 120, thereby suppressing the dynamic performance degradation of the device.

[0046] Specifically, the number of high-resistance layers is n layers, and the number of lattice mismatch layers is n - 1 layers. That is to say, the dislocation control layer 130 includes n high-resistance layers and n - 1 lattice mismatch layers, and one lattice mismatch layer is formed between two adjacent high-resistance layers. Among them, 2 ≤ n ≤ 6, and n is an integer. For example, n = 3, n = 4, n = 5 or n = 6. When the number of lattice mismatch layers is more than two, the number and density of edge dislocations can be increased, which is beneficial to further alleviate the electron accumulation in the buffer layer 120 and further suppress the dynamic performance degradation of the device.

[0047] In some embodiments, the dislocation control layer 130 includes n stacked high-resistivity layers and n-1 lattice-mismatched layers, where n=2, that is, the dislocation control layer 130 includes two stacked high-resistivity layers and one lattice-mismatched layer, with the lattice-mismatched layer located between two adjacent high-resistivity layers. Specifically, as shown... Figure 1 As shown, the two stacked high-resistivity layers are a first high-resistivity layer 131 and a second high-resistivity layer 133, and a lattice mismatch layer is a first lattice mismatch layer 132. The first lattice mismatch layer 132 is located on and covers the first high-resistivity layer 131, and the second high-resistivity layer 133 is located on and covers the first lattice mismatch layer 132. That is, the first lattice mismatch layer 132 is formed between the first high-resistivity layer 131 and the second high-resistivity layer 133. In other words, the first high-resistivity layer 131, the first lattice mismatch layer 132, and the second high-resistivity layer 133 are stacked sequentially from bottom to top. Both the first lattice mismatch layer 132 and the second high-resistivity layer (i.e., the high-resistivity layer located on the lattice mismatch layer) 133 contain edge dislocations.

[0048] In some embodiments, such as Figure 2 As shown, the dislocation control layer 130 comprises n stacked high-resistivity layers and n-1 lattice mismatch layers, where n=3, meaning the dislocation control layer 130 comprises three stacked high-resistivity layers and two lattice mismatch layers. Specifically, the three stacked high-resistivity layers are a first high-resistivity layer 131, a second high-resistivity layer 133, and a third high-resistivity layer 135, and the two lattice mismatch layers are a first lattice mismatch layer 132 and a second lattice mismatch layer 134. The first high-resistivity layer 131, the first lattice mismatch layer 132, the second high-resistivity layer 133, the second lattice mismatch layer 134, and the third high-resistivity layer 135 are stacked sequentially from bottom to top. Each of the first lattice mismatch layer 132, the second high-resistivity layer 133, the second lattice mismatch layer 134, and the third high-resistivity layer 135 contains an edge dislocation.

[0049] It should be noted that the total number of lattice mismatch layers in the dislocation control layer 130 cannot be too large. For example, if it is greater than five layers, the total thickness of the dislocation control layer 130 will increase accordingly, and the density and number of edge dislocations will also increase. Based on this, in this embodiment, the total number of lattice mismatch layers in the dislocation control layer 130 is one to five layers, in order to alleviate electron accumulation in the buffer layer 120, suppress the dynamic performance degradation of the device, and at the same time, avoid the problem of too many edge dislocations introduced due to too many lattice mismatch layers in the dislocation control layer 130, and avoid the problem of the total thickness of the dislocation control layer 130 being too thick.

[0050] In this embodiment, the thickness of each high-resistivity layer can be the same, and the thickness of the high-resistivity layer can be 100 nm to 300 nm. The material of the high-resistivity layer can be gallium nitride doped with carbon.

[0051] In this embodiment, the material of the lattice mismatch layer is Al x Ga 1-x N or In x Ga 1-x N, where 0.1 < x ≤ 1. The larger the value of x, the greater the lattice mismatch in the lattice mismatch layer, and the more edge dislocations are induced. When the total number of lattice mismatch layers in the dislocation control layer 130 is two or more, the thickness of each lattice mismatch layer can be the same. The thickness of the lattice mismatch layer can be 10 nm to 100 nm. For example, it can be 20 nm, 30 nm, 40 nm, 50 nm or 60 nm. By controlling the thickness and number of lattice mismatch layers, the density of edge dislocations can be effectively regulated, so as to match the requirements of different device voltage levels, and the total epitaxial thickness of the dislocation control layer 130 can be adjusted accordingly.

[0052] In this embodiment, as Figure 1 shown, the semiconductor power device further includes a channel layer 140, and the channel layer 140 is formed on the dislocation control layer 130. The material of the channel layer 140 can be undoped gallium nitride, and the thickness of the channel layer 140 can be 100 nm - 500 nm.

[0053] As Figure 1 shown, the semiconductor power device further includes a barrier layer 150, and the barrier layer 150 is formed on the channel layer 140, and the barrier layer 150 can cover the channel layer 140. The material of the barrier layer 150 includes AlN (aluminum nitride) and / or Al x Ga 1-x N (aluminum gallium nitride), where 0.15 < x ≤ 0.25, and the thickness of the barrier layer 150 can be 10 nm - 25 nm.

[0054] As Figure 1 shown, the semiconductor power device further includes a cap layer 160, and the cap layer 160 is formed on the barrier layer 150, and the cap layer 160 can cover the barrier layer 150. The material of the cap layer 160 can be gallium nitride. Further, if the semiconductor power device is a depletion-type device (normally on), the material of the barrier layer 150 is undoped gallium nitride, and the thickness of the cap layer 160 is 1 nm - 3 nm; if the semiconductor power device is an enhancement-type device (normally off), the material of the barrier layer 150 is P-type doped gallium nitride, and the thickness of the cap layer 160 is 70 nm - 100 nm.

[0055] In this embodiment, the semiconductor power device can be a gallium nitride high electron mobility transistor (GaN HEMT, High Electron Mobility Transistor).

[0056] Figure 3 This is a schematic flowchart of the method for forming a semiconductor power device provided by the present invention. Figure 3 As shown, this embodiment also provides a method for forming a semiconductor power device, including:

[0057] Step S1: Provide a substrate;

[0058] Step S2: Forming a nucleation layer on the substrate;

[0059] Step S3: Form a buffer layer on the nucleation layer;

[0060] Step S4: Form a dislocation control layer, which is formed on the buffer layer. The dislocation control layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer have edge dislocations.

[0061] Figures 4 to 6 This is a schematic diagram of the structure formed in the method for forming a semiconductor power device provided in an embodiment of the present invention. The following will refer to the accompanying drawings. Figures 4 to 6 The method for forming the semiconductor power device provided in this embodiment will be described in more detail.

[0062] First, such as Figure 4 As shown, step S1 is performed, providing a substrate 100. The substrate 100 can be made of any suitable material known to those skilled in the art; for example, the substrate 100 can be a silicon substrate 100, and the crystal orientation of the substrate 100 is... <111> .

[0063] Next, as Figure 4 As shown, step S2 is performed to form a nucleation layer 110, which is formed on the substrate 100. The material of the nucleation layer 110 can be aluminum nitride (AlN), which can act as a wetting layer and provide pre-stress.

[0064] Next, as Figure 4 As shown, step S3 is performed to form a buffer layer 120, which is formed on the nucleation layer 110. The buffer layer 120 can cover the top surface of the nucleation layer 110. The buffer layer 120 is used to store compressive stress to compensate for the tensile stress experienced by the dislocation modulation layer 130 during device cooling.

[0065] In some embodiments, the material of the buffer layer 120 may include AlN and / or AlGaN.

[0066] In some embodiments, the buffer layer 120 may be a superlattice structure consisting of alternating stacks of Al(Ga)N and AlGaN layers.

[0067] Next, as Figure 5 As shown, step S4 is executed to form a dislocation control layer 130. The dislocation control layer 130 is formed on the buffer layer 120. The dislocation control layer 130 includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. That is, in the dislocation control layer 130, the high-resistivity layers and the lattice mismatch layers are stacked alternately in sequence, and the starting layer and the ending layer of the dislocation control layer 130 are both high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer located on the lattice mismatch layer contain edge dislocations; furthermore, both the lattice mismatch layer and the high-resistivity layer located on the lattice mismatch layer contain edge dislocations caused by lattice mismatch. Due to the presence of edge dislocations, a continuous distribution of hole traps can be induced around them, and these traps can couple with the original traps in the buffer layer to form a channel for hole transport (i.e., a hole channel). Hole redistribution can be achieved through this channel, which can effectively relieve the accumulation of electrons in the stress-relieving buffer layer and thus suppress the dynamic performance degradation of the device.

[0068] Specifically, the high-resistivity layer has n layers, and the lattice mismatch layer has n-1 layers. That is, the dislocation control layer 130 includes n high-resistivity layers and n-1 lattice mismatch layers, with one lattice mismatch layer formed between two adjacent high-resistivity layers. Here, 2 ≤ n ≤ 6, and n is an integer, such as n=3, n=4, n=5, or n=6. When the number of lattice mismatch layers is two or more, the number and density of edge dislocations can be increased, which helps to further alleviate electron accumulation in the buffer layer and further suppress the dynamic performance degradation of the device.

[0069] Figure 5 This is a schematic diagram of the structure after the formation of a dislocation modulation layer in a method for forming a semiconductor power device according to an embodiment of the present invention. Figure 5As shown, in some embodiments, the dislocation control layer 130 includes n stacked high-resistivity layers and n-1 lattice mismatch layers, where n=2, that is, the dislocation control layer 130 includes two stacked high-resistivity layers and one lattice mismatch layer, with the lattice mismatch layer located between two adjacent high-resistivity layers. Specifically, the two stacked high-resistivity layers are a first high-resistivity layer 131 and a second high-resistivity layer 133, with a first lattice mismatch layer 132 formed between the first high-resistivity layer 131 and the second high-resistivity layer 133. The first lattice mismatch layer 132 is located on and covers the first high-resistivity layer 131, and the second high-resistivity layer 133 is located on and covers the first lattice mismatch layer 132. In other words, the first high-resistivity layer 131, the first lattice mismatch layer 132, and the second high-resistivity layer 133 are stacked sequentially from bottom to top. Both the first lattice mismatch layer 132 and the second high-resistivity layer 133 (i.e., the high-resistivity layer located on the lattice mismatch layer) have edge dislocations.

[0070] More specifically, the method of forming the first high-resistivity layer 131, the first lattice mismatch layer 132, and the second high-resistivity layer 133 includes: firstly, forming the first high-resistivity layer 131 on the buffer layer 120, wherein the first high-resistivity layer 131 covers the buffer layer;

[0071] Then, a first lattice mismatch layer 132 is formed on the first high-resistivity layer 131. The formation temperature of the first lattice mismatch layer 132 can be 600℃-900℃, and the first lattice mismatch layer 132 contains misfit dislocations. During the formation of the first lattice mismatch layer 132, because the lattice constant of the lattice mismatch layer is different from that of the first high-resistivity layer 131, the atoms in the first lattice mismatch layer 132 will be subjected to biaxial strain, undergoing elastic stretching or compression to adapt to the interatomic spacing of the underlying first high-resistivity layer 131. When the strain energy accumulates to a critical point, the first lattice mismatch layer 132 itself will relax through dislocation slip, causing edge dislocations to nucleate at the interface between the first lattice mismatch layer 132 and the first high-resistivity layer 131. After the edge dislocations nucleate, their dislocation lines will slide upward along the corresponding slip plane and extend, penetrating the first lattice mismatch layer 132 to its top surface.

[0072] Next, a second high-resistivity layer 133 is formed on the surface of the first lattice mismatch layer 132. The edge dislocations in the second high-resistivity layer 133 consist of two parts: one part is that during the formation of the second high-resistivity layer 133, due to the difference in lattice constant between the second high-resistivity layer 133 and the first lattice mismatch layer 132, the atoms in the second high-resistivity layer 133 are subjected to biaxial strain, undergoing elastic stretching or compression to adapt to the interatomic spacing of the underlying first lattice mismatch layer 132. When the strain energy accumulates to a critical point, the second high-resistivity layer 133 itself relaxes through dislocation slip, causing the edge dislocations to nucleate at the interface between the second high-resistivity layer 133 and the first lattice mismatch layer 132. After the edge dislocations nucleate, their dislocation lines slide upwards along the corresponding slip plane and extend through the second high-resistivity layer 133 to its top surface. Another part is that since there are already edge dislocations extending to the top surface in the first lattice mismatch layer 132, during the growth of the second high-resistivity layer 133, the dislocation lines in the first lattice mismatch layer 132 will continue to extend upward and into the interior of the second high-resistivity layer 133, thereby forming edge dislocations in the second high-resistivity layer 133 as well.

[0073] Following this pattern, as the number of lattice mismatch layers increases, edge dislocations induced by lattice mismatch multiply layer by layer and extend upwards. It should be noted that the total number of lattice mismatch layers should not be excessive. When the total number of lattice mismatch layers is too high, for example, more than five layers, although more edge dislocations can be generated, too many heterostructures will actually hinder the upward extension of edge dislocations and lead to an excessively thick total thickness of the dislocation control layer 130, causing uncontrollable stress and warping problems. Therefore, in this embodiment, the total number of lattice mismatch layers is one to five layers to avoid an excessively thick total thickness of the dislocation control layer 130, thereby avoiding uncontrollable stress and warping problems.

[0074] Figure 6 This is a schematic diagram of the structure after forming a dislocation modulation layer in a method for forming a semiconductor power device according to another embodiment of the present invention. Figure 6 As shown, in some embodiments, the dislocation control layer 130 includes n stacked high-resistivity layers and n-1 lattice mismatch layers, where n=3, i.e., the dislocation control layer 130 includes three stacked high-resistivity layers and two lattice mismatch layers. Specifically, the three stacked high-resistivity layers are a first high-resistivity layer 131, a second high-resistivity layer 133, and a third high-resistivity layer 135, and the two lattice mismatch layers are a first lattice mismatch layer 132 and a second lattice mismatch layer 134, which are stacked sequentially from bottom to top. Each of the first lattice mismatch layer 132, the second high-resistivity layer 133, the second lattice mismatch layer 134, and the third high-resistivity layer 135 contains an edge dislocation.

[0075] In this embodiment, in the dislocation control layer 130, the material of the high-resistance layer can be gallium nitride doped with carbon. Exemplarily, the high-resistance layer can be formed by metal organic chemical vapor deposition (MOCVD). Among them, C2H4 can be used as a carbon doping source to form gallium nitride doped with carbon, and then the high-resistance layer is formed.

[0076] In this embodiment, the thickness of each high-resistance layer can be the same. For example, the thickness of the high-resistance layer can be 100 nm to 300 nm.

[0077] In this embodiment, the material of the lattice mismatch layer is Al x Ga 1-x N or In x Ga 1-x N, 0.1 < x ≤ 1, such as x = 0.2, x = 0.5 or x = 0.8. Among them, the larger x is, the greater the lattice mismatch in the lattice mismatch layer, and the more edge dislocations are induced to form.

[0078] In this embodiment, the lattice mismatch layer can be formed by an epitaxial process. Exemplarily, the lattice mismatch layer can be formed by a metal organic chemical vapor deposition process (MOCVD) or a molecular beam epitaxy process (MBE). The formation temperature of the lattice mismatch layer is 600 °C - 900 °C, such as 650 °C, 700 °C, 750 °C or 800 °C. When the total number of lattice mismatch layers in the dislocation control layer 130 is more than two, the thickness of each lattice mismatch layer can be the same. Among them, the thickness of the lattice mismatch layer can be 10 nm to 100 nm.

[0079] Preferably, the formation temperature of the lattice mismatch layer is 800 °C - 900 °C. In this way, it is beneficial to reduce or avoid the generation of screw dislocations.

[0080] As Figure 1 shown, after forming the dislocation control layer 130, a channel layer 140 is formed. The channel layer 140 is formed on the dislocation control layer 130, and the channel layer 140 can cover the top surface of the dislocation control layer 130. Among them, the material of the channel layer 140 can be undoped gallium nitride, and the thickness of the channel layer 140 can be 100 nm - 500 nm.

[0081] Then, as Figure 1As shown, a barrier layer 150 is formed on the channel layer 140, and the barrier layer 150 can cover the channel layer 140. The material of the barrier layer 150 includes AlN (aluminum nitride) and / or Al. x Ga 1-x N (aluminum gallium nitride), where 0.15 <x≤0.25。

[0082] In this embodiment, the thickness of the barrier layer 150 can be 10nm-25nm.

[0083] After that, as Figure 1 As shown, a cap layer 160 is formed on the barrier layer 150, and the cap layer 160 can cover the barrier layer 150. The material of the cap layer 160 can be gallium nitride.

[0084] Furthermore, if the semiconductor power device is a depletion-type device (normally on), then the material of the barrier layer 150 is undoped gallium nitride, and the thickness of the cap layer 160 is 1nm-3nm; if the semiconductor power device is an enhancement-type device (normally off), then the material of the barrier layer 150 is P-type doped gallium nitride, and the thickness of the cap layer 160 is 70nm-100nm.

[0085] In summary, the semiconductor power device and its formation method provided by this invention include: a nucleation layer formed on the substrate; a buffer layer formed on the nucleation layer; and a dislocation control layer formed on the buffer layer. The dislocation control layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer contain edge dislocations. Because both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer contain edge dislocations, continuously distributed hole traps can be induced around them and coupled with the original traps in the buffer layer to form a channel for hole transport (i.e., a hole channel). Through this channel, hole redistribution can be achieved, effectively alleviating electron accumulation in the buffer layer and thus suppressing the dynamic performance degradation of the device.

[0086] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0087] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor power device, characterized in that, include: Substrate; A nucleation layer is formed on the substrate; A buffer layer is formed on the nucleation layer; A dislocation control layer is formed on the buffer layer. The dislocation control layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer have edge dislocations.

2. The semiconductor power device as described in claim 1, characterized in that, The lattice mismatch layer is made of Al. x Ga 1- x N or In x Ga 1-x N, where 0.1 <x≤1。 3. The semiconductor power device as described in claim 1, characterized in that, In the dislocation control layer, the number of high-resistivity layers is n, and the number of lattice mismatch layers is n-1, where 2≤n≤6, and n is an integer.

4. The semiconductor power device as described in claim 1, characterized in that, The high-resistivity layer is made of gallium nitride doped with carbon.

5. The semiconductor power device as described in claim 1, characterized in that, The semiconductor power device further includes: A channel layer is formed on the dislocation control layer; A barrier layer is formed on the channel layer; A cap layer is formed on the barrier layer.

6. A method for forming a semiconductor power device, characterized in that, include: Provide substrate; A nucleation layer is formed on the substrate; A buffer layer is formed on the nucleation layer; A dislocation control layer is formed on the buffer layer. The dislocation control layer includes at least two stacked high-resistivity layers and a lattice mismatch layer formed between two adjacent high-resistivity layers. Both the lattice mismatch layer and the high-resistivity layer on the lattice mismatch layer have edge dislocations.

7. The method for forming a semiconductor power device as described in claim 6, characterized in that, The lattice mismatch layer is made of Al. x Ga 1-x N or In x Ga 1-x N, where 0.1 <x≤1。 8. The method for forming a semiconductor power device as described in claim 6, characterized in that, In the dislocation control layer, the number of high-resistivity layers is n, and the number of lattice mismatch layers is n-1, where 2≤n≤6, and n is an integer.

9. The method for forming a semiconductor power device as described in claim 6, characterized in that, The lattice mismatch layer is formed at a temperature of 600℃-900℃.

10. The method for forming a semiconductor power device as described in claim 6, characterized in that, After forming the dislocation control layer, the method further includes: A channel layer is formed on the dislocation control layer; A barrier layer is formed on the channel layer; A cap layer is formed on the barrier layer.

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