Transistor, semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a transistor, a semiconductor device, a preparation method thereof and electronic equipment. The transistor comprises a source electrode, a channel region and a drain electrode which are sequentially arranged along a first direction, and a grid electrode which is arranged at the periphery of the channel region in an insulating manner; the source electrode comprises a first semiconductor layer and a second semiconductor layer, the same ends of the first semiconductor layer and the second semiconductor layer in the first direction are connected with the channel region, and the second semiconductor layer is located on the side, close to the grid electrode, of the first semiconductor layer in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is smaller than that of the second semiconductor layer. The invention relates to the technical field of semiconductor devices, in particular to a transistor, a semiconductor device, a preparation method of the semiconductor device and electronic equipment, and aims to restrain accumulation of holes in a channel as a starting point, relieve formation of a parasitic bipolar transistor and prolong storage retention time.

Description

Technical Field

[0001] This article relates to the field of semiconductor device technology, and in particular to a transistor, a semiconductor device, its fabrication method, and an electronic device. Background Technology

[0002] The demand for storage density in dynamic random access memory (DRAM) is constantly increasing, and the cell area of ​​traditional planar structures is continuously shrinking. Planar structures are approaching their limits in terms of both manufacturing processes and reliability. Memory technologies that utilize space stacking to reduce the requirements for planar linewidth and device miniaturization are gradually becoming the mainstream products in the market. For memory, the performance of the gating transistor affects the data retention performance of the memory. Therefore, further improving the performance of transistors is extremely important. Summary of the Invention

[0003] This application provides a transistor, including a source, a channel region, and a drain arranged sequentially along a first direction, and a gate insulated and disposed on the outer periphery of the channel region; The source includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are connected to the channel region at the same end in the first direction. The second semiconductor layer is located on the side of the first semiconductor layer that is close to the gate in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is less than that of the second semiconductor layer.

[0004] In some exemplary embodiments, the doping concentration of the first semiconductor layer is set to be the same as the doping concentration of the channel region.

[0005] In some exemplary embodiments, the material of the first semiconductor layer is the same as the material of the channel region, and the first semiconductor layer and the channel region are configured as a single unit.

[0006] In some exemplary embodiments, the material of the first semiconductor layer includes silicon, and the material of the second semiconductor layer includes N-type heavily doped silicon.

[0007] In some exemplary embodiments, the gate includes a first gate and a second gate, the first gate and the second gate being located on opposite sides of the channel region in a second direction, the second direction being perpendicular to the first direction; The second semiconductor layer includes a first sublayer and a second sublayer, wherein the first sublayer, the first semiconductor layer and the second sublayer are stacked sequentially in the second direction.

[0008] In some exemplary embodiments, the first sublayer is located on the side of the first semiconductor layer near the first gate in the second direction, and the second sublayer is located on the side of the first semiconductor layer near the second gate in the second direction, and the material of the first sublayer is set to be the same as the material of the second sublayer.

[0009] In some exemplary embodiments, the thickness of one of the first sub-layer and the second sub-layer is set to be not less than the thickness of the first semiconductor layer; The thickness of the first semiconductor layer is the maximum distance between the end face of the first semiconductor layer near the first sub-layer and the end face near the second sub-layer. The thickness of the first sub-layer is the maximum distance between the end face of the first sub-layer near the first semiconductor layer and the end face away from the first semiconductor layer. The thickness of the second sub-layer is the maximum distance between the end face of the second sub-layer near the first semiconductor layer and the end face away from the first semiconductor layer.

[0010] In some exemplary embodiments, the orthographic projections of the first sublayer, the first semiconductor layer, and the second sublayer on a first plane overlap, wherein the first plane is perpendicular to the second direction and parallel to the first direction.

[0011] In some exemplary embodiments, the gate surrounds the channel region and forms a ring, thus forming a ring gate structure; The first semiconductor layer extends along the first direction, and the second semiconductor layer covers the circumferential surface of the first semiconductor layer and forms a ring.

[0012] This application provides a semiconductor device including multiple memory cells, which are stacked and periodically distributed along a direction perpendicular to the substrate; Each of the memory cells includes a transistor, the transistor including a source, a channel region and a drain arranged sequentially along a first direction, and a gate insulated on the channel region, the gate being located on both sides of the channel region in a second direction, the first direction being parallel to the substrate and the second direction being perpendicular to the substrate; The source includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are connected to the channel region at the same end in the first direction. The second semiconductor layer is located on the side of the first semiconductor layer closer to the gate in the second direction. The doping concentration of the first semiconductor layer is less than that of the second semiconductor layer.

[0013] In some exemplary embodiments, the second semiconductor layer includes a first sublayer and a second sublayer, wherein the first sublayer is located on the side of the first semiconductor layer away from the substrate, and the second sublayer is located on the side of the first semiconductor layer closer to the substrate.

[0014] In some exemplary embodiments, the memory cell further includes a capacitor, the transistor and the capacitor are arranged sequentially in the first direction, and the capacitor is arranged close to the drain of the transistor.

[0015] In some exemplary embodiments, it also includes multiple bit lines and multiple word lines. The bit line extends in a direction perpendicular to the substrate, and the transistors of the plurality of memory cells stacked in a direction perpendicular to the substrate are all connected to a bit line, the bit line being connected to the end of the source away from the channel region. The gate includes a first gate and a second gate, wherein the first gate is located on the side of the channel region away from the substrate, and the second gate is located on the side of the channel region close to the substrate; The word lines extend along a third direction, and each word line is formed by connecting the first gate or the second gate on the transistors of a plurality of memory cells arranged along the third direction, which is perpendicular to the first direction and the second direction.

[0016] This application provides a method for fabricating a semiconductor device, applicable to the aforementioned semiconductor device, comprising: Semiconductor layers and sacrificial layers are alternately grown on a substrate to obtain a stacked structure, and the stacked structure is etched. The remaining semiconductor layers form multiple semiconductor pillars, which extend along the first direction. The second semiconductor layer is formed on the semiconductor pillar.

[0017] In some exemplary embodiments, the semiconductor pillar includes a first region, a second region, and a third region arranged sequentially along the first direction; The formation of the second semiconductor layer on the semiconductor pillar includes: An oxide film is deposited on the surface of the first region; Annealing causes the doping elements in the oxide film to diffuse into the first region, forming the second semiconductor layer.

[0018] In some exemplary embodiments, depositing an oxide thin film on the surface of the first region includes: The sacrificial layer is etched while retaining the sacrificial layer covering the second region on the side face of the second region near the substrate and the side face of the second region away from the substrate in a second direction, the second direction being perpendicular to the substrate; An oxide film is deposited on the end face of the first region in the second direction, on the side close to the substrate and the side far from the substrate.

[0019] In some exemplary embodiments, the method further includes: removing the remaining sacrificial layer.

[0020] This application provides an electronic device, including the transistor described above, or the semiconductor device described above, or the semiconductor device formed by the method for preparing the semiconductor device described above.

[0021] The transistors and semiconductor devices of this application, based on the principle of suppressing hole accumulation in the channel, can alleviate the formation of parasitic bipolar junction transistors (BJTs) and improve memory retention time. In the transistors and semiconductor devices of this application, a "sandwich" doped structure is formed at the source, with a lower doping concentration in the middle of the source. By reducing the hole barrier height, holes are promptly removed, suppressing the formation of parasitic bipolar junction transistors. When the bit line state changes, the amplification of leakage current is greatly reduced or even eliminated. Simultaneously, timely removal of holes suppresses hole accumulation in the channel, weakening the parasitic bipolar junction transistor effect and effectively reducing the increased leakage current caused by the parasitic bipolar junction transistor effect. This improves memory leakage current, enhances memory data retention performance, and reduces integrated circuit power consumption.

[0022] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 A schematic diagram of a transistor in this exemplary embodiment; Figure 2 for Figure 1 A schematic diagram of the a-a' cross-section of the transistor in the image; Figure 3 Another schematic diagram of a transistor for this exemplary embodiment; Figure 4 for Figure 3 A schematic diagram of the b-b' cross-section of the transistor in the image; Figure 5 A schematic diagram of a semiconductor device according to an exemplary embodiment of this invention; Figure 6 for Figure 5 A schematic diagram of the c-c' cross-section of the semiconductor device in the diagram; Figure 7 A schematic diagram of another semiconductor device for this exemplary embodiment; Figure 8 This is a schematic diagram of a preparation method according to an exemplary embodiment of the present invention; Figure 9 This is a first fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 10 This is a second fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 11 This is a third fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 12 This is a fourth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 13 This is a fifth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 14 A sixth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment; Figure 15 A seventh fabrication schematic diagram of a semiconductor device according to this exemplary embodiment; Figure 16 This is an eighth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 17 A ninth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment; Figure 18 A tenth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment; Figure 19 This is an eleventh fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 20 This is a schematic diagram illustrating the twelfth fabrication step of a semiconductor device according to an exemplary embodiment of the present invention; Figure 21 This is a thirteenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 22 for Figure 2 A schematic diagram of charge flow in the first region of the image; Figure 23 for Figure 2 A schematic diagram of charge flow in the second region; Figure 24 This is a simulation diagram of a semiconductor device for this exemplary embodiment. Detailed Implementation

[0025] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0026] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0027] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0028] Currently, the leakage current of the gate transistors in memory mainly consists of gate-induced drain leakage current (GIDL) caused by band-to-band tunneling. Simultaneously, holes accumulate in the channel, a phenomenon known as the floating body effect. The source, floating body, and drain form a parasitic bipolar junction transistor (BJT). When a memory cell stores a "1" and is in a data retention state, and other cells perform a write "0" operation (i.e., the bit line is at a low potential), the parasitic bipolar junction transistors in the transistors on the same word line that are in a turn-off state enter amplification mode. This leads to a significant increase in leakage current, severely impacting the data retention capability and further scaling of the memory cell.

[0029] Figure 1 This is a schematic diagram of a transistor in an exemplary embodiment of the present invention. Figure 2 for Figure 1 A schematic diagram of the a-a' cross-section of the transistor in the diagram. Figure 3 This is another schematic diagram of a transistor in this exemplary embodiment. Figure 4 for Figure 3 A schematic diagram of the b-b' cross-section of a transistor in this application. This application provides a transistor, which can be a gating transistor, such as... Figures 1 to 4 As shown, transistor 100 may include a source 101, a channel region 102, and a drain 103 arranged sequentially along a first direction, and a gate 104 insulated and disposed on the outer periphery of the channel region 102. The source 101 may include a first semiconductor layer 1011 and a second semiconductor layer 1012. The same end of the first semiconductor layer 1011 and the second semiconductor layer 1012 in the first direction may both be connected to the channel region 102. The second semiconductor layer 1012 may be located on the side of the first semiconductor layer 1011 perpendicular to the first direction, closer to the gate 104. The doping concentration of the first semiconductor layer 1011 is less than the doping concentration of the second semiconductor layer 1012. Therefore, the transistor 100 of this embodiment, with the aim of suppressing hole accumulation in the channel region 102, can alleviate the formation of parasitic bipolar junction transistors (BJTs).

[0030] In some exemplary embodiments, such as Figure 1 and Figure 2As shown, transistor 100 can be a dual-gate transistor structure. Gate 104 may include a first gate 1041 and a second gate 1042, which are located on opposite sides of channel region 102 in a second direction, perpendicular to the first direction. The orthographic projection of the first gate 1041 onto a first plane P1 may fall within the orthographic projection range of channel region 102 onto the first plane P1, and the orthographic projection of the second gate 1042 onto the first plane P1 may also fall within the orthographic projection range of channel region 102 onto the first plane P1. The first plane P1 is parallel to the first direction and perpendicular to the second direction. In this example, the orthographic projections of the first gate 1041 and the second gate 1042 onto the first plane P1 may both overlap with the orthographic projection of channel region 102 onto the first plane P1. Additionally, transistor 100 also includes a gate insulating layer 105, which may be located between gate 104 and channel region 102 to provide insulation. The gate insulating layer 105 may include a first gate dielectric layer 1051 and a second gate dielectric layer 1052. The first gate dielectric layer 1051 may be located between the first gate 1041 and channel region 102, and the orthographic projection of the first gate dielectric layer 1051 on the first plane P1 overlaps with the orthographic projection of the channel region 102 on the first plane P1. The second gate dielectric layer 1052 may be located between the second gate 1042 and channel region 102, and the orthographic projection of the second gate dielectric layer 1052 on the first plane P1 overlaps with the orthographic projection of the channel region 102 on the first plane P1. The first gate 1041 and the second gate 1042 may be made of the same material, and may both comprise metals or metal alloys, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The first gate dielectric layer 1051 and the second gate dielectric layer 1052 may be made of the same material, and may both comprise low dielectric constant dielectric materials, such as silicon oxide, or may both comprise high dielectric constant dielectric materials, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof, and may be formed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD.

[0031] In some exemplary embodiments, such as Figure 1 and Figure 2As shown, the material of the channel region 102 may include silicon-based materials such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon. In this example, the material of the channel region 102 may be silicon, making the channel region 102 undoped, with a doping concentration of 0. The source 101 is located on one side of the channel region 102 in the first direction, and the drain 103 is located on the other side of the channel region 102 in the first direction. The orthogonal projections of the source 101 and the drain 103 onto the first plane P1 do not overlap with the orthogonal projection of the channel region 102 onto the first plane P1. The material of the drain 103 may be N-type heavily doped silicon, that is, silicon doped with dopants such as phosphorus (P) or arsenic (As), which can be formed by diffusing phosphorus or arsenic into the silicon material through an annealing process.

[0032] In some exemplary embodiments, such as Figure 1 and Figure 2 As shown, with respect to the source 101, the second semiconductor layer 1012 may include a first sublayer 1012a and a second sublayer 1012b. The first sublayer 1012a, the first semiconductor layer 1011, and the second sublayer 1012b may be stacked sequentially in the second direction. Thus, the first sublayer 1012a and the second sublayer 1012b sandwich the first semiconductor layer 1011, forming a sandwich-like structure. The first sublayer 1012a, the first semiconductor layer 1011, and the second sublayer 1012b are all connected to the channel region 102 at one end in the first direction. The first sublayer 1012a is located on the side of the first semiconductor layer 1011 in the second direction near the first gate 1041, and the second sublayer 1012b may be located on the side of the first semiconductor layer 1011 in the second direction near the second gate 1042. The orthographic projection of the first sublayer 1012a onto the first plane P1, the orthographic projection of the first semiconductor layer 1011 onto the first plane P1, and the orthographic projection of the second sublayer 1012b onto the first plane P1 overlap, the first plane P1 being perpendicular to the second direction and parallel to the first direction.

[0033] In some exemplary embodiments, such as Figure 1 and Figure 2As shown, the thickness of the first semiconductor layer 1011 can be a first thickness (D1), where the thickness (D1) of the first semiconductor layer 1011 is the maximum distance between the end face of the first semiconductor layer 1011 near the first sub-layer 1012a and the end face of the first sub-layer 1012b near the second sub-layer 1012b; the thickness of the first sub-layer 1012a can be a second thickness (D2), where the thickness (D2) of the first sub-layer 1012a is the maximum distance between the end face of the first sub-layer 1012a near the first semiconductor layer 1011 and the end face of the first sub-layer 1012b far from the first semiconductor layer 1012a. The maximum distance between the end faces of the conductor layer 1011; the thickness of the second sub-layer 1012b may be a third thickness (D3), and the thickness (D3) of the second sub-layer 1012b may be the maximum distance between the end face of the second sub-layer 1012b near the first semiconductor layer 1011 and the end face away from the first semiconductor layer 1011; the thickness of one of the first sub-layer 1012a and the second sub-layer 1012b may not be less than the thickness of the first semiconductor layer 1011, that is, D2≥D1 or D3≥D1. In some exemplary embodiments, D2=D3>D1, and the ratio of D2 to D1 is greater than 1 and less than or equal to 2, but is not limited thereto. For example, D2 is not equal to D3 and both are greater than D1, the ratio of D2 to D1 is greater than 1 and less than or equal to 2, and the ratio of D3 to D1 is greater than 1 and less than or equal to 2; or, for example, D2=D3=D1.

[0034] In some exemplary embodiments, such as Figure 1 and Figure 2 As shown, the material of the first sublayer 1012a can be the same as the material of the second sublayer 1012b, and the materials of the first sublayer 1012a and the second sublayer 1012b can be the same as the material of the drain 103. Both can be N-type heavily doped silicon, meaning that phosphorus (P) or arsenic (As) is doped into the silicon material. Phosphorus or arsenic can be diffused into the silicon material through an annealing process. The doping concentration of both the first sublayer 1012a and the second sublayer 1012b is greater than 0, and the doping concentration of the first sublayer 1012a and the second sublayer 1012b can be 10. 19 cubic centimeters to 10 20Cubic centimeters. However, this is not the only possibility; for example, the first sublayer 1012a and the second sublayer 1012b may be made of the same material, but different from the material of the drain 103. The material of the first semiconductor layer 1011 may be the same as the material of the channel region 102, and may both be silicon-based materials such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon. In this example, the material of the first semiconductor layer 1011 may be silicon, making the first semiconductor layer 1011 undoped, with a doping concentration of 0. Based on the fact that the first semiconductor layer 1011 and the channel region 102 have the same doping type, the first semiconductor layer 1011 and the channel region 102 have the same doping concentration, and the first semiconductor layer 1011 and the channel region 102 may be integral, i.e., formed by a strip of semiconductor material extending along a first direction. Therefore, the material of the first semiconductor layer 1011 is silicon, undoped. Silicon has a relatively low conductivity in its intrinsic state. The materials of the first sublayer 1012a and the second sublayer 1012b can be heavily doped N-type silicon, and the doping concentration of the first sublayer 1012a and the second sublayer 1012b can be 10⁻⁶. 19 cubic centimeters to 10 20 In cubic centimeters, the doping concentration of the first semiconductor layer 1011 (doping concentration is 0) is less than the doping concentration of the first sublayer 1012a and the second sublayer 1012b. The doping elements (i.e., phosphorus elements) of the first sublayer 1012a and the second sublayer 1012b provide additional charge carriers (electrons or holes) and reduce the potential barrier height of the charge carriers.

[0035] Figure 22 for Figure 2 A schematic diagram of charge flow in the first region of the image. Figure 23 for Figure 2 A schematic diagram of charge flow in the second region, as shown in some exemplary embodiments, such as Figure 1 , Figure 2 , Figure 22 and Figure 23 As shown, transistor 100 includes a first region C1 and a second region C2 in the second direction, with a first sub-layer 1012a located in the first region C1 and a first semiconductor layer 1011 and a first sub-layer 1012b located in the second region C2. Figure 22 and Figure 23 In the image, the dashed arrows indicate the direction of positive and negative charge flow, according to... Figure 22 and Figure 23 Based on the charge flow in the transistor and the structure of transistor 100, it can be seen that transistor 100 forms a "sandwich" doped structure in the source 101. That is, for NPN transistor 100, intrinsic silicon (Si) or P-type doping is used in the middle of the source 101. By reducing the hole barrier height, the holes are eliminated in time, and the formation of parasitic bipolar transistors is suppressed.

[0036] In some exemplary embodiments, such as Figure 3 and Figure 4 As shown, transistor 100 can be a ring-gate transistor structure, with gate 104 surrounding channel region 102 in a ring shape, i.e., gate 104 surrounds channel region 102 in a direction perpendicular to the first direction. The second plane P2 is perpendicular to the first direction, and the orthographic projection of gate 104 onto the second plane P2 forms a ring and is located on the outer periphery of the orthographic projection of channel region 102 onto the second plane P2. Gate 104 and channel region 102 are aligned in the first direction, and their two ends are flush with each other in the first direction. Transistor 100 also includes a gate insulating layer 105, which can be located between gate 104 and channel region 102, serving an insulating function. The orthographic projection of gate insulating layer 105 onto the second plane P2 forms a ring and is located between the orthographic projection of channel region 102 onto the second plane P2 and the orthographic projection of gate 104 onto the second plane P2. The gate 104 may be made of a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The gate insulating layer 105 may be made of a low-dielectric-constant dielectric material, such as silicon oxide, or may consist entirely of a high-dielectric-constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof, and may be deposited by one or more suitable deposition processes, such as CVD, PVD, and / or ALD.

[0037] In some exemplary embodiments, such as Figure 3 and Figure 4As shown, a first semiconductor layer 1011 extends along a first direction, and a second semiconductor layer 1012 covers the circumferential surface of the first semiconductor layer 1011 and forms a ring. The second semiconductor layer 1012 surrounds the first semiconductor layer 1011 in a direction perpendicular to the first direction. The orthographic projection of the second semiconductor layer 1012 onto the second plane P2 is a ring and surrounds the orthographic projection of the first semiconductor layer 1011 onto the second plane P2. The orthographic projections of both the first semiconductor layer 1011 and the second semiconductor layer 1012 onto the second plane P2 are located within the orthographic projection range of the channel region 102 onto the second plane P2. Thus, the second semiconductor layer 1012 encloses the first semiconductor layer 1011, forming a sandwich structure. The thickness of the first semiconductor layer 1011 can be a first thickness (D1), which can be the maximum dimension of the first semiconductor layer 1011 perpendicular to the first direction; the thickness of the second semiconductor layer 1012 can be a second thickness (D2), which can be the maximum dimension between the end face of the second semiconductor layer 1012 near the first semiconductor layer 1011 and the end face away from the first semiconductor layer 1011; the thickness of the second semiconductor layer 1012 (D2) can be not less than the thickness of the first semiconductor layer 1011 (D1), that is, D2≥D1. In some exemplary embodiments, the ratio of D2 to D1 is greater than 1 and less than or equal to 2, but is not limited thereto, for example, D2=D1.

[0038] In some exemplary embodiments, such as Figure 3 and Figure 4 As shown, the material of the second semiconductor layer 1012 may include N-type heavily doped silicon, i.e., phosphorus or arsenic is doped into the silicon material, which can be formed by annealing to diffuse phosphorus or arsenic into the silicon material. The material of the first semiconductor layer 1011 may be the same as the material of the channel region 102. The material of the first semiconductor layer 1011 is silicon, undoped, and the conductivity of silicon is relatively low in the intrinsic state. The material of the second semiconductor layer 1012 may be N-type heavily doped silicon, so that the doping concentration of the second semiconductor layer 1012 is greater than that of the first semiconductor layer 1011. The gate-ring transistor 100 forms a sandwich structure at the source 101. For example, for an NPN transistor 100, intrinsic silicon (Si) or P-type doping is used in the middle of the source 101. By reducing the hole barrier height, holes are eliminated in time, and the formation of parasitic bipolar transistors is suppressed.

[0039] Figure 5 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 6 for Figure 5 A schematic cross-sectional view of a semiconductor device along line c-c' is shown. In some exemplary embodiments, this exemplary embodiment provides a semiconductor device, such as... Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, the semiconductor device includes a plurality of memory cells 200, which are stacked and periodically distributed along a direction perpendicular to the substrate (not shown). This direction perpendicular to the substrate (not shown) can be a second direction, which is perpendicular to both the first and third directions. Each memory cell 200 may include, for example, […]. Figure 1 and Figure 2 The transistor 100 shown includes a source 101, a channel region 102, and a drain 103 arranged sequentially along a first direction, and a gate 104 insulatedly disposed on the channel region 102. The gate 104 is located on both sides of the channel region 102 in a second direction, which is parallel to the substrate (not shown in the figure). The source 101 may include a first semiconductor layer 1011 and a second semiconductor layer 1012. The same end of the first semiconductor layer 1011 and the second semiconductor layer 1012 are connected to the channel region 102 in the first direction. The second semiconductor layer 1012 may be located on the side of the first semiconductor layer closer to the gate 104 in the second direction. The doping concentration of the first semiconductor layer 1011 may be less than the doping concentration of the second semiconductor layer 1012. In semiconductor devices, the source of transistor 100 forms a "sandwich" doped structure. For example, for NPN transistors, intrinsic silicon (Si) or P-type doping is used in the middle of the source. By reducing the hole barrier height, holes are promptly removed, suppressing the formation of parasitic bipolar transistors. When the bit line state changes, the leakage current amplification phenomenon is greatly reduced or even eliminated. At the same time, timely removal of holes suppresses hole accumulation in the channel, weakens the parasitic bipolar transistor effect, effectively reduces the problem of increased leakage current caused by the parasitic bipolar transistor effect, improves memory leakage current, enhances memory data retention performance, and reduces integrated circuit power consumption.

[0040] Figure 24 This is a simulation diagram of a semiconductor device for this exemplary embodiment. In some exemplary embodiments, such as Figure 24 As shown, the semiconductor device in this example was simulated. The horizontal axis represents time, and the vertical axis represents voltage. The dotted line is the simulation curve of the semiconductor device in this example, and the solid line is the simulation curve of the related semiconductor device. The simulation results show that when the semiconductor device is in the state of storing information "1" and holding, the holding time of the semiconductor device in this example and the holding time of the related semiconductor device increased by a difference S. The holding time of the semiconductor device in this example can be improved by an order of magnitude.

[0041] In some examples, such as Figure 1 , Figure 2 , Figure 5 and Figure 6As shown, the semiconductor device also includes a bit line 400 and a word line 500. The bit line 400 extends along a second direction, and the word line 500 extends along a third direction, which is perpendicular to the first and second directions. Multiple memory cells 200 are arranged at intervals along the second direction to form a memory cell column. The multiple memory cell columns are arranged in an array along the first and third directions. Multiple memory cells 200 in a memory cell column share a single bit line 400, and one end of the memory cell 200 having a source 101 is connected to the bit line 400. The bit line 400 can be made of metal; in this example, the bit line 400 can be made of tungsten. Each word line 500 is formed by connecting a first gate 1041 on the transistors 100 of the multiple memory cells 200 arranged along the third direction, but is not limited to this; for example, each word line 500 can be formed by connecting a second gate 1042 on the transistors 100 of the multiple memory cells 200 arranged along the third direction.

[0042] In some examples, such as Figure 1 , Figure 2 , Figure 5 and Figure 6As shown, the transistor 100 in the memory cell 200 includes a semiconductor pillar 600 extending along a first direction. The semiconductor pillar 600 includes a first region 600a, a second region 600b, and a third region 600c arranged sequentially along the first direction. The material of the semiconductor pillar 600 may include silicon. The first region 600a of the semiconductor pillar 600 is doped to form a source 101. The second region 600b of the semiconductor pillar 600 constitutes the aforementioned channel region 102. The portion of the third region 600c of the semiconductor pillar 600 near the second region 600b is doped to form a drain 103. One end of the source 101 away from the channel 102 is connected to the bit line 400. The first sublayer 1012a of the source 101 is located on the side of the first semiconductor layer 1011 of the source 101 away from the substrate (not shown in the figure). The first sublayer 1012a can be formed by doping the side of the first region 600a of the semiconductor pillar 600 away from the substrate (not shown in the figure). The first semiconductor layer 1011 can be formed by undoping the first region 600a of the semiconductor pillar 600. The second sublayer 1012b of the source 101 is located on the side of the first semiconductor layer 1011 of the source 101 close to the substrate (not shown in the figure). The second sublayer 1012b can be formed by doping the side of the first region 600a of the semiconductor pillar 600 close to the substrate (not shown in the figure). The gate insulating layer 105 and the gate 104 of the transistor 100 are both disposed corresponding to the second region 600b of the semiconductor pillar 600. The first gate 1041 of the gate 104 is located on the side of the second region 600b of the semiconductor pillar 600 away from the substrate (not shown in the figure); the second gate 1042 of the gate 104 is located on the side of the second region 600b of the semiconductor pillar 600 close to the substrate (not shown in the figure); the first gate dielectric layer 1051 of the gate insulating layer 105 is located between the second region 600b of the semiconductor pillar 600 and the first gate 1041; the second gate dielectric layer 1052 of the gate insulating layer 105 is located between the second region 600b of the semiconductor pillar 600 and the second gate 1042.

[0043] In some examples, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, the memory cell 200 also includes a capacitor 300, which is located at the end of the semiconductor pillar 600 away from the bit line. The capacitor 300 surrounds the end of the third region 600c of the semiconductor pillar 600 away from the second region 600b. The capacitor 300 includes an inner electrode plate 301, a first insulating layer 302, and an outer electrode plate 303 arranged sequentially from the inside to the outside. The inner electrode plate 301 and the outer electrode plate 303 can be made of metal or conductive metal compound. In this example, the inner electrode plate 301 and the outer electrode plate 303 can be made of the same material and both are titanium nitride (TiN). The first insulating layer 302 can be a high dielectric material.

[0044] Figure 7 This is a schematic diagram of another semiconductor device according to this exemplary embodiment. In some exemplary embodiments, two memory cell columns are arranged sequentially in a first direction, with a bit line 400 between the two memory cell columns and the bit line 400 between them. Multiple memory cells 200 in the two memory cell columns share the bit line 400. The source 101 of the transistor 100 in each of the multiple memory cells 200 in the two memory cell columns is connected to the bit line 400.

[0045] Figure 8 This is a schematic diagram of a preparation method of this exemplary embodiment. Figures 9 to 21 This is a schematic diagram of the semiconductor device fabrication process. In some exemplary embodiments, such as... Figures 8 to 21 As shown, a method for fabricating a semiconductor device is applied to... Figure 7 The semiconductor device shown is fabricated using the following methods: S1: Semiconductor layers and sacrificial layers are alternately grown on the substrate to obtain a stacked structure.

[0046] Figure 9 This is a first fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 9 As shown, semiconductor layers and sacrificial layers are alternately grown on a substrate to obtain a stacked structure, including: Semiconductor layers 802 and sacrificial layers 801 are alternately grown on substrate 700. For example, a sacrificial layer 801 is first grown on substrate 700, with this sacrificial layer 801 in contact with substrate 700. Then, a semiconductor layer 802 is grown on the side of the sacrificial layer 801 away from substrate 700, and so on, alternatingly growing other sacrificial layers 801 and semiconductor layers 802. The semiconductor layer 802 may be made of semiconductor materials, such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon. In this example, the semiconductor layer 802 may be made of silicon. The semiconductor layer 802 can be formed by a thin film deposition process, including but not limited to CVD, PVD, ALD, sputtering, evaporation, or combinations thereof. The sacrificial layer 801 may be made of silicon germanium (SiGe). Multiple semiconductor layers 802 and multiple sacrificial layers 801 are stacked to form a stacked structure 800.

[0047] The substrate 700 may be constructed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 700 may be a single-layer structure or a multi-layer structure. For example, the substrate 700 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 700 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. In this example, the substrate 700 may be a silicon substrate.

[0048] S2: Forms a supporting structure.

[0049] Figure 10 This is a second fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 11 This is a third fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 12 This is a fourth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 12 for Figure 11 A schematic diagram of the cross-section of d-d' in some exemplary embodiments, such as Figures 10 to 12 As shown, a supporting structure is formed, including: First, the stacked structure 800 is etched for the first time, wherein the semiconductor layer 802 is etched at both ends in the first direction to form a first groove 803, so that the semiconductor layer 802 is recessed relative to the sacrificial layer 801 at both ends in the first direction, just as... Figure 10 As shown.

[0050] Subsequently, support structures 900 are deposited on the substrate 700. Two support structures 900 are located at opposite ends of the stacked structure 800 in the first direction. The support structures 900 fill the aforementioned first groove 803, as... Figure 11 and Figure 12 As shown, the support structure 900 provides support for subsequent fabrication processes, preventing the stacked structure 800 from collapsing. The material of the support structure 900 can be silicon nitride.

[0051] S3: Etch trenches to form semiconductor pillars.

[0052] Figure 13 This is a fifth schematic diagram illustrating the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as... Figures 11 to 13As shown, etching trenches to form semiconductor pillars includes: performing a second etching on the stacked structure 800, wherein the etching process forms a plurality of trenches 804 extending along a first direction. The trenches 804 extend from the end face of the stacked structure 800 away from the substrate 700 to the substrate 700, and the plurality of trenches 804 are arranged at equal intervals in a third direction. The plurality of trenches 804 divide the semiconductor layer 802 into a plurality of semiconductor strips 802a, which extend along the first direction and are arranged in an array within the space formed by the first direction, the second direction, and the third direction. Each semiconductor strip 802a includes two semiconductor pillars 600 arranged sequentially in the first direction, and the two semiconductor pillars 600 are connected and are a single structure. Each semiconductor pillar 600 includes a first region 600a, a second region 600b, and a third region 600c arranged sequentially along a first direction. The first regions 600a of two semiconductor pillars 600 in a semiconductor strip 802a are connected, such that the third regions 600c of the two semiconductor pillars 600 are connected by corresponding support structures 900 to form support.

[0053] S4: Etch the sacrificial layer while retaining the sacrificial layer covering the second region.

[0054] In some exemplary embodiments, such as Figure 12 and Figure 13 As shown, the sacrificial layer is etched while retaining the sacrificial layer covering the second region, including: The sacrificial layer 801 is etched, but not all of it is completely removed. The sacrificial layer 801 is retained on the second region 600b of the semiconductor pillar 600, covering both the end face near the substrate 700 and the end face away from the substrate 700 in the second direction. This results in the remaining sacrificial layer 801 covering both the end face near the substrate 700 and the end face away from the substrate 700 in the second direction of the semiconductor pillar 600.

[0055] S5: Form a second semiconductor layer on the semiconductor pillar.

[0056] Figure 14 This is a sixth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 15 This is a seventh fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 16 This is an eighth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figures 13 to 16 As shown, a second semiconductor layer is formed on the semiconductor pillar, including: First, an oxide thin film 601 is deposited on the end faces of the first region 600a of the semiconductor pillar 600, both near and away from the substrate 700 in the second direction. The oxide thin film 601 can be a phosphorus-containing oxide thin film. It is a transparent conductive thin film material with high transmittance and low resistivity in the visible light range, and can be deposited using atomic layer deposition (ALD) technology. The oxide thin film 601 covers the end faces of the first region 600a of the semiconductor pillar 600, both near and away from the substrate 700 in the second direction. The sacrificial layer 801 covers the second region 600b, facilitating the deposition of the oxide thin film 601 and preventing it from affecting the doping of the second region 600b.

[0057] Next, annealing is performed. The annealing process allows the dopant elements (phosphorus or arsenic) in the oxide film 601 to diffuse into the first region 600a of the semiconductor pillar 600, improving the material of the first region 600a. Annealing is a commonly used technique in semiconductor manufacturing, mainly used to control the diffusion depth of dopant impurities and increase the impurity activation concentration. This forms a sandwich structure in the first region 600a of the semiconductor pillar 600. This sandwich structure includes a first sublayer 1012a, a first semiconductor layer 1011, and a second sublayer 1012b sequentially stacked in the second direction. The first sublayer 1012a is located on the side of the first semiconductor layer 1011 away from the substrate 700. The first sublayer 1012a can be formed by the diffusion of dopant elements (phosphorus or arsenic) in the oxide film 601 into the first region 600a of the semiconductor pillar 600 on the side away from the substrate 700. The second sublayer 1012b is located on the side of the first semiconductor layer 1011 near the substrate 700. The second sublayer 1012b can be formed by doping the first region 600a of the semiconductor pillar 600 near the substrate 700 by a doping element (phosphorus or arsenic) in the oxide thin film 601 diffused into the substrate 700.

[0058] Subsequently, the third region 600c of the semiconductor pillar 600 is doped using the aforementioned ALD deposition technology and annealing process, which diffuses phosphorus or arsenic into the third region 600c of the semiconductor pillar 600, changing the material of the third region 600c so that it is no longer just silicon.

[0059] S6: Remove the sacrificial layer.

[0060] Figure 17 This is a ninth schematic diagram illustrating the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as... Figure 16 and Figure 17As shown, removing the sacrificial layer includes removing the remaining sacrificial layer 801 by etching, that is, removing the sacrificial layer 801 covering the second region 600b, so that the second region 600b is exposed at the end face near the substrate 700 and the end face away from the substrate 700 in the second direction, and the second region 600b of the semiconductor pillar 600 forms the channel region 102 of the transistor.

[0061] S7: Deposit to form the gate.

[0062] Figure 18 This is a tenth schematic diagram of the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 15 , Figure 17 and Figure 18 As shown, a gate is deposited to form a gate, including: First, an insulating film is deposited on the second region 600b of the semiconductor pillar 600 at both the end face away from the substrate 700 and the end face near the substrate 700 to form a gate insulating layer 105. Then, a conductive material film is deposited on the side of the gate insulating layer 105 away from the semiconductor pillar 600 to form a gate 104. Thus, the structure of the transistor 100 is formed. The first region 600a of the semiconductor pillar 600, after doping in step S5, forms the source of the transistor 100. The second region 600b of the semiconductor pillar 600 forms the channel region 102 of the transistor 100. The third region 600c of the semiconductor pillar 600, after doping in step S5, forms the drain of the transistor 100.

[0063] S8: Forms a capacitor.

[0064] Figure 19 This is an eleventh fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figures 17 to 19 As shown, a capacitor is formed by sequentially growing an inner electrode plate 301, a first insulating layer 302, and an outer electrode plate 303 around the outer periphery of the third region 600c of the semiconductor pillar 600, away from the channel region 102, to obtain a capacitor 300 surrounding the third region 600c. The inner electrode plate 301 and the outer electrode plate 303 can be made of metal or a conductive metal compound, and the first insulating layer 302 can be a high-dielectric-constant dielectric material. For example, the outer electrode plates 303 of a row of memory cells stacked along the second direction can be formed as a single unit.

[0065] S9: Form bit line.

[0066] Figure 20 This is a schematic diagram illustrating the twelfth fabrication step of a semiconductor device according to an exemplary embodiment. Figure 21 This is a thirteenth schematic diagram of the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 20 and Figure 21As shown, a bit line is formed, including: First, the semiconductor strip is etched at the junction of the two semiconductor pillars 600 of the semiconductor strip. After etching, a first gap 602 is formed, which separates the two semiconductor pillars 600 of the semiconductor strip.

[0067] Subsequently, a conductive thin film is deposited on the substrate 700, with the deposition location corresponding to the first gap 602, so that the conductive thin film forms a bit line 400 extending along the second direction after deposition. Thus, the fabrication process of the semiconductor device is completed.

[0068] In some exemplary embodiments, a method for fabricating a semiconductor device is applied to Figure 7 The semiconductor device shown includes: Semiconductor layers and sacrificial layers are alternately grown on a substrate to obtain a stacked structure, and the stacked structure is etched. The remaining semiconductor layers form multiple semiconductor pillars, which extend along the first direction. The second semiconductor layer is formed on the semiconductor pillar.

[0069] In some exemplary embodiments, an electronic device includes the transistor described above, or the semiconductor device described above, or a semiconductor device obtained by the semiconductor device fabrication method described above. This electronic device can be any electronic product with storage functionality, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0070] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0071] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0072] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0073] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0074] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0076] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A transistor, characterized in that, It includes a source, a channel region, and a drain arranged sequentially along a first direction, and a gate insulated on the outer periphery of the channel region; The source includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are connected to the channel region at the same end in the first direction. The second semiconductor layer is located on the side of the first semiconductor layer that is close to the gate in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is less than that of the second semiconductor layer.

2. The transistor according to claim 1, characterized in that, The doping concentration of the first semiconductor layer is set to be the same as the doping concentration of the channel region.

3. The transistor according to claim 2, characterized in that, The first semiconductor layer is made of the same material as the channel region, and the first semiconductor layer and the channel region are integrally formed.

4. The transistor according to claim 3, characterized in that, The first semiconductor layer is made of silicon, and the second semiconductor layer is made of N-type heavily doped silicon.

5. The transistor according to claim 1, characterized in that, The gate includes a first gate and a second gate, the first gate and the second gate being located on both sides of the channel region in a second direction, the second direction being perpendicular to the first direction; The second semiconductor layer includes a first sublayer and a second sublayer, wherein the first sublayer, the first semiconductor layer and the second sublayer are stacked sequentially in the second direction.

6. The transistor according to claim 5, characterized in that, The first sublayer is located on the side of the first semiconductor layer in the second direction closer to the first gate, and the second sublayer is located on the side of the first semiconductor layer in the second direction closer to the second gate. The material of the first sublayer is set to be the same as that of the second sublayer.

7. The transistor according to claim 5, characterized in that, The thickness of one of the first sub-layer and the second sub-layer is set to be not less than the thickness of the first semiconductor layer; The thickness of the first semiconductor layer is the maximum distance between the end face of the first semiconductor layer near the first sub-layer and the end face near the second sub-layer. The thickness of the first sub-layer is the maximum distance between the end face of the first sub-layer near the first semiconductor layer and the end face away from the first semiconductor layer. The thickness of the second sub-layer is the maximum distance between the end face of the second sub-layer near the first semiconductor layer and the end face away from the first semiconductor layer.

8. The transistor according to claim 5, characterized in that, The first sublayer, the first semiconductor layer, and the second sublayer have their orthogonal projections on a first plane that overlap, and the first plane is perpendicular to the second direction and parallel to the first direction.

9. The transistor according to claim 1, characterized in that, The gate surrounds the channel region and forms a ring, thus forming a ring gate structure; The first semiconductor layer extends along the first direction, and the second semiconductor layer covers the circumferential surface of the first semiconductor layer and forms a ring.

10. A semiconductor device, characterized in that, It includes multiple memory cells, which are stacked and periodically distributed along a direction perpendicular to the substrate; Each of the memory cells includes a transistor, the transistor including a source, a channel region and a drain arranged sequentially along a first direction, and a gate insulated on the channel region, the gate being located on both sides of the channel region in a second direction, the first direction being parallel to the substrate and the second direction being perpendicular to the substrate; The source includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are connected to the channel region at the same end in the first direction. The second semiconductor layer is located on the side of the first semiconductor layer closer to the gate in the second direction. The doping concentration of the first semiconductor layer is less than that of the second semiconductor layer.

11. The semiconductor device according to claim 10, characterized in that, The second semiconductor layer includes a first sublayer and a second sublayer, wherein the first sublayer is located on the side of the first semiconductor layer away from the substrate, and the second sublayer is located on the side of the first semiconductor layer closer to the substrate.

12. The semiconductor device according to claim 10, characterized in that, The memory cell further includes a capacitor, and the transistor and the capacitor are arranged sequentially in the first direction, with the capacitor positioned close to the drain of the transistor.

13. The semiconductor device according to claim 11, characterized in that, It also includes multiple bit lines and multiple word lines. The bit line extends in a direction perpendicular to the substrate, and the transistors of the plurality of memory cells stacked in a direction perpendicular to the substrate are all connected to a bit line, the bit line being connected to the end of the source away from the channel region. The gate includes a first gate and a second gate, wherein the first gate is located on the side of the channel region away from the substrate, and the second gate is located on the side of the channel region close to the substrate; The word lines extend along a third direction, and each word line is formed by connecting the first gate or the second gate on the transistors of a plurality of memory cells arranged along the third direction, which is perpendicular to the first direction and the second direction.

14. A method for fabricating a semiconductor device, characterized in that, Applied to the semiconductor device of claim 10, comprising: Semiconductor layers and sacrificial layers are alternately grown on a substrate to obtain a stacked structure, and the stacked structure is etched. The remaining semiconductor layers form multiple semiconductor pillars, which extend along the first direction. The second semiconductor layer is formed on the semiconductor pillar.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The semiconductor pillar includes a first region, a second region, and a third region arranged sequentially along the first direction; The formation of the second semiconductor layer on the semiconductor pillar includes: An oxide film is deposited on the surface of the first region; Annealing causes the doping elements in the oxide film to diffuse into the first region, forming the second semiconductor layer.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, Depositing an oxide film on the surface of the first region includes: The sacrificial layer is etched while retaining the sacrificial layer covering the second region on the side face of the second region near the substrate and the side face of the second region away from the substrate in a second direction, the second direction being perpendicular to the substrate; An oxide film is deposited on the end face of the first region in the second direction, on the side close to the substrate and the side far from the substrate.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, Also includes: Remove the remaining sacrifice layer.

18. An electronic device, characterized in that, It includes a transistor as described in any one of claims 1 to 9, or a semiconductor device as described in any one of claims 10 to 13, or a semiconductor device formed by a method of fabricating a semiconductor device as described in any one of claims 14 to 17.

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