Semiconductor device and method

Abstract

The invention relates to a semiconductor device and a method. A semiconductor device and a method of forming the same are provided. The semiconductor device may include: a source / drain region; a first nanostructure along a sidewall of the source / drain region; a gate structure surrounding the first nanostructure; a first gate spacer along sidewalls of the first portion of the gate structure; a first dielectric layer over the source / drain region and the gate structure; a first conductive contact extending through the first dielectric layer and electrically connected to the source / drain region; and a first dielectric liner along a sidewall of the first conductive contact. The first dielectric liner may extend from a level of a top surface of the first conductive contact to a top surface of the source / drain region. The first dielectric liner may be in contact with a sidewall of the first gate spacer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a source / drain region; a first nanostructure along a sidewall of the source / drain region; a gate structure surrounding the first nanostructure; a first gate spacer along a sidewall of a first portion of the gate structure; a first dielectric layer located over the source / drain region and the gate structure; a first conductive contact extending through the first dielectric layer and electrically connected to the source / drain region; and a first dielectric liner along a sidewall of the first conductive contact, wherein the first dielectric liner extends horizontally from a top surface of the first conductive contact to a top surface of the source / drain region, and wherein the first dielectric liner contacts a sidewall of the first gate spacer.

[0005] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a first nanostructure on a semiconductor substrate; depositing a first gate spacer on the first nanostructure; forming a first opening through the first nanostructure, wherein the first opening exposes the sidewalls of the first nanostructure; growing source / drain regions in the first opening, wherein the source / drain regions are located on the sidewalls of the first nanostructure, and wherein a first portion of the source / drain regions is located on the sidewalls of the first gate spacer; forming a first contact etch stop layer on the source / drain regions, and in the first opening... A first dielectric layer is formed over a contact etch stop layer, wherein a first portion of the first contact etch stop layer is located on a sidewall of the first gate spacer; a second opening is formed through the first dielectric layer, wherein forming the second opening includes at least partially removing a first portion of the source / drain region located on the sidewall of the first gate spacer and a first portion of the first contact etch stop layer; a first dielectric liner is deposited in the second opening, wherein the first dielectric liner comprises a low-k material; and a first conductive contact is formed in the second opening, wherein the first conductive contact is electrically connected to the source / drain region.

[0006] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a first nanostructure on a semiconductor substrate; depositing a first gate spacer on the first nanostructure; growing source / drain regions, wherein a first portion of the source / drain regions is located on a sidewall of the first gate spacer, and wherein a second portion of the source / drain regions is located on a sidewall of the first nanostructure; forming a first contact etch stop layer on the source / drain regions, wherein a first portion of the first contact etch stop layer is located on a sidewall of the first gate spacer; forming a first opening by removing the first portion of the first contact etch stop layer and the first portion of the source / drain regions, wherein the first opening exposes a sidewall of the first gate spacer; depositing a first dielectric liner in the first opening and on the sidewall of the first gate spacer; and forming a first conductive contact in the first opening. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1An example of a nanostructured field-effect transistor (nano-FET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B and Figure 24C This is a view of an intermediate process for manufacturing a semiconductor device including a nanostructured FET, according to some embodiments.

[0010] Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B and Figure 27C This is a view of an intermediate process for manufacturing a semiconductor device including a nanostructured FET, according to some embodiments.

[0011] Figure 28A , Figure 28B , Figure 28C , Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B and Figure 30C This is a view of an intermediate process for manufacturing a semiconductor device including a nanostructured FET, according to some embodiments.

[0012] Figure 31A , Figure 31B and Figure 31C This is a view of a semiconductor device including a nanostructured FET according to some embodiments.

[0013] Figure 32A , Figure 32B and Figure 32C This is a view of a semiconductor device including a nanostructured FET according to some embodiments.

[0014] Figure 33A , Figure 33B and Figure 33C This is a view of a semiconductor device including a nanostructured FET according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0017] Various embodiments provide a semiconductor device and a method of forming the same. The semiconductor device may include a stack of nanostructures, a gate structure surrounding each nanostructure of the stack, source / drain regions located on the sidewalls of the nanostructure stack, and conductive contacts located above the source / drain regions. The semiconductor device may also include a spacer between an upper portion of the gate structure and the conductive contacts. By at least partially removing portions of the source / drain regions from the sidewalls of the spacer and adding one or more dielectric linings to the sidewalls of the spacer, sufficient electrical insulation can be established between the conductive contacts and the gate structure, thereby eliminating or reducing parasitic capacitance between the conductive contacts and the gate structure. Therefore, the performance and reliability of the semiconductor device can be improved.

[0018] Some of the embodiments discussed herein are described in the context of semiconductor devices including nanostructured FETs. However, various embodiments may be applied to dies that replace or are combined with nanostructured FETs to include other types of transistors (e.g., FinFETs, VFETs, CFETs, planar transistors, etc.).

[0019] Figure 1An example of a nanostructured FET (e.g., nanowire FET, nanosheet FET, etc.) is shown in a three-dimensional view. The nanostructured FET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) situated above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as the channel region of the nanostructured FET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and from between adjacent STI regions 68. Although the STI regions 68 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an STI region. Furthermore, although the bottom portion of the fin 66 is shown as a single continuous material with respect to the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68. A gate dielectric layer 100 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0020] Figure 1 Reference sections used in the following figures are further illustrated. Reference section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanostructure FET. Reference section B-B' is parallel to reference section A-A' and extends through the epitaxial source / drain regions 92 of the plurality of nanostructure FETs. Reference section C-C' is perpendicular to reference section A-A' and parallel to the longitudinal axis of the fin 66 of the nanostructure FET and in, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nanostructure FET. Reference section D-D' is parallel to reference section C-C' and extends through the plurality of gate electrodes 102. For clarity, the following figures refer to these reference sections. Some embodiments discussed herein are discussed in the context of nanostructure FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in FinFETs.

[0021] Figures 2 to 24C This is a view of an intermediate process for manufacturing a semiconductor device including a nanostructured FET device, according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12 , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It shows along Figure 1 The cross-sectional view of reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B and Figure 24B It shows along Figure 1 The cross-sectional view of reference section B-B' is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C and Figure 24C It shows along Figure 1 The cross-sectional view of the reference section C-C' is shown.

[0022] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0023] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type nanostructure FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type nanostructure FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0024] Further in Figure 2In this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of a nanostructured FET in an n-type region 50N and a p-type region 50P. In some embodiments, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nanostructured FET in the n-type region 50N, and the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nanostructured FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of the nanostructure FET in the n-type region 50N, and the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of the nanostructure FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form channel regions of the nanostructure FET in both the n-type region 50N and the p-type region 50P.

[0025] For illustrative purposes, the multilayer stack 64 is shown as three layers comprising each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material, such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material, such as silicon.

[0026] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. This allows the first semiconductor layer 51 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanostructured FET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanostructured FET.

[0027] exist Figure 3 In some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0028] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fin 66 and nanostructure 55, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0029] For illustrative purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be larger or thinner than the width of the fin 66 in the p-type region 50P. Furthermore, while each of the fins 66 and nanostructures 55 is shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0030] exist Figure 4In the substrate 50, adjacent fins 66 form shallow trench isolation (STI) regions 68. The STI regions 68 can be formed by depositing an insulating material on the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. Once the insulating material is formed, an annealing process can be performed. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers.

[0031] A removal process can then be applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etching back, or a combination thereof can be employed. This planarization process exposes the nanostructure 55 such that, after the planarization process is complete, the top surfaces of the nanostructure 55 and the insulating material can be substantially coplanar or flush. The insulating material can then be recessed to form STI regions 68. The insulating material can be recessed such that the upper portions of the fins 66 in the n-type regions 50N and p-type regions 50P protrude between adjacent STI regions 68. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material and etches the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructure 55. For example, diluted hydrofluoric acid can be used when the insulating material is an oxide. After the removal process, the top surface of the STI regions 68 can have a flat surface (as shown), a convex surface, a concave surface, or a combination thereof.

[0032] The above about Figures 2 to 4 The described process is an example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using a mask and epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include alternating semiconductor materials as described above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can avoid prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0033] Furthermore, for illustrative purposes, the first semiconductor layer 51 (and the resulting first nanostructure 52) is shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N, and the second semiconductor layer 53 (and the resulting second nanostructure 54) is shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer 51 may comprise different materials in the p-type region 50P and the n-type region 50N. In some embodiments, the second semiconductor layer 53 may comprise different materials in the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer 51 may comprise different materials in the p-type region 50P and the n-type region 50N, and the second semiconductor layer 53 may comprise different materials in the p-type region 50P and the n-type region 50N.

[0034] Further in Figure 4 In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be implemented using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0035] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, with the photoresist serving as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region at a concentration of approximately 10. 13atoms / cm 3 To about 10 14 atoms / cm 3 Within the range. After implantation, the photoresist can be removed, for example, by an acceptable ashing process. After implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, but in-situ doping and implantation doping can be used together.

[0036] exist Figure 5 In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0037] Figures 6A to 24C Various additional processes in fabricating nanostructured FEI devices are illustrated according to some embodiments. Figures 6A to 24C Features of either or both of the n-type region 50N or the p-type region 50P are shown. Figures 6A to 6C In this process, a mask 78, a dummy gate 76, and a dummy gate dielectric 71 are formed. The dummy gate 76 and the dummy gate dielectric 71 can be collectively referred to as the dummy gate structure. The mask layer 74 can be patterned using appropriate photolithography and etching processes (see [link to image]). Figure 5A mask 78 is formed by etching. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 using a suitable etching process to form the dummy gate 76 and the dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66 and the corresponding overlying nanostructure 55. The pattern of the mask 78 can be used to separate each dummy gate 76 from its adjacent counterpart. The dummy gate 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0038] exist Figures 7A to 7C In this process, a spacer 81 is formed. The spacer 81 may also be referred to as a gate spacer. The spacer 81 can self-align with subsequently formed source / drain regions and protect the dummy gate dielectric 71 and dummy gate 76 during subsequent etching processes. The spacer 81 can be a single layer of a single material or multiple sublayers of different materials with different etching rates. In some embodiments, the spacer 81 comprises two sublayers of different materials with different etching rates, which may be selected from silicon oxide, silicon nitride, silicon oxynitride, etc. The spacer 81 can be formed by forming a spacer layer through thermal oxidation or a suitable deposition process (e.g., CVD, ALD, etc.) and then patterning the spacer layer through a suitable etching process (e.g., isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process) etc.).

[0039] Spacer layers can be formed on the top surface of STI region 68; the top surface and sidewalls of fin 66, nanostructure 55, and mask 78; and the sidewalls of dummy gate 76 and dummy gate dielectric 71. After etching, spacer 81 can remain on the top surface of STI region 68 and the sidewalls of fin 66 and nanostructure 55, as shown below. Figure 7B As shown. After the etching process, spacer 81 can remain on the top surface of nanostructure 55 and on the sidewalls of mask 78, dummy gate 76, and dummy gate dielectric 71, as shown. Figure 7C As shown.

[0040] exist Figures 8A to 8C In this structure, a first recess 86 is formed in the fin 66 and the nanostructure 55. The first recess 86 can extend through the first nanostructure 52 and the second nanostructure 54, and into the fin 66. Figure 8BAs shown, the top surface of the STI region 68 (e.g., the top surface of the fin 66) may be flush with the bottom surface of the first recess 86. In some embodiments, the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68. The first recess 86 can be formed by partially removing the fin 66 and nanostructure 55 using an anisotropic etching process such as RIE, NBE, etc. Spacer 81 and mask 78 can mask portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the first recess 86. Each layer of the nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching after the first recess 86 has reached the desired depth.

[0041] exist Figures 9A to 9C In the process, the portion of the first nanostructure 52 exposed by the first recess 86 is etched to form the second recess 88. Although in Figure 9C The sidewalls of the first nanostructure 52 adjacent to the second recess 88 are shown as straight, but the sidewalls may be recessed or convex. The first nanostructure 52 can be etched using an isotropic etching process (e.g., wet etching). In embodiments where the first nanostructure 52 includes silicon, germanium, etc., and the second nanostructure 54 includes silicon, silicon carbide, etc., the first nanostructure 52 can be etched using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0042] exist Figures 10A to 10C An internal spacer 90 is formed in the second recess 88. The internal spacer 90 provides electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure, as discussed in more detail below. The internal spacer 90 may extend along the sidewalls of the first nanostructure 52 and partially contact the top and bottom surfaces of the previously exposed second nanostructure 54. The internal spacer 90 can be formed by... Figures 9A to 9C An internal spacer layer (not shown separately) is deposited on the structure shown, and then etched to form the internal spacer layer. The internal spacer layer can be deposited by a suitable deposition process (e.g., CVD, ALD, etc.). The internal spacer layer may include a dielectric material, such as silicon nitride, etc. The material of the internal spacer layer may have a dielectric constant (k) of less than about 3.5. The internal spacer layer can be etched by an anisotropic etching process (e.g., RIE, NBE, etc.) to form the internal spacer 90. For example, the outer wall of the internal spacer 90 is... Figure 10C The inner spacer 90 is shown as straight and flush with the sidewall of the second nanostructure 54. In some embodiments, the outer sidewall of the inner spacer 90 may extend beyond the sidewall of the second nanostructure 54 (e.g., protruding) or be recessed from the sidewall of the second nanostructure 54 (e.g., recessed).

[0043] exist Figures 11A to 11C In the first recess 86, an epitaxial source / drain region 92 is formed. One or more epitaxial source / drain regions 92 may individually or collectively refer to a source or drain, depending on the context. In some embodiments, the epitaxial source / drain regions 92 may apply stress to the second nanostructure 54, thereby improving performance. Figure 11C As shown, epitaxial source / drain regions 92 are formed in the first recess 86, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. The epitaxial source / drain regions 92 may be located on the sidewalls of the second nanostructure 54, the internal spacer 90, and the spacer 81. The top surface of the epitaxial source / drain regions 92 may be above the top surface of the second nanostructure 54C.

[0044] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by masking the p-type region 50P (e.g., a PMOS region). Subsequently, the epitaxial source / drain region 92 is epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc.

[0045] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Subsequently, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material that applies compressive strain to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc.

[0046] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing process. The impurity concentration of the source / drain region can be approximately 1 × 10⁻⁶. 19 atoms / cm 3 1×10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0047] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper portion of the epitaxial source / drain regions 92 may have crystal faces that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these crystal faces cause adjacent epitaxial source / drain regions 92 of the same nanostructure FET to merge, such as... Figure 11B As shown. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process, as... Figure 12 As shown.

[0048] The epitaxial source / drain region 92 may include one or more semiconductor material layers. In some embodiments, the epitaxial source / drain region 92 includes a first liner layer 92A on the sidewall of the second nanostructure 54, a second liner layer 92B on the first liner layer 92A, and a filling layer 92C on the second liner layer 92B, such as... Figure 11C As shown. The first liner layer 92A, the second liner layer 92B, and the fill layer 92C can be formed from different semiconductor materials and / or can be doped with different dopant concentrations. The first liner layer 92A can be grown first, the second liner layer 92B can be grown on the first liner layer 92A, and the fill layer 92C can be grown on the second liner layer 92B.

[0049] exist Figures 13A to 13C In Figures 11A to 11C A first interlayer dielectric (ILD) 96 is deposited on the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. A contact etch stop layer (CESL) 94 may be disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and spacer 81. CESL 94 may include a dielectric material having an etch rate different from that of the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0050] exist Figures 14A to 14CIn this process, a planarization process such as CMP can be performed to make the top surfaces of the first ILD 96 and CESL 94 flush with the top surface of the dummy gate 76 or mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, as well as portions of the spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, spacer 81, ILD 96, and CESL 94 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surfaces of the first ILD 96 and CESL 94 flush with the top surfaces of the mask 78 and spacer 81.

[0051] exist Figures 15A to 15C In one or more etching processes, a dummy gate 76 and a dummy gate dielectric 71 are removed to form a third recess 98. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 and the dummy gate dielectric 71 at a rate faster than the first ILD 96 and / or the spacer 81. Each third recess 98 exposes and / or overlays a portion of the nanostructure 55 that will serve as a channel region in the subsequently completed nanostructure FET. The portion of the nanostructure 55 that can serve as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During the etching process, the dummy gate dielectric 71 may serve as an etch stop layer when the dummy gate 76 is removed and may be removed after the dummy gate 76 is removed.

[0052] exist Figures 16A to 16C In this process, the first nanostructure 52 can be removed, which extends the third recess 98. Removing the first nanostructure 52 may include using a suitable etching process, such as an isotropic etching process. This etching process selectively removes material from the first nanostructure 52 without significantly removing material from the second nanostructure 54, the fin 66, or the internal spacer 90. In embodiments where the first nanostructure 52 comprises silicon-germanium and the second nanostructure 54 comprises silicon, an etching process utilizing tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like is used to remove the first nanostructure 52.

[0053] exist Figures 17A to 17CIn the third recess 98, a gate dielectric layer 100 and a gate electrode 102 are formed. The gate dielectric layer 100 may be conformally deposited in the third recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, CESL 94, spacer 81, and STI region 68, and on the sidewalls of spacer 81 and internal spacer 90.

[0054] In some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer situated on top of the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, in which case the gate dielectric layer 100 may have a dielectric constant (k) greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0055] Gate electrodes 102 are deposited on the gate dielectric layer 100 and fill the remaining portion of the third recess 98. Gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in Figure 17A and Figure 17C A single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50.

[0056] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0057] After filling the third recess 98, a planarization process such as CMP can be performed to remove material from the gate electrode 102 and excess portions of the gate dielectric layer 100 above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanostructured FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the gate structure.

[0058] exist Figures 18A to 18C In the recess, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed, the gate mask 104 is formed in the recess, and the second ILD 106 is formed on the first ILD 96 and the gate mask 104. Figure 18C The following figures, along the same cross section C-C', show the region of the structure above substrate 50 including the interface between fin 66 and STI region 68. Recesses may be formed directly above the gate structure and between opposing portions of spacer 81. Gate mask 104 may comprise one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc. A planarization process may be performed to remove excess material from gate mask 104. Second ILD 106 may be formed of a dielectric material, such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, such as CVD, PECVD, FCVD, etc. CESL 105 may be provided prior to the deposition of second ILD 106. CESL 105 may comprise a dielectric material having a different etch rate than the material of second ILD 106, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0059] exist Figures 19A to 19C An opening 108 is formed in the middle. The opening 108 may include an opening 108A, which may be formed through the second ILD 106, CESL 105, first ILD 96, and CESL 94 to expose the epitaxial source / drain region 92, such as... Figure 19Band Figure 19C As shown. Figure 19B An embodiment is shown in which opening 108A exposes one of the merged epitaxial source / drain regions 92. In other embodiments, opening 108A exposes both of the merged epitaxial source / drain regions 92. Opening 108 may include opening 108B, which may be formed through the second ILD 106 and CESL 105 to expose the first ILD 96 and CESL 94. In opening 108A, the top portion of the epitaxial source / drain region 92 adjacent to the spacer 81 may be removed by an etching process, which reduces the parasitic capacitance between the source / drain contacts subsequently formed over the epitaxial source / drain region 92 and the adjacent gate structure, as discussed in more detail below. After the etching process, the epitaxial source / drain region 92 may have a recessed top surface below the top surface of the second nanostructure 54C.

[0060] like Figure 19C As shown, the first ILD 96 and CESL 94 above the epitaxial source / drain region 92 can be completely removed, and the opening 108A may not have the first ILD 96 and CESL 94. The sidewalls of the spacer 81 can be fully exposed, and the spacer 81 can be completely separated from the epitaxial source / drain region 92. The opening 108A may have a width W1, which can be the distance between the sidewalls of the spacers 81 located on opposite sides of the opening 108A. The epitaxial source / drain region 92 may have a width W2, which can be the distance between the sidewalls of the inner spacers 90 located on opposite sides of the epitaxial source / drain region 92. The width W1 may be the same as the width W2. In the opening 108B, the upper portions of the first ILD 96 and CESL 94 can be completely removed by an etching process. After the etching process, the first ILD 96 may have a recessed top surface, and the sidewalls of the spacer 81 may be partially exposed. Opening 108A may have a depth D1, and opening 108B may have a depth D2. Depth D2 may be greater than depth D1, which may be due to etching selectivity during the etching process.

[0061] The opening 108 can be formed by a series of suitable etching processes, such as anisotropic dry etching processes like RIE, NBE, etc., using fluorine-based etchants, etc. A hard mask (not shown) can be formed on the second ILD 106, and the pattern of the hard mask can be used to define the opening 108 during the etching process. In some embodiments, the opening in the hard mask may have the same width as the opening 108. In some embodiments, the opening in the hard mask may have a smaller width than the opening 108. The hard mask can be removed after the etching process.

[0062] exist Figures 20A to 20C In Figures 19A to 19CA dielectric liner layer 107' is formed over the structure shown. The dielectric liner layer 107' may be formed on the top surface of the second ILD 106, and on the surface exposed by the opening 108, including the sidewalls of the second ILD 106, CESL 105, and spacer 81, and the top surfaces of the epitaxial source / drain regions 92, the first ILD 96, and CESL 94. The dielectric liner layer 107' may include a material having a low dielectric constant (k), which may be referred to as a low-k material, such as silicon carbide oxycarbide, silicon carbonitride oxycarbonitride, silicon carbonitride, boron nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, etc. The dielectric liner layer 107' may be formed by a suitable deposition process, such as CVD, ALD, etc.

[0063] exist Figures 21A to 21C In this process, the horizontal portion of the dielectric liner layer 107' (e.g., the portion of the dielectric liner layer 107' on the top surface of the second ILD 106, the epitaxial source / drain region 92, and the first ILD 96) is removed. The remaining vertical portion of the dielectric liner layer 107' (e.g., the portion of the dielectric liner layer 107' on the sidewalls of the second ILD 106, CESL 105, and spacer 81) may be referred to as dielectric liner 107. The sidewalls of spacer 81 may be completely covered by dielectric liner 107. The horizontal portion of the dielectric liner layer 107' can be removed by a suitable anisotropic dry etching process (e.g., RIE, NBE, etc.), using fluorine-based etchants, etc. After the etching process, the top surface of the epitaxial source / drain region 92 is exposed.

[0064] exist Figures 22A to 22C In this embodiment, a silicide region 110 is formed on the top surface of an epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed as follows: first, a metal layer (not shown) is deposited on the exposed top surface of the epitaxial source / drain region 92, followed by a thermal annealing process. During the thermal annealing process, portions of the metal layer may react with portions of the epitaxial source / drain region 92 to form the silicide region 110. The metal layer may include a metallic material capable of reacting with the underlying semiconductor material of the epitaxial source / drain region 92 (e.g., silicon, silicon-germanium, germanium) to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other rare earth metals, or alloys thereof. Unreacted portions of the metal layer can then be removed by a suitable etching process. Although the silicide region 110 is referred to as a silicide region, it may also be a germanide region or a silicon-germanium region (e.g., a region comprising both silicides and germanides).

[0065] exist Figures 23A to 23CIn the middle, conductive contacts 112 are formed in opening 108. The conductive contacts 112 formed in opening 108A can be electrically connected to the epitaxial source / drain regions 92 through the silicide region 110, and can be referred to as source / drain contacts. The conductive contacts 112 formed in opening 108A can be formed on the sidewalls of the dielectric liner 107 and the top surface of the silicide region 110. The conductive contacts 112 formed in opening 108B can be used to establish electrical connections in a direction parallel to the substrate 50. The conductive contacts 112 formed in opening 108B can be formed on the sidewalls of the dielectric liner 107 and the top surface of the first ILD 96 and CESL 94.

[0066] like Figure 23C As shown, the conductive contact 112 is separated from the adjacent gate structure by the spacer 81 and the dielectric liner 107. The sidewalls of the conductive contact 112 can be completely covered by the dielectric liner 107. The combined width of the conductive contact 112 and the dielectric liner 107 located on the opposite side of the conductive contact 112 can be a width W1, which can be the same as the width W2 of the epitaxial source / drain region 92. Since a portion of the epitaxial source / drain region 92 is removed from the sidewall of the spacer 81, and a dielectric liner 107 (which may have a lower dielectric constant (k) than the epitaxial source / drain region 92) is added to the sidewall of the spacer 81, sufficient electrical insulation can be established between the conductive contact 112 and the adjacent gate structure, thereby eliminating or reducing the parasitic capacitance between the conductive contact 112 and the adjacent gate structure. Therefore, the performance and reliability of the subsequently formed semiconductor device can be improved.

[0067] The conductive contact 112 may be formed of a metallic material, such as copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc., and formed by appropriate processes, such as electroplating, CVD, PVD, etc. The conductive contact 112 may include a barrier layer (not shown) on its sidewalls and bottom surface. The barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and formed by appropriate processes, such as CVD, PVD, etc. A planarization process (e.g., CMP) may be performed to remove excess material from the top surface of the second ILD 106. After the planarization process, the second ILD 106, the dielectric liner 107, and the top surface of the conductive contact 112 may be flush with the process.

[0068] exist Figures 24A to 24C In this process, a conductive contact 114 is formed, which can also be called a gate contact. Figures 24A to 24CThe structure shown may be referred to as semiconductor device 120. A conductive contact 114 is formed through the second ILD 106, CESL 105, and gate mask 104 to electrically connect to the gate electrode 102. The conductive contact 114 may be formed by forming an opening to expose the top surface of the gate electrode 102, and then forming a metallic material, such as copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc., within the opening by a suitable process (e.g., electroplating, CVD, PVD, etc.). The conductive contact 114 may include a barrier layer (not shown) on its sidewalls and bottom surface. The barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and formed by a suitable process, such as CVD, PVD, etc. A planarization process (e.g., CMP) may be performed to remove excess material from the second ILD 106 and the top surface of the conductive contact 112. After the planarization process, the top surfaces of the second ILD 106, dielectric liner 107, conductive contact 112, and conductive contact 114 can be flush with each other within the process variation.

[0069] Figures 25A to 27C This is a view of an intermediate process for manufacturing a semiconductor device 120 according to some embodiments. Figure 25A , Figure 26A and Figure 27A It shows along Figure 1 The cross-sectional view of reference section A-A' is shown. Figure 25B , Figure 26B and Figure 27B It shows along Figure 1 The cross-sectional view of reference section B-B' is shown. Figure 25C , Figure 26C and Figure 27C It shows along Figure 1 The cross-sectional view of the reference section C-C' is shown.

[0070] Figures 25A to 25C The structure shown is based on Figures 20A to 20C The structures shown indicate that the same labels refer to the same features formed through the same process. Figures 25A to 25C In this process, a dielectric liner layer 109' is formed on top of the dielectric liner layer 107'. The dielectric liner layer 109' may include silicon carbide oxycarbonide, silicon carbonitride, silicon carbonitride, boron nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, etc. The dielectric liner layer 109' and the dielectric liner layer 107' may include different materials. The dielectric liner layer 109' may be formed by an appropriate deposition process, such as CVD, ALD, etc.

[0071] exist Figures 26A to 26CIn this process, the horizontal portions of dielectric liner layers 107' and 109' (e.g., portions of dielectric liner layers 107' and 109' on the top surfaces of the second ILD 106, the epitaxial source / drain region 92, and the first ILD 96) are removed. The remaining vertical portions of dielectric liner layers 107' and 109' (e.g., portions of dielectric liner layers 107' and 109' on the sidewalls of the second ILD 106, CESL 105, and spacer 81) may be referred to as dielectric liners 107 and 109. The horizontal portions of dielectric liner layers 107' and 109' can be removed by a series of suitable anisotropic dry etching processes (e.g., RIE, NBE, etc.) using fluorine-based etchants, etc. After the etching process, the top surface of the epitaxial source / drain region 92 is exposed.

[0072] Figures 27A to 27C A semiconductor device 120 according to some embodiments is shown. The semiconductor device 120 can be used with... Figures 26A to 26C The structure shown performs about Figures 22A to 24C The described process is subsequently obtained, wherein the same reference numerals refer to the same features formed by the same process. The conductive contact 112 formed in opening 108A may be formed on the sidewalls of dielectric liner 107 and dielectric liner 109, and on the top surface of silicide region 110. The conductive contact 112 formed in opening 108B may be formed on the sidewalls of dielectric liner 107 and dielectric liner 109, and on the top surface of first ILD 96 and CESL 94.

[0073] like Figure 27C As shown, the conductive contact 112 is separated from the adjacent gate structure by spacer 81, dielectric liner 107, and dielectric liner 109. The combined width of the conductive contact 112 and the dielectric liners 107 and 109 located on opposite sides of the conductive contact 112 can be a width W1, which can be the same as the width W2 of the epitaxial source / drain region 92. Since a portion of the epitaxial source / drain region 92 is removed from the sidewall of spacer 81, and dielectric liners 107 and 109 (which may have a lower dielectric constant (k) than the epitaxial source / drain region 92) are added to the sidewall of spacer 81, sufficient electrical insulation can be established between the conductive contact 112 and the adjacent gate structure, thereby eliminating or reducing the parasitic capacitance between the conductive contact 112 and the adjacent gate structure. Therefore, the performance and reliability of the semiconductor device 120 can be improved.

[0074] Figures 28A to 30C This is a view of an intermediate process for manufacturing a semiconductor device 120 according to some embodiments. Figure 28A , Figure 29A and Figure 30A It shows along Figure 1 The cross-sectional view of reference section A-A' is shown. Figure 28B , Figure 29B and Figure 30B It shows along Figure 1 The cross-sectional view of reference section B-B' is shown. Figure 28C , Figure 29C and Figure 30C It shows along Figure 1 The cross-sectional view of the reference section C-C' is shown.

[0075] Figures 28A to 30C The structure shown is based on Figures 21A to 21C The structures shown indicate that the same labels refer to the same features formed through the same process. Figures 28A to 28C In this structure, a dielectric liner layer 109' is formed on the top surfaces of the second ILD 106, the first ILD 96, and the epitaxial source / drain region 92, as well as on the sidewalls of the dielectric liner 107. The dielectric liner layer 109' may include silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, etc. The dielectric liner layer 109' and the dielectric liner 107 may include different materials. The dielectric liner layer 109' may be formed by a suitable deposition process, such as CVD, ALD, etc.

[0076] exist Figures 29A to 29C In this process, the horizontal portion of the dielectric liner 109' (e.g., the portion of the dielectric liner 109' on the top surface of the second ILD 106, the epitaxial source / drain region 92, and the first ILD 96) is removed. The remaining vertical portion of the dielectric liner 109' on the sidewall of the dielectric liner 107 may be referred to as the dielectric liner 109. The horizontal portion of the dielectric liner 109' can be removed by a suitable anisotropic dry etching process (e.g., RIE, NBE, etc.), using fluorine-based etchants, etc. After the etching process, the top surface of the epitaxial source / drain region 92 is exposed.

[0077] Figures 30A to 30C A semiconductor device 120 according to some embodiments is shown. The semiconductor device 120 can be used with... Figures 29A to 29C The structure shown performs about Figures 22A to 24C The described process is subsequently obtained, wherein the same reference numerals refer to the same features formed by the same process. The conductive contact 112 formed in opening 108A may be formed on the sidewalls of the dielectric liner 109 and the top surface of the silicide region 110. The conductive contact 112 formed in opening 108B may be formed on the sidewalls of the dielectric liner 109 and the top surface of the first ILD 96 and CESL 94. The conductive contact 112 can be separated from the dielectric liner 107 via the dielectric liner 109.

[0078] like Figure 30C As shown, the conductive contact 112 is separated from the adjacent gate structure by spacer 81, dielectric liner 107, and dielectric liner 109. The combined width of the conductive contact 112 and the dielectric liners 107 and 109 located on opposite sides of the conductive contact 112 can be a width W1, which can be the same as the width W2 of the epitaxial source / drain region 92. Since a portion of the epitaxial source / drain region 92 is removed from the sidewall of spacer 81, and dielectric liners 107 and 109 (which may have a lower dielectric constant (k) than the epitaxial source / drain region 92) are added to the sidewall of spacer 81, sufficient electrical insulation can be established between the conductive contact 112 and the adjacent gate structure, thereby eliminating or reducing the parasitic capacitance between the conductive contact 112 and the adjacent gate structure. Therefore, the performance and reliability of the semiconductor device 120 can be improved.

[0079] Figures 31A to 31C This is a view of a semiconductor device 120 according to some embodiments, and... Figures 27A to 27C The illustrated embodiments are similar, wherein the same reference numerals refer to the same features formed by the same process. For example... Figure 31C As shown, portions of CESL 94 and the epitaxial source / drain region 92 on the sidewall of spacer 81 can be partially removed. Therefore, the remaining portions of CESL 94 and the epitaxial source / drain region 92 lie between spacer 81 and dielectric liner 107. The remaining portion of the epitaxial source / drain region 92 between spacer 81 and dielectric liner 107 may have a thickness T1, which can generate sufficient electrical insulation between conductive contact 112 and adjacent gate structures, thereby eliminating or reducing parasitic capacitance between conductive contact 112 and adjacent gate structures. Therefore, the performance and reliability of semiconductor device 120 can be improved.

[0080] like Figure 31C As shown, the upper portion of CESL 94 can be partially removed. Therefore, the upper portion of CESL 94 is located between spacer 81 and dielectric liner 107. After partial removal, the upper portion of CESL 94 may have a thickness T2, and the lower portion of CESL 94 may have a thickness T3. Thickness T3 may be greater than thickness T2. For example, Figures 31A to 31C It shows having with Figures 27A to 27C The illustrated embodiment shows a similar configuration of dielectric liners 107 and 109. In other embodiments, the configuration of dielectric liners 107 and 109 is similar to... Figures 30A to 30C The illustrated embodiment is similar. In further embodiments, the dielectric liner 109 is omitted, and the configuration of the dielectric liner 107 is the same as... Figures 24A to 24C The illustrated embodiment is similar.

[0081] Figures 32A to 32C This is a view of a semiconductor device 120 according to some embodiments, and... Figures 24A to 24C The illustrated embodiments are similar, wherein the same reference numerals refer to the same features formed by the same process. For example... Figure 32C As shown, the spacer 81 above the STI region 68 may have an "L" shape, with its horizontal portion located on the top surface of the STI region 68.

[0082] Figures 33A to 33C This is a view of a semiconductor device 120 according to some embodiments, and... Figures 27A to 27C The illustrated embodiments are similar, wherein the same reference numerals refer to the same features formed by the same process. For example... Figure 33B and Figure 33C As shown, the bottom surface of the conductive contact 112 may extend beyond the bottom surface of the dielectric liner 109 into the epitaxial source / drain region 92 and the first ILD 96.

[0083] The embodiments of this disclosure have several advantageous features. By at least partially removing a portion of the epitaxial source / drain region 92 from the sidewall of spacer 81 and adding a dielectric liner 107 and optionally a dielectric liner 109 to the sidewall of spacer 81, sufficient electrical insulation can be established between the conductive contact 112 and the adjacent gate structure, thereby eliminating or reducing parasitic capacitance between the conductive contact 112 and the adjacent gate structure. Therefore, the performance and reliability of the semiconductor device 120 can be improved.

[0084] In one embodiment, a semiconductor device includes: a source / drain region; a first nanostructure along a sidewall of the source / drain region; a gate structure surrounding the first nanostructure; a first gate spacer along a sidewall of a first portion of the gate structure; a first dielectric layer over the source / drain region and the gate structure; a first conductive contact extending through the first dielectric layer and electrically connected to the source / drain region; and a first dielectric liner along a sidewall of the first conductive contact, wherein the first dielectric liner extends horizontally from a top surface of the first conductive contact to a top surface of the source / drain region, and wherein the first dielectric liner contacts a sidewall of the first gate spacer. In one embodiment, the sidewall of the first gate spacer is completely covered by the first dielectric liner. In another embodiment, the first dielectric liner contacts a sidewall of the first conductive contact. In an embodiment, the semiconductor device further includes a second dielectric liner located between the first dielectric liner and the first conductive contact, wherein the second dielectric liner extends horizontally from the top surface of the first conductive contact toward the source / drain region, and wherein the second dielectric liner comprises a different material than the first dielectric liner. In an embodiment, the first dielectric liner extends below the second dielectric liner and contacts the sidewall of the first conductive contact. In an embodiment, the second dielectric liner extends to the top surface of the source / drain region. In an embodiment, the semiconductor device further includes: a semiconductor substrate located below the first nanostructure; an isolation region located above the semiconductor substrate and below the first dielectric layer; a second gate spacer located between the isolation region and the first dielectric layer; a second conductive contact extending through the first dielectric layer; and a second dielectric liner along the sidewall of the second conductive contact, wherein the second dielectric liner extends through the first dielectric layer, and wherein the second dielectric liner contacts the sidewall of the second gate spacer. In an embodiment, the first dielectric liner and the second dielectric liner comprise the same material.

[0085] In an embodiment, a method of forming a semiconductor device includes: forming a first nanostructure on a semiconductor substrate; depositing a first gate spacer on the first nanostructure; forming a first opening through the first nanostructure, wherein the first opening exposes the sidewalls of the first nanostructure; growing source / drain regions in the first opening, wherein the source / drain regions are located on the sidewalls of the first nanostructure, and wherein a first portion of the source / drain regions is located on the sidewalls of the first gate spacer; forming a first contact etch stop layer over the source / drain regions, and forming a first dielectric layer over the first contact etch stop layer, wherein a first portion of the first contact etch stop layer is located on the sidewalls of the first gate spacer; forming a second opening through the first dielectric layer, wherein forming the second opening includes at least partially removing the first portion of the source / drain regions located on the sidewalls of the first gate spacer and the first portion of the first contact etch stop layer; depositing a first dielectric liner in the second opening, wherein the first dielectric liner comprises a low-k material; and forming a first conductive contact in the second opening, wherein the first conductive contact is electrically connected to the source / drain regions. In an embodiment, the sidewalls of the first gate spacer are exposed after the second opening is formed. In one embodiment, the second opening exposes the sidewall of the first gate spacer, and a first dielectric liner is formed on the sidewall of the first gate spacer. In another embodiment, the method further includes depositing a second dielectric liner in the second opening after depositing the first dielectric liner and before forming the first conductive contact, wherein the first and second dielectric liners comprise different materials. In yet another embodiment, the method further includes forming an isolation region on a semiconductor substrate; depositing a second gate spacer on the isolation region, wherein a second portion of the first contact etch stop layer is located on the sidewall of the second gate spacer; forming a third opening by partially removing the second portion of the first contact etch stop layer; and depositing a second dielectric liner in the third opening. In another embodiment, the third opening exposes the sidewall of the second gate spacer, and a second dielectric liner is located on the sidewall of the second gate spacer.

[0086] In an embodiment, a method of forming a semiconductor device includes: forming a first nanostructure on a semiconductor substrate; depositing a first gate spacer on the first nanostructure; growing source / drain regions, wherein a first portion of the source / drain regions is located on a sidewall of the first gate spacer, and wherein a second portion of the source / drain regions is located on a sidewall of the first nanostructure; forming a first contact etch stop layer on the source / drain regions, wherein a first portion of the first contact etch stop layer is located on a sidewall of the first gate spacer; forming a first opening by removing the first portion of the first contact etch stop layer and the first portion of the source / drain regions, wherein the first opening exposes the sidewall of the first gate spacer; depositing a first dielectric liner in the first opening and on the sidewall of the first gate spacer; and forming a first conductive contact in the first opening. In an embodiment, the first opening and the source / drain regions have the same width in a cross-sectional view. In an embodiment, the first dielectric liner comprises a low-k material. In one embodiment, the method further includes: depositing a third dielectric liner in the first opening, wherein the third dielectric liner is located between the first dielectric liner and the first conductive contact, and wherein the first dielectric liner is in contact with the first conductive contact. In another embodiment, the method further includes: depositing a third dielectric liner in the first opening, wherein the third dielectric liner is located between the first dielectric liner and the first conductive contact, and wherein the first dielectric liner is separated from the first conductive contact by the third dielectric liner. In another embodiment, the top surface of the source / drain region is concave after the first opening is formed.

[0087] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0088] Example 1 is a semiconductor device comprising: a source / drain region; a first nanostructure along a sidewall of the source / drain region; a gate structure surrounding the first nanostructure; a first gate spacer along a sidewall of a first portion of the gate structure; a first dielectric layer over the source / drain region and the gate structure; a first conductive contact extending through the first dielectric layer and electrically connected to the source / drain region; and a first dielectric liner along a sidewall of the first conductive contact, wherein the first dielectric liner extends horizontally from a top surface of the first conductive contact to a top surface of the source / drain region, and wherein the first dielectric liner contacts a sidewall of the first gate spacer.

[0089] Example 2 is the semiconductor device described in Example 1, wherein the sidewall of the first gate spacer is completely covered by the first dielectric liner.

[0090] Example 3 is the semiconductor device described in Example 1, wherein the first dielectric liner is in contact with the sidewall of the first conductive contact.

[0091] Example 4 is the semiconductor device described in Example 1, further comprising a second dielectric liner located between the first dielectric liner and the first conductive contact, wherein the second dielectric liner extends from the horizontal plane of the top surface of the first conductive contact toward the source / drain region, and wherein the second dielectric liner comprises a material different from the first dielectric liner.

[0092] Example 5 is the semiconductor device described in Example 4, wherein the first dielectric liner extends below the second dielectric liner and contacts the sidewall of the first conductive contact.

[0093] Example 6 is the semiconductor device described in Example 4, wherein the second dielectric liner extends to the top surface of the source / drain region.

[0094] Example 7 is the semiconductor device described in Example 1, further comprising: a semiconductor substrate located below the first nanostructure; an isolation region located above the semiconductor substrate and below the first dielectric layer; a second gate spacer located between the isolation region and the first dielectric layer; a second conductive contact extending through the first dielectric layer; and a second dielectric liner along a sidewall of the second conductive contact, wherein the second dielectric liner extends through the first dielectric layer, and wherein the second dielectric liner contacts a sidewall of the second gate spacer.

[0095] Example 8 is the semiconductor device described in Example 7, wherein the first dielectric liner and the second dielectric liner comprise the same material.

[0096] Example 9 is a method of forming a semiconductor device, the method comprising: forming a first nanostructure on a semiconductor substrate; depositing a first gate spacer on the first nanostructure; forming a first opening through the first nanostructure, wherein the first opening exposes a sidewall of the first nanostructure; growing a source / drain region in the first opening, wherein the source / drain region is located on a sidewall of the first nanostructure, and wherein a first portion of the source / drain region is located on a sidewall of the first gate spacer; forming a first contact etch stop layer on the source / drain region and forming a first dielectric layer on the first contact etch stop layer, wherein a first portion of the first contact etch stop layer is located on a sidewall of the first gate spacer; forming a second opening through the first dielectric layer, wherein forming the second opening comprises at least partially removing a first portion of the source / drain region located on a sidewall of the first gate spacer and a first portion of the first contact etch stop layer; depositing a first dielectric liner in the second opening, wherein the first dielectric liner comprises a low-k material; and forming a first conductive contact in the second opening, wherein the first conductive contact is electrically connected to the source / drain region.

[0097] Example 10 is the method of Example 9, wherein the sidewall of the first gate spacer is exposed after the second opening is formed.

[0098] Example 11 is the method of Example 9, wherein the second opening exposes the sidewall of the first gate spacer, and wherein the first dielectric liner is formed on the sidewall of the first gate spacer.

[0099] Example 12 is the method of Example 9, further comprising: depositing a second dielectric liner in the second opening after depositing the first dielectric liner and before forming the first conductive contact, wherein the first dielectric liner and the second dielectric liner comprise different materials.

[0100] Example 13 is the method of Example 9, further comprising: forming an isolation region on the semiconductor substrate; depositing a second gate spacer on the isolation region, wherein a second portion of the first contact etch stop layer is located on a sidewall of the second gate spacer; forming a third opening by partially removing the second portion of the first contact etch stop layer; and depositing a second dielectric liner in the third opening.

[0101] Example 14 is the method of Example 13, wherein the third opening exposes the sidewall of the second gate spacer, and wherein the second dielectric liner is located on the sidewall of the second gate spacer.

[0102] Example 15 is a method of forming a semiconductor device, the method comprising: forming a first nanostructure on a semiconductor substrate; depositing a first gate spacer on the first nanostructure; growing source / drain regions, wherein a first portion of the source / drain regions is located on a sidewall of the first gate spacer, and wherein a second portion of the source / drain regions is located on a sidewall of the first nanostructure; forming a first contact etch stop layer on the source / drain regions, wherein a first portion of the first contact etch stop layer is located on a sidewall of the first gate spacer; forming a first opening by removing the first portion of the first contact etch stop layer and the first portion of the source / drain regions, wherein the first opening exposes a sidewall of the first gate spacer; depositing a first dielectric liner in the first opening and on the sidewall of the first gate spacer; and forming a first conductive contact in the first opening.

[0103] Example 16 is the method described in Example 15, wherein the first opening and the source / drain regions have the same width in a cross-sectional view.

[0104] Example 17 is the method of Example 16, wherein the first dielectric liner comprises a low-k material.

[0105] Example 18 is the method of Example 15, further comprising: depositing a third dielectric liner in the first opening, wherein the third dielectric liner is located between the first dielectric liner and the first conductive contact, and wherein the first dielectric liner is in contact with the first conductive contact.

[0106] Example 19 is the method of Example 15, further comprising: depositing a third dielectric liner in the first opening, wherein the third dielectric liner is located between the first dielectric liner and the first conductive contact, and wherein the first dielectric liner is separated from the first conductive contact by the third dielectric liner.

[0107] Example 20 is the method described in Example 15, wherein the top surface of the source / drain region is concave after the first opening is formed.

Claims

1. A semiconductor device, comprising: Source / drain regions; The first nanostructure is located along the sidewall of the source / drain region; A gate structure surrounding the first nanostructure; A first gate spacer is located along the sidewall of a first portion of the gate structure. A first dielectric layer is located above the source / drain region and the gate structure; A first conductive contact extends through the first dielectric layer and is electrically connected to the source / drain region; as well as A first dielectric liner extends horizontally from the top surface of the first conductive contact to the top surface of the source / drain region, and the first dielectric liner contacts the sidewall of the first gate spacer.

2. The semiconductor device according to claim 1, wherein, The sidewalls of the first gate spacer are completely covered by the first dielectric liner.

3. The semiconductor device according to claim 1, wherein, The first dielectric liner is in contact with the sidewall of the first conductive contact.

4. The semiconductor device of claim 1, further comprising a second dielectric liner located between the first dielectric liner and the first conductive contact, wherein, The second dielectric liner extends horizontally from the top surface of the first conductive contact toward the source / drain region, and wherein the second dielectric liner comprises a material different from the first dielectric liner.

5. The semiconductor device according to claim 4, wherein, The first dielectric liner extends below the second dielectric liner and contacts the sidewall of the first conductive contact.

6. The semiconductor device according to claim 4, wherein, The second dielectric liner extends to the top surface of the source / drain region.

7. The semiconductor device according to claim 1, further comprising: A semiconductor substrate is located below the first nanostructure; An isolation region is located above the semiconductor substrate and below the first dielectric layer; The second gate spacer is located between the isolation region and the first dielectric layer; The second conductive contact extends through the first dielectric layer; as well as A second dielectric liner extends along the sidewall of the second conductive contact, wherein the second dielectric liner extends through the first dielectric layer, and wherein the second dielectric liner contacts the sidewall of the second gate spacer.

8. The semiconductor device according to claim 7, wherein, The first dielectric liner and the second dielectric liner comprise the same material.

9. A method for forming a semiconductor device, the method comprising: The first nanostructure is formed on a semiconductor substrate; A first gate spacer is deposited on the first nanostructure; A first opening is formed through the first nanostructure, wherein the first opening exposes the sidewall of the first nanostructure; A source / drain region is grown in the first opening, wherein the source / drain region is located on the sidewall of the first nanostructure, and wherein a first portion of the source / drain region is located on the sidewall of the first gate spacer. A first contact etch stop layer is formed over the source / drain region, and a first dielectric layer is formed over the first contact etch stop layer, wherein a first portion of the first contact etch stop layer is located on the sidewall of the first gate spacer. A second opening is formed through the first dielectric layer, wherein forming the second opening includes at least partially removing a first portion of the source / drain region located on the sidewall of the first gate spacer and a first portion of the first contact etch stop layer; A first dielectric liner is deposited in the second opening, wherein the first dielectric liner comprises a low-k material; and A first conductive contact is formed in the second opening, wherein the first conductive contact is electrically connected to the source / drain region.

10. A method of forming a semiconductor device, the method comprising: The first nanostructure is formed on a semiconductor substrate; A first gate spacer is deposited on the first nanostructure; A source / drain region is grown, wherein a first portion of the source / drain region is located on the sidewall of the first gate spacer, and wherein a second portion of the source / drain region is located on the sidewall of the first nanostructure. A first contact etch stop layer is formed over the source / drain region, wherein a first portion of the first contact etch stop layer is located on the sidewall of the first gate spacer; A first opening is formed by removing the first portion of the first contact etch stop layer and the first portion of the source / drain region, wherein the first opening exposes the sidewall of the first gate spacer. A first dielectric liner is deposited in the first opening and on the sidewall of the first gate spacer; and A first conductive contact is formed in the first opening.

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