Display panel and electronic equipment

Abstract

The invention provides a display panel and electronic equipment. The display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a stacked structure in the second region and including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode; a groove in the third region and separating the at least one organic material layer contained in the intermediate layer; and at least one metal layer in the third region and including a first opening overlapping the groove, where the groove is defined in a multilayer film including an organic layer and an inorganic layer on the organic layer, and the at least one metal layer is between the substrate and the multilayer film.

Description

[0001] This application is a divisional application of patent application No. 202010190972.7, filed on March 18, 2020, entitled “Display Panel”.

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0032539, filed on March 21, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more example implementations relate to a display panel included in a first region of the display area. Background Technology

[0004] In recent years, the uses and applications of display devices have diversified. Furthermore, display devices have become thinner and lighter, thus expanding their range of applications.

[0005] As the display area of ​​a display device increases, various functions connected to or linked to the display device can be added. Because of this method of adding various functions while increasing the display area, a display device can include various components disposed within the display area.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] One or more example embodiments may include a display panel and a display device including the display panel, the display panel including a first region in which various types of components can be disposed in the display area. However, the above are merely examples, and embodiments according to this disclosure are not limited thereto.

[0008] According to some example embodiments, the display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a stacked structure located in the second region and including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode; a trench located in the third region and separating at least one organic material layer contained in the intermediate layer; and a metal layer located in the third region and including a first opening overlapping the trench.

[0009] According to some example embodiments, the trench can be defined in a multilayer film including an organic layer and an inorganic layer on the organic layer, and at least one metal layer can be disposed between the substrate and the multilayer film.

[0010] According to some example implementations, the inorganic layer of a multilayer film may include a pair of tips protruding toward the center of the groove.

[0011] According to some example embodiments, the organic layer of the multilayer film may include openings, and the inorganic layer of the multilayer film may be in direct contact with at least one metal layer through the openings in the organic layer.

[0012] According to some example implementations, the inorganic layer of a multilayer film may include a metal layer.

[0013] According to some example embodiments, the display panel may further include at least one inorganic insulating layer between the substrate and the multilayer film and including a second opening that overlaps with the groove and the first opening.

[0014] According to some example embodiments, the display panel may be further included in a second region and electrically connected to transistors and storage capacitors in a stacked structure, wherein at least one metal layer comprises the same material as at least one of the gate electrodes of the transistors or the electrodes of the storage capacitors.

[0015] According to some example implementations, the width of the first opening in at least one metal layer is greater than the width of the groove.

[0016] According to some example implementations, when viewed in a direction perpendicular to the upper surface of the substrate, at least one metal layer may have an annular shape surrounding the first region.

[0017] According to some example implementations, the display panel may further include a lower metal layer between the substrate and the multilayer film.

[0018] According to some example implementations, the bottom surface of the groove may be at the same level as the upper surface of the lower metal layer.

[0019] According to some example implementations, the lower metal layer may include a third opening corresponding to the groove.

[0020] According to some example implementations, the display panel may include a hole located in the first region and passing through the display panel.

[0021] According to some example embodiments, a display panel includes: a substrate including an opening region, a display region, and an intermediate region between the opening region and the display region; a transistor disposed in the display region; a display element including a pixel electrode electrically connected to the transistor, an intermediate layer on the pixel electrode, and a counter electrode on the intermediate layer; a first organic insulating layer between the transistor and the pixel electrode, the first organic insulating layer extending into the intermediate region; a groove located in the intermediate region and having an undercut structure, the groove separating at least one organic material layer contained in the intermediate layer; and an inorganic structure between the substrate and the first organic insulating layer and having a first opening corresponding to the groove.

[0022] According to some example embodiments, the trench can be defined in a multilayer film, and the multilayer film can include a first organic insulating layer on a substrate and an inorganic layer on the first organic insulating layer, and the inorganic layer can include a pair of tips extending toward the center of the trench.

[0023] According to some example implementations, the inorganic layer may include a metal.

[0024] According to some example implementations, the width of the portion of the groove that passes through the first organic insulating layer may be greater than the width of the first opening.

[0025] According to some example implementations, the inorganic structure may include at least one inorganic insulating layer and at least one metal layer.

[0026] According to some example implementations, at least one metal layer may include a second opening that corresponds to and is larger than the first opening of the inorganic structure.

[0027] According to some example implementations, the display panel may further include a lower metal layer between the substrate and the inorganic structure.

[0028] According to some example implementations, the bottom surface of the groove may be at the same level as the upper surface of the lower metal layer.

[0029] According to some example implementations, the lower metal layer may include a third opening that overlaps with the groove.

[0030] According to some example implementations, the display panel may further include an inorganic contact area disposed adjacent to the slot.

[0031] According to some example embodiments, the display panel may further include a metal layer disposed on a first organic insulating layer, and the metal layer may directly contact the inorganic structure through an opening in the first organic insulating layer to provide an inorganic contact area.

[0032] According to some example implementations, inorganic contact areas can be provided on each of the two sides of the groove, with the groove between the inorganic contact areas.

[0033] According to some example implementations, the depth of the groove can be greater than the maximum thickness of the portion of the first organic insulating layer located in the display area.

[0034] Apart from the details described above, other aspects, features, and characteristics will become clear from the following drawings, claims, and detailed description. Attached Figure Description

[0035] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

[0036] Figure 1 This is a schematic perspective view illustrating a display device according to some exemplary embodiments;

[0037] Figure 2 This is a schematic cross-sectional view of a display device according to some example embodiments;

[0038] Figure 3 This is a schematic cross-sectional view of a display device according to some example embodiments;

[0039] Figures 4A to 4D This is a schematic cross-sectional view of a display panel according to some example implementations;

[0040] Figure 5 This is a schematic plan view of a display panel according to some example implementations;

[0041] Figure 6 This is a schematic equivalent circuit diagram of the pixels of a display panel according to some example implementations;

[0042] Figure 7 This is a plan view of a portion of a display panel according to some example implementations;

[0043] Figure 8 This is a cross-sectional view of a display panel according to some example implementations;

[0044] Figures 9A to 9C as well as Figure 9E This is a cross-sectional view of a display panel manufacturing process according to some example implementations;

[0045] Figure 9D yes Figure 9C Enlarged cross-sectional view of region IXd;

[0046] Figure 9F The illustrations show some example implementations. Figure 9B A modified version of the display panel;

[0047] Figure 10 It is a plan view of a portion of the central area of ​​a display panel according to some example embodiments;

[0048] Figure 11 This is a cross-sectional view of the middle region of a display panel according to some example embodiments; and

[0049] Figure 12 This is a schematic cross-sectional view of a display panel according to some example implementations. Detailed Implementation

[0050] For the purposes of now referring to exemplary embodiments in more detail, these exemplary embodiments are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, exemplary embodiments of this application may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the exemplary embodiments described below with reference to the accompanying drawings are merely for the purpose of explaining various aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…”, when placed after the list of elements, modify the entire list of elements and do not modify individual elements in the list.

[0051] Since different modifications and several embodiments are possible according to the present disclosure, exemplary embodiments are shown and will be described in more detail in the accompanying drawings. The effects, features, and implementation methods of the embodiments will be explained in detail with reference to the embodiments described below and the accompanying drawings. However, the embodiments may take different forms and should not be construed as limited to the descriptions set forth herein.

[0052] In the following, aspects of some exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments according to the present disclosure are illustrated. In the drawings, the same elements are labeled with the same reference numerals, and repeated descriptions thereof will be omitted.

[0053] While terms such as "first" and "second" can be used to describe different components, such components are not necessarily limited to the terms mentioned above. The use of these terms is merely to distinguish one component from another.

[0054] Use the singular form to encompass the plural form unless it has a distinctly different meaning in the context.

[0055] In this specification, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of a feature or component disclosed in the specification and are not intended to exclude the possibility that one or more other features or components may be added.

[0056] It will be understood that when a layer, area, or component is referred to as being "formed on" another layer, area, or component, it can be formed directly or indirectly on that other layer, area, or component. That is, for example, intermediate layers, areas, or components may exist.

[0057] For ease of explanation, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0058] When a particular implementation can be carried out differently, a specific process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0059] Throughout the disclosure, the expression "A and / or B" indicates only A, only B, or both A and B. Furthermore, the expression "at least one of A and B" indicates only A, only B, or both A and B.

[0060] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being directly connected or / and indirectly connected through other constituent elements therebetween. For example, when a layer, region, element, etc., is described as electrically connected, the layer, region, element, etc., can be directly electrically connected and / or indirectly electrically connected through another layer, region, element, etc. therebetween.

[0061] Figure 1 This is a perspective view schematically illustrating a display device according to some example embodiments.

[0062] refer to Figure 1 The display device 1 includes a first region OA and a display region DA that partially surrounds the first region OA. The display device 1 can provide or display an image using light emitted from a plurality of pixels disposed in the display region DA. The first region OA can be completely surrounded by the display region DA. The first region OA may be a region in which a reference is disposed. Figure 2 The area of ​​the component being described.

[0063] The intermediate region MA is placed as a third region between the first region OA and the display region DA, which is the second region. The display region DA can be surrounded by the outer region PA, which is the fourth region. The intermediate region MA and the outer region PA can be non-display regions in which no pixels are set. The intermediate region MA can be completely surrounded by the display region DA, and the display region DA can be completely surrounded by the outer region PA.

[0064] In the following description, the organic light-emitting display device will be used as an example of display device 1 according to some exemplary embodiments, but the display device according to the embodiments of this disclosure is not limited thereto. According to some exemplary embodiments, display device 1 may be, for example, an inorganic light-emitting display (or an inorganic EL display) or a quantum dot light-emitting display. For example, the emitting layer of the display element included in display device 1 may include organic materials, inorganic materials, quantum dots, or both organic materials and quantum dots, or both inorganic materials and quantum dots.

[0065] although Figure 1The illustration shows a first region OA that is approximately circular, but the implementation is not limited to this. There may be two or more first regions OA, and their shapes may be varied, such as circular, elliptical, star-shaped, rhomboid, etc.

[0066] Figure 2 This is a schematic cross-sectional view of a display device 1 according to some exemplary embodiments, and can be compared with... Figure 1 The section cut by line II-II' corresponds to the section. Figure 3 and Figure 2 The modified implementation of display device 1 corresponds to this.

[0067] refer to Figure 2 The display device 1 may include a display panel 10, an input sensing layer 40 disposed on the display panel 10, and an optical functional layer 50 that can be covered by a window 60. The display device 1 may be various types of electronic devices, such as mobile phones, laptops, or smartwatches.

[0068] The display panel 10 can display images. The display panel 10 includes pixels disposed in the display area DA. Each pixel may include a display element and pixel circuitry connected to the display element.

[0069] The input sensing layer 40 acquires coordinate information based on external inputs such as touch events. The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 can sense external inputs using mutual capacitance and / or self-capacitance methods.

[0070] The input sensing layer 40 can be formed directly on the display panel 10 or it can be formed separately and then bonded to the display panel 10 using an adhesive layer such as an optically clear adhesive. For example, the input sensing layer 40 can be formed continuously after the process of forming the display panel 10, and in this case, the input sensing layer 40 can be considered part of the display panel 10, and there may be no adhesive layer between the input sensing layer 40 and the display panel 10. Figure 2 The diagram illustrates an input sensing layer 40 positioned between the display panel 10 and the optical functional layer 50. However, according to some exemplary embodiments, the input sensing layer 40 may also be disposed on the optical functional layer 50.

[0071] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (external light) incident on the display panel 10 from the outside through the window 60. The anti-reflective layer may include a retarder and a polarizer. The retarder may be film-type or liquid-coated type, and may include a λ / 2 retarder or a λ / 4 retarder. The polarizer may also be film-type or liquid-coated type, and film-type polarizers may include a stretchable synthetic resin film, while liquid-coated polarizers may include liquid crystals arranged in a specific configuration. The retarder and polarizer may further include a protective film.

[0072] According to some example embodiments, the antireflective layer may include a black matrix and color filters. The color filters can be configured by taking into account the colors of light emitted from the pixels of the display panel 10. The color filters may each include red, green, or blue pigments or dyes. Optionally, in addition to the aforementioned pigments or dyes, the color filters may further include quantum dots. Optionally, some of the color filters may not include the aforementioned pigments or dyes, but may instead include scattering particles such as titanium dioxide.

[0073] According to some example implementations, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. First reflected light and second reflected light, reflected by the first reflective layer and the second reflective layer respectively, can undergo destructive interference, thereby reducing the reflectivity of external light.

[0074] The optical functional layer 50 may include a lens layer. The lens layer may increase the output efficiency of light emitted from the display panel 10, or may reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or multiple layers with different refractive indices. The optical functional layer 50 may include both or one of the anti-reflective layer and lens layer described above.

[0075] According to some exemplary embodiments, the optical functional layer 50 can be formed continuously after the processes for forming the display panel 10 and / or the input sensing layer 40. In this case, an adhesive layer may not be provided between the optical functional layer 50 and the display panel 10 or between the optical functional layer 50 and the input sensing layer 40.

[0076] The display panel 10, the input sensing layer 40, and / or the optical functional layer 50 may include through-holes. For example... Figure 2As shown, the display panel 10, the input sensing layer 40, and the optical functional layer 50 may each include through-holes 10H, 40H, and 50H, and these through-holes may overlap each other. The through-holes 10H, 40H, and 50H are positioned to correspond to a first region OA. The first region OA may be a component region (e.g., a sensor region, a camera region, a speaker region, etc.) where components 20 included to add various functions to the display device 1 as described above are located.

[0077] Component 20 can be located in through holes 10H, 40H, and 50H, such as Figure 2 As shown in the diagram. Component 20 may include electronic elements. For example, component 20 may be an electronic element that uses light or sound. For example, the electronic element may include a sensor (such as an infrared sensor) that outputs and / or receives light, a camera that receives light to capture an image, a sensor that measures distance or senses fingerprints by outputting or sensing light or sound, a small lamp that outputs light, a speaker that outputs sound, etc. Electronic elements using light can use light of various wavelengths, such as visible light, infrared light, and ultraviolet light. In some embodiments, the first region OA may be a transmissive region through which light and / or sound output from component 20 to the outside or propagating from the outside into component 20 passes.

[0078] Figure 2 The illustration shows that the display panel 10, the input sensing layer 40, and the optical functional layer 50 include through holes 10H, 40H, and 50H, respectively, but the implementation is not limited to this.

[0079] According to another embodiment, one or more of the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include vias. For example, any one or two selected from the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include vias. Optionally, the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include vias, such as... Figure 3 As shown in the diagram. In this case, component 20 can be positioned below the display panel 10, as shown in the diagram. Figure 3 As shown in the image.

[0080] According to some example implementations, when the display device 1 is used as a smartwatch or a vehicle dashboard, component 20 may be a watch hand or an element such as a pointer indicating specific information (e.g., vehicle speed). When the display device 1 includes a watch or a pointer for a vehicle dashboard, component 20 may pass through window 60 and be exposed to the outside, and window 60 may have a through-hole corresponding to the first area OA.

[0081] Component 20 may include components related to the function of the display panel 10 as described above, or components such as accessories that enhance the aesthetics of the display panel 10. Although in Figure 2 and Figure 3 Not shown, but a layer including an optically transparent adhesive may be between window 60 and optical functional layer 50.

[0082] Figures 4A to 4D This is a schematic cross-sectional view of the display panel 10 according to the embodiment.

[0083] refer to Figure 4A The display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. The substrate 100 may be multilayered. For example, such as Figure 4A As shown in the enlarged view, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104.

[0084] Each of the first substrate layer 101 and the second substrate layer 103 may comprise a polymer resin. For example, the first substrate layer 101 and the second substrate layer 103 may comprise a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), or cellulose acetate propionate (CAP). The polymer may be transparent.

[0085] The first barrier layer 102 and the second barrier layer 104 are barrier layers that prevent the penetration of external foreign matter, and may include materials such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x ( ) Inorganic materials with single-layer or multi-layer structures.

[0086] Display layer 200 includes a plurality of pixels. Display layer 200 may include a display element layer 200A and a pixel circuit layer 200B. Display element layer 200A includes a display element disposed in each pixel, and pixel circuit layer 200B includes pixel circuitry and an insulating layer disposed in each pixel. Display element layer 200A may have a pixel electrode, a counter electrode, and a stacked structure between the pixel electrode and the counter electrode, and each display element may be an organic light-emitting diode (OLED). Each pixel circuitry may include a thin-film transistor and a storage capacitor.

[0087] The display elements of the display layer 200 can be covered by encapsulation elements such as the thin-film encapsulation layer 300, and the thin-film encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Since the display panel 10 includes a substrate 100 containing a polymer resin and a thin-film encapsulation layer 300 containing inorganic and organic encapsulation layers, the flexibility of the display panel 10 can be enhanced.

[0088] The display panel 10 may include a through-hole 10H passing through the display panel 10. The through-hole 10H may be located in a first region OA, and the first region OA may in this case be of the type of a hole region. Figure 4A In the display panel 100, the substrate 100 and the thin-film encapsulation layer 300 respectively include through holes 100H and 300H corresponding to the through holes 10H of the display panel 10. The display layer 200 may also include a through hole 200H corresponding to the first region 0A.

[0089] According to some example implementations, such as Figure 4B As shown, substrate 100 may not include vias corresponding to the first region OA. Display layer 200 may include vias 200H corresponding to the first region OA. Thin-film encapsulation layer 300 may not include vias corresponding to the first region OA. According to some exemplary embodiments, such as Figure 4C As shown, the display layer 200 may not include the via 200H corresponding to the first region OA.

[0090] Despite Figures 4A to 4C The display element layer 200A is not located in the first region OA, but the implementation is not limited to this. According to some example implementations, such as... Figure 4D As shown, the auxiliary display element layer 200C may be located in the first region OA. The auxiliary display element layer 200C may include display elements having a different structure from the display elements of the display element layer 200A and / or operating in a different manner from the display elements of the display element layer 200A.

[0091] According to some example embodiments, each pixel of the display element layer 200A may include an active organic light-emitting diode (OLED), and the auxiliary display element layer 200C may include pixels containing passive organic light-emitting diodes (OLEDs). When the auxiliary display element layer 200C includes a display element with passive OLEDs, components constituting the pixel circuitry below the passive OLEDs may be omitted. For example, the portion of the pixel circuitry layer 200B below the auxiliary display element layer 200C may not include transistors and storage capacitors.

[0092] According to some example embodiments, the auxiliary display element layer 200C may include display elements of the same type as those in the display element layer 200A (e.g., active organic light-emitting diodes), but the pixel circuitry beneath the auxiliary display element layer 200C may have a different structure. For example, the pixel circuitry beneath the auxiliary display element layer 200C (e.g., pixel circuitry including a light-shielding layer between the substrate and the transistor) may have a different structure than the pixel circuitry beneath the display element layer 200A. Optionally, the display elements of the auxiliary display element layer 200C may be operated according to control signals different from the control signals of the display elements in the display element layer 200A. In the first region OA in which the auxiliary display element layer 200C is disposed, components that do not require relatively high transmittance (e.g., infrared sensors) may be disposed. In this case, the first region OA may be considered both a component region and an auxiliary display region.

[0093] Figure 5 This is a schematic diagram illustrating a plan view of a display panel 10 according to some exemplary embodiments, and Figure 6 It is a schematic diagram illustrating the equivalent circuit of any pixel of the display panel 10.

[0094] refer to Figure 5 The display panel 10 may include a first area OA, a display area DA as a second area, a middle area MA as a third area, and a peripheral area PA as a fourth area. Figure 5 This can be understood as a substrate 100 contained in the display panel 10. For example, it can be understood that the substrate 100 includes a first region OA, a display region DA, a middle region MA, and a peripheral region PA.

[0095] The display panel 10 includes a plurality of pixels P disposed in a display area DA. Each pixel P may include a pixel circuit PC and an organic light-emitting diode (OLED) as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. Each pixel P may emit red, green, blue, or white light through the organic light-emitting diode OLED.

[0096] The second thin-film transistor T2 is a switching thin-film transistor and is connected to the scan line SL and the data line DL. The second thin-film transistor T2 can transmit the data voltage input via the data line DL to the first thin-film transistor T1 based on the switching voltage input via the scan line SL. A storage capacitor Cst is connected to the second thin-film transistor T2 and the drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the second thin-film transistor T2 and the first power supply voltage ELVDD supplied to the drive voltage line PL.

[0097] The first thin-film transistor T1 is a driving thin-film transistor connected to the driving voltage line PL and the storage capacitor Cst. The driving current flowing through the organic light-emitting diode (OLED) from the driving voltage line PL can be controlled according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a specific brightness via the driving current. The counter electrode (e.g., cathode) of the OLED can receive a second power supply voltage ELVSS.

[0098] Figure 6 The illustration shows a pixel circuit PC comprising two thin-film transistors and one storage capacitor, but the implementation is not limited to this. The number of thin-film transistors and the number of storage capacitors can vary depending on the design of the pixel circuit PC. For example, in addition to the two thin-film transistors described above, the pixel circuit PC may further include four or more thin-film transistors.

[0099] Return to reference Figure 5 In the plan view, the intermediate region MA may surround the first region OA. The intermediate region MA is the area where display elements such as organic light-emitting diodes are not disposed. Signal lines may be located within the intermediate region MA, through which signals are provided to pixels P disposed on the periphery of the first region OA. In the peripheral region PA, a scan driver 1100 providing scan signals to each pixel P, a data driver 1200 providing data signals to each pixel P, and main power supply wiring (not shown) providing a first power supply voltage and a second power supply voltage may be disposed therethrough. Although... Figure 5 The illustration shows the data driver 1200 positioned adjacent to one side of the substrate 100, but according to some example embodiments, the data driver 1200 may be positioned on a flexible printed circuit board (FPCB) electrically connected to pads positioned on one side of the display panel 10.

[0100] Figure 7 This is a schematic plan view of a portion of a display panel according to an embodiment.

[0101] refer to Figure 7 Pixels P can be spaced apart from each other around the first region OA. The first region OA can be defined within pixels P. For example, as... Figure 7 As shown in the plan view, pixel P can be set above and below the first region OA, and pixel P can be set to the left and right of the first region OA.

[0102] The signal line used to supply signals to pixel P and adjacent to the first region OA can be arranged around the first region OA. Figure 7At least one data line DL passing through the display area DA in the plane can extend in the y-direction to provide data signals to pixels P located above and below the first area OA, and can simultaneously travel around the boundary of the first area OA in the intermediate area MA. At least one scan line SL passing through the display area DA in the plan view can extend in the x-direction to provide scan signals to pixels P located to the left and right of the first area OA, and can simultaneously travel around the boundary of the first area OA in the intermediate area MA.

[0103] The bypass portion (or bypass portion) SL-D of scan line SL and the extension portion SL-L passing through display area DA are located on the same layer. The bypass portion SL-D can be integrally formed with the extension portion SL-L. The bypass portion DL-D1 of data line DL can be formed on a different layer than the extension portion DL-L1 passing through display area DA, and the bypass portion DL-D1 and the extension portion DL-L1 of data line DL can be connected through contact hole CNT. The bypass portion DL-D2 of another data line DL is located on the same layer as the extension portion DL-L2, and can be integrally formed with the extension portion DL-L2.

[0104] One or more slots G may be located between a first region OA and a region in which scan lines SL and data lines DL are arranged in rows around the first region OA. In a plan view, each slot G may have an annular shape around the first region OA, and the slots G may be spaced apart from each other.

[0105] Figure 8 This is a cross-sectional view of the display panel according to the embodiment, and can be compared with the view along... Figure 7 The cross-sectional view corresponding to line VIII-VIII'. Figures 9A to 9C as well as Figure 9E This is a cross-sectional view of a display panel during the manufacturing process, according to some example embodiments. Figure 9D yes Figure 9C A magnified cross-sectional view of region IXd. Figure 9F yes Figure 9B A modified implementation of the display panel.

[0106] refer to Figure 8 The display area DA, substrate 100 may include a glass material or a polymer resin. According to some example embodiments, substrate 100 may include multiple sublayers, as described above. Figure 4A As shown in the enlarged image.

[0107] A buffer layer 201 may be formed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer Act of the thin-film transistor (TFT). The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multiple layers comprising the aforementioned inorganic insulating material.

[0108] The pixel circuit PC can be disposed on the buffer layer 201. The pixel circuit PC includes a thin-film transistor (TFT) and a storage capacitor Cst. The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0109] The data line DL of the pixel circuit PC is not in Figure 8 The diagram shows a switching thin-film transistor (TFT) electrically connected to a pixel circuit PC. According to some example embodiments, a top-gate TFT is illustrated, where the gate electrode GE is disposed on the semiconductor layer Act, and a gate insulating layer 203 is located between the gate electrode GE and the semiconductor layer Act. However, according to some example embodiments, the TFT can also be a bottom-gate TFT.

[0110] The semiconductor layer Act may include polycrystalline silicon. Optionally, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include multiple layers or a single layer containing the above materials.

[0111] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer 203 may be a single layer or multiple layers comprising the above materials.

[0112] The source electrode SE and drain electrode DE can be located on the same layer as the data line DL, and can include the same material as the data line. The source electrode SE, drain electrode DE, and data line DL can include materials with high conductivity. The source electrode SE and drain electrode DE can include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can include multiple layers or a single layer containing the above materials. According to some example embodiments, each of the source electrode SE, drain electrode DE, and data line DL can include a multilayer of Ti / Al / Ti.

[0113] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 that overlap each other, with a first interlayer insulating layer 205 between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap with a thin-film transistor (TFT). In this regard, Figure 8The diagram illustrates the gate electrode GE of a thin-film transistor TFT, which serves as the lower electrode CE1 of a storage capacitor Cst. According to some example embodiments, the storage capacitor Cst may not overlap with the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may comprise a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may comprise multiple layers or a single layer containing the aforementioned materials.

[0114] Each of the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. Each of the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise a single layer or multiple layers comprising the aforementioned materials.

[0115] The pixel circuit PC, including a thin-film transistor (TFT) and a storage capacitor (Cst), can be covered by a first organic insulating layer 209. The first organic insulating layer 209 may include an approximately flat upper surface.

[0116] The third interlayer insulation layer 208 may be disposed below the first organic insulation layer 209. The third interlayer insulation layer 208 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0117] The pixel circuit PC can be electrically connected to the pixel electrode 221. For example, as... Figure 8 As shown, a contact metal layer CM can be disposed between the thin-film transistor TFT and the pixel electrode 221. The contact metal layer CM can be connected to the thin-film transistor TFT via contact holes formed in the first organic insulating layer 209, and the pixel electrode 221 can be connected to the contact metal layer CM via contact holes formed in the second organic insulating layer 211 on the contact metal layer CM. The contact metal layer CM may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include multiple layers or a single layer comprising the above materials. According to some example embodiments, the contact metal layer CM may include a Ti / Al / Ti multilayer.

[0118] The first organic insulating layer 209 and the second organic insulating layer 211 may comprise organic insulating materials, such as general-purpose polymers (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. According to some example embodiments, each of the first organic insulating layer 209 and the second organic insulating layer 211 may comprise polyimide.

[0119] Pixel electrode 221 may be formed on the second organic insulating layer 211. Pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). According to some example embodiments, pixel electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. According to some example embodiments, pixel electrode 221 may further include a film formed of ITO, IZO, ZnO, or In2O3 on or below the aforementioned reflective layer.

[0120] A pixel defining layer 215 may be formed on the pixel electrode 221. The pixel defining layer 215 may include an opening exposing the upper surface of the pixel electrode 221 and covering the edge of the pixel electrode 221. The pixel defining layer 215 may include an organic insulating material. Optionally, the pixel defining layer 215 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Optionally, the pixel defining layer 215 may include both organic and inorganic insulating materials.

[0121] The intermediate layer 222 includes an emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed below the emitting layer 222b and / or a second functional layer 222c disposed on the emitting layer 222b. The emitting layer 222b may include a polymer or a low molecular weight organic material that emits light of a predetermined color.

[0122] The first functional layer 222a can be a single layer or multiple layers. For example, when the first functional layer 222a is formed of a polymer material, it may include a hole transport layer (HTL) with a single-layer structure and may be formed of poly(3,4)-ethylene-dihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a is formed of a low molecular weight material, it may include a hole injection layer (HIL) and an HTL.

[0123] The second functional layer 222c may be omitted. For example, when the first functional layer 222a and the emitter layer 222b are formed of a polymer material, the second functional layer 222c may preferably be formed. The second functional layer 222c may comprise a single layer or multiple layers. The second functional layer 222c may comprise an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0124] The emitter layer 222b of the intermediate layer 222 can be disposed in each pixel in the display area DA. The emitter layer 222b can be patterned to correspond to the pixel electrode 221. Unlike the emitter layer 222b, the first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 can extend toward the intermediate region MA, so as to be present not only in the display area DA but also in the intermediate region MA.

[0125] The counter electrode 223 can be formed of a conductive material with a low work function. For example, the counter electrode 223 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Optionally, the counter electrode 223 may further include a material such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the aforementioned materials. The counter electrode 223 may be formed not only in the display region DA but also in the intermediate region MA. The first functional layer 222a, the second functional layer 222c, and the counter electrode 223 can be formed using a thermal deposition method.

[0126] The capping layer 230 may be located on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed using a thermal deposition method. In some embodiments, the capping layer 230 may be omitted.

[0127] The spacer 217 may be formed on the pixel defining layer 215. The spacer 217 may include an organic insulating material such as polyimide. Alternatively, the spacer 217 may include an inorganic insulating material, or both an organic insulating material and an inorganic insulating material.

[0128] The spacer 217 may comprise a material different from or the same as the pixel defining layer 215. According to some example embodiments, the pixel defining layer 215 and the spacer 217 may comprise polyimide. The pixel defining layer 215 and the spacer 217 may be formed together in a masking process using a halftone mask.

[0129] An organic light-emitting diode (OLED) can be covered by a thin-film encapsulation layer 300. The thin-film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. According to some example embodiments, Figure 8 The illustration shows a thin-film encapsulation layer 300 including a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. According to some example embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the order in which these layers are stacked can be modified.

[0130] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise a single layer or multiple layers containing the aforementioned materials. The organic encapsulation layer 320 may comprise a polymeric material. Examples of polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. According to some exemplary embodiments, the organic encapsulation layer 320 may comprise acrylates.

[0131] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have different thicknesses. The first inorganic encapsulation layer 310 may be thicker than the second inorganic encapsulation layer 330. Optionally, the second inorganic encapsulation layer 330 may be thicker than the first inorganic encapsulation layer 310, or the first inorganic encapsulation layer 310 may have the same thickness as the second inorganic encapsulation layer 330.

[0132] refer to Figure 8 The intermediate region MA can include a first sub-intermediate region SMA1 that is relatively far from the first region OA and a second sub-intermediate region SMA2 that is relatively close to the first region OA. Lines and slots G can be set around the first region OA within the intermediate region MA.

[0133] Line (e.g., such as) Figure 8 The data line DL shown can be located in the first sub-intermediate region SMA1. Figure 8 The data line DL of the first sub-intermediate region SMA1 shown above is related to the reference above. Figure 7 The described data line DL's bypass portion (e.g., DL-D1 or DL-D2) corresponds to this. The first sub-intermediate region SMA1 can be understood as a line region or bypass region bypassed by a line such as the aforementioned data line DL.

[0134] Data lines DL can be alternately arranged, with an insulation layer between them. For example, one of adjacent data lines DL can be positioned below an insulation layer (e.g., the first organic insulation layer 209), and the other can be positioned on top of the insulation layer (e.g., the first organic insulation layer 209), thus alternating between the data lines DL on and below the first organic insulation layer 209. When the data lines DL are alternately arranged, the distance (Δd, spacing) between the data lines DL can be reduced. Although in Figure 8 The diagram shows the data line DL located in the first sub-intermediate region SMA1, but the scan line SL (e.g., the bypass portion of the scan line SL) can also be located in the first sub-intermediate region SMA1.

[0135] The data line DL, located below the first organic insulating layer 209, can be covered by a third interlayer insulating layer 208 extending to the intermediate region MA. The upper surface of the third interlayer insulating layer 208 may include an uneven surface. Here, the uneven surface may refer not only to a simple uneven surface, but also to a surface with valleys located in the data line DL below the third interlayer insulating layer 208. In this regard, Figure 8 The illustration shows the formation of valleys that are approximately V-shaped or U-shaped.

[0136] In the second sub-intermediate region SMA2, one or more slots G may be provided. The organic material layers contained in the intermediate layer 222 (e.g., the first functional layer 222a and / or the second functional layer 222c) may be disconnected (or spaced apart) by the slots G. The second sub-intermediate region SMA2 can be understood as the slot region or the disconnected region (or spaced region) of the organic material layers.

[0137] The groove G can be formed in a multilayer film ML between the substrate 100 and the pixel electrode 221. The multilayer film ML may include a first sublayer and a second sublayer on the first sublayer, and in this regard, Figure 8 The illustration shows a multilayer film ML comprising a first organic insulating layer 209 as a first sublayer and an inorganic layer 210 as a second sublayer. The inorganic layer 210 may be located on the same layer (e.g., the first organic insulating layer 209) as the contact metal layer CM and may be formed using the same masking process as the contact metal layer CM. The inorganic layer 210 may comprise the same material as the contact metal layer CM. For example, the inorganic layer 210 may comprise a metal, and the inorganic layer 210 may comprise three sublayers such as Ti / Al / Ti.

[0138] The inorganic structure ILS can be located between the substrate 100 and the multilayer film ML. The inorganic structure ILS may include one or more sublayers, and the sublayers may include inorganic materials. For example, the inorganic structure ILS may include at least one inorganic insulating layer and / or at least one metal layer. According to some example embodiments, such as... Figure 8 As shown, the inorganic structure ILS may include a first interlayer insulation layer 205, a first metal layer 206A, a second interlayer insulation layer 207, a second metal layer 206B, and a third interlayer insulation layer 208. Since the inorganic structure ILS includes piers MD located on both sides of the groove G (the groove G is between the piers MD), the depth of the groove G can be increased.

[0139] refer to Figure 9A The inorganic structure ILS can be disposed on the substrate 100 prior to the operation of forming the first organic insulating layer 209. The inorganic structure ILS may include an inorganic insulating layer and / or a metal layer. According to some example embodiments, Figure 9AThe illustration shows an inorganic interlayer insulating layer (ILS) comprising a first interlayer insulating layer 205, a first metal layer 206A, a second interlayer insulating layer 207, a second metal layer 206B, and a third interlayer insulating layer 208. According to some example embodiments, one or more of the first interlayer insulating layer 205, the first metal layer 206A, the second interlayer insulating layer 207, the second metal layer 206B, and the third interlayer insulating layer 208 included in the inorganic ILS may be omitted.

[0140] It can be used to form a reference Figure 8 The storage capacitor Cst described uses the same process to form a first metal layer 206A as the upper electrode CE2, and the first metal layer 206A may comprise the same material as the upper electrode CE2. This can be achieved using the same process as the reference. Figure 8 The second metal layer 206B is formed using the same process as the data line DL, source electrode SE, and / or drain electrode DE of the pixel circuit PC, and the second metal layer 206B may include the same material as these.

[0141] The inorganic insulating layers (e.g., first interlaminar insulation layer 205, second interlaminar insulation layer 207, and / or third interlaminar insulation layer 208) included in the inorganic structure ILS may comprise inorganic insulating materials that are relatively resistant to moisture penetration. The first interlaminar insulation layer 205, second interlaminar insulation layer 207, and / or third interlaminar insulation layer 208 may comprise silicon nitride and / or silicon oxide. Silicon nitride and silicon oxide are more resistant to moisture than silicon oxynitride and are less likely to oxidize even when exposed to moisture.

[0142] The inorganic structure ILS may include a first opening ILS-OP. A metal layer contained in the inorganic structure ILS may include a second opening corresponding to the first opening ILS-OP, and the second opening may have a width greater than the width W31 of the first opening ILS-OP. For example, the width Wma of the second-first opening 206A-OP of the first metal layer 206A may be greater than the width W31 of the first opening ILS-OP, and the width Wmb of the second-second opening 206B-OP of the second metal layer 206B may be greater than the width W31 of the first opening ILS-OP. The width W31 of the first opening ILS-OP formed in the inorganic structure ILS may be defined by the width of the opening passing through the inorganic insulating layers (e.g., the first interlayer insulating layer 205, the second interlayer insulating layer 207, and the third interlayer insulating layer 208) substantially contained in the inorganic structure ILS.

[0143] The first organic insulating layer 209 can fill the first opening ILS-OP and can be formed on the inorganic structure ILS. By leveling the organic material, a first portion of the first organic insulating layer 209 corresponding to the first opening ILS-OP of the inorganic structure ILS can be formed, and the thickness T is greater than the thickness of other portions of the first organic insulating layer 209. For example, the thickness T of the first portion of the first organic insulating layer 209 can be greater than the maximum thickness t0 of the second portion of the first organic insulating layer 209 corresponding to the display area DA. Figure 8 The thickness T of the first portion of the first organic insulating layer 209 can be greater than the maximum thickness t1 of the third portion of the first organic insulating layer 209 on the inorganic structure ILS located in the intermediate region MA.

[0144] The first portion of the first organic insulating layer 209 will be referenced later. Figure 9B The process described is removed to form groove G ( Figure 9B Furthermore, since the thickness T of the first part is greater than the thickness of the other parts, sufficient depth of the groove G can be ensured.

[0145] In this embodiment, the inorganic layer 210 is located on the first organic insulating layer 209 and may be a metal layer. The inorganic layer 210 can contact the second metal layer 206B below the inorganic layer 210 through an opening 209OD formed in the first organic insulating layer 209 and an opening 208OD formed in the third interlayer insulating layer 208, and may form an inorganic contact region ICR.

[0146] According to some exemplary embodiments, the third interlayer insulating layer 208 may not include the opening 208OD, and the inorganic layer 210 may contact the upper surface of the third interlayer insulating layer 208 through the opening 209OD formed in the first organic insulating layer 209. In this case, an inorganic contact region ICR can be formed through the contact between the inorganic layer 210 and the third interlayer insulating layer 208.

[0147] The lower metal layer 250 can be located below the inorganic ILS structure. It can be used in conjunction with the formation of a reference layer. Figure 8 The lower metal layer 250 is formed using the same process as the lower electrode CE1 of the described gate electrode GE or storage capacitor Cst, and the lower metal layer 250 may include the same material as these.

[0148] refer to Figure 9B Since a first portion of the first organic insulating layer 209 corresponding to the first hole 210H formed in the inorganic layer 210 is etched, a second hole 209H can be formed in the first organic insulating layer 209. A trench G can be defined in a multilayer film ML of the inorganic layer 210 and the first organic insulating layer 209, and can include the first hole 210H and the second hole 209H overlapping each other.

[0149] As referenced above Figure 9A As described, the second hole 209H is formed by etching a first portion of the first organic insulating layer 209 located in the first opening ILS-OP. The lower metal layer 250 can be used as an etching barrier in the etching process to form the second hole 209H. The bottom surface of the trench G can be at the same level as the upper surface of the lower metal layer 250. The bottom surface of the trench G can be at the same level as the upper surface of the lower metal layer 250. The upper surface of the lower metal layer 250 can be the bottom surface of the trench G.

[0150] The width of the second hole 209H can be equal to or greater than the width of the first opening ILS-OP. For example, as Figure 9B As shown, the width W21 of the lower portion of the second hole 209H can be substantially equal to the width W32 of the upper portion of the first opening ILS-OP. The inner surface of the inorganic structure ILS defining the first opening ILS-OP and the inner surface of the first organic insulating layer 209 defining the second hole 209H can constitute the inner surface of the groove G, and the first opening ILS-OP of the inorganic structure ILS can be regarded as defining the groove G together with the first hole 210H and the second hole 209H.

[0151] Optionally, such as Figure 9F As shown, the width W21' of the lower portion of the second hole 209H can be greater than the width W32 of the upper portion of the first opening ILS-OP. The inorganic structure ILS and the first organic insulating layer 209 can form a step. The inner surface of the inorganic structure ILS defining the first opening ILS-OP, a portion of the upper surface of the inorganic structure ILS, and the inner surface of the first organic insulating layer 209 defining the second hole 209H can constitute the inner surface of the groove G. As described above, the first opening ILS-OP of the inorganic structure ILS can be considered as defining the groove G together with the first hole 210H and the second hole 209H.

[0152] The groove G may have an undercut structure (or undercut section). The width W1 of the first hole 210H may be smaller than the width W22 of the upper portion of the second hole 209H. The inorganic layer 210 may include a pair of tips PT (or eaves) projecting toward the center of the groove G. For example, the end of the inorganic layer 210 defining the first hole 210H may project toward the center of the groove G and form a pair of tips PT. The length d1 of each tip PT may be about 1.0 μm or greater and about 2.0 μm or less. For example, the length d1 of the tip PT may be from about 1.1 μm to about 1.7 μm, from about 1.1 μm to about 1.5 μm, or from about 1.1 μm to about 1.3 μm.

[0153] The length d of the groove G can be greater than the length d1 of the tip PT. For example, the length d of the groove G can be approximately 2.5 μm or greater. Specifically, the length d of the groove G can be approximately 2.8 μm or greater, or approximately 3.0 μm or greater.

[0154] Although the width W32 of the upper part of the first opening ILS-OP is in Figure 9B and Figure 9C The width W31 of the upper portion of the first opening ILS-OP is shown in the diagram as being greater than the width of the lower portion of the first opening ILS-OP, but the implementation is not limited to this. According to some example embodiments, the width W32 of the upper portion of the first opening ILS-OP of the inorganic structure ILS can be substantially equal to the width W31 of the lower portion of the first opening ILS-OP of the inorganic structure ILS. Although in Figure 9B and Figure 9C In this embodiment, the width W22 of the upper portion of the second hole 209H differs from the widths W21 and W21' of the lower portion of the second hole 209H, but the implementation is not limited to this. According to some example embodiments, the width W22 of the upper portion of the second hole 209H may be substantially equal to the widths W21 and W21' of the lower portion of the second hole 209H.

[0155] refer to Figure 9C and Figure 9D After forming groove G, intermediate layer 222 can be formed. Figure 8 Furthermore, at least one organic material layer of the intermediate layer 222 can be disconnected or spaced apart by the groove G. For example, the first functional layer 222a and / or the second functional layer 222c can be disconnected or spaced apart by the groove G. Similarly, the counter electrode 223 and the capping layer 230 can also be disconnected or spaced apart by the groove G.

[0156] Before the formation of the intermediate layer 222, the partition wall PW can be formed in the intermediate region MA. The partition wall PW may include a plurality of sub-partition wall layers 211P, 215P, and 217P stacked on the first organic insulating layer 209. A portion 209P of the first organic insulating layer 209 may also form the partition wall PW. The plurality of sub-partition wall layers 211P, 215P, and 217P may correspond to the references above, respectively. Figure 8 A portion of the second organic insulating layer 211, a portion of the pixel defining layer 215, and a portion of the separator 217 are described. One or more of the plurality of sub-partition wall layers 211P, 215P, and 217P can be omitted. In this case, the height from the substrate 100 to the upper surface of the partition wall PW can be lower than the height from the substrate 100 to the upper surface of the separator 217 in the display area DA. Figure 8 The height of ). Although Figure 9C and Figure 9EThe illustration shows a partition wall PW located in the intermediate region MA, but according to some example implementations, two or more partition walls may be located in the intermediate region MA.

[0157] refer to Figure 9E After forming the intermediate layer 222, counter electrode 223, and capping layer 230, a thin-film encapsulation layer 300 can be formed. A first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 can be formed using chemical vapor deposition. Because the first inorganic encapsulation layer 310 has relatively excellent stepped coverage, it can be continuously formed to cover the inner surface of the trench G. For example, the first inorganic encapsulation layer 310 can extend while covering the upper, side, and lower surfaces of the tip PT, and thus can cover the inner surface of the first organic insulating layer 209 defining the second hole 209H. Figure 9B ) and an organic material layer spaced apart and located on the bottom surface of the groove G.

[0158] The organic encapsulation layer 320 can be located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, and the end of the organic encapsulation layer 320 can be positioned adjacent to one side of the partition wall PW between adjacent slots G. The internal space of some slots G (e.g., slot G adjacent to the display area DA) can be at least partially filled by the organic encapsulation layer 320.

[0159] Similar to the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330 also has relatively superior stepped coverage. Therefore, the second inorganic encapsulation layer 330 can be continuously formed along the inner surface of the groove G that is not covered by the organic encapsulation layer 320.

[0160] Figure 10 This is a plan view of a portion of the central area of ​​a display panel according to an embodiment. For ease of description, Figure 10 A partial view of the grooves and metal layers contained in the inorganic structure is shown. According to some example embodiments, the second metal layer 206B is illustrated as being contained within... Figure 10 The metal layer in the inorganic structure; however, Figure 10 The structure is also applied to the above reference. Figure 8 The first metal layer 206A is described.

[0161] refer to Figure 10 Multiple slots G are arranged around the first region OA, and each slot G can extend to surround the first region OA, as shown in the reference above. Figure 7 Described.

[0162] Similarly, the second metal layer 206B can also extend to surround the first region OA. For example... Figure 10As shown, the second metal layer 206B may have an annular shape surrounding the first region OA, and may include a second-second opening 206B-OP corresponding to the groove G.

[0163] The width Wmb of the second-second opening 206B-OP of the second metal layer 206B is greater than the width of the groove G. For example, the width Wmb of the second-second opening 206B-OP of the second metal layer 206B can correspond to the width of the groove G, for example, the width W1 of the first hole 210H of the inorganic layer 210. Figure 9B ).

[0164] Figure 11 This is a cross-sectional view of the middle region of the display panel 10-2 according to another embodiment.

[0165] refer to Figure 11 Display panel 10-2 and the above reference Figure 8 The described display panel 10-1 differs in structure from the lower metal layer 250'.

[0166] refer to Figure 11 The lower metal layer 250' may include a third opening 250'OP corresponding to the groove G. The width Wm1 of the third opening 250'OP may be greater than the width W31 of the first opening ILS-OP of the inorganic structure ILS. The bottom surface of the groove G may be at a lower level than the upper surface of the lower metal layer 250'. The bottom surface of the groove G may be located on a virtual surface between the upper surface of the buffer layer 201 and the upper surface of the lower metal layer 250'. According to some example embodiments, such as... Figure 11 As shown, the bottom surface of the groove G is on the same surface as the upper surface of the gate insulating layer 203. The lower metal layer 250', including the third opening 250'OP, can be considered as a component of the inorganic structure ILS.

[0167] Figure 12 This is a schematic cross-sectional view of the display panel 10-3 according to the embodiment.

[0168] Figure 12 The display panel 10-3 may include a planarized organic layer 420 located on the thin-film encapsulation layer 300 and in the intermediate region MA. The structure from the substrate 100 to the thin-film encapsulation layer 300 is the same as described above. Figures 8 to 9F The structures described are the same.

[0169] The planarization organic layer 420 may be disposed only in the intermediate region MA. The planarization organic layer 420 may be an organic insulating layer. The planarization organic layer 420 may include polymeric materials. For example, the planarization organic layer 420 may include silicone resins, acrylic resins, epoxy resins, polyimides, and polyethylene, etc. According to some example embodiments, the planarization organic layer 420 may include a material different from the organic encapsulation layer 320.

[0170] The planarization organic layer 420 can cover at least one slot G located in the intermediate region MA. The planarization organic layer 420 can cover areas in the intermediate region MA not covered by the organic encapsulation layer 320, thereby increasing the flatness of the display panel 10-3 around the first region OA. Therefore, it can prevent the input sensing layer 40 located on the display panel 10-3 from being obstructed. Figure 2 or Figure 3 ) or / and optical functional layer 50 ( Figure 2 or Figure 3 The organic layer 420 may be spaced apart or detached. A portion of the planarization organic layer 420 may overlap with the organic encapsulation layer 320. One end of the planarization organic layer 420 (e.g., the first end 420e adjacent to the display area DA) may be located on the organic encapsulation layer 320.

[0171] The planarization organic layer 420 can be formed on the intermediate region MA using processes such as exposure and development. In some processes of forming the planarization organic layer 420 (e.g., cleaning processes), the organic light-emitting diodes (OLEDs) in the display region DA may be damaged when foreign matter, such as moisture, travels in the lateral direction (or the x-direction parallel to the upper surface of the substrate) of the display panel 10-3. However, according to an embodiment, insulating layers are respectively provided below and above the planarization organic layer 420, for example, a first insulating layer 410 and a second insulating layer 430, and therefore, the aforementioned problems caused by moisture penetration and / or the shedding of layers surrounding the planarization organic layer 420 can be prevented during the formation of the planarization organic layer 420 and in other subsequent processes.

[0172] The first insulating layer 410 and the second insulating layer 430 may be in direct contact with the lower and upper surfaces of the planarized organic layer 420, respectively. The first insulating layer 410 and the second insulating layer 430 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Each of the first insulating layer 410 and the second insulating layer 430 may comprise a single layer or multiple layers containing the aforementioned materials.

[0173] The planarization organic layer 420 may form a step with the layer below it. For example, the portion of the planarization organic layer 420 including the first end 420e may form a step with the upper surface of the first insulating layer 410. During and / or after the manufacture of the display panel 10-3, in order to prevent the planarization organic layer 420 from being spaced apart or to prevent the planarization organic layer 420 from floating from the layer below it due to the step difference, the cover layer 440 may be located above the first end 420e.

[0174] The cover layer 440 may include metal. The first insulating layer 410, the second insulating layer 430, and the third insulating layer 450, which will be described later, extend not only to the intermediate region MA but also to the display region DA, while the cover layer 440, having a specific width, may cover the first end 420e of the planarized organic layer 420. The cover layer 440 on the planarized organic layer 420 may extend beyond the first end 420e of the planarized organic layer 420 and extend a specific width toward the display region DA.

[0175] The third insulating layer 450 may be located on the cover layer 440. The third insulating layer 450 may include an organic insulating material. For example, the third insulating layer 450 may include an organic insulating material (which is a photoresist (negative or positive) or a polymeric organic material) and may extend to the display area DA to cover the display area DA.

[0176] refer to Figure 12 The described structure can also be applied to references Figure 11 The described implementation methods and other implementation methods derived therefrom.

[0177] refer to Figure 8 , Figure 11 and Figure 12 The described display panels 10-1, 10-2, and 10-3 include through holes 10H corresponding to the first region OA, and the substrate 100 also includes through holes corresponding to the first region OA, but the embodiments are not limited thereto. According to some exemplary embodiments, as referenced above... Figure 4B As described above, the display panel may not have holes passing through the substrate 100.

[0178] In the display panel according to the embodiment, damage to the display elements due to external impurities such as moisture around the first area can be prevented. However, the effect described above is merely an example.

[0179] It should be understood that the embodiments described herein should be considered for descriptive purposes only and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered as applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: A substrate, including a top surface and a bottom surface, the substrate having a through hole extending from the top surface through the substrate to the bottom surface; The first transistor is located in the display area and is electrically connected to the scan line and the data line; A second transistor is located in the display area and is electrically connected to the first transistor; A capacitor is located in the display area and is electrically connected to the second transistor; A light-emitting diode is located in the display area, and the light-emitting diode includes a pixel electrode, a counter electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the counter electrode; An encapsulation layer is located on the light-emitting diode in the display area; A partition wall is located in the non-display area between the through-hole of the substrate and the display area; as well as A first stacked structure is located in the non-display area. In a plan view, the first stacked structure is disposed between the through-hole of the substrate and the partition wall. The first stacked structure includes: Metal layer; A first metal layer is disposed between the substrate and the metal layer, wherein the metal layer overlaps with the first metal layer; and A second metal layer is disposed between the first metal layer and the first metal layer. The second metal layer overlaps with the first metal layer, and the first insulating layer is disposed between the first metal layer and the second metal layer.

2. The display panel according to claim 1, further comprising a second insulating layer disposed between the second metal layer and the metal layer.

3. The display panel according to claim 2, wherein, The thickness of the second insulating layer is greater than the thickness of the first insulating layer.

4. The display panel according to claim 2, wherein, The second insulating layer has holes, and the metal layer directly contacts the top surface of the second metal layer through the holes in the second insulating layer.

5. The display panel according to claim 1, further comprising a second stacking structure separated from the first stacking structure in the non-display area, wherein, The second stacking structure includes: Metal layer; A first metal layer is disposed between the substrate and the metal layer of the second stacked structure; and A second metal layer is disposed between the first metal layer and the metal layer of the second stacked structure. In this configuration, the second metal layer of the second stacked structure overlaps with the first metal layer of the second stacked structure, and the first insulating layer is located between the first metal layer and the second metal layer of the second stacked structure.

6. The display panel according to claim 5, wherein, The first insulating layer has a hole, which is disposed in the region between the first stacked structure and the second stacked structure.

7. The display panel according to claim 1, wherein, The metal layer of the first stacked structure comprises three sublayers: a first titanium layer, an aluminum layer, and a second titanium layer.

8. The display panel according to claim 1, wherein, The encapsulation layer includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer. In the non-display area, a portion of the second inorganic encapsulation layer is in direct contact with a portion of the first inorganic encapsulation layer above the first stacked structure.

9. The display panel according to claim 8, further comprising a planarized organic layer disposed above the direct contact area between the portion of the second inorganic encapsulation layer and the portion of the first inorganic encapsulation layer.

10. The display panel according to claim 1, wherein, The through-hole of each of the first metal layer and the second metal layer of the first stacked structure surrounding the substrate in the plan view.

11. A display panel, comprising: A substrate, including a top surface and a bottom surface, the substrate having a through hole extending from the top surface through the substrate to the bottom surface; The first transistor is located in the display area and is electrically connected to the scan line and the data line; A second transistor is located in the display area and is electrically connected to the first transistor; A capacitor, located in the display area and electrically connected to the second transistor, the capacitor including a lower electrode and an upper electrode; A light-emitting diode is located in the display area, and the light-emitting diode includes a pixel electrode, a counter electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the counter electrode; An encapsulation layer is located on the light-emitting diode in the display area; A partition wall is located in the non-display area between the through-hole of the substrate and the display area; A metal layer is located in the non-display area, and the metal layer is disposed between the through hole of the substrate and the partition wall in the plan view; A first metal layer is disposed between the substrate and the metal layer; A second metal layer is disposed between the first metal layer and the metal layer; as well as A first insulating layer is located between the first metal layer and the second metal layer, wherein the metal layer, the second metal layer and the first metal layer overlap each other.

12. The display panel according to claim 11, wherein: The second metal layer and the upper electrode of the capacitor comprise the same material, and The first metal layer and the lower electrode of the capacitor are made of the same material.

13. The display panel according to claim 11, wherein, The metal layer comprises three sublayers: a first titanium layer, an aluminum layer, and a second titanium layer.

14. The display panel according to claim 11, further comprising a second insulating layer disposed between the second metal layer and the metal layer.

15. The display panel according to claim 14, wherein, The thickness of the second insulating layer is greater than the thickness of the first insulating layer.

16. The display panel according to claim 14, wherein, The second insulating layer has holes, and the metal layer directly contacts the top surface of the second metal layer through the holes in the second insulating layer.

17. The display panel according to claim 11, wherein, The encapsulation layer includes a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer. In the non-display area, a portion of the second inorganic encapsulation layer is in direct contact with a portion of the first inorganic encapsulation layer above the metal layer.

18. The display panel of claim 17, further comprising a planarized organic layer disposed above the direct contact area between the portion of the second inorganic encapsulation layer and the portion of the first inorganic encapsulation layer.

19. The display panel according to claim 11, wherein, Each of the first metal layer and the second metal layer surrounds the through-hole of the substrate in the plan view.

20. The display panel according to claim 11, wherein, Each of the side surfaces of the first metal layer and the second metal layer has a positive conical slope.

21. An electronic device, comprising: Display panel according to any one of claims 1 to 20; as well as The component corresponds to the through-hole of the substrate and includes a camera or sensor.

Images